./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.10.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9c9d0ce9-6300-469c-a982-9e357a564b79/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9c9d0ce9-6300-469c-a982-9e357a564b79/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9c9d0ce9-6300-469c-a982-9e357a564b79/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9c9d0ce9-6300-469c-a982-9e357a564b79/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.10.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9c9d0ce9-6300-469c-a982-9e357a564b79/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9c9d0ce9-6300-469c-a982-9e357a564b79/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 9102a3dc168a1a089cfcbe45042daf88c4c5eebedf113fc0c98e676c1fbaab5b --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 15:24:19,477 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 15:24:19,546 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9c9d0ce9-6300-469c-a982-9e357a564b79/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 15:24:19,551 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 15:24:19,551 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 15:24:19,575 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 15:24:19,576 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 15:24:19,576 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 15:24:19,577 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 15:24:19,577 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 15:24:19,577 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 15:24:19,577 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 15:24:19,577 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 15:24:19,578 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 15:24:19,578 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 15:24:19,578 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 15:24:19,578 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 15:24:19,578 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 15:24:19,578 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 15:24:19,578 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 15:24:19,579 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 15:24:19,579 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 15:24:19,579 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 15:24:19,579 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 15:24:19,579 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 15:24:19,579 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 15:24:19,579 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 15:24:19,579 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 15:24:19,580 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 15:24:19,580 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 15:24:19,580 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 15:24:19,580 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 15:24:19,580 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 15:24:19,580 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 15:24:19,580 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 15:24:19,581 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 15:24:19,581 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 15:24:19,581 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 15:24:19,581 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 15:24:19,581 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9c9d0ce9-6300-469c-a982-9e357a564b79/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 9102a3dc168a1a089cfcbe45042daf88c4c5eebedf113fc0c98e676c1fbaab5b [2024-11-13 15:24:19,866 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 15:24:19,874 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 15:24:19,876 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 15:24:19,877 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 15:24:19,878 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 15:24:19,879 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9c9d0ce9-6300-469c-a982-9e357a564b79/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/token_ring.10.cil-1.c Unable to find full path for "g++" [2024-11-13 15:24:21,778 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 15:24:22,056 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 15:24:22,056 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9c9d0ce9-6300-469c-a982-9e357a564b79/sv-benchmarks/c/systemc/token_ring.10.cil-1.c [2024-11-13 15:24:22,069 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9c9d0ce9-6300-469c-a982-9e357a564b79/bin/uautomizer-verify-qhAvR1uOyd/data/a4408db9a/c9332a5de533439d9b08489e4fc5ffd9/FLAGaeb7fc1da [2024-11-13 15:24:22,352 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9c9d0ce9-6300-469c-a982-9e357a564b79/bin/uautomizer-verify-qhAvR1uOyd/data/a4408db9a/c9332a5de533439d9b08489e4fc5ffd9 [2024-11-13 15:24:22,354 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 15:24:22,356 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 15:24:22,357 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 15:24:22,357 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 15:24:22,362 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 15:24:22,362 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:24:22" (1/1) ... [2024-11-13 15:24:22,363 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@502c4d38 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:24:22, skipping insertion in model container [2024-11-13 15:24:22,364 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:24:22" (1/1) ... [2024-11-13 15:24:22,399 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 15:24:22,653 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:24:22,676 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 15:24:22,797 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:24:22,822 INFO L204 MainTranslator]: Completed translation [2024-11-13 15:24:22,822 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:24:22 WrapperNode [2024-11-13 15:24:22,823 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 15:24:22,825 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 15:24:22,825 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 15:24:22,825 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 15:24:22,837 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:24:22" (1/1) ... [2024-11-13 15:24:22,855 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:24:22" (1/1) ... [2024-11-13 15:24:22,960 INFO L138 Inliner]: procedures = 48, calls = 63, calls flagged for inlining = 58, calls inlined = 212, statements flattened = 3210 [2024-11-13 15:24:22,961 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 15:24:22,961 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 15:24:22,962 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 15:24:22,962 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 15:24:22,976 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:24:22" (1/1) ... [2024-11-13 15:24:22,977 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:24:22" (1/1) ... [2024-11-13 15:24:22,984 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:24:22" (1/1) ... [2024-11-13 15:24:23,013 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 15:24:23,014 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:24:22" (1/1) ... [2024-11-13 15:24:23,014 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:24:22" (1/1) ... [2024-11-13 15:24:23,056 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:24:22" (1/1) ... [2024-11-13 15:24:23,115 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:24:22" (1/1) ... [2024-11-13 15:24:23,122 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:24:22" (1/1) ... [2024-11-13 15:24:23,131 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:24:22" (1/1) ... [2024-11-13 15:24:23,150 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 15:24:23,151 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 15:24:23,152 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 15:24:23,152 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 15:24:23,154 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:24:22" (1/1) ... [2024-11-13 15:24:23,163 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:24:23,179 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9c9d0ce9-6300-469c-a982-9e357a564b79/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:24:23,192 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9c9d0ce9-6300-469c-a982-9e357a564b79/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:24:23,196 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9c9d0ce9-6300-469c-a982-9e357a564b79/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 15:24:23,225 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 15:24:23,225 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 15:24:23,226 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 15:24:23,226 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 15:24:23,398 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 15:24:23,400 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 15:24:26,188 INFO L? ?]: Removed 666 outVars from TransFormulas that were not future-live. [2024-11-13 15:24:26,188 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 15:24:26,255 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 15:24:26,255 INFO L316 CfgBuilder]: Removed 13 assume(true) statements. [2024-11-13 15:24:26,256 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:24:26 BoogieIcfgContainer [2024-11-13 15:24:26,256 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 15:24:26,257 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 15:24:26,257 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 15:24:26,264 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 15:24:26,265 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:24:26,265 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 03:24:22" (1/3) ... [2024-11-13 15:24:26,265 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@36c9d17e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:24:26, skipping insertion in model container [2024-11-13 15:24:26,266 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:24:26,266 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:24:22" (2/3) ... [2024-11-13 15:24:26,266 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@36c9d17e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:24:26, skipping insertion in model container [2024-11-13 15:24:26,266 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:24:26,266 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:24:26" (3/3) ... [2024-11-13 15:24:26,267 INFO L333 chiAutomizerObserver]: Analyzing ICFG token_ring.10.cil-1.c [2024-11-13 15:24:26,361 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 15:24:26,361 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 15:24:26,361 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 15:24:26,361 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 15:24:26,362 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 15:24:26,362 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 15:24:26,362 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 15:24:26,362 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 15:24:26,376 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1387 states, 1386 states have (on average 1.5021645021645023) internal successors, (2082), 1386 states have internal predecessors, (2082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:26,466 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1244 [2024-11-13 15:24:26,467 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:24:26,467 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:24:26,480 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:26,482 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:26,482 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 15:24:26,487 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1387 states, 1386 states have (on average 1.5021645021645023) internal successors, (2082), 1386 states have internal predecessors, (2082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:26,518 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1244 [2024-11-13 15:24:26,519 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:24:26,519 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:24:26,524 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:26,528 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:26,536 INFO L745 eck$LassoCheckResult]: Stem: 205#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1274#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1023#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1268#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1171#L731true assume !(1 == ~m_i~0);~m_st~0 := 2; 1034#L731-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 940#L736-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1010#L741-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1328#L746-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 169#L751-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 229#L756-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 850#L761-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 386#L766-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 335#L771-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 170#L776-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10#L781-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54#L1036true assume !(0 == ~M_E~0); 1043#L1036-2true assume !(0 == ~T1_E~0); 620#L1041-1true assume !(0 == ~T2_E~0); 982#L1046-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 193#L1051-1true assume !(0 == ~T4_E~0); 759#L1056-1true assume !(0 == ~T5_E~0); 814#L1061-1true assume !(0 == ~T6_E~0); 137#L1066-1true assume !(0 == ~T7_E~0); 1166#L1071-1true assume !(0 == ~T8_E~0); 739#L1076-1true assume !(0 == ~T9_E~0); 83#L1081-1true assume !(0 == ~T10_E~0); 300#L1086-1true assume 0 == ~E_M~0;~E_M~0 := 1; 1183#L1091-1true assume !(0 == ~E_1~0); 1045#L1096-1true assume !(0 == ~E_2~0); 1278#L1101-1true assume !(0 == ~E_3~0); 344#L1106-1true assume !(0 == ~E_4~0); 559#L1111-1true assume !(0 == ~E_5~0); 462#L1116-1true assume !(0 == ~E_6~0); 1105#L1121-1true assume !(0 == ~E_7~0); 338#L1126-1true assume 0 == ~E_8~0;~E_8~0 := 1; 539#L1131-1true assume !(0 == ~E_9~0); 629#L1136-1true assume !(0 == ~E_10~0); 905#L1141-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 799#L514true assume 1 == ~m_pc~0; 749#L515true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 348#L525true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 877#is_master_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1117#L1285true assume !(0 != activate_threads_~tmp~1#1); 1204#L1285-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 145#L533true assume !(1 == ~t1_pc~0); 1059#L533-2true is_transmit1_triggered_~__retres1~1#1 := 0; 506#L544true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 919#L1293true assume !(0 != activate_threads_~tmp___0~0#1); 653#L1293-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 909#L552true assume 1 == ~t2_pc~0; 269#L553true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 941#L563true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 340#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 986#L1301true assume !(0 != activate_threads_~tmp___1~0#1); 357#L1301-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 518#L571true assume 1 == ~t3_pc~0; 503#L572true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 691#L582true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 660#L1309true assume !(0 != activate_threads_~tmp___2~0#1); 465#L1309-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48#L590true assume !(1 == ~t4_pc~0); 517#L590-2true is_transmit4_triggered_~__retres1~4#1 := 0; 1300#L601true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 92#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1129#L1317true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 676#L1317-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 463#L609true assume 1 == ~t5_pc~0; 1290#L610true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1114#L620true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 881#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1388#L1325true assume !(0 != activate_threads_~tmp___4~0#1); 457#L1325-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1287#L628true assume !(1 == ~t6_pc~0); 540#L628-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1264#L639true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 324#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1194#L1333true assume !(0 != activate_threads_~tmp___5~0#1); 715#L1333-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 859#L647true assume 1 == ~t7_pc~0; 345#L648true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 896#L658true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1294#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 346#L1341true assume !(0 != activate_threads_~tmp___6~0#1); 1257#L1341-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1230#L666true assume !(1 == ~t8_pc~0); 797#L666-2true is_transmit8_triggered_~__retres1~8#1 := 0; 356#L677true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 800#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 482#L1349true assume !(0 != activate_threads_~tmp___7~0#1); 298#L1349-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1147#L685true assume 1 == ~t9_pc~0; 1310#L686true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 920#L696true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 381#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 316#L1357true assume !(0 != activate_threads_~tmp___8~0#1); 1017#L1357-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 599#L704true assume !(1 == ~t10_pc~0); 1102#L704-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1052#L715true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 495#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 71#L1365true assume !(0 != activate_threads_~tmp___9~0#1); 197#L1365-2true havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 704#L1154true assume !(1 == ~M_E~0); 1190#L1154-2true assume !(1 == ~T1_E~0); 182#L1159-1true assume !(1 == ~T2_E~0); 1320#L1164-1true assume !(1 == ~T3_E~0); 480#L1169-1true assume !(1 == ~T4_E~0); 382#L1174-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 253#L1179-1true assume !(1 == ~T6_E~0); 174#L1184-1true assume !(1 == ~T7_E~0); 217#L1189-1true assume !(1 == ~T8_E~0); 289#L1194-1true assume !(1 == ~T9_E~0); 1368#L1199-1true assume !(1 == ~T10_E~0); 263#L1204-1true assume !(1 == ~E_M~0); 1225#L1209-1true assume !(1 == ~E_1~0); 672#L1214-1true assume 1 == ~E_2~0;~E_2~0 := 2; 1318#L1219-1true assume !(1 == ~E_3~0); 1200#L1224-1true assume !(1 == ~E_4~0); 500#L1229-1true assume !(1 == ~E_5~0); 117#L1234-1true assume !(1 == ~E_6~0); 786#L1239-1true assume !(1 == ~E_7~0); 143#L1244-1true assume !(1 == ~E_8~0); 836#L1249-1true assume !(1 == ~E_9~0); 747#L1254-1true assume 1 == ~E_10~0;~E_10~0 := 2; 68#L1259-1true assume { :end_inline_reset_delta_events } true; 1179#L1565-2true [2024-11-13 15:24:26,539 INFO L747 eck$LassoCheckResult]: Loop: 1179#L1565-2true assume !false; 680#L1566true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1073#L1011-1true assume !true; 811#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 512#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 754#L1036-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1080#L1036-5true assume !(0 == ~T1_E~0); 1316#L1041-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 844#L1046-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1201#L1051-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 755#L1056-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 191#L1061-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 192#L1066-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1333#L1071-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1083#L1076-3true assume !(0 == ~T9_E~0); 65#L1081-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1247#L1086-3true assume 0 == ~E_M~0;~E_M~0 := 1; 88#L1091-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1157#L1096-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1012#L1101-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1079#L1106-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1134#L1111-3true assume 0 == ~E_5~0;~E_5~0 := 1; 998#L1116-3true assume !(0 == ~E_6~0); 609#L1121-3true assume 0 == ~E_7~0;~E_7~0 := 1; 944#L1126-3true assume 0 == ~E_8~0;~E_8~0 := 1; 870#L1131-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1311#L1136-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1284#L1141-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 613#L514-36true assume 1 == ~m_pc~0; 1362#L515-12true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 283#L525-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1026#is_master_triggered_returnLabel#13true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 651#L1285-36true assume !(0 != activate_threads_~tmp~1#1); 221#L1285-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 400#L533-36true assume !(1 == ~t1_pc~0); 751#L533-38true is_transmit1_triggered_~__retres1~1#1 := 0; 969#L544-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1024#is_transmit1_triggered_returnLabel#13true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 690#L1293-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 516#L1293-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1377#L552-36true assume !(1 == ~t2_pc~0); 1349#L552-38true is_transmit2_triggered_~__retres1~2#1 := 0; 558#L563-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 857#is_transmit2_triggered_returnLabel#13true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1188#L1301-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 203#L1301-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 847#L571-36true assume !(1 == ~t3_pc~0); 975#L571-38true is_transmit3_triggered_~__retres1~3#1 := 0; 254#L582-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 378#is_transmit3_triggered_returnLabel#13true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 842#L1309-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 887#L1309-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 238#L590-36true assume 1 == ~t4_pc~0; 705#L591-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1027#L601-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 525#is_transmit4_triggered_returnLabel#13true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1323#L1317-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 807#L1317-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1070#L609-36true assume !(1 == ~t5_pc~0); 1340#L609-38true is_transmit5_triggered_~__retres1~5#1 := 0; 520#L620-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 978#is_transmit5_triggered_returnLabel#13true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 876#L1325-36true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 580#L1325-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 435#L628-36true assume !(1 == ~t6_pc~0); 1144#L628-38true is_transmit6_triggered_~__retres1~6#1 := 0; 1148#L639-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 364#is_transmit6_triggered_returnLabel#13true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 760#L1333-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 614#L1333-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1111#L647-36true assume !(1 == ~t7_pc~0); 678#L647-38true is_transmit7_triggered_~__retres1~7#1 := 0; 77#L658-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 948#is_transmit7_triggered_returnLabel#13true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85#L1341-36true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 706#L1341-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 779#L666-36true assume 1 == ~t8_pc~0; 181#L667-12true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1209#L677-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 604#is_transmit8_triggered_returnLabel#13true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1222#L1349-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 268#L1349-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 595#L685-36true assume !(1 == ~t9_pc~0); 132#L685-38true is_transmit9_triggered_~__retres1~9#1 := 0; 888#L696-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 403#is_transmit9_triggered_returnLabel#13true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1277#L1357-36true assume !(0 != activate_threads_~tmp___8~0#1); 354#L1357-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 363#L704-36true assume !(1 == ~t10_pc~0); 266#L704-38true is_transmit10_triggered_~__retres1~10#1 := 0; 1163#L715-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 305#is_transmit10_triggered_returnLabel#13true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 732#L1365-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 139#L1365-38true havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1361#L1154-3true assume 1 == ~M_E~0;~M_E~0 := 2; 981#L1154-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 769#L1159-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1335#L1164-3true assume !(1 == ~T3_E~0); 1107#L1169-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 309#L1174-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1196#L1179-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 923#L1184-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 78#L1189-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 929#L1194-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 274#L1199-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1371#L1204-3true assume !(1 == ~E_M~0); 497#L1209-3true assume 1 == ~E_1~0;~E_1~0 := 2; 17#L1214-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1021#L1219-3true assume 1 == ~E_3~0;~E_3~0 := 2; 658#L1224-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1382#L1229-3true assume 1 == ~E_5~0;~E_5~0 := 2; 679#L1234-3true assume 1 == ~E_6~0;~E_6~0 := 2; 144#L1239-3true assume 1 == ~E_7~0;~E_7~0 := 2; 535#L1244-3true assume !(1 == ~E_8~0); 1086#L1249-3true assume 1 == ~E_9~0;~E_9~0 := 2; 999#L1254-3true assume 1 == ~E_10~0;~E_10~0 := 2; 664#L1259-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 763#L794-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1296#L851-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 297#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 618#L1584true assume !(0 == start_simulation_~tmp~3#1); 643#L1584-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 150#L794-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 943#L851-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 32#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 342#L1539true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 987#L1546true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 528#stop_simulation_returnLabel#1true start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1174#L1597true assume !(0 != start_simulation_~tmp___0~1#1); 1179#L1565-2true [2024-11-13 15:24:26,544 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:26,545 INFO L85 PathProgramCache]: Analyzing trace with hash 121410427, now seen corresponding path program 1 times [2024-11-13 15:24:26,553 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:26,554 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1955139128] [2024-11-13 15:24:26,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:26,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:26,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:26,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:26,920 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:26,921 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1955139128] [2024-11-13 15:24:26,921 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1955139128] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:26,921 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:26,922 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:26,923 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1645344515] [2024-11-13 15:24:26,924 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:26,927 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:24:26,928 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:26,928 INFO L85 PathProgramCache]: Analyzing trace with hash 160609195, now seen corresponding path program 1 times [2024-11-13 15:24:26,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:26,929 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [774532312] [2024-11-13 15:24:26,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:26,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:26,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:27,004 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:27,005 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:27,005 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [774532312] [2024-11-13 15:24:27,005 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [774532312] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:27,005 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:27,005 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:24:27,005 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [531963866] [2024-11-13 15:24:27,005 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:27,011 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:24:27,012 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:24:27,060 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:24:27,060 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:24:27,068 INFO L87 Difference]: Start difference. First operand has 1387 states, 1386 states have (on average 1.5021645021645023) internal successors, (2082), 1386 states have internal predecessors, (2082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:27,199 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:24:27,200 INFO L93 Difference]: Finished difference Result 1383 states and 2049 transitions. [2024-11-13 15:24:27,201 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1383 states and 2049 transitions. [2024-11-13 15:24:27,214 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2024-11-13 15:24:27,230 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1383 states to 1377 states and 2043 transitions. [2024-11-13 15:24:27,231 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2024-11-13 15:24:27,233 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2024-11-13 15:24:27,234 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2043 transitions. [2024-11-13 15:24:27,240 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:24:27,241 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2043 transitions. [2024-11-13 15:24:27,258 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2043 transitions. [2024-11-13 15:24:27,329 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2024-11-13 15:24:27,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4836601307189543) internal successors, (2043), 1376 states have internal predecessors, (2043), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:27,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2043 transitions. [2024-11-13 15:24:27,340 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2043 transitions. [2024-11-13 15:24:27,343 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:24:27,348 INFO L424 stractBuchiCegarLoop]: Abstraction has 1377 states and 2043 transitions. [2024-11-13 15:24:27,348 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 15:24:27,348 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2043 transitions. [2024-11-13 15:24:27,358 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2024-11-13 15:24:27,358 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:24:27,359 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:24:27,363 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:27,367 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:27,368 INFO L745 eck$LassoCheckResult]: Stem: 3197#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3198#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4074#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4075#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4137#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 4078#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4038#L736-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4039#L741-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4067#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3136#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3137#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3242#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3487#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3413#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3138#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 2797#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2798#L1036 assume !(0 == ~M_E~0); 2895#L1036-2 assume !(0 == ~T1_E~0); 3800#L1041-1 assume !(0 == ~T2_E~0); 3801#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3172#L1051-1 assume !(0 == ~T4_E~0); 3173#L1056-1 assume !(0 == ~T5_E~0); 3929#L1061-1 assume !(0 == ~T6_E~0); 3067#L1066-1 assume !(0 == ~T7_E~0); 3068#L1071-1 assume !(0 == ~T8_E~0); 3911#L1076-1 assume !(0 == ~T9_E~0); 2957#L1081-1 assume !(0 == ~T10_E~0); 2958#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3358#L1091-1 assume !(0 == ~E_1~0); 4086#L1096-1 assume !(0 == ~E_2~0); 4087#L1101-1 assume !(0 == ~E_3~0); 3426#L1106-1 assume !(0 == ~E_4~0); 3427#L1111-1 assume !(0 == ~E_5~0); 3591#L1116-1 assume !(0 == ~E_6~0); 3592#L1121-1 assume !(0 == ~E_7~0); 3417#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 3418#L1131-1 assume !(0 == ~E_9~0); 3693#L1136-1 assume !(0 == ~E_10~0); 3808#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3957#L514 assume 1 == ~m_pc~0; 3922#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3435#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3436#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4009#L1285 assume !(0 != activate_threads_~tmp~1#1); 4122#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3086#L533 assume !(1 == ~t1_pc~0); 3087#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3606#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2852#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2853#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 3829#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3830#L552 assume 1 == ~t2_pc~0; 3307#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3308#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3421#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3422#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 3453#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3454#L571 assume 1 == ~t3_pc~0; 3646#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3647#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2795#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2796#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 3596#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2881#L590 assume !(1 == ~t4_pc~0); 2882#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3654#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2975#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2976#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3857#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3593#L609 assume 1 == ~t5_pc~0; 3594#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4119#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4011#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4012#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 3585#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3586#L628 assume !(1 == ~t6_pc~0); 3518#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3517#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3395#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3396#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 3891#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3892#L647 assume 1 == ~t7_pc~0; 3428#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3429#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4020#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3433#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 3434#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4148#L666 assume !(1 == ~t8_pc~0); 3219#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3220#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3447#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3618#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 3356#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3357#L685 assume 1 == ~t9_pc~0; 4127#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4028#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3481#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3385#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 3386#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3771#L704 assume !(1 == ~t10_pc~0); 3375#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3374#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3636#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2929#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 2930#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3181#L1154 assume !(1 == ~M_E~0); 3879#L1154-2 assume !(1 == ~T1_E~0); 3155#L1159-1 assume !(1 == ~T2_E~0); 3156#L1164-1 assume !(1 == ~T3_E~0); 3615#L1169-1 assume !(1 == ~T4_E~0); 3482#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3286#L1179-1 assume !(1 == ~T6_E~0); 3140#L1184-1 assume !(1 == ~T7_E~0); 3141#L1189-1 assume !(1 == ~T8_E~0); 3217#L1194-1 assume !(1 == ~T9_E~0); 3344#L1199-1 assume !(1 == ~T10_E~0); 3298#L1204-1 assume !(1 == ~E_M~0); 3299#L1209-1 assume !(1 == ~E_1~0); 3852#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3853#L1219-1 assume !(1 == ~E_3~0); 4141#L1224-1 assume !(1 == ~E_4~0); 3640#L1229-1 assume !(1 == ~E_5~0); 3024#L1234-1 assume !(1 == ~E_6~0); 3025#L1239-1 assume !(1 == ~E_7~0); 3082#L1244-1 assume !(1 == ~E_8~0); 3083#L1249-1 assume !(1 == ~E_9~0); 3920#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 2924#L1259-1 assume { :end_inline_reset_delta_events } true; 2925#L1565-2 [2024-11-13 15:24:27,369 INFO L747 eck$LassoCheckResult]: Loop: 2925#L1565-2 assume !false; 3858#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3624#L1011-1 assume !false; 3587#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3360#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3124#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3460#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3152#L866 assume !(0 != eval_~tmp~0#1); 3154#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3657#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3658#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3924#L1036-5 assume !(0 == ~T1_E~0); 4103#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3985#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3986#L1051-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3925#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3169#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3170#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3171#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4105#L1076-3 assume !(0 == ~T9_E~0); 2916#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2917#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2971#L1091-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2972#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4069#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4070#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4102#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4061#L1116-3 assume !(0 == ~E_6~0); 3786#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3787#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4000#L1131-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4001#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4153#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3789#L514-36 assume !(1 == ~m_pc~0); 3498#L514-38 is_master_triggered_~__retres1~0#1 := 0; 3333#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3334#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3828#L1285-36 assume !(0 != activate_threads_~tmp~1#1); 3226#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3227#L533-36 assume 1 == ~t1_pc~0; 3507#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3603#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4051#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3866#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3663#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3664#L552-36 assume 1 == ~t2_pc~0; 3221#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3222#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3722#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3993#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3193#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3194#L571-36 assume 1 == ~t3_pc~0; 3581#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3284#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3285#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3477#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3984#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3253#L590-36 assume !(1 == ~t4_pc~0); 3254#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 3880#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3673#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3674#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3963#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3964#L609-36 assume 1 == ~t5_pc~0; 3841#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3666#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3667#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4008#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3750#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3557#L628-36 assume 1 == ~t6_pc~0; 3405#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3406#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3456#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3457#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3791#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3792#L647-36 assume 1 == ~t7_pc~0; 3715#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2943#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2944#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2961#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2962#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3881#L666-36 assume 1 == ~t8_pc~0; 3149#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3150#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3779#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3780#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3304#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3305#L685-36 assume 1 == ~t9_pc~0; 3766#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3056#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3511#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3512#L1357-36 assume !(0 != activate_threads_~tmp___8~0#1); 3444#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3445#L704-36 assume 1 == ~t10_pc~0; 3043#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3044#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3365#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3366#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3071#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3072#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4055#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3938#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3939#L1164-3 assume !(1 == ~T3_E~0); 4116#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3371#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3372#L1179-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4030#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2945#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2946#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3315#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3316#L1204-3 assume !(1 == ~E_M~0); 3635#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2813#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2814#L1219-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3835#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3836#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3856#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3084#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3085#L1244-3 assume !(1 == ~E_8~0); 3686#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4062#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3839#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3840#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2893#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3353#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3354#L1584 assume !(0 == start_simulation_~tmp~3#1); 3797#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3098#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2793#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2845#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 2846#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3423#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3679#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3680#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 2925#L1565-2 [2024-11-13 15:24:27,369 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:27,370 INFO L85 PathProgramCache]: Analyzing trace with hash -825627459, now seen corresponding path program 1 times [2024-11-13 15:24:27,370 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:27,370 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [766757497] [2024-11-13 15:24:27,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:27,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:27,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:27,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:27,591 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:27,591 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [766757497] [2024-11-13 15:24:27,591 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [766757497] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:27,592 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:27,592 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:27,592 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1351234102] [2024-11-13 15:24:27,592 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:27,592 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:24:27,593 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:27,593 INFO L85 PathProgramCache]: Analyzing trace with hash 1255214839, now seen corresponding path program 1 times [2024-11-13 15:24:27,593 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:27,593 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [306777203] [2024-11-13 15:24:27,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:27,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:27,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:27,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:27,769 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:27,770 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [306777203] [2024-11-13 15:24:27,770 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [306777203] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:27,770 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:27,770 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:27,770 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1984773364] [2024-11-13 15:24:27,770 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:27,771 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:24:27,771 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:24:27,771 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:24:27,771 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:24:27,772 INFO L87 Difference]: Start difference. First operand 1377 states and 2043 transitions. cyclomatic complexity: 667 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:27,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:24:27,811 INFO L93 Difference]: Finished difference Result 1377 states and 2042 transitions. [2024-11-13 15:24:27,811 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2042 transitions. [2024-11-13 15:24:27,825 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2024-11-13 15:24:27,837 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2042 transitions. [2024-11-13 15:24:27,838 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2024-11-13 15:24:27,839 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2024-11-13 15:24:27,841 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2042 transitions. [2024-11-13 15:24:27,843 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:24:27,846 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2042 transitions. [2024-11-13 15:24:27,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2042 transitions. [2024-11-13 15:24:27,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2024-11-13 15:24:27,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4829339143064633) internal successors, (2042), 1376 states have internal predecessors, (2042), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:27,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2042 transitions. [2024-11-13 15:24:27,883 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2042 transitions. [2024-11-13 15:24:27,884 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:24:27,884 INFO L424 stractBuchiCegarLoop]: Abstraction has 1377 states and 2042 transitions. [2024-11-13 15:24:27,884 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 15:24:27,885 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2042 transitions. [2024-11-13 15:24:27,895 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2024-11-13 15:24:27,895 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:24:27,895 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:24:27,902 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:27,902 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:27,902 INFO L745 eck$LassoCheckResult]: Stem: 5958#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 5959#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6835#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6836#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6898#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 6839#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6799#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6800#L741-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6828#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5895#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5896#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6003#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6248#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6174#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5897#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5558#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5559#L1036 assume !(0 == ~M_E~0); 5656#L1036-2 assume !(0 == ~T1_E~0); 6561#L1041-1 assume !(0 == ~T2_E~0); 6562#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5933#L1051-1 assume !(0 == ~T4_E~0); 5934#L1056-1 assume !(0 == ~T5_E~0); 6690#L1061-1 assume !(0 == ~T6_E~0); 5828#L1066-1 assume !(0 == ~T7_E~0); 5829#L1071-1 assume !(0 == ~T8_E~0); 6672#L1076-1 assume !(0 == ~T9_E~0); 5718#L1081-1 assume !(0 == ~T10_E~0); 5719#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6119#L1091-1 assume !(0 == ~E_1~0); 6846#L1096-1 assume !(0 == ~E_2~0); 6847#L1101-1 assume !(0 == ~E_3~0); 6187#L1106-1 assume !(0 == ~E_4~0); 6188#L1111-1 assume !(0 == ~E_5~0); 6352#L1116-1 assume !(0 == ~E_6~0); 6353#L1121-1 assume !(0 == ~E_7~0); 6178#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 6179#L1131-1 assume !(0 == ~E_9~0); 6454#L1136-1 assume !(0 == ~E_10~0); 6569#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6718#L514 assume 1 == ~m_pc~0; 6683#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6196#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6197#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6770#L1285 assume !(0 != activate_threads_~tmp~1#1); 6882#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5847#L533 assume !(1 == ~t1_pc~0); 5848#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6367#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5611#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5612#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 6590#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6591#L552 assume 1 == ~t2_pc~0; 6067#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6068#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6182#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6183#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 6209#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6210#L571 assume 1 == ~t3_pc~0; 6405#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6406#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5556#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5557#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 6357#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5642#L590 assume !(1 == ~t4_pc~0); 5643#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6415#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5736#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5737#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6617#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6354#L609 assume 1 == ~t5_pc~0; 6355#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6880#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6772#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6773#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 6346#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6347#L628 assume !(1 == ~t6_pc~0); 6279#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6278#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6155#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6156#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 6652#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6653#L647 assume 1 == ~t7_pc~0; 6189#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6190#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6781#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6192#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 6193#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6909#L666 assume !(1 == ~t8_pc~0); 5980#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5981#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6208#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6378#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 6116#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6117#L685 assume 1 == ~t9_pc~0; 6888#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6789#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6242#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6146#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 6147#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6532#L704 assume !(1 == ~t10_pc~0); 6136#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6135#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6396#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5690#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 5691#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5942#L1154 assume !(1 == ~M_E~0); 6640#L1154-2 assume !(1 == ~T1_E~0); 5916#L1159-1 assume !(1 == ~T2_E~0); 5917#L1164-1 assume !(1 == ~T3_E~0); 6376#L1169-1 assume !(1 == ~T4_E~0); 6243#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6045#L1179-1 assume !(1 == ~T6_E~0); 5901#L1184-1 assume !(1 == ~T7_E~0); 5902#L1189-1 assume !(1 == ~T8_E~0); 5978#L1194-1 assume !(1 == ~T9_E~0); 6103#L1199-1 assume !(1 == ~T10_E~0); 6057#L1204-1 assume !(1 == ~E_M~0); 6058#L1209-1 assume !(1 == ~E_1~0); 6611#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6612#L1219-1 assume !(1 == ~E_3~0); 6902#L1224-1 assume !(1 == ~E_4~0); 6400#L1229-1 assume !(1 == ~E_5~0); 5785#L1234-1 assume !(1 == ~E_6~0); 5786#L1239-1 assume !(1 == ~E_7~0); 5843#L1244-1 assume !(1 == ~E_8~0); 5844#L1249-1 assume !(1 == ~E_9~0); 6681#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 5685#L1259-1 assume { :end_inline_reset_delta_events } true; 5686#L1565-2 [2024-11-13 15:24:27,903 INFO L747 eck$LassoCheckResult]: Loop: 5686#L1565-2 assume !false; 6619#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6384#L1011-1 assume !false; 6348#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6121#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5885#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6221#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5908#L866 assume !(0 != eval_~tmp~0#1); 5910#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6417#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6418#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6685#L1036-5 assume !(0 == ~T1_E~0); 6864#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6746#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6747#L1051-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6686#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5930#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5931#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5932#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6866#L1076-3 assume !(0 == ~T9_E~0); 5677#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5678#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5728#L1091-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5729#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6830#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6831#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6863#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6822#L1116-3 assume !(0 == ~E_6~0); 6547#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6548#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6761#L1131-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6762#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6914#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6550#L514-36 assume !(1 == ~m_pc~0); 6259#L514-38 is_master_triggered_~__retres1~0#1 := 0; 6094#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6095#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6589#L1285-36 assume !(0 != activate_threads_~tmp~1#1); 5987#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5988#L533-36 assume 1 == ~t1_pc~0; 6268#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6361#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6812#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6627#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6424#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6425#L552-36 assume !(1 == ~t2_pc~0); 5984#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 5983#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6483#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6754#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5954#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5955#L571-36 assume 1 == ~t3_pc~0; 6342#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6046#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6047#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6238#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6745#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6017#L590-36 assume !(1 == ~t4_pc~0); 6018#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 6641#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6434#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6435#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6724#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6725#L609-36 assume 1 == ~t5_pc~0; 6602#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6427#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6428#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6769#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6511#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6318#L628-36 assume 1 == ~t6_pc~0; 6166#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6167#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6217#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6218#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6552#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6553#L647-36 assume 1 == ~t7_pc~0; 6476#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5704#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5705#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5722#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5723#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6642#L666-36 assume 1 == ~t8_pc~0; 5913#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5914#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6540#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6541#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6065#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6066#L685-36 assume !(1 == ~t9_pc~0); 5816#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 5817#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6272#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6273#L1357-36 assume !(0 != activate_threads_~tmp___8~0#1); 6205#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6206#L704-36 assume 1 == ~t10_pc~0; 5804#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5805#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6126#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6127#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5832#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5833#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6816#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6699#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6700#L1164-3 assume !(1 == ~T3_E~0); 6877#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6132#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6133#L1179-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6791#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5706#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5707#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6076#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6077#L1204-3 assume !(1 == ~E_M~0); 6397#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5574#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5575#L1219-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6596#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6597#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6618#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5845#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5846#L1244-3 assume !(1 == ~E_8~0); 6451#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6823#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6600#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6601#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5654#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6114#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6115#L1584 assume !(0 == start_simulation_~tmp~3#1); 6558#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5859#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5554#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5606#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 5607#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6185#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6440#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 6441#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 5686#L1565-2 [2024-11-13 15:24:27,903 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:27,903 INFO L85 PathProgramCache]: Analyzing trace with hash 1224781439, now seen corresponding path program 1 times [2024-11-13 15:24:27,903 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:27,903 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1182605533] [2024-11-13 15:24:27,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:27,904 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:27,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:28,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:28,026 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:28,026 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1182605533] [2024-11-13 15:24:28,026 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1182605533] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:28,026 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:28,026 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:28,026 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269575110] [2024-11-13 15:24:28,026 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:28,027 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:24:28,027 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:28,027 INFO L85 PathProgramCache]: Analyzing trace with hash -2024908615, now seen corresponding path program 1 times [2024-11-13 15:24:28,027 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:28,027 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039593318] [2024-11-13 15:24:28,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:28,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:28,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:28,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:28,188 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:28,188 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1039593318] [2024-11-13 15:24:28,189 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1039593318] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:28,189 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:28,189 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:28,189 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [419694022] [2024-11-13 15:24:28,189 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:28,189 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:24:28,190 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:24:28,190 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:24:28,190 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:24:28,191 INFO L87 Difference]: Start difference. First operand 1377 states and 2042 transitions. cyclomatic complexity: 666 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:28,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:24:28,233 INFO L93 Difference]: Finished difference Result 1377 states and 2041 transitions. [2024-11-13 15:24:28,233 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2041 transitions. [2024-11-13 15:24:28,243 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2024-11-13 15:24:28,251 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2041 transitions. [2024-11-13 15:24:28,252 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2024-11-13 15:24:28,254 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2024-11-13 15:24:28,254 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2041 transitions. [2024-11-13 15:24:28,257 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:24:28,257 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2041 transitions. [2024-11-13 15:24:28,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2041 transitions. [2024-11-13 15:24:28,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2024-11-13 15:24:28,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4822076978939724) internal successors, (2041), 1376 states have internal predecessors, (2041), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:28,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2041 transitions. [2024-11-13 15:24:28,285 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2041 transitions. [2024-11-13 15:24:28,287 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:24:28,288 INFO L424 stractBuchiCegarLoop]: Abstraction has 1377 states and 2041 transitions. [2024-11-13 15:24:28,288 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 15:24:28,288 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2041 transitions. [2024-11-13 15:24:28,296 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2024-11-13 15:24:28,296 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:24:28,296 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:24:28,300 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:28,300 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:28,300 INFO L745 eck$LassoCheckResult]: Stem: 8719#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 8720#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 9596#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9597#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9659#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 9600#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9560#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9561#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9589#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8656#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8657#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8764#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9009#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8935#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8658#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8319#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8320#L1036 assume !(0 == ~M_E~0); 8417#L1036-2 assume !(0 == ~T1_E~0); 9322#L1041-1 assume !(0 == ~T2_E~0); 9323#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8694#L1051-1 assume !(0 == ~T4_E~0); 8695#L1056-1 assume !(0 == ~T5_E~0); 9451#L1061-1 assume !(0 == ~T6_E~0); 8589#L1066-1 assume !(0 == ~T7_E~0); 8590#L1071-1 assume !(0 == ~T8_E~0); 9433#L1076-1 assume !(0 == ~T9_E~0); 8479#L1081-1 assume !(0 == ~T10_E~0); 8480#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8880#L1091-1 assume !(0 == ~E_1~0); 9607#L1096-1 assume !(0 == ~E_2~0); 9608#L1101-1 assume !(0 == ~E_3~0); 8948#L1106-1 assume !(0 == ~E_4~0); 8949#L1111-1 assume !(0 == ~E_5~0); 9113#L1116-1 assume !(0 == ~E_6~0); 9114#L1121-1 assume !(0 == ~E_7~0); 8939#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 8940#L1131-1 assume !(0 == ~E_9~0); 9215#L1136-1 assume !(0 == ~E_10~0); 9330#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9479#L514 assume 1 == ~m_pc~0; 9444#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8957#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8958#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9531#L1285 assume !(0 != activate_threads_~tmp~1#1); 9643#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8608#L533 assume !(1 == ~t1_pc~0); 8609#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9128#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8372#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8373#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 9351#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9352#L552 assume 1 == ~t2_pc~0; 8828#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8829#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8943#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8944#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 8970#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8971#L571 assume 1 == ~t3_pc~0; 9166#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9167#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8317#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8318#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 9118#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8403#L590 assume !(1 == ~t4_pc~0); 8404#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9176#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8497#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8498#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9378#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9115#L609 assume 1 == ~t5_pc~0; 9116#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9641#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9533#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9534#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 9107#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9108#L628 assume !(1 == ~t6_pc~0); 9040#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9039#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8916#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8917#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 9413#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9414#L647 assume 1 == ~t7_pc~0; 8950#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8951#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9542#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8953#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 8954#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9670#L666 assume !(1 == ~t8_pc~0); 8741#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8742#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8969#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9139#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 8877#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8878#L685 assume 1 == ~t9_pc~0; 9649#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9550#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9003#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8907#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 8908#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9293#L704 assume !(1 == ~t10_pc~0); 8897#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8896#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9157#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8451#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 8452#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8703#L1154 assume !(1 == ~M_E~0); 9401#L1154-2 assume !(1 == ~T1_E~0); 8677#L1159-1 assume !(1 == ~T2_E~0); 8678#L1164-1 assume !(1 == ~T3_E~0); 9137#L1169-1 assume !(1 == ~T4_E~0); 9004#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8806#L1179-1 assume !(1 == ~T6_E~0); 8662#L1184-1 assume !(1 == ~T7_E~0); 8663#L1189-1 assume !(1 == ~T8_E~0); 8739#L1194-1 assume !(1 == ~T9_E~0); 8864#L1199-1 assume !(1 == ~T10_E~0); 8818#L1204-1 assume !(1 == ~E_M~0); 8819#L1209-1 assume !(1 == ~E_1~0); 9372#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9373#L1219-1 assume !(1 == ~E_3~0); 9663#L1224-1 assume !(1 == ~E_4~0); 9161#L1229-1 assume !(1 == ~E_5~0); 8546#L1234-1 assume !(1 == ~E_6~0); 8547#L1239-1 assume !(1 == ~E_7~0); 8604#L1244-1 assume !(1 == ~E_8~0); 8605#L1249-1 assume !(1 == ~E_9~0); 9442#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 8446#L1259-1 assume { :end_inline_reset_delta_events } true; 8447#L1565-2 [2024-11-13 15:24:28,301 INFO L747 eck$LassoCheckResult]: Loop: 8447#L1565-2 assume !false; 9380#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9146#L1011-1 assume !false; 9109#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8882#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8646#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8982#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8669#L866 assume !(0 != eval_~tmp~0#1); 8671#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9178#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9179#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9446#L1036-5 assume !(0 == ~T1_E~0); 9625#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9507#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9508#L1051-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9447#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8691#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8692#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8693#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9627#L1076-3 assume !(0 == ~T9_E~0); 8438#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8439#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8489#L1091-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8490#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9591#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9592#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9624#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9583#L1116-3 assume !(0 == ~E_6~0); 9308#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9309#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9522#L1131-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9523#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9675#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9311#L514-36 assume 1 == ~m_pc~0; 9312#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8855#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8856#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9350#L1285-36 assume !(0 != activate_threads_~tmp~1#1); 8748#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8749#L533-36 assume 1 == ~t1_pc~0; 9029#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9122#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9573#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9388#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9185#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9186#L552-36 assume 1 == ~t2_pc~0; 8743#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8744#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9244#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9515#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8715#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8716#L571-36 assume !(1 == ~t3_pc~0); 9104#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 8807#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8808#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8999#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9506#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8778#L590-36 assume !(1 == ~t4_pc~0); 8779#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 9402#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9196#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9197#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9485#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9486#L609-36 assume 1 == ~t5_pc~0; 9363#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9188#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9189#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9530#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9272#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9079#L628-36 assume !(1 == ~t6_pc~0); 8929#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 8928#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8978#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8979#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9313#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9314#L647-36 assume 1 == ~t7_pc~0; 9237#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8465#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8466#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8483#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8484#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9403#L666-36 assume 1 == ~t8_pc~0; 8674#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8675#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9301#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9302#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8826#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8827#L685-36 assume !(1 == ~t9_pc~0); 8577#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 8578#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9033#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9034#L1357-36 assume !(0 != activate_threads_~tmp___8~0#1); 8966#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8967#L704-36 assume 1 == ~t10_pc~0; 8565#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8566#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8887#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8888#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8593#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8594#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9577#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9460#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9461#L1164-3 assume !(1 == ~T3_E~0); 9638#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8893#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8894#L1179-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9552#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8467#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8468#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8837#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8838#L1204-3 assume !(1 == ~E_M~0); 9158#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8338#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8339#L1219-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9357#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9358#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9379#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8606#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8607#L1244-3 assume !(1 == ~E_8~0); 9212#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9584#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9361#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9362#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8415#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8875#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 8876#L1584 assume !(0 == start_simulation_~tmp~3#1); 9319#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8620#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8315#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8367#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 8368#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8946#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9201#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 9202#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 8447#L1565-2 [2024-11-13 15:24:28,302 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:28,302 INFO L85 PathProgramCache]: Analyzing trace with hash 736734333, now seen corresponding path program 1 times [2024-11-13 15:24:28,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:28,302 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1134065057] [2024-11-13 15:24:28,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:28,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:28,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:28,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:28,394 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:28,394 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1134065057] [2024-11-13 15:24:28,394 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1134065057] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:28,394 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:28,394 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:28,394 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1009251275] [2024-11-13 15:24:28,395 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:28,395 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:24:28,395 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:28,395 INFO L85 PathProgramCache]: Analyzing trace with hash -630740487, now seen corresponding path program 1 times [2024-11-13 15:24:28,395 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:28,396 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2129863187] [2024-11-13 15:24:28,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:28,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:28,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:28,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:28,552 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:28,552 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2129863187] [2024-11-13 15:24:28,552 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2129863187] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:28,552 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:28,552 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:28,552 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1719511898] [2024-11-13 15:24:28,552 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:28,553 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:24:28,553 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:24:28,553 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:24:28,553 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:24:28,553 INFO L87 Difference]: Start difference. First operand 1377 states and 2041 transitions. cyclomatic complexity: 665 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:28,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:24:28,589 INFO L93 Difference]: Finished difference Result 1377 states and 2040 transitions. [2024-11-13 15:24:28,589 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2040 transitions. [2024-11-13 15:24:28,598 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2024-11-13 15:24:28,605 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2040 transitions. [2024-11-13 15:24:28,605 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2024-11-13 15:24:28,606 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2024-11-13 15:24:28,606 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2040 transitions. [2024-11-13 15:24:28,609 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:24:28,609 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2040 transitions. [2024-11-13 15:24:28,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2040 transitions. [2024-11-13 15:24:28,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2024-11-13 15:24:28,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4814814814814814) internal successors, (2040), 1376 states have internal predecessors, (2040), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:28,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2040 transitions. [2024-11-13 15:24:28,639 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2040 transitions. [2024-11-13 15:24:28,639 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:24:28,640 INFO L424 stractBuchiCegarLoop]: Abstraction has 1377 states and 2040 transitions. [2024-11-13 15:24:28,640 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 15:24:28,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2040 transitions. [2024-11-13 15:24:28,648 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2024-11-13 15:24:28,648 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:24:28,651 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:24:28,653 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:28,653 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:28,657 INFO L745 eck$LassoCheckResult]: Stem: 11480#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 11481#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 12357#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12358#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12420#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 12361#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12321#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12322#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12350#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11419#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11420#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11525#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11770#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11696#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11421#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11080#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11081#L1036 assume !(0 == ~M_E~0); 11178#L1036-2 assume !(0 == ~T1_E~0); 12083#L1041-1 assume !(0 == ~T2_E~0); 12084#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11455#L1051-1 assume !(0 == ~T4_E~0); 11456#L1056-1 assume !(0 == ~T5_E~0); 12212#L1061-1 assume !(0 == ~T6_E~0); 11350#L1066-1 assume !(0 == ~T7_E~0); 11351#L1071-1 assume !(0 == ~T8_E~0); 12194#L1076-1 assume !(0 == ~T9_E~0); 11240#L1081-1 assume !(0 == ~T10_E~0); 11241#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 11641#L1091-1 assume !(0 == ~E_1~0); 12369#L1096-1 assume !(0 == ~E_2~0); 12370#L1101-1 assume !(0 == ~E_3~0); 11709#L1106-1 assume !(0 == ~E_4~0); 11710#L1111-1 assume !(0 == ~E_5~0); 11874#L1116-1 assume !(0 == ~E_6~0); 11875#L1121-1 assume !(0 == ~E_7~0); 11700#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 11701#L1131-1 assume !(0 == ~E_9~0); 11976#L1136-1 assume !(0 == ~E_10~0); 12091#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12240#L514 assume 1 == ~m_pc~0; 12205#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11718#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11719#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12293#L1285 assume !(0 != activate_threads_~tmp~1#1); 12405#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11369#L533 assume !(1 == ~t1_pc~0); 11370#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11889#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11135#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11136#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 12112#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12113#L552 assume 1 == ~t2_pc~0; 11590#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11591#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11704#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11705#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 11736#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11737#L571 assume 1 == ~t3_pc~0; 11929#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11930#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11078#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11079#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 11879#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11164#L590 assume !(1 == ~t4_pc~0); 11165#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11938#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11258#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11259#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12140#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11876#L609 assume 1 == ~t5_pc~0; 11877#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12402#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12294#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12295#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 11868#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11869#L628 assume !(1 == ~t6_pc~0); 11801#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11800#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11678#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11679#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 12174#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12175#L647 assume 1 == ~t7_pc~0; 11711#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11712#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12303#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11716#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 11717#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12431#L666 assume !(1 == ~t8_pc~0); 11502#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11503#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11730#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11901#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 11639#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11640#L685 assume 1 == ~t9_pc~0; 12410#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12311#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11764#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11668#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 11669#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12054#L704 assume !(1 == ~t10_pc~0); 11658#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11657#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11919#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11212#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 11213#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11464#L1154 assume !(1 == ~M_E~0); 12162#L1154-2 assume !(1 == ~T1_E~0); 11438#L1159-1 assume !(1 == ~T2_E~0); 11439#L1164-1 assume !(1 == ~T3_E~0); 11898#L1169-1 assume !(1 == ~T4_E~0); 11765#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11569#L1179-1 assume !(1 == ~T6_E~0); 11423#L1184-1 assume !(1 == ~T7_E~0); 11424#L1189-1 assume !(1 == ~T8_E~0); 11500#L1194-1 assume !(1 == ~T9_E~0); 11627#L1199-1 assume !(1 == ~T10_E~0); 11581#L1204-1 assume !(1 == ~E_M~0); 11582#L1209-1 assume !(1 == ~E_1~0); 12135#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 12136#L1219-1 assume !(1 == ~E_3~0); 12424#L1224-1 assume !(1 == ~E_4~0); 11923#L1229-1 assume !(1 == ~E_5~0); 11307#L1234-1 assume !(1 == ~E_6~0); 11308#L1239-1 assume !(1 == ~E_7~0); 11365#L1244-1 assume !(1 == ~E_8~0); 11366#L1249-1 assume !(1 == ~E_9~0); 12203#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 11207#L1259-1 assume { :end_inline_reset_delta_events } true; 11208#L1565-2 [2024-11-13 15:24:28,657 INFO L747 eck$LassoCheckResult]: Loop: 11208#L1565-2 assume !false; 12141#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11907#L1011-1 assume !false; 11870#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11646#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11407#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11743#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11435#L866 assume !(0 != eval_~tmp~0#1); 11437#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11940#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11941#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12207#L1036-5 assume !(0 == ~T1_E~0); 12386#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12268#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12269#L1051-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12208#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11452#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11453#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11454#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12388#L1076-3 assume !(0 == ~T9_E~0); 11199#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11200#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11254#L1091-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11255#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12352#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12353#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12385#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12344#L1116-3 assume !(0 == ~E_6~0); 12069#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12070#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12283#L1131-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12284#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12436#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12072#L514-36 assume !(1 == ~m_pc~0); 11781#L514-38 is_master_triggered_~__retres1~0#1 := 0; 11616#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11617#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12111#L1285-36 assume !(0 != activate_threads_~tmp~1#1); 11509#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11510#L533-36 assume 1 == ~t1_pc~0; 11789#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11883#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12334#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12149#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11946#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11947#L552-36 assume 1 == ~t2_pc~0; 11504#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11505#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12005#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12276#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11476#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11477#L571-36 assume 1 == ~t3_pc~0; 11864#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11567#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11568#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11760#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12267#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11539#L590-36 assume !(1 == ~t4_pc~0); 11540#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 12163#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11956#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11957#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12246#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12247#L609-36 assume 1 == ~t5_pc~0; 12124#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11949#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11950#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12291#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12033#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11840#L628-36 assume 1 == ~t6_pc~0; 11688#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11689#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11739#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11740#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12074#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12075#L647-36 assume 1 == ~t7_pc~0; 11998#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11226#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11227#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11244#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11245#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12164#L666-36 assume 1 == ~t8_pc~0; 11432#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11433#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12062#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12063#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11587#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11588#L685-36 assume 1 == ~t9_pc~0; 12049#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11339#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11794#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11795#L1357-36 assume !(0 != activate_threads_~tmp___8~0#1); 11727#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11728#L704-36 assume !(1 == ~t10_pc~0); 11328#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 11327#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11648#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11649#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11354#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11355#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12338#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12221#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12222#L1164-3 assume !(1 == ~T3_E~0); 12399#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11654#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11655#L1179-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12313#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11228#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11229#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11598#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11599#L1204-3 assume !(1 == ~E_M~0); 11918#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11096#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11097#L1219-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12118#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12119#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12139#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11367#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11368#L1244-3 assume !(1 == ~E_8~0); 11969#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12345#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12122#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 12123#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11176#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11636#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 11637#L1584 assume !(0 == start_simulation_~tmp~3#1); 12080#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11381#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11076#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11128#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 11129#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11707#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11962#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 11963#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 11208#L1565-2 [2024-11-13 15:24:28,658 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:28,658 INFO L85 PathProgramCache]: Analyzing trace with hash 1829369535, now seen corresponding path program 1 times [2024-11-13 15:24:28,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:28,658 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [863656808] [2024-11-13 15:24:28,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:28,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:28,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:28,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:28,741 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:28,741 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [863656808] [2024-11-13 15:24:28,741 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [863656808] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:28,741 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:28,741 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:28,742 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [873546296] [2024-11-13 15:24:28,742 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:28,742 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:24:28,742 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:28,742 INFO L85 PathProgramCache]: Analyzing trace with hash 770040120, now seen corresponding path program 1 times [2024-11-13 15:24:28,742 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:28,743 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1249882736] [2024-11-13 15:24:28,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:28,743 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:28,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:28,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:28,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:28,870 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1249882736] [2024-11-13 15:24:28,870 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1249882736] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:28,871 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:28,871 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:28,871 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1727355931] [2024-11-13 15:24:28,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:28,871 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:24:28,871 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:24:28,872 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:24:28,872 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:24:28,872 INFO L87 Difference]: Start difference. First operand 1377 states and 2040 transitions. cyclomatic complexity: 664 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:28,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:24:28,909 INFO L93 Difference]: Finished difference Result 1377 states and 2039 transitions. [2024-11-13 15:24:28,909 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2039 transitions. [2024-11-13 15:24:28,918 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2024-11-13 15:24:28,926 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2039 transitions. [2024-11-13 15:24:28,926 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2024-11-13 15:24:28,927 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2024-11-13 15:24:28,928 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2039 transitions. [2024-11-13 15:24:28,930 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:24:28,930 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2039 transitions. [2024-11-13 15:24:28,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2039 transitions. [2024-11-13 15:24:28,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2024-11-13 15:24:28,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4807552650689906) internal successors, (2039), 1376 states have internal predecessors, (2039), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:28,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2039 transitions. [2024-11-13 15:24:28,961 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2039 transitions. [2024-11-13 15:24:28,962 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:24:28,962 INFO L424 stractBuchiCegarLoop]: Abstraction has 1377 states and 2039 transitions. [2024-11-13 15:24:28,962 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 15:24:28,962 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2039 transitions. [2024-11-13 15:24:28,971 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2024-11-13 15:24:28,971 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:24:28,971 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:24:28,974 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:28,975 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:28,976 INFO L745 eck$LassoCheckResult]: Stem: 14241#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 14242#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 15118#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15119#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15181#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 15122#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15082#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15083#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15111#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14178#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14179#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14286#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14531#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14457#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14180#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13841#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13842#L1036 assume !(0 == ~M_E~0); 13939#L1036-2 assume !(0 == ~T1_E~0); 14844#L1041-1 assume !(0 == ~T2_E~0); 14845#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14216#L1051-1 assume !(0 == ~T4_E~0); 14217#L1056-1 assume !(0 == ~T5_E~0); 14973#L1061-1 assume !(0 == ~T6_E~0); 14111#L1066-1 assume !(0 == ~T7_E~0); 14112#L1071-1 assume !(0 == ~T8_E~0); 14955#L1076-1 assume !(0 == ~T9_E~0); 14001#L1081-1 assume !(0 == ~T10_E~0); 14002#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 14402#L1091-1 assume !(0 == ~E_1~0); 15129#L1096-1 assume !(0 == ~E_2~0); 15130#L1101-1 assume !(0 == ~E_3~0); 14470#L1106-1 assume !(0 == ~E_4~0); 14471#L1111-1 assume !(0 == ~E_5~0); 14635#L1116-1 assume !(0 == ~E_6~0); 14636#L1121-1 assume !(0 == ~E_7~0); 14461#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 14462#L1131-1 assume !(0 == ~E_9~0); 14737#L1136-1 assume !(0 == ~E_10~0); 14852#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15001#L514 assume 1 == ~m_pc~0; 14966#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14479#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14480#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15053#L1285 assume !(0 != activate_threads_~tmp~1#1); 15165#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14130#L533 assume !(1 == ~t1_pc~0); 14131#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14650#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13894#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13895#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 14873#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14874#L552 assume 1 == ~t2_pc~0; 14350#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14351#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14465#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14466#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 14492#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14493#L571 assume 1 == ~t3_pc~0; 14688#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14689#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13839#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13840#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 14640#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13925#L590 assume !(1 == ~t4_pc~0); 13926#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14698#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14019#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14020#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14900#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14637#L609 assume 1 == ~t5_pc~0; 14638#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15163#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15055#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15056#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 14629#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14630#L628 assume !(1 == ~t6_pc~0); 14562#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14561#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14438#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14439#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 14935#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14936#L647 assume 1 == ~t7_pc~0; 14472#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14473#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15064#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14475#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 14476#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15192#L666 assume !(1 == ~t8_pc~0); 14263#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14264#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14491#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14661#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 14399#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14400#L685 assume 1 == ~t9_pc~0; 15171#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15072#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14525#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14429#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 14430#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14815#L704 assume !(1 == ~t10_pc~0); 14419#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14418#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14679#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13973#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 13974#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14225#L1154 assume !(1 == ~M_E~0); 14923#L1154-2 assume !(1 == ~T1_E~0); 14199#L1159-1 assume !(1 == ~T2_E~0); 14200#L1164-1 assume !(1 == ~T3_E~0); 14659#L1169-1 assume !(1 == ~T4_E~0); 14526#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14328#L1179-1 assume !(1 == ~T6_E~0); 14184#L1184-1 assume !(1 == ~T7_E~0); 14185#L1189-1 assume !(1 == ~T8_E~0); 14261#L1194-1 assume !(1 == ~T9_E~0); 14386#L1199-1 assume !(1 == ~T10_E~0); 14340#L1204-1 assume !(1 == ~E_M~0); 14341#L1209-1 assume !(1 == ~E_1~0); 14894#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 14895#L1219-1 assume !(1 == ~E_3~0); 15185#L1224-1 assume !(1 == ~E_4~0); 14683#L1229-1 assume !(1 == ~E_5~0); 14068#L1234-1 assume !(1 == ~E_6~0); 14069#L1239-1 assume !(1 == ~E_7~0); 14126#L1244-1 assume !(1 == ~E_8~0); 14127#L1249-1 assume !(1 == ~E_9~0); 14964#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 13968#L1259-1 assume { :end_inline_reset_delta_events } true; 13969#L1565-2 [2024-11-13 15:24:28,977 INFO L747 eck$LassoCheckResult]: Loop: 13969#L1565-2 assume !false; 14902#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14667#L1011-1 assume !false; 14631#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14404#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 14168#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14504#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14191#L866 assume !(0 != eval_~tmp~0#1); 14193#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14700#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14701#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14968#L1036-5 assume !(0 == ~T1_E~0); 15147#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15029#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15030#L1051-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14969#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14213#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14214#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14215#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15149#L1076-3 assume !(0 == ~T9_E~0); 13960#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13961#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14011#L1091-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14012#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15113#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15114#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15146#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15105#L1116-3 assume !(0 == ~E_6~0); 14830#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14831#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15044#L1131-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15045#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15197#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14833#L514-36 assume 1 == ~m_pc~0; 14834#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14377#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14378#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14872#L1285-36 assume !(0 != activate_threads_~tmp~1#1); 14270#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14271#L533-36 assume 1 == ~t1_pc~0; 14551#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14644#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15095#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14910#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14707#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14708#L552-36 assume 1 == ~t2_pc~0; 14265#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14266#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14766#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15037#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14237#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14238#L571-36 assume 1 == ~t3_pc~0; 14625#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14329#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14330#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14521#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15028#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14300#L590-36 assume !(1 == ~t4_pc~0); 14301#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 14924#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14717#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14718#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15007#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15008#L609-36 assume 1 == ~t5_pc~0; 14885#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14710#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14711#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15052#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14794#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14601#L628-36 assume 1 == ~t6_pc~0; 14449#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14450#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14500#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14501#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14835#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14836#L647-36 assume 1 == ~t7_pc~0; 14759#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13987#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13988#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14005#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14006#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14925#L666-36 assume 1 == ~t8_pc~0; 14196#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14197#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14823#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14824#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14348#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14349#L685-36 assume !(1 == ~t9_pc~0); 14099#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 14100#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14555#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14556#L1357-36 assume !(0 != activate_threads_~tmp___8~0#1); 14488#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14489#L704-36 assume 1 == ~t10_pc~0; 14087#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14088#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14409#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14410#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14115#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14116#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15099#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14982#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14983#L1164-3 assume !(1 == ~T3_E~0); 15160#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14415#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14416#L1179-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15074#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13989#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13990#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14359#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14360#L1204-3 assume !(1 == ~E_M~0); 14680#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13857#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13858#L1219-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14879#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14880#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14901#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14128#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14129#L1244-3 assume !(1 == ~E_8~0); 14734#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15106#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 14883#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14884#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13937#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14397#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 14398#L1584 assume !(0 == start_simulation_~tmp~3#1); 14841#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14142#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13837#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13889#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 13890#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14468#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14723#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 14724#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 13969#L1565-2 [2024-11-13 15:24:28,978 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:28,978 INFO L85 PathProgramCache]: Analyzing trace with hash -1183425475, now seen corresponding path program 1 times [2024-11-13 15:24:28,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:28,978 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733985630] [2024-11-13 15:24:28,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:28,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:28,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:29,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:29,049 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:29,049 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1733985630] [2024-11-13 15:24:29,050 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1733985630] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:29,050 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:29,050 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:29,050 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [170322187] [2024-11-13 15:24:29,052 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:29,053 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:24:29,053 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:29,053 INFO L85 PathProgramCache]: Analyzing trace with hash 391764407, now seen corresponding path program 1 times [2024-11-13 15:24:29,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:29,054 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1367089403] [2024-11-13 15:24:29,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:29,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:29,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:29,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:29,157 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:29,157 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1367089403] [2024-11-13 15:24:29,157 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1367089403] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:29,157 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:29,158 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:29,158 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [397691367] [2024-11-13 15:24:29,158 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:29,158 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:24:29,158 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:24:29,159 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:24:29,159 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:24:29,159 INFO L87 Difference]: Start difference. First operand 1377 states and 2039 transitions. cyclomatic complexity: 663 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:29,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:24:29,202 INFO L93 Difference]: Finished difference Result 1377 states and 2038 transitions. [2024-11-13 15:24:29,202 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2038 transitions. [2024-11-13 15:24:29,215 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2024-11-13 15:24:29,223 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2038 transitions. [2024-11-13 15:24:29,224 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2024-11-13 15:24:29,226 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2024-11-13 15:24:29,226 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2038 transitions. [2024-11-13 15:24:29,229 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:24:29,229 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2038 transitions. [2024-11-13 15:24:29,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2038 transitions. [2024-11-13 15:24:29,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2024-11-13 15:24:29,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4800290486564995) internal successors, (2038), 1376 states have internal predecessors, (2038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:29,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2038 transitions. [2024-11-13 15:24:29,263 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2038 transitions. [2024-11-13 15:24:29,265 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:24:29,265 INFO L424 stractBuchiCegarLoop]: Abstraction has 1377 states and 2038 transitions. [2024-11-13 15:24:29,265 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 15:24:29,266 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2038 transitions. [2024-11-13 15:24:29,276 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2024-11-13 15:24:29,276 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:24:29,276 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:24:29,278 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:29,278 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:29,279 INFO L745 eck$LassoCheckResult]: Stem: 17002#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 17003#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 17879#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17880#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17942#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 17883#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17843#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17844#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17872#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16939#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16940#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17047#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17292#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17218#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16941#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16602#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16603#L1036 assume !(0 == ~M_E~0); 16700#L1036-2 assume !(0 == ~T1_E~0); 17605#L1041-1 assume !(0 == ~T2_E~0); 17606#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16977#L1051-1 assume !(0 == ~T4_E~0); 16978#L1056-1 assume !(0 == ~T5_E~0); 17734#L1061-1 assume !(0 == ~T6_E~0); 16872#L1066-1 assume !(0 == ~T7_E~0); 16873#L1071-1 assume !(0 == ~T8_E~0); 17716#L1076-1 assume !(0 == ~T9_E~0); 16762#L1081-1 assume !(0 == ~T10_E~0); 16763#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 17163#L1091-1 assume !(0 == ~E_1~0); 17890#L1096-1 assume !(0 == ~E_2~0); 17891#L1101-1 assume !(0 == ~E_3~0); 17231#L1106-1 assume !(0 == ~E_4~0); 17232#L1111-1 assume !(0 == ~E_5~0); 17396#L1116-1 assume !(0 == ~E_6~0); 17397#L1121-1 assume !(0 == ~E_7~0); 17222#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 17223#L1131-1 assume !(0 == ~E_9~0); 17498#L1136-1 assume !(0 == ~E_10~0); 17613#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17762#L514 assume 1 == ~m_pc~0; 17727#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17240#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17241#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17814#L1285 assume !(0 != activate_threads_~tmp~1#1); 17926#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16891#L533 assume !(1 == ~t1_pc~0); 16892#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17411#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16655#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16656#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 17634#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17635#L552 assume 1 == ~t2_pc~0; 17111#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17112#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17226#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17227#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 17253#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17254#L571 assume 1 == ~t3_pc~0; 17449#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17450#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16600#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16601#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 17401#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16686#L590 assume !(1 == ~t4_pc~0); 16687#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17459#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16780#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16781#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17662#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17398#L609 assume 1 == ~t5_pc~0; 17399#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17924#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17816#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17817#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 17390#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17391#L628 assume !(1 == ~t6_pc~0); 17323#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17322#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17199#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17200#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 17696#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17697#L647 assume 1 == ~t7_pc~0; 17233#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17234#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17825#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17236#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 17237#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17953#L666 assume !(1 == ~t8_pc~0); 17024#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17025#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17252#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17422#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 17160#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17161#L685 assume 1 == ~t9_pc~0; 17932#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17833#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17286#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17190#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 17191#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17576#L704 assume !(1 == ~t10_pc~0); 17180#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17179#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17441#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16734#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 16735#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16986#L1154 assume !(1 == ~M_E~0); 17684#L1154-2 assume !(1 == ~T1_E~0); 16960#L1159-1 assume !(1 == ~T2_E~0); 16961#L1164-1 assume !(1 == ~T3_E~0); 17420#L1169-1 assume !(1 == ~T4_E~0); 17287#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17089#L1179-1 assume !(1 == ~T6_E~0); 16945#L1184-1 assume !(1 == ~T7_E~0); 16946#L1189-1 assume !(1 == ~T8_E~0); 17022#L1194-1 assume !(1 == ~T9_E~0); 17147#L1199-1 assume !(1 == ~T10_E~0); 17101#L1204-1 assume !(1 == ~E_M~0); 17102#L1209-1 assume !(1 == ~E_1~0); 17655#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 17656#L1219-1 assume !(1 == ~E_3~0); 17946#L1224-1 assume !(1 == ~E_4~0); 17444#L1229-1 assume !(1 == ~E_5~0); 16829#L1234-1 assume !(1 == ~E_6~0); 16830#L1239-1 assume !(1 == ~E_7~0); 16887#L1244-1 assume !(1 == ~E_8~0); 16888#L1249-1 assume !(1 == ~E_9~0); 17725#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 16729#L1259-1 assume { :end_inline_reset_delta_events } true; 16730#L1565-2 [2024-11-13 15:24:29,280 INFO L747 eck$LassoCheckResult]: Loop: 16730#L1565-2 assume !false; 17663#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17429#L1011-1 assume !false; 17392#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17165#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16929#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17265#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16952#L866 assume !(0 != eval_~tmp~0#1); 16954#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17461#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17462#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17729#L1036-5 assume !(0 == ~T1_E~0); 17908#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17790#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17791#L1051-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17730#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16974#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16975#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16976#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17910#L1076-3 assume !(0 == ~T9_E~0); 16721#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16722#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16772#L1091-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16773#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17874#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17875#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17907#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17866#L1116-3 assume !(0 == ~E_6~0); 17591#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17592#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17805#L1131-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17806#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17958#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17594#L514-36 assume !(1 == ~m_pc~0); 17303#L514-38 is_master_triggered_~__retres1~0#1 := 0; 17138#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17139#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17633#L1285-36 assume !(0 != activate_threads_~tmp~1#1); 17031#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17032#L533-36 assume 1 == ~t1_pc~0; 17312#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17405#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17856#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17671#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17468#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17469#L552-36 assume 1 == ~t2_pc~0; 17026#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17027#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17527#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17798#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16998#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16999#L571-36 assume 1 == ~t3_pc~0; 17386#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17090#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17091#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17282#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17789#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17061#L590-36 assume !(1 == ~t4_pc~0); 17062#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 17685#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17479#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17480#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17768#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17769#L609-36 assume 1 == ~t5_pc~0; 17646#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17471#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17472#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17813#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17555#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17362#L628-36 assume 1 == ~t6_pc~0; 17210#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17211#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17261#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17262#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17596#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17597#L647-36 assume 1 == ~t7_pc~0; 17520#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16750#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16751#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16766#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16767#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17686#L666-36 assume 1 == ~t8_pc~0; 16957#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16958#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17584#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17585#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17109#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17110#L685-36 assume 1 == ~t9_pc~0; 17570#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16859#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17315#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17316#L1357-36 assume !(0 != activate_threads_~tmp___8~0#1); 17249#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17250#L704-36 assume 1 == ~t10_pc~0; 16848#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16849#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17170#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17171#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16874#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16875#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17860#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17743#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17744#L1164-3 assume !(1 == ~T3_E~0); 17921#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17176#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17177#L1179-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17835#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16748#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16749#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17120#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17121#L1204-3 assume !(1 == ~E_M~0); 17440#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16618#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16619#L1219-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17640#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17641#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17661#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16889#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16890#L1244-3 assume !(1 == ~E_8~0); 17491#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17867#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17644#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17645#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16698#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17158#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 17159#L1584 assume !(0 == start_simulation_~tmp~3#1); 17602#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16903#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16598#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16650#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 16651#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17228#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17484#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 17485#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 16730#L1565-2 [2024-11-13 15:24:29,281 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:29,282 INFO L85 PathProgramCache]: Analyzing trace with hash 659050239, now seen corresponding path program 1 times [2024-11-13 15:24:29,282 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:29,282 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [301657360] [2024-11-13 15:24:29,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:29,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:29,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:29,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:29,345 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:29,345 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [301657360] [2024-11-13 15:24:29,345 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [301657360] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:29,345 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:29,345 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:29,345 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [559784741] [2024-11-13 15:24:29,345 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:29,346 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:24:29,346 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:29,346 INFO L85 PathProgramCache]: Analyzing trace with hash 1255214839, now seen corresponding path program 2 times [2024-11-13 15:24:29,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:29,347 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317504098] [2024-11-13 15:24:29,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:29,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:29,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:29,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:29,458 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:29,459 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1317504098] [2024-11-13 15:24:29,459 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1317504098] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:29,459 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:29,459 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:29,459 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [721275300] [2024-11-13 15:24:29,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:29,459 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:24:29,459 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:24:29,460 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:24:29,460 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:24:29,460 INFO L87 Difference]: Start difference. First operand 1377 states and 2038 transitions. cyclomatic complexity: 662 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:29,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:24:29,499 INFO L93 Difference]: Finished difference Result 1377 states and 2037 transitions. [2024-11-13 15:24:29,499 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2037 transitions. [2024-11-13 15:24:29,511 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2024-11-13 15:24:29,518 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2037 transitions. [2024-11-13 15:24:29,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2024-11-13 15:24:29,520 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2024-11-13 15:24:29,521 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2037 transitions. [2024-11-13 15:24:29,523 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:24:29,523 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2037 transitions. [2024-11-13 15:24:29,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2037 transitions. [2024-11-13 15:24:29,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2024-11-13 15:24:29,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4793028322440087) internal successors, (2037), 1376 states have internal predecessors, (2037), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:29,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2037 transitions. [2024-11-13 15:24:29,554 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2037 transitions. [2024-11-13 15:24:29,554 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:24:29,556 INFO L424 stractBuchiCegarLoop]: Abstraction has 1377 states and 2037 transitions. [2024-11-13 15:24:29,557 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 15:24:29,557 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2037 transitions. [2024-11-13 15:24:29,564 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2024-11-13 15:24:29,564 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:24:29,564 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:24:29,566 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:29,566 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:29,567 INFO L745 eck$LassoCheckResult]: Stem: 19763#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 19764#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 20640#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20641#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20703#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 20644#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20604#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20605#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20633#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19702#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19703#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19808#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20053#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19979#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19704#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19363#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19364#L1036 assume !(0 == ~M_E~0); 19461#L1036-2 assume !(0 == ~T1_E~0); 20366#L1041-1 assume !(0 == ~T2_E~0); 20367#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19738#L1051-1 assume !(0 == ~T4_E~0); 19739#L1056-1 assume !(0 == ~T5_E~0); 20495#L1061-1 assume !(0 == ~T6_E~0); 19633#L1066-1 assume !(0 == ~T7_E~0); 19634#L1071-1 assume !(0 == ~T8_E~0); 20477#L1076-1 assume !(0 == ~T9_E~0); 19523#L1081-1 assume !(0 == ~T10_E~0); 19524#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 19924#L1091-1 assume !(0 == ~E_1~0); 20652#L1096-1 assume !(0 == ~E_2~0); 20653#L1101-1 assume !(0 == ~E_3~0); 19992#L1106-1 assume !(0 == ~E_4~0); 19993#L1111-1 assume !(0 == ~E_5~0); 20157#L1116-1 assume !(0 == ~E_6~0); 20158#L1121-1 assume !(0 == ~E_7~0); 19983#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 19984#L1131-1 assume !(0 == ~E_9~0); 20259#L1136-1 assume !(0 == ~E_10~0); 20374#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20523#L514 assume 1 == ~m_pc~0; 20488#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20001#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20002#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20576#L1285 assume !(0 != activate_threads_~tmp~1#1); 20688#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19655#L533 assume !(1 == ~t1_pc~0); 19656#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20172#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19418#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19419#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 20395#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20396#L552 assume 1 == ~t2_pc~0; 19873#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19874#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19987#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19988#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 20019#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20020#L571 assume 1 == ~t3_pc~0; 20212#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20213#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19361#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19362#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 20162#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19447#L590 assume !(1 == ~t4_pc~0); 19448#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20221#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19541#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19542#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20423#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20159#L609 assume 1 == ~t5_pc~0; 20160#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20685#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20577#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20578#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 20151#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20152#L628 assume !(1 == ~t6_pc~0); 20084#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 20083#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19963#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19964#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 20457#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20458#L647 assume 1 == ~t7_pc~0; 19994#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19995#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20586#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19999#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 20000#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20714#L666 assume !(1 == ~t8_pc~0); 19785#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19786#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20013#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20184#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 19922#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19923#L685 assume 1 == ~t9_pc~0; 20693#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20594#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20047#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19951#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 19952#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20337#L704 assume !(1 == ~t10_pc~0); 19941#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19940#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20202#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19495#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 19496#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19747#L1154 assume !(1 == ~M_E~0); 20445#L1154-2 assume !(1 == ~T1_E~0); 19721#L1159-1 assume !(1 == ~T2_E~0); 19722#L1164-1 assume !(1 == ~T3_E~0); 20181#L1169-1 assume !(1 == ~T4_E~0); 20048#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19852#L1179-1 assume !(1 == ~T6_E~0); 19706#L1184-1 assume !(1 == ~T7_E~0); 19707#L1189-1 assume !(1 == ~T8_E~0); 19783#L1194-1 assume !(1 == ~T9_E~0); 19910#L1199-1 assume !(1 == ~T10_E~0); 19864#L1204-1 assume !(1 == ~E_M~0); 19865#L1209-1 assume !(1 == ~E_1~0); 20418#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 20419#L1219-1 assume !(1 == ~E_3~0); 20707#L1224-1 assume !(1 == ~E_4~0); 20206#L1229-1 assume !(1 == ~E_5~0); 19590#L1234-1 assume !(1 == ~E_6~0); 19591#L1239-1 assume !(1 == ~E_7~0); 19648#L1244-1 assume !(1 == ~E_8~0); 19649#L1249-1 assume !(1 == ~E_9~0); 20486#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 19490#L1259-1 assume { :end_inline_reset_delta_events } true; 19491#L1565-2 [2024-11-13 15:24:29,567 INFO L747 eck$LassoCheckResult]: Loop: 19491#L1565-2 assume !false; 20424#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20190#L1011-1 assume !false; 20153#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19929#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19690#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 20026#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19718#L866 assume !(0 != eval_~tmp~0#1); 19720#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20223#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20224#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20490#L1036-5 assume !(0 == ~T1_E~0); 20670#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20551#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20552#L1051-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20491#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19735#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19736#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19737#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20671#L1076-3 assume !(0 == ~T9_E~0); 19482#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19483#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19537#L1091-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19538#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20635#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20636#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20668#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20627#L1116-3 assume !(0 == ~E_6~0); 20352#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20353#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20566#L1131-3 assume 0 == ~E_9~0;~E_9~0 := 1; 20567#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20719#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20354#L514-36 assume 1 == ~m_pc~0; 20355#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19899#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19900#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20394#L1285-36 assume !(0 != activate_threads_~tmp~1#1); 19792#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19793#L533-36 assume 1 == ~t1_pc~0; 20072#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20166#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20617#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20432#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20229#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20230#L552-36 assume 1 == ~t2_pc~0; 19787#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19788#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20288#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20559#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19759#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19760#L571-36 assume 1 == ~t3_pc~0; 20147#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19850#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19851#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20043#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20550#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19822#L590-36 assume 1 == ~t4_pc~0; 19824#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20446#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20239#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20240#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20529#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20530#L609-36 assume 1 == ~t5_pc~0; 20407#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20232#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20233#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20574#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20316#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20123#L628-36 assume 1 == ~t6_pc~0; 19971#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19972#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20022#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20023#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20357#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20358#L647-36 assume 1 == ~t7_pc~0; 20281#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19509#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19510#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19527#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19528#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20447#L666-36 assume 1 == ~t8_pc~0; 19715#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19716#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20345#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20346#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19870#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19871#L685-36 assume !(1 == ~t9_pc~0); 19621#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 19622#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20077#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20078#L1357-36 assume !(0 != activate_threads_~tmp___8~0#1); 20010#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20011#L704-36 assume 1 == ~t10_pc~0; 19609#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19610#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19931#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19932#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19637#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19638#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20621#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20504#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20505#L1164-3 assume !(1 == ~T3_E~0); 20682#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19937#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19938#L1179-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20596#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19511#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19512#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19881#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19882#L1204-3 assume !(1 == ~E_M~0); 20201#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19379#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19380#L1219-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20401#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20402#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20422#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19650#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19651#L1244-3 assume !(1 == ~E_8~0); 20252#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20628#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20405#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 20406#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19459#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19919#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 19920#L1584 assume !(0 == start_simulation_~tmp~3#1); 20363#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19664#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19359#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19411#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 19412#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19990#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20245#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 20246#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 19491#L1565-2 [2024-11-13 15:24:29,570 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:29,570 INFO L85 PathProgramCache]: Analyzing trace with hash -1913914371, now seen corresponding path program 1 times [2024-11-13 15:24:29,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:29,571 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [215651772] [2024-11-13 15:24:29,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:29,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:29,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:29,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:29,642 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:29,642 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [215651772] [2024-11-13 15:24:29,643 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [215651772] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:29,643 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:29,643 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:29,643 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [452736844] [2024-11-13 15:24:29,643 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:29,643 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:24:29,644 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:29,644 INFO L85 PathProgramCache]: Analyzing trace with hash -2060889098, now seen corresponding path program 1 times [2024-11-13 15:24:29,644 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:29,644 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [141852684] [2024-11-13 15:24:29,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:29,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:29,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:29,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:29,755 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:29,756 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [141852684] [2024-11-13 15:24:29,756 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [141852684] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:29,756 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:29,756 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:29,756 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1567333399] [2024-11-13 15:24:29,758 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:29,759 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:24:29,759 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:24:29,759 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:24:29,759 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:24:29,759 INFO L87 Difference]: Start difference. First operand 1377 states and 2037 transitions. cyclomatic complexity: 661 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:29,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:24:29,798 INFO L93 Difference]: Finished difference Result 1377 states and 2036 transitions. [2024-11-13 15:24:29,798 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2036 transitions. [2024-11-13 15:24:29,808 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2024-11-13 15:24:29,817 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2036 transitions. [2024-11-13 15:24:29,817 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2024-11-13 15:24:29,819 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2024-11-13 15:24:29,819 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2036 transitions. [2024-11-13 15:24:29,822 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:24:29,822 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2036 transitions. [2024-11-13 15:24:29,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2036 transitions. [2024-11-13 15:24:29,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2024-11-13 15:24:29,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.478576615831518) internal successors, (2036), 1376 states have internal predecessors, (2036), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:29,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2036 transitions. [2024-11-13 15:24:29,854 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2036 transitions. [2024-11-13 15:24:29,854 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:24:29,855 INFO L424 stractBuchiCegarLoop]: Abstraction has 1377 states and 2036 transitions. [2024-11-13 15:24:29,856 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 15:24:29,857 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2036 transitions. [2024-11-13 15:24:29,864 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2024-11-13 15:24:29,864 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:24:29,864 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:24:29,867 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:29,867 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:29,867 INFO L745 eck$LassoCheckResult]: Stem: 22524#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 22525#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 23401#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23402#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23464#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 23405#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23365#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23366#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23394#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22461#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22462#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22569#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22814#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22740#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22463#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22124#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22125#L1036 assume !(0 == ~M_E~0); 22222#L1036-2 assume !(0 == ~T1_E~0); 23127#L1041-1 assume !(0 == ~T2_E~0); 23128#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22499#L1051-1 assume !(0 == ~T4_E~0); 22500#L1056-1 assume !(0 == ~T5_E~0); 23256#L1061-1 assume !(0 == ~T6_E~0); 22394#L1066-1 assume !(0 == ~T7_E~0); 22395#L1071-1 assume !(0 == ~T8_E~0); 23238#L1076-1 assume !(0 == ~T9_E~0); 22284#L1081-1 assume !(0 == ~T10_E~0); 22285#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 22685#L1091-1 assume !(0 == ~E_1~0); 23412#L1096-1 assume !(0 == ~E_2~0); 23413#L1101-1 assume !(0 == ~E_3~0); 22753#L1106-1 assume !(0 == ~E_4~0); 22754#L1111-1 assume !(0 == ~E_5~0); 22918#L1116-1 assume !(0 == ~E_6~0); 22919#L1121-1 assume !(0 == ~E_7~0); 22744#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 22745#L1131-1 assume !(0 == ~E_9~0); 23020#L1136-1 assume !(0 == ~E_10~0); 23135#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23284#L514 assume 1 == ~m_pc~0; 23249#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22762#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22763#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23336#L1285 assume !(0 != activate_threads_~tmp~1#1); 23448#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22413#L533 assume !(1 == ~t1_pc~0); 22414#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22933#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22177#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22178#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 23156#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23157#L552 assume 1 == ~t2_pc~0; 22633#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22634#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22748#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22749#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 22775#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22776#L571 assume 1 == ~t3_pc~0; 22971#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22972#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22122#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22123#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 22923#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22208#L590 assume !(1 == ~t4_pc~0); 22209#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22981#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22302#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22303#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23183#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22920#L609 assume 1 == ~t5_pc~0; 22921#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23446#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23338#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23339#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 22912#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22913#L628 assume !(1 == ~t6_pc~0); 22845#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22844#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22721#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22722#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 23218#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23219#L647 assume 1 == ~t7_pc~0; 22755#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22756#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23347#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22758#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 22759#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23475#L666 assume !(1 == ~t8_pc~0); 22546#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22547#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22774#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22944#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 22682#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22683#L685 assume 1 == ~t9_pc~0; 23454#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23355#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22808#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22712#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 22713#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23098#L704 assume !(1 == ~t10_pc~0); 22702#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22701#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22962#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22256#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 22257#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22508#L1154 assume !(1 == ~M_E~0); 23206#L1154-2 assume !(1 == ~T1_E~0); 22482#L1159-1 assume !(1 == ~T2_E~0); 22483#L1164-1 assume !(1 == ~T3_E~0); 22942#L1169-1 assume !(1 == ~T4_E~0); 22809#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22611#L1179-1 assume !(1 == ~T6_E~0); 22467#L1184-1 assume !(1 == ~T7_E~0); 22468#L1189-1 assume !(1 == ~T8_E~0); 22544#L1194-1 assume !(1 == ~T9_E~0); 22669#L1199-1 assume !(1 == ~T10_E~0); 22623#L1204-1 assume !(1 == ~E_M~0); 22624#L1209-1 assume !(1 == ~E_1~0); 23177#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 23178#L1219-1 assume !(1 == ~E_3~0); 23468#L1224-1 assume !(1 == ~E_4~0); 22966#L1229-1 assume !(1 == ~E_5~0); 22351#L1234-1 assume !(1 == ~E_6~0); 22352#L1239-1 assume !(1 == ~E_7~0); 22409#L1244-1 assume !(1 == ~E_8~0); 22410#L1249-1 assume !(1 == ~E_9~0); 23247#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22251#L1259-1 assume { :end_inline_reset_delta_events } true; 22252#L1565-2 [2024-11-13 15:24:29,868 INFO L747 eck$LassoCheckResult]: Loop: 22252#L1565-2 assume !false; 23185#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22950#L1011-1 assume !false; 22914#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22687#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22451#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22787#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22474#L866 assume !(0 != eval_~tmp~0#1); 22476#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22983#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22984#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23251#L1036-5 assume !(0 == ~T1_E~0); 23430#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23312#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23313#L1051-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23252#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22496#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22497#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22498#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23432#L1076-3 assume !(0 == ~T9_E~0); 22243#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22244#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22294#L1091-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22295#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23396#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23397#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23429#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23388#L1116-3 assume !(0 == ~E_6~0); 23113#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23114#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23327#L1131-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23328#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23480#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23116#L514-36 assume !(1 == ~m_pc~0); 22825#L514-38 is_master_triggered_~__retres1~0#1 := 0; 22660#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22661#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23155#L1285-36 assume !(0 != activate_threads_~tmp~1#1); 22553#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22554#L533-36 assume 1 == ~t1_pc~0; 22834#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22927#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23378#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23193#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22990#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22991#L552-36 assume 1 == ~t2_pc~0; 22548#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22549#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23049#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23320#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22520#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22521#L571-36 assume 1 == ~t3_pc~0; 22908#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22612#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22613#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22804#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23311#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22583#L590-36 assume !(1 == ~t4_pc~0); 22584#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 23207#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23000#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23001#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23290#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23291#L609-36 assume 1 == ~t5_pc~0; 23168#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22993#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22994#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23335#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23077#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22884#L628-36 assume 1 == ~t6_pc~0; 22732#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22733#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22783#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22784#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23118#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23119#L647-36 assume 1 == ~t7_pc~0; 23042#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22270#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22271#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22288#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22289#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23208#L666-36 assume !(1 == ~t8_pc~0); 22481#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 22480#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23106#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23107#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22631#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22632#L685-36 assume 1 == ~t9_pc~0; 23093#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22383#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22838#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22839#L1357-36 assume !(0 != activate_threads_~tmp___8~0#1); 22771#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22772#L704-36 assume 1 == ~t10_pc~0; 22370#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22371#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22692#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22693#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22398#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22399#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 23382#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23265#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23266#L1164-3 assume !(1 == ~T3_E~0); 23443#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22698#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22699#L1179-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23357#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22272#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22273#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22642#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22643#L1204-3 assume !(1 == ~E_M~0); 22963#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22140#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22141#L1219-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23162#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23163#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23184#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22411#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22412#L1244-3 assume !(1 == ~E_8~0); 23017#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23389#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23166#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 23167#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22220#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22680#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 22681#L1584 assume !(0 == start_simulation_~tmp~3#1); 23124#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22425#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22120#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22172#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 22173#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22751#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23006#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 23007#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 22252#L1565-2 [2024-11-13 15:24:29,868 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:29,868 INFO L85 PathProgramCache]: Analyzing trace with hash -1581271233, now seen corresponding path program 1 times [2024-11-13 15:24:29,868 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:29,868 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1089034187] [2024-11-13 15:24:29,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:29,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:29,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:29,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:29,966 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:29,966 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1089034187] [2024-11-13 15:24:29,966 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1089034187] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:29,966 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:29,966 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:29,967 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1141433536] [2024-11-13 15:24:29,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:29,967 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:24:29,967 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:29,968 INFO L85 PathProgramCache]: Analyzing trace with hash 981436344, now seen corresponding path program 1 times [2024-11-13 15:24:29,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:29,968 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [42381550] [2024-11-13 15:24:29,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:29,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:29,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:30,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:30,059 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:30,059 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [42381550] [2024-11-13 15:24:30,059 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [42381550] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:30,059 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:30,059 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:30,060 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2139682765] [2024-11-13 15:24:30,060 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:30,060 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:24:30,060 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:24:30,060 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:24:30,060 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:24:30,061 INFO L87 Difference]: Start difference. First operand 1377 states and 2036 transitions. cyclomatic complexity: 660 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:30,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:24:30,099 INFO L93 Difference]: Finished difference Result 1377 states and 2035 transitions. [2024-11-13 15:24:30,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2035 transitions. [2024-11-13 15:24:30,108 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2024-11-13 15:24:30,115 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2035 transitions. [2024-11-13 15:24:30,116 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2024-11-13 15:24:30,117 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2024-11-13 15:24:30,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2035 transitions. [2024-11-13 15:24:30,120 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:24:30,120 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2035 transitions. [2024-11-13 15:24:30,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2035 transitions. [2024-11-13 15:24:30,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2024-11-13 15:24:30,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4778503994190269) internal successors, (2035), 1376 states have internal predecessors, (2035), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:30,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2035 transitions. [2024-11-13 15:24:30,149 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2035 transitions. [2024-11-13 15:24:30,149 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:24:30,150 INFO L424 stractBuchiCegarLoop]: Abstraction has 1377 states and 2035 transitions. [2024-11-13 15:24:30,150 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 15:24:30,150 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2035 transitions. [2024-11-13 15:24:30,157 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2024-11-13 15:24:30,158 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:24:30,158 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:24:30,161 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:30,161 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:30,161 INFO L745 eck$LassoCheckResult]: Stem: 25285#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 25286#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 26162#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26163#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26225#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 26166#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26126#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26127#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26155#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25222#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25223#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25330#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25575#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 25501#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25224#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 24885#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24886#L1036 assume !(0 == ~M_E~0); 24983#L1036-2 assume !(0 == ~T1_E~0); 25888#L1041-1 assume !(0 == ~T2_E~0); 25889#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25260#L1051-1 assume !(0 == ~T4_E~0); 25261#L1056-1 assume !(0 == ~T5_E~0); 26017#L1061-1 assume !(0 == ~T6_E~0); 25155#L1066-1 assume !(0 == ~T7_E~0); 25156#L1071-1 assume !(0 == ~T8_E~0); 25999#L1076-1 assume !(0 == ~T9_E~0); 25045#L1081-1 assume !(0 == ~T10_E~0); 25046#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 25446#L1091-1 assume !(0 == ~E_1~0); 26173#L1096-1 assume !(0 == ~E_2~0); 26174#L1101-1 assume !(0 == ~E_3~0); 25514#L1106-1 assume !(0 == ~E_4~0); 25515#L1111-1 assume !(0 == ~E_5~0); 25679#L1116-1 assume !(0 == ~E_6~0); 25680#L1121-1 assume !(0 == ~E_7~0); 25505#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 25506#L1131-1 assume !(0 == ~E_9~0); 25781#L1136-1 assume !(0 == ~E_10~0); 25896#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26045#L514 assume 1 == ~m_pc~0; 26010#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25523#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25524#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26097#L1285 assume !(0 != activate_threads_~tmp~1#1); 26209#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25174#L533 assume !(1 == ~t1_pc~0); 25175#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25694#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24938#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24939#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 25917#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25918#L552 assume 1 == ~t2_pc~0; 25394#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25395#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25509#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25510#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 25539#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25540#L571 assume 1 == ~t3_pc~0; 25732#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25733#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24883#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24884#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 25684#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24969#L590 assume !(1 == ~t4_pc~0); 24970#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 25742#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25063#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25064#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25945#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25681#L609 assume 1 == ~t5_pc~0; 25682#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26207#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26099#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26100#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 25673#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25674#L628 assume !(1 == ~t6_pc~0); 25606#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25605#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25482#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25483#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 25979#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25980#L647 assume 1 == ~t7_pc~0; 25516#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25517#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26108#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25519#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 25520#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26236#L666 assume !(1 == ~t8_pc~0); 25307#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25308#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25535#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25705#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 25443#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25444#L685 assume 1 == ~t9_pc~0; 26215#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26116#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25569#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25473#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 25474#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25859#L704 assume !(1 == ~t10_pc~0); 25463#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25462#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25724#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25017#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 25018#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25269#L1154 assume !(1 == ~M_E~0); 25967#L1154-2 assume !(1 == ~T1_E~0); 25243#L1159-1 assume !(1 == ~T2_E~0); 25244#L1164-1 assume !(1 == ~T3_E~0); 25703#L1169-1 assume !(1 == ~T4_E~0); 25570#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25372#L1179-1 assume !(1 == ~T6_E~0); 25228#L1184-1 assume !(1 == ~T7_E~0); 25229#L1189-1 assume !(1 == ~T8_E~0); 25305#L1194-1 assume !(1 == ~T9_E~0); 25430#L1199-1 assume !(1 == ~T10_E~0); 25384#L1204-1 assume !(1 == ~E_M~0); 25385#L1209-1 assume !(1 == ~E_1~0); 25940#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25941#L1219-1 assume !(1 == ~E_3~0); 26229#L1224-1 assume !(1 == ~E_4~0); 25727#L1229-1 assume !(1 == ~E_5~0); 25112#L1234-1 assume !(1 == ~E_6~0); 25113#L1239-1 assume !(1 == ~E_7~0); 25170#L1244-1 assume !(1 == ~E_8~0); 25171#L1249-1 assume !(1 == ~E_9~0); 26008#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 25012#L1259-1 assume { :end_inline_reset_delta_events } true; 25013#L1565-2 [2024-11-13 15:24:30,162 INFO L747 eck$LassoCheckResult]: Loop: 25013#L1565-2 assume !false; 25946#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25712#L1011-1 assume !false; 25675#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25448#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 25212#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25548#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25238#L866 assume !(0 != eval_~tmp~0#1); 25240#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25744#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25745#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26012#L1036-5 assume !(0 == ~T1_E~0); 26191#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26073#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26074#L1051-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26013#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25257#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25258#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25259#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26193#L1076-3 assume !(0 == ~T9_E~0); 25004#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25005#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25055#L1091-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25056#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26157#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26158#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26190#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26149#L1116-3 assume !(0 == ~E_6~0); 25874#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25875#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26088#L1131-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26089#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26241#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25877#L514-36 assume !(1 == ~m_pc~0); 25586#L514-38 is_master_triggered_~__retres1~0#1 := 0; 25421#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25422#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25916#L1285-36 assume !(0 != activate_threads_~tmp~1#1); 25314#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25315#L533-36 assume 1 == ~t1_pc~0; 25595#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25688#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26139#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25954#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25751#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25752#L552-36 assume 1 == ~t2_pc~0; 25309#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25310#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25810#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26081#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25281#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25282#L571-36 assume 1 == ~t3_pc~0; 25669#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25373#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25374#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25565#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26072#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25346#L590-36 assume !(1 == ~t4_pc~0); 25347#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 25968#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25762#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25763#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26051#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26052#L609-36 assume 1 == ~t5_pc~0; 25929#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25754#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25755#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26096#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25838#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25645#L628-36 assume 1 == ~t6_pc~0; 25493#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25494#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25544#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25545#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25879#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25880#L647-36 assume 1 == ~t7_pc~0; 25803#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25031#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25032#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25049#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25050#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25969#L666-36 assume 1 == ~t8_pc~0; 25235#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25236#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25867#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25868#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25392#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25393#L685-36 assume !(1 == ~t9_pc~0); 25141#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 25142#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25598#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25599#L1357-36 assume !(0 != activate_threads_~tmp___8~0#1); 25532#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25533#L704-36 assume 1 == ~t10_pc~0; 25131#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25132#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25453#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25454#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25157#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25158#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26143#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26026#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26027#L1164-3 assume !(1 == ~T3_E~0); 26204#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25459#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25460#L1179-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26118#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25033#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25034#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25403#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25404#L1204-3 assume !(1 == ~E_M~0); 25723#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24901#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24902#L1219-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25923#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25924#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25944#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25172#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25173#L1244-3 assume !(1 == ~E_8~0); 25774#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 26150#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25927#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25928#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24981#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25441#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 25442#L1584 assume !(0 == start_simulation_~tmp~3#1); 25885#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25186#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24881#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24933#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 24934#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25511#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25767#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 25768#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 25013#L1565-2 [2024-11-13 15:24:30,162 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:30,162 INFO L85 PathProgramCache]: Analyzing trace with hash 711809793, now seen corresponding path program 1 times [2024-11-13 15:24:30,162 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:30,162 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1005588986] [2024-11-13 15:24:30,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:30,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:30,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:30,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:30,289 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:30,289 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1005588986] [2024-11-13 15:24:30,289 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1005588986] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:30,289 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:30,289 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:30,289 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1910337425] [2024-11-13 15:24:30,290 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:30,290 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:24:30,290 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:30,290 INFO L85 PathProgramCache]: Analyzing trace with hash -638227336, now seen corresponding path program 1 times [2024-11-13 15:24:30,290 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:30,290 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [517647037] [2024-11-13 15:24:30,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:30,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:30,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:30,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:30,365 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:30,365 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [517647037] [2024-11-13 15:24:30,365 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [517647037] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:30,365 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:30,365 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:30,365 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1997043962] [2024-11-13 15:24:30,365 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:30,366 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:24:30,366 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:24:30,366 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:24:30,366 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:24:30,367 INFO L87 Difference]: Start difference. First operand 1377 states and 2035 transitions. cyclomatic complexity: 659 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:30,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:24:30,611 INFO L93 Difference]: Finished difference Result 2536 states and 3734 transitions. [2024-11-13 15:24:30,611 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2536 states and 3734 transitions. [2024-11-13 15:24:30,627 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2375 [2024-11-13 15:24:30,641 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2536 states to 2536 states and 3734 transitions. [2024-11-13 15:24:30,641 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2536 [2024-11-13 15:24:30,644 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2536 [2024-11-13 15:24:30,644 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2536 states and 3734 transitions. [2024-11-13 15:24:30,648 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:24:30,648 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2536 states and 3734 transitions. [2024-11-13 15:24:30,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2536 states and 3734 transitions. [2024-11-13 15:24:30,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2536 to 2536. [2024-11-13 15:24:30,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2536 states, 2536 states have (on average 1.472397476340694) internal successors, (3734), 2535 states have internal predecessors, (3734), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:30,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2536 states to 2536 states and 3734 transitions. [2024-11-13 15:24:30,711 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2536 states and 3734 transitions. [2024-11-13 15:24:30,712 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:24:30,712 INFO L424 stractBuchiCegarLoop]: Abstraction has 2536 states and 3734 transitions. [2024-11-13 15:24:30,712 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 15:24:30,712 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2536 states and 3734 transitions. [2024-11-13 15:24:30,725 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2375 [2024-11-13 15:24:30,725 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:24:30,726 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:24:30,728 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:30,728 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:30,728 INFO L745 eck$LassoCheckResult]: Stem: 29208#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 29209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 30102#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30103#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30176#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 30107#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30061#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30062#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30093#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29145#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29146#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29253#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29501#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29426#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29147#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 28808#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28809#L1036 assume !(0 == ~M_E~0); 28906#L1036-2 assume !(0 == ~T1_E~0); 29817#L1041-1 assume !(0 == ~T2_E~0); 29818#L1046-1 assume !(0 == ~T3_E~0); 29183#L1051-1 assume !(0 == ~T4_E~0); 29184#L1056-1 assume !(0 == ~T5_E~0); 29951#L1061-1 assume !(0 == ~T6_E~0); 29078#L1066-1 assume !(0 == ~T7_E~0); 29079#L1071-1 assume !(0 == ~T8_E~0); 29933#L1076-1 assume !(0 == ~T9_E~0); 28968#L1081-1 assume !(0 == ~T10_E~0); 28969#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 29370#L1091-1 assume !(0 == ~E_1~0); 30115#L1096-1 assume !(0 == ~E_2~0); 30116#L1101-1 assume !(0 == ~E_3~0); 29439#L1106-1 assume !(0 == ~E_4~0); 29440#L1111-1 assume !(0 == ~E_5~0); 29605#L1116-1 assume !(0 == ~E_6~0); 29606#L1121-1 assume !(0 == ~E_7~0); 29430#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 29431#L1131-1 assume !(0 == ~E_9~0); 29708#L1136-1 assume !(0 == ~E_10~0); 29825#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29979#L514 assume 1 == ~m_pc~0; 29944#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29448#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29449#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30032#L1285 assume !(0 != activate_threads_~tmp~1#1); 30157#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29097#L533 assume !(1 == ~t1_pc~0); 29098#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29620#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28861#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28862#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 29848#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29849#L552 assume 1 == ~t2_pc~0; 29317#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29318#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29434#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29435#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 29461#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29462#L571 assume 1 == ~t3_pc~0; 29659#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29660#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28806#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28807#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 29610#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28892#L590 assume !(1 == ~t4_pc~0); 28893#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 29669#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28986#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28987#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29876#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29607#L609 assume 1 == ~t5_pc~0; 29608#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30155#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30034#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30035#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 29599#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29600#L628 assume !(1 == ~t6_pc~0); 29532#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29531#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29407#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29408#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 29913#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29914#L647 assume 1 == ~t7_pc~0; 29441#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29442#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30043#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29444#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 29445#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30191#L666 assume !(1 == ~t8_pc~0); 29230#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29231#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29460#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29632#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 29367#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29368#L685 assume 1 == ~t9_pc~0; 30165#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30051#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29495#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29397#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 29398#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29788#L704 assume !(1 == ~t10_pc~0); 29387#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29386#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29650#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28940#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 28941#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29192#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 29900#L1154-2 assume !(1 == ~T1_E~0); 29166#L1159-1 assume !(1 == ~T2_E~0); 29167#L1164-1 assume !(1 == ~T3_E~0); 29630#L1169-1 assume !(1 == ~T4_E~0); 29496#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29295#L1179-1 assume !(1 == ~T6_E~0); 29151#L1184-1 assume !(1 == ~T7_E~0); 29152#L1189-1 assume !(1 == ~T8_E~0); 29228#L1194-1 assume !(1 == ~T9_E~0); 30341#L1199-1 assume !(1 == ~T10_E~0); 30339#L1204-1 assume !(1 == ~E_M~0); 30337#L1209-1 assume !(1 == ~E_1~0); 30335#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 30333#L1219-1 assume !(1 == ~E_3~0); 30331#L1224-1 assume !(1 == ~E_4~0); 30328#L1229-1 assume !(1 == ~E_5~0); 30326#L1234-1 assume !(1 == ~E_6~0); 30278#L1239-1 assume !(1 == ~E_7~0); 30274#L1244-1 assume !(1 == ~E_8~0); 30253#L1249-1 assume !(1 == ~E_9~0); 30241#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 30233#L1259-1 assume { :end_inline_reset_delta_events } true; 30229#L1565-2 [2024-11-13 15:24:30,729 INFO L747 eck$LassoCheckResult]: Loop: 30229#L1565-2 assume !false; 30224#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30222#L1011-1 assume !false; 30221#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30220#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30209#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30208#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 30206#L866 assume !(0 != eval_~tmp~0#1); 30205#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30204#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30202#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30203#L1036-5 assume !(0 == ~T1_E~0); 31170#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31169#L1046-3 assume !(0 == ~T3_E~0); 31168#L1051-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31167#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31166#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31165#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31164#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 31163#L1076-3 assume !(0 == ~T9_E~0); 31162#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31161#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 31160#L1091-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31159#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 31158#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31157#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31156#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 31033#L1116-3 assume !(0 == ~E_6~0); 31032#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 31031#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30023#L1131-3 assume 0 == ~E_9~0;~E_9~0 := 1; 30024#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 30197#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29806#L514-36 assume !(1 == ~m_pc~0); 29512#L514-38 is_master_triggered_~__retres1~0#1 := 0; 29344#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29345#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29847#L1285-36 assume !(0 != activate_threads_~tmp~1#1); 29237#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29238#L533-36 assume 1 == ~t1_pc~0; 29521#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29614#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30076#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29886#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29678#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29679#L552-36 assume 1 == ~t2_pc~0; 29232#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29233#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29738#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30016#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29204#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29205#L571-36 assume 1 == ~t3_pc~0; 29595#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29296#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29297#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29491#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30007#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29267#L590-36 assume !(1 == ~t4_pc~0); 29268#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 29902#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29689#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29690#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29985#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29986#L609-36 assume 1 == ~t5_pc~0; 29861#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29681#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29682#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30031#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29767#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29571#L628-36 assume 1 == ~t6_pc~0; 29418#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29419#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29469#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29470#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29808#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29809#L647-36 assume 1 == ~t7_pc~0; 29731#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28954#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28955#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28972#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28973#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29903#L666-36 assume 1 == ~t8_pc~0; 29163#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29164#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29796#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29797#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29315#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29316#L685-36 assume 1 == ~t9_pc~0; 29783#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29067#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29525#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29526#L1357-36 assume !(0 != activate_threads_~tmp___8~0#1); 29457#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29458#L704-36 assume !(1 == ~t10_pc~0); 29056#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 29055#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30954#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30952#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30950#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30947#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30201#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30944#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30942#L1164-3 assume !(1 == ~T3_E~0); 30199#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30939#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30936#L1179-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30934#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30932#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30930#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30928#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30926#L1204-3 assume !(1 == ~E_M~0); 30923#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30921#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30919#L1219-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30918#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30917#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30916#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30915#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30914#L1244-3 assume !(1 == ~E_8~0); 30913#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30087#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30088#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30672#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30664#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30661#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 30659#L1584 assume !(0 == start_simulation_~tmp~3#1); 30196#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30312#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30301#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30273#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 30252#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30251#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30240#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 30232#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 30229#L1565-2 [2024-11-13 15:24:30,729 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:30,729 INFO L85 PathProgramCache]: Analyzing trace with hash 1478663553, now seen corresponding path program 1 times [2024-11-13 15:24:30,729 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:30,729 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [320201371] [2024-11-13 15:24:30,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:30,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:30,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:30,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:30,836 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:30,836 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [320201371] [2024-11-13 15:24:30,836 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [320201371] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:30,836 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:30,836 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:30,836 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [441261944] [2024-11-13 15:24:30,836 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:30,836 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:24:30,837 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:30,837 INFO L85 PathProgramCache]: Analyzing trace with hash 1258087226, now seen corresponding path program 1 times [2024-11-13 15:24:30,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:30,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [195268829] [2024-11-13 15:24:30,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:30,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:30,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:30,915 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:30,915 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:30,915 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [195268829] [2024-11-13 15:24:30,916 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [195268829] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:30,916 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:30,916 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:30,916 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [934233958] [2024-11-13 15:24:30,916 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:30,916 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:24:30,916 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:24:30,917 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:24:30,917 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:24:30,917 INFO L87 Difference]: Start difference. First operand 2536 states and 3734 transitions. cyclomatic complexity: 1200 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:31,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:24:31,164 INFO L93 Difference]: Finished difference Result 4684 states and 6883 transitions. [2024-11-13 15:24:31,164 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4684 states and 6883 transitions. [2024-11-13 15:24:31,246 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4491 [2024-11-13 15:24:31,269 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4684 states to 4684 states and 6883 transitions. [2024-11-13 15:24:31,269 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4684 [2024-11-13 15:24:31,274 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4684 [2024-11-13 15:24:31,274 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4684 states and 6883 transitions. [2024-11-13 15:24:31,281 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:24:31,281 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4684 states and 6883 transitions. [2024-11-13 15:24:31,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4684 states and 6883 transitions. [2024-11-13 15:24:31,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4684 to 4682. [2024-11-13 15:24:31,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4682 states, 4682 states have (on average 1.4696710807347289) internal successors, (6881), 4681 states have internal predecessors, (6881), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:31,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4682 states to 4682 states and 6881 transitions. [2024-11-13 15:24:31,416 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4682 states and 6881 transitions. [2024-11-13 15:24:31,417 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:24:31,418 INFO L424 stractBuchiCegarLoop]: Abstraction has 4682 states and 6881 transitions. [2024-11-13 15:24:31,418 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 15:24:31,418 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4682 states and 6881 transitions. [2024-11-13 15:24:31,444 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4491 [2024-11-13 15:24:31,444 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:24:31,445 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:24:31,447 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:31,447 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:31,448 INFO L745 eck$LassoCheckResult]: Stem: 36438#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 36439#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 37387#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37388#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37474#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 37391#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37342#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37343#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37379#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36377#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36378#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36483#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36736#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36659#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36379#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36038#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36039#L1036 assume !(0 == ~M_E~0); 36136#L1036-2 assume !(0 == ~T1_E~0); 37068#L1041-1 assume !(0 == ~T2_E~0); 37069#L1046-1 assume !(0 == ~T3_E~0); 36413#L1051-1 assume !(0 == ~T4_E~0); 36414#L1056-1 assume !(0 == ~T5_E~0); 37211#L1061-1 assume !(0 == ~T6_E~0); 36308#L1066-1 assume !(0 == ~T7_E~0); 36309#L1071-1 assume !(0 == ~T8_E~0); 37191#L1076-1 assume !(0 == ~T9_E~0); 36198#L1081-1 assume !(0 == ~T10_E~0); 36199#L1086-1 assume !(0 == ~E_M~0); 36603#L1091-1 assume !(0 == ~E_1~0); 37400#L1096-1 assume !(0 == ~E_2~0); 37401#L1101-1 assume !(0 == ~E_3~0); 36672#L1106-1 assume !(0 == ~E_4~0); 36673#L1111-1 assume !(0 == ~E_5~0); 36846#L1116-1 assume !(0 == ~E_6~0); 36847#L1121-1 assume !(0 == ~E_7~0); 36663#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 36664#L1131-1 assume !(0 == ~E_9~0); 36955#L1136-1 assume !(0 == ~E_10~0); 37082#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37243#L514 assume 1 == ~m_pc~0; 37204#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36681#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36682#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37310#L1285 assume !(0 != activate_threads_~tmp~1#1); 37449#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36330#L533 assume !(1 == ~t1_pc~0); 36331#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36862#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36093#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36094#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 37106#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37107#L552 assume 1 == ~t2_pc~0; 36551#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36552#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36667#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36668#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 36699#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36700#L571 assume 1 == ~t3_pc~0; 36907#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36908#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36036#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36037#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 36851#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36122#L590 assume !(1 == ~t4_pc~0); 36123#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36916#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36216#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36217#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37136#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36848#L609 assume 1 == ~t5_pc~0; 36849#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37444#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37311#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37312#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 36840#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36841#L628 assume !(1 == ~t6_pc~0); 36770#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36769#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36643#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36644#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 37171#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37172#L647 assume 1 == ~t7_pc~0; 36674#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36675#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37320#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36679#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 36680#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37497#L666 assume !(1 == ~t8_pc~0); 36460#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36461#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36693#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36877#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 36601#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36602#L685 assume 1 == ~t9_pc~0; 37458#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37329#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36729#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36630#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 36631#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37038#L704 assume !(1 == ~t10_pc~0); 36620#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36619#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36896#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36170#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 36171#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36422#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 37158#L1154-2 assume !(1 == ~T1_E~0); 36396#L1159-1 assume !(1 == ~T2_E~0); 36397#L1164-1 assume !(1 == ~T3_E~0); 37528#L1169-1 assume !(1 == ~T4_E~0); 37761#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37742#L1179-1 assume !(1 == ~T6_E~0); 36381#L1184-1 assume !(1 == ~T7_E~0); 36382#L1189-1 assume !(1 == ~T8_E~0); 36458#L1194-1 assume !(1 == ~T9_E~0); 36589#L1199-1 assume !(1 == ~T10_E~0); 37538#L1204-1 assume !(1 == ~E_M~0); 37684#L1209-1 assume !(1 == ~E_1~0); 37682#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 37680#L1219-1 assume !(1 == ~E_3~0); 37678#L1224-1 assume !(1 == ~E_4~0); 37676#L1229-1 assume !(1 == ~E_5~0); 37673#L1234-1 assume !(1 == ~E_6~0); 37671#L1239-1 assume !(1 == ~E_7~0); 37669#L1244-1 assume !(1 == ~E_8~0); 37666#L1249-1 assume !(1 == ~E_9~0); 37582#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 37574#L1259-1 assume { :end_inline_reset_delta_events } true; 37568#L1565-2 [2024-11-13 15:24:31,448 INFO L747 eck$LassoCheckResult]: Loop: 37568#L1565-2 assume !false; 37563#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37561#L1011-1 assume !false; 37560#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37559#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37548#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37547#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37546#L866 assume !(0 != eval_~tmp~0#1); 37545#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37544#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37543#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37424#L1036-5 assume !(0 == ~T1_E~0); 37425#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37275#L1046-3 assume !(0 == ~T3_E~0); 37276#L1051-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37207#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36410#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36411#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36412#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37426#L1076-3 assume !(0 == ~T9_E~0); 36157#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36158#L1086-3 assume !(0 == ~E_M~0); 36212#L1091-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36213#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37381#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37382#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37422#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37371#L1116-3 assume !(0 == ~E_6~0); 37053#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37054#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37295#L1131-3 assume 0 == ~E_9~0;~E_9~0 := 1; 37296#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37519#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37055#L514-36 assume 1 == ~m_pc~0; 37056#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36577#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36578#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37105#L1285-36 assume !(0 != activate_threads_~tmp~1#1); 36467#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36468#L533-36 assume 1 == ~t1_pc~0; 36756#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36855#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37358#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37145#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36924#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36925#L552-36 assume !(1 == ~t2_pc~0); 36464#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 36463#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36985#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37286#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37481#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39055#L571-36 assume 1 == ~t3_pc~0; 39052#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39051#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39050#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39049#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39048#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39047#L590-36 assume !(1 == ~t4_pc~0); 39045#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 39044#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39043#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39042#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39041#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39040#L609-36 assume 1 == ~t5_pc~0; 39038#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39037#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39036#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39035#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 39034#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39033#L628-36 assume !(1 == ~t6_pc~0); 39031#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 39030#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39029#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39028#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 39027#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39026#L647-36 assume 1 == ~t7_pc~0; 39024#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39023#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39022#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39021#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 39020#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39019#L666-36 assume !(1 == ~t8_pc~0); 39017#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 39016#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39015#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39014#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39013#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39012#L685-36 assume 1 == ~t9_pc~0; 39010#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39009#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39007#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39006#L1357-36 assume !(0 != activate_threads_~tmp___8~0#1); 39004#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39002#L704-36 assume 1 == ~t10_pc~0; 38999#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38997#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38995#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38992#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38990#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38988#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37536#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38985#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38983#L1164-3 assume !(1 == ~T3_E~0); 37532#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38946#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 38940#L1179-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38936#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38859#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38857#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38855#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38846#L1204-3 assume !(1 == ~E_M~0); 38036#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38034#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38032#L1219-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38030#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37953#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37910#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37755#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37736#L1244-3 assume !(1 == ~E_8~0); 37734#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37694#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37629#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37618#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37606#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37602#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 37601#L1584 assume !(0 == start_simulation_~tmp~3#1); 37518#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37600#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37589#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37586#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 37585#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37583#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37581#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 37573#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 37568#L1565-2 [2024-11-13 15:24:31,448 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:31,449 INFO L85 PathProgramCache]: Analyzing trace with hash 171521155, now seen corresponding path program 1 times [2024-11-13 15:24:31,449 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:31,449 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328853574] [2024-11-13 15:24:31,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:31,449 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:31,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:31,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:31,565 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:31,565 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328853574] [2024-11-13 15:24:31,565 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1328853574] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:31,565 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:31,565 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:31,565 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [821690945] [2024-11-13 15:24:31,565 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:31,566 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:24:31,566 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:31,566 INFO L85 PathProgramCache]: Analyzing trace with hash -1077385603, now seen corresponding path program 1 times [2024-11-13 15:24:31,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:31,566 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1996024216] [2024-11-13 15:24:31,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:31,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:31,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:31,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:31,647 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:31,647 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1996024216] [2024-11-13 15:24:31,647 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1996024216] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:31,647 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:31,647 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:31,647 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [942872835] [2024-11-13 15:24:31,647 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:31,648 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:24:31,648 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:24:31,648 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:24:31,648 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:24:31,648 INFO L87 Difference]: Start difference. First operand 4682 states and 6881 transitions. cyclomatic complexity: 2203 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:31,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:24:31,916 INFO L93 Difference]: Finished difference Result 8780 states and 12872 transitions. [2024-11-13 15:24:31,916 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8780 states and 12872 transitions. [2024-11-13 15:24:31,968 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8565 [2024-11-13 15:24:32,012 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8780 states to 8780 states and 12872 transitions. [2024-11-13 15:24:32,012 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8780 [2024-11-13 15:24:32,021 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8780 [2024-11-13 15:24:32,021 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8780 states and 12872 transitions. [2024-11-13 15:24:32,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:24:32,035 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8780 states and 12872 transitions. [2024-11-13 15:24:32,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8780 states and 12872 transitions. [2024-11-13 15:24:32,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8780 to 8776. [2024-11-13 15:24:32,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8776 states, 8776 states have (on average 1.466271649954421) internal successors, (12868), 8775 states have internal predecessors, (12868), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:32,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8776 states to 8776 states and 12868 transitions. [2024-11-13 15:24:32,258 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8776 states and 12868 transitions. [2024-11-13 15:24:32,259 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:24:32,259 INFO L424 stractBuchiCegarLoop]: Abstraction has 8776 states and 12868 transitions. [2024-11-13 15:24:32,259 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 15:24:32,260 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8776 states and 12868 transitions. [2024-11-13 15:24:32,301 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8565 [2024-11-13 15:24:32,301 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:24:32,301 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:24:32,303 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:32,304 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:32,304 INFO L745 eck$LassoCheckResult]: Stem: 49911#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 49912#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 50807#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50808#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50870#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 50811#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50770#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50771#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50800#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49848#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49849#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49957#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50206#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50131#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49850#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49510#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49511#L1036 assume !(0 == ~M_E~0); 49608#L1036-2 assume !(0 == ~T1_E~0); 50524#L1041-1 assume !(0 == ~T2_E~0); 50525#L1046-1 assume !(0 == ~T3_E~0); 49886#L1051-1 assume !(0 == ~T4_E~0); 49887#L1056-1 assume !(0 == ~T5_E~0); 50656#L1061-1 assume !(0 == ~T6_E~0); 49780#L1066-1 assume !(0 == ~T7_E~0); 49781#L1071-1 assume !(0 == ~T8_E~0); 50638#L1076-1 assume !(0 == ~T9_E~0); 49670#L1081-1 assume !(0 == ~T10_E~0); 49671#L1086-1 assume !(0 == ~E_M~0); 50075#L1091-1 assume !(0 == ~E_1~0); 50818#L1096-1 assume !(0 == ~E_2~0); 50819#L1101-1 assume !(0 == ~E_3~0); 50144#L1106-1 assume !(0 == ~E_4~0); 50145#L1111-1 assume !(0 == ~E_5~0); 50311#L1116-1 assume !(0 == ~E_6~0); 50312#L1121-1 assume !(0 == ~E_7~0); 50135#L1126-1 assume !(0 == ~E_8~0); 50136#L1131-1 assume !(0 == ~E_9~0); 50416#L1136-1 assume !(0 == ~E_10~0); 50532#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50684#L514 assume 1 == ~m_pc~0; 50649#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 50153#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50154#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50740#L1285 assume !(0 != activate_threads_~tmp~1#1); 50854#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49800#L533 assume !(1 == ~t1_pc~0); 49801#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50326#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49563#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49564#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 50554#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50555#L552 assume 1 == ~t2_pc~0; 50023#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50024#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50139#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50140#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 50166#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50167#L571 assume 1 == ~t3_pc~0; 50366#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50367#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49508#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49509#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 50316#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49594#L590 assume !(1 == ~t4_pc~0); 49595#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 50376#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49688#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49689#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50581#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50313#L609 assume 1 == ~t5_pc~0; 50314#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50852#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50742#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50743#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 50305#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50306#L628 assume !(1 == ~t6_pc~0); 50238#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50237#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50112#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50113#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 50617#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50618#L647 assume 1 == ~t7_pc~0; 50146#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50147#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50751#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50149#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 50150#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50884#L666 assume !(1 == ~t8_pc~0); 49934#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 49935#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50165#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50339#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 50072#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50073#L685 assume 1 == ~t9_pc~0; 50860#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50760#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50199#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50102#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 50103#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50494#L704 assume !(1 == ~t10_pc~0); 50092#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50091#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50357#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49642#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 49643#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49895#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 50604#L1154-2 assume !(1 == ~T1_E~0); 49869#L1159-1 assume !(1 == ~T2_E~0); 49870#L1164-1 assume !(1 == ~T3_E~0); 50896#L1169-1 assume !(1 == ~T4_E~0); 50200#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50201#L1179-1 assume !(1 == ~T6_E~0); 49854#L1184-1 assume !(1 == ~T7_E~0); 49855#L1189-1 assume !(1 == ~T8_E~0); 51763#L1194-1 assume !(1 == ~T9_E~0); 50902#L1199-1 assume !(1 == ~T10_E~0); 50903#L1204-1 assume !(1 == ~E_M~0); 51657#L1209-1 assume !(1 == ~E_1~0); 51620#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 51588#L1219-1 assume !(1 == ~E_3~0); 51584#L1224-1 assume !(1 == ~E_4~0); 51557#L1229-1 assume !(1 == ~E_5~0); 51542#L1234-1 assume !(1 == ~E_6~0); 51540#L1239-1 assume !(1 == ~E_7~0); 51517#L1244-1 assume !(1 == ~E_8~0); 51082#L1249-1 assume !(1 == ~E_9~0); 50947#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 50939#L1259-1 assume { :end_inline_reset_delta_events } true; 50933#L1565-2 [2024-11-13 15:24:32,304 INFO L747 eck$LassoCheckResult]: Loop: 50933#L1565-2 assume !false; 50928#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50926#L1011-1 assume !false; 50925#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50924#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50913#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50912#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 50910#L866 assume !(0 != eval_~tmp~0#1); 50909#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50908#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50906#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50907#L1036-5 assume !(0 == ~T1_E~0); 58233#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 58231#L1046-3 assume !(0 == ~T3_E~0); 58229#L1051-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 58226#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 58224#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 58222#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 58220#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 58218#L1076-3 assume !(0 == ~T9_E~0); 58216#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 58213#L1086-3 assume !(0 == ~E_M~0); 58211#L1091-3 assume 0 == ~E_1~0;~E_1~0 := 1; 58209#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 58207#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 58205#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 58203#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 58200#L1116-3 assume !(0 == ~E_6~0); 58198#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 58196#L1126-3 assume !(0 == ~E_8~0); 58194#L1131-3 assume 0 == ~E_9~0;~E_9~0 := 1; 58192#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 58190#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58187#L514-36 assume 1 == ~m_pc~0; 58184#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 58182#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58180#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 58178#L1285-36 assume !(0 != activate_threads_~tmp~1#1); 58176#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58173#L533-36 assume 1 == ~t1_pc~0; 58170#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58168#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58166#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 58164#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58162#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58159#L552-36 assume 1 == ~t2_pc~0; 58156#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58154#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58152#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58151#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58150#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58149#L571-36 assume 1 == ~t3_pc~0; 58147#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58146#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58145#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58144#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 58143#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58142#L590-36 assume !(1 == ~t4_pc~0); 58140#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 58139#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58138#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58137#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58135#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58132#L609-36 assume 1 == ~t5_pc~0; 58129#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58127#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58042#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58041#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 58040#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58039#L628-36 assume !(1 == ~t6_pc~0); 58037#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 58036#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58035#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58034#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 58033#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58032#L647-36 assume 1 == ~t7_pc~0; 58030#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52856#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52854#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52852#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 52776#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52774#L666-36 assume !(1 == ~t8_pc~0); 52771#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 52769#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52767#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52766#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52765#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52764#L685-36 assume 1 == ~t9_pc~0; 52762#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52656#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52654#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52652#L1357-36 assume !(0 != activate_threads_~tmp___8~0#1); 52651#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52649#L704-36 assume 1 == ~t10_pc~0; 52646#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 52586#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52584#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52582#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 52580#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52578#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50901#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52575#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52514#L1164-3 assume !(1 == ~T3_E~0); 52512#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52510#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 52508#L1179-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 52462#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 52460#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 52458#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52455#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52341#L1204-3 assume !(1 == ~E_M~0); 52339#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 52225#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 52223#L1219-3 assume 1 == ~E_3~0;~E_3~0 := 2; 52221#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51985#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51767#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 51766#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 51678#L1244-3 assume !(1 == ~E_8~0); 51632#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51630#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51596#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 51566#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 51551#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 51550#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 51549#L1584 assume !(0 == start_simulation_~tmp~3#1); 50890#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 51533#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 51084#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 51066#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 51064#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 51061#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50946#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 50938#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 50933#L1565-2 [2024-11-13 15:24:32,306 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:32,306 INFO L85 PathProgramCache]: Analyzing trace with hash -711987835, now seen corresponding path program 1 times [2024-11-13 15:24:32,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:32,306 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1920822484] [2024-11-13 15:24:32,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:32,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:32,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:32,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:32,388 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:32,388 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1920822484] [2024-11-13 15:24:32,388 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1920822484] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:32,389 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:32,389 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:24:32,389 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1655620734] [2024-11-13 15:24:32,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:32,389 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:24:32,389 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:32,389 INFO L85 PathProgramCache]: Analyzing trace with hash 427737150, now seen corresponding path program 1 times [2024-11-13 15:24:32,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:32,390 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1562027684] [2024-11-13 15:24:32,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:32,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:32,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:32,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:32,456 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:32,456 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1562027684] [2024-11-13 15:24:32,456 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1562027684] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:32,456 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:32,456 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:32,456 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1612206710] [2024-11-13 15:24:32,456 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:32,456 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:24:32,456 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:24:32,457 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:24:32,457 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:24:32,458 INFO L87 Difference]: Start difference. First operand 8776 states and 12868 transitions. cyclomatic complexity: 4100 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:32,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:24:32,662 INFO L93 Difference]: Finished difference Result 17195 states and 25019 transitions. [2024-11-13 15:24:32,662 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17195 states and 25019 transitions. [2024-11-13 15:24:32,807 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16969 [2024-11-13 15:24:32,875 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17195 states to 17195 states and 25019 transitions. [2024-11-13 15:24:32,876 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17195 [2024-11-13 15:24:32,893 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17195 [2024-11-13 15:24:32,893 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17195 states and 25019 transitions. [2024-11-13 15:24:32,916 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:24:32,917 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17195 states and 25019 transitions. [2024-11-13 15:24:32,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17195 states and 25019 transitions. [2024-11-13 15:24:33,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17195 to 16587. [2024-11-13 15:24:33,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16587 states, 16587 states have (on average 1.4567432326520768) internal successors, (24163), 16586 states have internal predecessors, (24163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:33,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16587 states to 16587 states and 24163 transitions. [2024-11-13 15:24:33,386 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16587 states and 24163 transitions. [2024-11-13 15:24:33,386 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:24:33,387 INFO L424 stractBuchiCegarLoop]: Abstraction has 16587 states and 24163 transitions. [2024-11-13 15:24:33,387 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 15:24:33,387 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16587 states and 24163 transitions. [2024-11-13 15:24:33,448 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16361 [2024-11-13 15:24:33,448 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:24:33,448 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:24:33,450 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:33,450 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:33,450 INFO L745 eck$LassoCheckResult]: Stem: 75901#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 75902#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 76972#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76973#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77083#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 76976#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76912#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76913#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76964#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75831#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 75832#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 75950#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76212#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 76135#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 75833#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 75488#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75489#L1036 assume !(0 == ~M_E~0); 75586#L1036-2 assume !(0 == ~T1_E~0); 76581#L1041-1 assume !(0 == ~T2_E~0); 76582#L1046-1 assume !(0 == ~T3_E~0); 75875#L1051-1 assume !(0 == ~T4_E~0); 75876#L1056-1 assume !(0 == ~T5_E~0); 76744#L1061-1 assume !(0 == ~T6_E~0); 75759#L1066-1 assume !(0 == ~T7_E~0); 75760#L1071-1 assume !(0 == ~T8_E~0); 76727#L1076-1 assume !(0 == ~T9_E~0); 75647#L1081-1 assume !(0 == ~T10_E~0); 75648#L1086-1 assume !(0 == ~E_M~0); 76079#L1091-1 assume !(0 == ~E_1~0); 76987#L1096-1 assume !(0 == ~E_2~0); 76988#L1101-1 assume !(0 == ~E_3~0); 76148#L1106-1 assume !(0 == ~E_4~0); 76149#L1111-1 assume !(0 == ~E_5~0); 76333#L1116-1 assume !(0 == ~E_6~0); 76334#L1121-1 assume !(0 == ~E_7~0); 76139#L1126-1 assume !(0 == ~E_8~0); 76140#L1131-1 assume !(0 == ~E_9~0); 76450#L1136-1 assume !(0 == ~E_10~0); 76593#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76785#L514 assume !(1 == ~m_pc~0); 76786#L514-2 is_master_triggered_~__retres1~0#1 := 0; 76157#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76158#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 76867#L1285 assume !(0 != activate_threads_~tmp~1#1); 77052#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75782#L533 assume !(1 == ~t1_pc~0); 75783#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 76353#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75543#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 75544#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 76620#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76621#L552 assume 1 == ~t2_pc~0; 76021#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 76022#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76143#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76144#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 76178#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76179#L571 assume 1 == ~t3_pc~0; 76396#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 76397#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75486#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75487#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 76338#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75572#L590 assume !(1 == ~t4_pc~0); 75573#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 76406#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75665#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75666#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 76653#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76335#L609 assume 1 == ~t5_pc~0; 76336#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 77046#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76868#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 76869#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 76327#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76328#L628 assume !(1 == ~t6_pc~0); 76248#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 76247#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76118#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76119#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 76699#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76700#L647 assume 1 == ~t7_pc~0; 76150#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 76151#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76882#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76155#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 76156#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77114#L666 assume !(1 == ~t8_pc~0); 75926#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 75927#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76170#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76366#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 76076#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76077#L685 assume 1 == ~t9_pc~0; 77062#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 76893#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76205#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76104#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 76105#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76546#L704 assume !(1 == ~t10_pc~0); 76095#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 76094#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76385#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 75619#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 75620#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75883#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 76682#L1154-2 assume !(1 == ~T1_E~0); 79890#L1159-1 assume !(1 == ~T2_E~0); 79889#L1164-1 assume !(1 == ~T3_E~0); 79888#L1169-1 assume !(1 == ~T4_E~0); 79887#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 79666#L1179-1 assume !(1 == ~T6_E~0); 79664#L1184-1 assume !(1 == ~T7_E~0); 79662#L1189-1 assume !(1 == ~T8_E~0); 76062#L1194-1 assume !(1 == ~T9_E~0); 76063#L1199-1 assume !(1 == ~T10_E~0); 76012#L1204-1 assume !(1 == ~E_M~0); 76013#L1209-1 assume !(1 == ~E_1~0); 76648#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 76649#L1219-1 assume !(1 == ~E_3~0); 77092#L1224-1 assume !(1 == ~E_4~0); 77093#L1229-1 assume !(1 == ~E_5~0); 78254#L1234-1 assume !(1 == ~E_6~0); 78225#L1239-1 assume !(1 == ~E_7~0); 78209#L1244-1 assume !(1 == ~E_8~0); 78193#L1249-1 assume !(1 == ~E_9~0); 78182#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 78174#L1259-1 assume { :end_inline_reset_delta_events } true; 78168#L1565-2 [2024-11-13 15:24:33,450 INFO L747 eck$LassoCheckResult]: Loop: 78168#L1565-2 assume !false; 78163#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 78161#L1011-1 assume !false; 78160#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 78159#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 78148#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 78147#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 78145#L866 assume !(0 != eval_~tmp~0#1); 78144#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 78143#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78140#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 78141#L1036-5 assume !(0 == ~T1_E~0); 79450#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 79448#L1046-3 assume !(0 == ~T3_E~0); 79446#L1051-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 79444#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 79442#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 79440#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 79438#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 79436#L1076-3 assume !(0 == ~T9_E~0); 79434#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 79432#L1086-3 assume !(0 == ~E_M~0); 79430#L1091-3 assume 0 == ~E_1~0;~E_1~0 := 1; 79428#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 79426#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 79424#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 79422#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 79420#L1116-3 assume !(0 == ~E_6~0); 79417#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 79415#L1126-3 assume !(0 == ~E_8~0); 79413#L1131-3 assume 0 == ~E_9~0;~E_9~0 := 1; 79411#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 79395#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79389#L514-36 assume !(1 == ~m_pc~0); 79385#L514-38 is_master_triggered_~__retres1~0#1 := 0; 79381#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79324#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 79312#L1285-36 assume !(0 != activate_threads_~tmp~1#1); 79310#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 79308#L533-36 assume !(1 == ~t1_pc~0); 79305#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 79302#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 79300#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 79298#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 79296#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 79294#L552-36 assume 1 == ~t2_pc~0; 79291#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 79289#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79287#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 79285#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 79283#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 79281#L571-36 assume 1 == ~t3_pc~0; 79277#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 79275#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 79273#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 79271#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 79269#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 79267#L590-36 assume 1 == ~t4_pc~0; 79265#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 79262#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 79260#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 79198#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 79192#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 79186#L609-36 assume 1 == ~t5_pc~0; 79179#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 79172#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 79165#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 79158#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 79152#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 79146#L628-36 assume 1 == ~t6_pc~0; 79136#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 79133#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 79131#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 79129#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 79127#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 79125#L647-36 assume 1 == ~t7_pc~0; 79115#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 79110#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 79105#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 78905#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 78902#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78900#L666-36 assume !(1 == ~t8_pc~0); 78897#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 78895#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 78893#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 78891#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 78890#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78887#L685-36 assume !(1 == ~t9_pc~0); 78757#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 78754#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 78752#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 78750#L1357-36 assume !(0 != activate_threads_~tmp___8~0#1); 78748#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 78746#L704-36 assume !(1 == ~t10_pc~0); 78743#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 78740#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78738#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78736#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 78734#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78687#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 78678#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 78671#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 78657#L1164-3 assume !(1 == ~T3_E~0); 78651#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 78646#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 78641#L1179-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 78636#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 78631#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 78626#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 78620#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 78613#L1204-3 assume !(1 == ~E_M~0); 78610#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 78607#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 78604#L1219-3 assume 1 == ~E_3~0;~E_3~0 := 2; 78601#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 78597#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 78594#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 78591#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 78587#L1244-3 assume !(1 == ~E_8~0); 78585#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 78583#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 78580#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 78302#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 78294#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 78292#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 78290#L1584 assume !(0 == start_simulation_~tmp~3#1); 77154#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 78250#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 78223#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 78221#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 78206#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 78192#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 78181#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 78173#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 78168#L1565-2 [2024-11-13 15:24:33,451 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:33,451 INFO L85 PathProgramCache]: Analyzing trace with hash -2098669114, now seen corresponding path program 1 times [2024-11-13 15:24:33,451 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:33,451 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1789544961] [2024-11-13 15:24:33,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:33,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:33,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:33,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:33,517 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:33,517 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1789544961] [2024-11-13 15:24:33,517 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1789544961] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:33,517 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:33,517 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:24:33,517 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [477801135] [2024-11-13 15:24:33,518 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:33,518 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:24:33,518 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:33,518 INFO L85 PathProgramCache]: Analyzing trace with hash -1643276992, now seen corresponding path program 1 times [2024-11-13 15:24:33,518 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:33,518 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857442433] [2024-11-13 15:24:33,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:33,519 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:33,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:33,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:33,606 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:33,606 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1857442433] [2024-11-13 15:24:33,606 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1857442433] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:33,606 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:33,606 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:24:33,606 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1514440447] [2024-11-13 15:24:33,606 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:33,607 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:24:33,607 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:24:33,607 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:24:33,607 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:24:33,607 INFO L87 Difference]: Start difference. First operand 16587 states and 24163 transitions. cyclomatic complexity: 7592 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:33,930 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:24:33,930 INFO L93 Difference]: Finished difference Result 31537 states and 45713 transitions. [2024-11-13 15:24:33,931 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31537 states and 45713 transitions. [2024-11-13 15:24:34,091 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 31264 [2024-11-13 15:24:34,232 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31537 states to 31537 states and 45713 transitions. [2024-11-13 15:24:34,232 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31537 [2024-11-13 15:24:34,267 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31537 [2024-11-13 15:24:34,267 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31537 states and 45713 transitions. [2024-11-13 15:24:34,314 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:24:34,314 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31537 states and 45713 transitions. [2024-11-13 15:24:34,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31537 states and 45713 transitions. [2024-11-13 15:24:35,025 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31537 to 31505. [2024-11-13 15:24:35,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31505 states, 31505 states have (on average 1.4499603237581336) internal successors, (45681), 31504 states have internal predecessors, (45681), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:35,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31505 states to 31505 states and 45681 transitions. [2024-11-13 15:24:35,227 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31505 states and 45681 transitions. [2024-11-13 15:24:35,228 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:24:35,228 INFO L424 stractBuchiCegarLoop]: Abstraction has 31505 states and 45681 transitions. [2024-11-13 15:24:35,228 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 15:24:35,228 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31505 states and 45681 transitions. [2024-11-13 15:24:35,318 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 31232 [2024-11-13 15:24:35,318 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:24:35,318 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:24:35,320 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:35,320 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:35,321 INFO L745 eck$LassoCheckResult]: Stem: 124028#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 124029#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 124980#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 124981#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 125058#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 124984#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 124933#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 124934#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 124972#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 123961#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 123962#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 124074#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 124321#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 124244#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 123963#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 123621#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 123622#L1036 assume !(0 == ~M_E~0); 123718#L1036-2 assume !(0 == ~T1_E~0); 124649#L1041-1 assume !(0 == ~T2_E~0); 124650#L1046-1 assume !(0 == ~T3_E~0); 124003#L1051-1 assume !(0 == ~T4_E~0); 124004#L1056-1 assume !(0 == ~T5_E~0); 124800#L1061-1 assume !(0 == ~T6_E~0); 123892#L1066-1 assume !(0 == ~T7_E~0); 123893#L1071-1 assume !(0 == ~T8_E~0); 124783#L1076-1 assume !(0 == ~T9_E~0); 123781#L1081-1 assume !(0 == ~T10_E~0); 123782#L1086-1 assume !(0 == ~E_M~0); 124188#L1091-1 assume !(0 == ~E_1~0); 124992#L1096-1 assume !(0 == ~E_2~0); 124993#L1101-1 assume !(0 == ~E_3~0); 124257#L1106-1 assume !(0 == ~E_4~0); 124258#L1111-1 assume !(0 == ~E_5~0); 124429#L1116-1 assume !(0 == ~E_6~0); 124430#L1121-1 assume !(0 == ~E_7~0); 124248#L1126-1 assume !(0 == ~E_8~0); 124249#L1131-1 assume !(0 == ~E_9~0); 124536#L1136-1 assume !(0 == ~E_10~0); 124659#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 124834#L514 assume !(1 == ~m_pc~0); 124835#L514-2 is_master_triggered_~__retres1~0#1 := 0; 124266#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124267#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 124899#L1285 assume !(0 != activate_threads_~tmp~1#1); 125036#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123912#L533 assume !(1 == ~t1_pc~0); 123913#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 124444#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123673#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 123674#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 124685#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 124686#L552 assume !(1 == ~t2_pc~0); 124391#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 124392#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 124252#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 124253#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 124279#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 124280#L571 assume 1 == ~t3_pc~0; 124486#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 124487#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123619#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 123620#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 124434#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123704#L590 assume !(1 == ~t4_pc~0); 123705#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 124496#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123799#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 123800#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 124717#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 124431#L609 assume 1 == ~t5_pc~0; 124432#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 125034#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 124901#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 124902#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 124422#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 124423#L628 assume !(1 == ~t6_pc~0); 124353#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 124352#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 124225#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 124226#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 124762#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 124763#L647 assume 1 == ~t7_pc~0; 124259#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 124260#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 124910#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 124262#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 124263#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 125079#L666 assume !(1 == ~t8_pc~0); 124052#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 124053#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 124278#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 124456#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 124185#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 124186#L685 assume 1 == ~t9_pc~0; 125046#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 124920#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 124314#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 124214#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 124215#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 124619#L704 assume !(1 == ~t10_pc~0); 124205#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 124204#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 124477#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 123753#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 123754#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124012#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 124746#L1154-2 assume !(1 == ~T1_E~0); 123984#L1159-1 assume !(1 == ~T2_E~0); 123985#L1164-1 assume !(1 == ~T3_E~0); 125106#L1169-1 assume !(1 == ~T4_E~0); 130354#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 130352#L1179-1 assume !(1 == ~T6_E~0); 130350#L1184-1 assume !(1 == ~T7_E~0); 130347#L1189-1 assume !(1 == ~T8_E~0); 130345#L1194-1 assume !(1 == ~T9_E~0); 130343#L1199-1 assume !(1 == ~T10_E~0); 130341#L1204-1 assume !(1 == ~E_M~0); 130339#L1209-1 assume !(1 == ~E_1~0); 130337#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 130334#L1219-1 assume !(1 == ~E_3~0); 130332#L1224-1 assume !(1 == ~E_4~0); 130330#L1229-1 assume !(1 == ~E_5~0); 130328#L1234-1 assume !(1 == ~E_6~0); 130326#L1239-1 assume !(1 == ~E_7~0); 130325#L1244-1 assume !(1 == ~E_8~0); 128718#L1249-1 assume !(1 == ~E_9~0); 130320#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 130318#L1259-1 assume { :end_inline_reset_delta_events } true; 130316#L1565-2 [2024-11-13 15:24:35,321 INFO L747 eck$LassoCheckResult]: Loop: 130316#L1565-2 assume !false; 129651#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 129648#L1011-1 assume !false; 129646#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 129641#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 129629#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 129627#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 129624#L866 assume !(0 != eval_~tmp~0#1); 129625#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 139873#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 139872#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 139871#L1036-5 assume !(0 == ~T1_E~0); 139870#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 139868#L1046-3 assume !(0 == ~T3_E~0); 139867#L1051-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 139866#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 139863#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 139861#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 139859#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 139857#L1076-3 assume !(0 == ~T9_E~0); 139855#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 139853#L1086-3 assume !(0 == ~E_M~0); 139850#L1091-3 assume 0 == ~E_1~0;~E_1~0 := 1; 139848#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 139846#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 139844#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 139842#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 139840#L1116-3 assume !(0 == ~E_6~0); 139821#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 139820#L1126-3 assume !(0 == ~E_8~0); 139819#L1131-3 assume 0 == ~E_9~0;~E_9~0 := 1; 139818#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 139817#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 139814#L514-36 assume !(1 == ~m_pc~0); 139786#L514-38 is_master_triggered_~__retres1~0#1 := 0; 139489#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 132765#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 132762#L1285-36 assume !(0 != activate_threads_~tmp~1#1); 132758#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 132754#L533-36 assume !(1 == ~t1_pc~0); 132750#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 132745#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 132741#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 132737#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 132733#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 132729#L552-36 assume !(1 == ~t2_pc~0); 132725#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 132720#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132718#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 132716#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 132715#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 132714#L571-36 assume 1 == ~t3_pc~0; 132712#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 132711#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 132699#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 132697#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 132695#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 132692#L590-36 assume 1 == ~t4_pc~0; 132690#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 132687#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 132685#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 132683#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 132681#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 132679#L609-36 assume 1 == ~t5_pc~0; 132676#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 132674#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 132672#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 132670#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 132668#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 132666#L628-36 assume !(1 == ~t6_pc~0); 132663#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 132661#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 132659#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 132657#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 132655#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 132653#L647-36 assume 1 == ~t7_pc~0; 132650#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 132648#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 132646#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 132644#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 132642#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 132640#L666-36 assume 1 == ~t8_pc~0; 132638#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 132635#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 132633#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 132631#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 132629#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 132627#L685-36 assume 1 == ~t9_pc~0; 132624#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 132622#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 132619#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 132617#L1357-36 assume !(0 != activate_threads_~tmp___8~0#1); 132615#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 132613#L704-36 assume 1 == ~t10_pc~0; 132610#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 132608#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 132606#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 132604#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 132602#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 132600#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 130475#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 132595#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 132493#L1164-3 assume !(1 == ~T3_E~0); 132491#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 132489#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 132487#L1179-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 132484#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 132482#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 132480#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 132478#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 131537#L1204-3 assume !(1 == ~E_M~0); 131535#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 131532#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 131530#L1219-3 assume 1 == ~E_3~0;~E_3~0 := 2; 131528#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 131526#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 131524#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 131522#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 130428#L1244-3 assume !(1 == ~E_8~0); 130426#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 130424#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 130422#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 130405#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 130397#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 130395#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 130393#L1584 assume !(0 == start_simulation_~tmp~3#1); 130390#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 130384#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 130372#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 130370#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 130367#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 130365#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 130363#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 130317#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 130316#L1565-2 [2024-11-13 15:24:35,321 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:35,321 INFO L85 PathProgramCache]: Analyzing trace with hash 353984391, now seen corresponding path program 1 times [2024-11-13 15:24:35,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:35,321 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437382645] [2024-11-13 15:24:35,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:35,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:35,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:35,405 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:35,405 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:35,405 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [437382645] [2024-11-13 15:24:35,405 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [437382645] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:35,406 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:35,406 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:24:35,406 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [686981038] [2024-11-13 15:24:35,406 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:35,406 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:24:35,406 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:35,407 INFO L85 PathProgramCache]: Analyzing trace with hash 79935, now seen corresponding path program 1 times [2024-11-13 15:24:35,407 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:35,407 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2117683527] [2024-11-13 15:24:35,407 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:35,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:35,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:35,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:35,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:35,467 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2117683527] [2024-11-13 15:24:35,467 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2117683527] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:35,467 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:35,467 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:35,467 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [894448518] [2024-11-13 15:24:35,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:35,468 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:24:35,468 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:24:35,468 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:24:35,468 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:24:35,468 INFO L87 Difference]: Start difference. First operand 31505 states and 45681 transitions. cyclomatic complexity: 14208 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:36,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:24:36,091 INFO L93 Difference]: Finished difference Result 59948 states and 86522 transitions. [2024-11-13 15:24:36,092 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59948 states and 86522 transitions. [2024-11-13 15:24:36,445 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 59580 [2024-11-13 15:24:36,642 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59948 states to 59948 states and 86522 transitions. [2024-11-13 15:24:36,642 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 59948 [2024-11-13 15:24:36,689 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 59948 [2024-11-13 15:24:36,689 INFO L73 IsDeterministic]: Start isDeterministic. Operand 59948 states and 86522 transitions. [2024-11-13 15:24:36,761 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:24:36,761 INFO L218 hiAutomatonCegarLoop]: Abstraction has 59948 states and 86522 transitions. [2024-11-13 15:24:36,811 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59948 states and 86522 transitions. [2024-11-13 15:24:37,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59948 to 59884. [2024-11-13 15:24:37,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59884 states, 59884 states have (on average 1.4437579320018703) internal successors, (86458), 59883 states have internal predecessors, (86458), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:38,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59884 states to 59884 states and 86458 transitions. [2024-11-13 15:24:38,183 INFO L240 hiAutomatonCegarLoop]: Abstraction has 59884 states and 86458 transitions. [2024-11-13 15:24:38,184 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:24:38,185 INFO L424 stractBuchiCegarLoop]: Abstraction has 59884 states and 86458 transitions. [2024-11-13 15:24:38,185 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 15:24:38,185 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59884 states and 86458 transitions. [2024-11-13 15:24:38,509 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 59516 [2024-11-13 15:24:38,509 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:24:38,509 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:24:38,513 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:38,513 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:38,514 INFO L745 eck$LassoCheckResult]: Stem: 215484#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 215485#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 216416#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 216417#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 216491#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 216423#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 216373#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 216374#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 216409#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 215415#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 215416#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 215529#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 215775#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 215699#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 215417#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 215081#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 215082#L1036 assume !(0 == ~M_E~0); 215178#L1036-2 assume !(0 == ~T1_E~0); 216101#L1041-1 assume !(0 == ~T2_E~0); 216102#L1046-1 assume !(0 == ~T3_E~0); 215456#L1051-1 assume !(0 == ~T4_E~0); 215457#L1056-1 assume !(0 == ~T5_E~0); 216239#L1061-1 assume !(0 == ~T6_E~0); 215349#L1066-1 assume !(0 == ~T7_E~0); 215350#L1071-1 assume !(0 == ~T8_E~0); 216221#L1076-1 assume !(0 == ~T9_E~0); 215240#L1081-1 assume !(0 == ~T10_E~0); 215241#L1086-1 assume !(0 == ~E_M~0); 215645#L1091-1 assume !(0 == ~E_1~0); 216434#L1096-1 assume !(0 == ~E_2~0); 216435#L1101-1 assume !(0 == ~E_3~0); 215712#L1106-1 assume !(0 == ~E_4~0); 215713#L1111-1 assume !(0 == ~E_5~0); 215884#L1116-1 assume !(0 == ~E_6~0); 215885#L1121-1 assume !(0 == ~E_7~0); 215703#L1126-1 assume !(0 == ~E_8~0); 215704#L1131-1 assume !(0 == ~E_9~0); 215991#L1136-1 assume !(0 == ~E_10~0); 216109#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 216271#L514 assume !(1 == ~m_pc~0); 216272#L514-2 is_master_triggered_~__retres1~0#1 := 0; 215721#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 215722#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 216339#L1285 assume !(0 != activate_threads_~tmp~1#1); 216475#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 215368#L533 assume !(1 == ~t1_pc~0); 215369#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 215900#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 215133#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 215134#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 216134#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 216135#L552 assume !(1 == ~t2_pc~0); 215844#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 215845#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 215707#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 215708#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 215734#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 215735#L571 assume !(1 == ~t3_pc~0); 215960#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 216043#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 215079#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 215080#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 215889#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 215164#L590 assume !(1 == ~t4_pc~0); 215165#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 215949#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 215258#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 215259#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 216165#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 215886#L609 assume 1 == ~t5_pc~0; 215887#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 216473#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 216341#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 216342#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 215878#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 215879#L628 assume !(1 == ~t6_pc~0); 215807#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 215806#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 215680#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 215681#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 216201#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 216202#L647 assume 1 == ~t7_pc~0; 215714#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 215715#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 216352#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 215717#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 215718#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 216510#L666 assume !(1 == ~t8_pc~0); 215506#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 215507#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 215733#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 215914#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 215642#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 215643#L685 assume 1 == ~t9_pc~0; 216481#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 216361#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 215769#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 215671#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 215672#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 216071#L704 assume !(1 == ~t10_pc~0); 215662#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 215661#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 215932#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 215212#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 215213#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 215466#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 216188#L1154-2 assume !(1 == ~T1_E~0); 215439#L1159-1 assume !(1 == ~T2_E~0); 215440#L1164-1 assume !(1 == ~T3_E~0); 227044#L1169-1 assume !(1 == ~T4_E~0); 215770#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 215569#L1179-1 assume !(1 == ~T6_E~0); 215423#L1184-1 assume !(1 == ~T7_E~0); 215424#L1189-1 assume !(1 == ~T8_E~0); 215504#L1194-1 assume !(1 == ~T9_E~0); 215629#L1199-1 assume !(1 == ~T10_E~0); 215583#L1204-1 assume !(1 == ~E_M~0); 215584#L1209-1 assume !(1 == ~E_1~0); 268232#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 268230#L1219-1 assume !(1 == ~E_3~0); 268228#L1224-1 assume !(1 == ~E_4~0); 268226#L1229-1 assume !(1 == ~E_5~0); 268224#L1234-1 assume !(1 == ~E_6~0); 268222#L1239-1 assume !(1 == ~E_7~0); 215364#L1244-1 assume !(1 == ~E_8~0); 215365#L1249-1 assume !(1 == ~E_9~0); 216306#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 266759#L1259-1 assume { :end_inline_reset_delta_events } true; 266754#L1565-2 [2024-11-13 15:24:38,514 INFO L747 eck$LassoCheckResult]: Loop: 266754#L1565-2 assume !false; 266748#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 266746#L1011-1 assume !false; 266745#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 256417#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 256405#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 256403#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 256400#L866 assume !(0 != eval_~tmp~0#1); 256401#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 268321#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 268319#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 268318#L1036-5 assume !(0 == ~T1_E~0); 268317#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 268316#L1046-3 assume !(0 == ~T3_E~0); 268315#L1051-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 268314#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 268313#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 268312#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 268311#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 268310#L1076-3 assume !(0 == ~T9_E~0); 268308#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 268306#L1086-3 assume !(0 == ~E_M~0); 268304#L1091-3 assume 0 == ~E_1~0;~E_1~0 := 1; 268302#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 268300#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 268298#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 268296#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 268293#L1116-3 assume !(0 == ~E_6~0); 268291#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 268289#L1126-3 assume !(0 == ~E_8~0); 268287#L1131-3 assume 0 == ~E_9~0;~E_9~0 := 1; 268285#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 268283#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 268281#L514-36 assume !(1 == ~m_pc~0); 268279#L514-38 is_master_triggered_~__retres1~0#1 := 0; 268277#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 268275#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 268273#L1285-36 assume !(0 != activate_threads_~tmp~1#1); 268271#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 268269#L533-36 assume 1 == ~t1_pc~0; 268266#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 268264#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 268262#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 268260#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 268258#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 268255#L552-36 assume !(1 == ~t2_pc~0); 268253#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 268153#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 268143#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 268134#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 268119#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 268108#L571-36 assume !(1 == ~t3_pc~0); 268102#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 268098#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 268093#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 268086#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 268080#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 268072#L590-36 assume !(1 == ~t4_pc~0); 268064#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 268058#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 268053#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 266448#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 266374#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 266369#L609-36 assume 1 == ~t5_pc~0; 266370#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 267594#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 267592#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 267590#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 267588#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 267586#L628-36 assume 1 == ~t6_pc~0; 267584#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 267581#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 267579#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 267577#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 267575#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 267573#L647-36 assume 1 == ~t7_pc~0; 267569#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 267567#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 267565#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 267563#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 267561#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 267559#L666-36 assume 1 == ~t8_pc~0; 267556#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 267553#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 267551#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 267549#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 267547#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 267545#L685-36 assume 1 == ~t9_pc~0; 267541#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 267539#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 267537#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 267535#L1357-36 assume !(0 != activate_threads_~tmp___8~0#1); 267533#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 267531#L704-36 assume 1 == ~t10_pc~0; 267527#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 267525#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 267523#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 267521#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 267519#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 267517#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 216885#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 267513#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 267511#L1164-3 assume !(1 == ~T3_E~0); 262090#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 267508#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 267506#L1179-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 267503#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 267501#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 267499#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 267497#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 267495#L1204-3 assume !(1 == ~E_M~0); 241237#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 267491#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 267489#L1219-3 assume 1 == ~E_3~0;~E_3~0 := 2; 267487#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 267485#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 267483#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 267482#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 267481#L1244-3 assume !(1 == ~E_8~0); 216838#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 267480#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 267479#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 267474#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 267467#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 267466#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 267465#L1584 assume !(0 == start_simulation_~tmp~3#1); 216530#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 267464#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 267450#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 267448#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 267446#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 267445#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 267442#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 266758#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 266754#L1565-2 [2024-11-13 15:24:38,515 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:38,515 INFO L85 PathProgramCache]: Analyzing trace with hash -1601336824, now seen corresponding path program 1 times [2024-11-13 15:24:38,515 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:38,515 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2105182555] [2024-11-13 15:24:38,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:38,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:38,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:38,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:38,619 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:38,619 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2105182555] [2024-11-13 15:24:38,619 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2105182555] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:38,619 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:38,619 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:24:38,619 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1201867194] [2024-11-13 15:24:38,620 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:38,620 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:24:38,620 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:38,620 INFO L85 PathProgramCache]: Analyzing trace with hash 802019391, now seen corresponding path program 1 times [2024-11-13 15:24:38,620 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:38,620 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [820302986] [2024-11-13 15:24:38,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:38,620 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:38,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:38,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:38,694 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:38,695 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [820302986] [2024-11-13 15:24:38,695 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [820302986] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:38,695 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:38,695 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:38,695 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [124001092] [2024-11-13 15:24:38,695 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:38,695 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:24:38,695 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:24:38,695 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:24:38,696 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:24:38,696 INFO L87 Difference]: Start difference. First operand 59884 states and 86458 transitions. cyclomatic complexity: 26638 Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:39,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:24:39,312 INFO L93 Difference]: Finished difference Result 61735 states and 88309 transitions. [2024-11-13 15:24:39,312 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61735 states and 88309 transitions. [2024-11-13 15:24:39,660 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 61364 [2024-11-13 15:24:39,856 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61735 states to 61735 states and 88309 transitions. [2024-11-13 15:24:39,856 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61735 [2024-11-13 15:24:39,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61735 [2024-11-13 15:24:39,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61735 states and 88309 transitions. [2024-11-13 15:24:39,924 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:24:39,924 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61735 states and 88309 transitions. [2024-11-13 15:24:39,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61735 states and 88309 transitions. [2024-11-13 15:24:40,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61735 to 61735. [2024-11-13 15:24:40,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61735 states, 61735 states have (on average 1.4304527415566535) internal successors, (88309), 61734 states have internal predecessors, (88309), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:41,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61735 states to 61735 states and 88309 transitions. [2024-11-13 15:24:41,037 INFO L240 hiAutomatonCegarLoop]: Abstraction has 61735 states and 88309 transitions. [2024-11-13 15:24:41,037 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:24:41,038 INFO L424 stractBuchiCegarLoop]: Abstraction has 61735 states and 88309 transitions. [2024-11-13 15:24:41,038 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 15:24:41,038 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61735 states and 88309 transitions. [2024-11-13 15:24:41,415 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 61364 [2024-11-13 15:24:41,415 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:24:41,416 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:24:41,418 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:41,418 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:41,418 INFO L745 eck$LassoCheckResult]: Stem: 337118#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 337119#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 338121#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 338122#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 338218#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 338128#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 338064#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 338065#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 338112#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 337047#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 337048#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 337163#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 337415#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 337339#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 337049#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 336709#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 336710#L1036 assume !(0 == ~M_E~0); 336806#L1036-2 assume !(0 == ~T1_E~0); 337758#L1041-1 assume !(0 == ~T2_E~0); 337759#L1046-1 assume !(0 == ~T3_E~0); 337091#L1051-1 assume !(0 == ~T4_E~0); 337092#L1056-1 assume !(0 == ~T5_E~0); 337906#L1061-1 assume !(0 == ~T6_E~0); 336979#L1066-1 assume !(0 == ~T7_E~0); 336980#L1071-1 assume !(0 == ~T8_E~0); 337888#L1076-1 assume !(0 == ~T9_E~0); 336869#L1081-1 assume !(0 == ~T10_E~0); 336870#L1086-1 assume !(0 == ~E_M~0); 337281#L1091-1 assume !(0 == ~E_1~0); 338139#L1096-1 assume !(0 == ~E_2~0); 338140#L1101-1 assume !(0 == ~E_3~0); 337352#L1106-1 assume !(0 == ~E_4~0); 337353#L1111-1 assume !(0 == ~E_5~0); 337530#L1116-1 assume !(0 == ~E_6~0); 337531#L1121-1 assume !(0 == ~E_7~0); 337343#L1126-1 assume !(0 == ~E_8~0); 337344#L1131-1 assume !(0 == ~E_9~0); 337641#L1136-1 assume !(0 == ~E_10~0); 337771#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 337939#L514 assume !(1 == ~m_pc~0); 337940#L514-2 is_master_triggered_~__retres1~0#1 := 0; 337361#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 337362#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 338019#L1285 assume !(0 != activate_threads_~tmp~1#1); 338191#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 336999#L533 assume !(1 == ~t1_pc~0); 337000#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 337548#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 336761#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 336762#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 337797#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 337798#L552 assume !(1 == ~t2_pc~0); 337489#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 337490#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 337347#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 337348#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 337376#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 337377#L571 assume !(1 == ~t3_pc~0); 337609#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 337694#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 336707#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 336708#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 337537#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 336792#L590 assume !(1 == ~t4_pc~0); 336793#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 337608#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 338300#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 338198#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 337828#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 337532#L609 assume 1 == ~t5_pc~0; 337533#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 338189#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 338023#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 338024#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 337523#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 337524#L628 assume !(1 == ~t6_pc~0); 337449#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 337448#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 337318#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 337319#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 337868#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 337869#L647 assume 1 == ~t7_pc~0; 337354#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 337355#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 338035#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 337357#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 337358#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 338249#L666 assume !(1 == ~t8_pc~0); 337140#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 337141#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 337375#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 337560#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 337278#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 337279#L685 assume 1 == ~t9_pc~0; 338202#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 338050#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 337409#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 337307#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 337308#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 337726#L704 assume !(1 == ~t10_pc~0); 337298#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 337297#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 337578#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 336841#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 336842#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 337100#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 337855#L1154-2 assume !(1 == ~T1_E~0); 337070#L1159-1 assume !(1 == ~T2_E~0); 337071#L1164-1 assume !(1 == ~T3_E~0); 339995#L1169-1 assume !(1 == ~T4_E~0); 339994#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 339993#L1179-1 assume !(1 == ~T6_E~0); 339462#L1184-1 assume !(1 == ~T7_E~0); 339460#L1189-1 assume !(1 == ~T8_E~0); 339458#L1194-1 assume !(1 == ~T9_E~0); 339456#L1199-1 assume !(1 == ~T10_E~0); 339454#L1204-1 assume !(1 == ~E_M~0); 339451#L1209-1 assume !(1 == ~E_1~0); 339449#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 339447#L1219-1 assume !(1 == ~E_3~0); 339445#L1224-1 assume !(1 == ~E_4~0); 339443#L1229-1 assume !(1 == ~E_5~0); 339441#L1234-1 assume !(1 == ~E_6~0); 339438#L1239-1 assume !(1 == ~E_7~0); 339436#L1244-1 assume !(1 == ~E_8~0); 339432#L1249-1 assume !(1 == ~E_9~0); 339430#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 339429#L1259-1 assume { :end_inline_reset_delta_events } true; 339425#L1565-2 [2024-11-13 15:24:41,419 INFO L747 eck$LassoCheckResult]: Loop: 339425#L1565-2 assume !false; 339069#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 339066#L1011-1 assume !false; 339063#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 339026#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 339014#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 339012#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 339009#L866 assume !(0 != eval_~tmp~0#1); 339010#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 343998#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 343996#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 343994#L1036-5 assume !(0 == ~T1_E~0); 343992#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 343990#L1046-3 assume !(0 == ~T3_E~0); 343988#L1051-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 343986#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 343984#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 343982#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 343980#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 343978#L1076-3 assume !(0 == ~T9_E~0); 343976#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 343974#L1086-3 assume !(0 == ~E_M~0); 343972#L1091-3 assume 0 == ~E_1~0;~E_1~0 := 1; 343970#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 343968#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 343966#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 343964#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 343962#L1116-3 assume !(0 == ~E_6~0); 343960#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 343958#L1126-3 assume !(0 == ~E_8~0); 343956#L1131-3 assume 0 == ~E_9~0;~E_9~0 := 1; 343954#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 343952#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 343950#L514-36 assume !(1 == ~m_pc~0); 343948#L514-38 is_master_triggered_~__retres1~0#1 := 0; 343946#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 343944#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 343942#L1285-36 assume !(0 != activate_threads_~tmp~1#1); 343940#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 343938#L533-36 assume !(1 == ~t1_pc~0); 343936#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 343932#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 343930#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 343928#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 343926#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 343924#L552-36 assume !(1 == ~t2_pc~0); 343922#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 343920#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 343918#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 343916#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 343914#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 343912#L571-36 assume !(1 == ~t3_pc~0); 343910#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 343908#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 343906#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 343904#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 343902#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 343900#L590-36 assume !(1 == ~t4_pc~0); 343894#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 343892#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 343890#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 343888#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 343884#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 343882#L609-36 assume 1 == ~t5_pc~0; 343879#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 343876#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 343874#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 343872#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 343870#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 343868#L628-36 assume !(1 == ~t6_pc~0); 343865#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 343862#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 343860#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 343858#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 343856#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 343854#L647-36 assume !(1 == ~t7_pc~0); 343852#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 343848#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 343846#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 343844#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 343842#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 343840#L666-36 assume !(1 == ~t8_pc~0); 343837#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 343834#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 343832#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 343830#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 343828#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 343826#L685-36 assume !(1 == ~t9_pc~0); 343824#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 343820#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 343818#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 343816#L1357-36 assume !(0 != activate_threads_~tmp___8~0#1); 343814#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 343812#L704-36 assume 1 == ~t10_pc~0; 343809#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 343806#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 343804#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 343802#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 343800#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 343798#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 341542#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 343795#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 343791#L1164-3 assume !(1 == ~T3_E~0); 343790#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 343789#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 343787#L1179-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 343786#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 343785#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 343784#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 343783#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 342831#L1204-3 assume !(1 == ~E_M~0); 342828#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 342826#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 342824#L1219-3 assume 1 == ~E_3~0;~E_3~0 := 2; 342822#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 342820#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 342819#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 342815#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 342436#L1244-3 assume !(1 == ~E_8~0); 342433#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 342431#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 342429#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 342250#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 342241#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 340153#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 340148#L1584 assume !(0 == start_simulation_~tmp~3#1); 340145#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 339642#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 339630#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 339628#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 339626#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 339624#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 339623#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 339428#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 339425#L1565-2 [2024-11-13 15:24:41,419 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:41,420 INFO L85 PathProgramCache]: Analyzing trace with hash 360237834, now seen corresponding path program 1 times [2024-11-13 15:24:41,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:41,420 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [172597405] [2024-11-13 15:24:41,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:41,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:41,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:41,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:41,536 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:41,536 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [172597405] [2024-11-13 15:24:41,536 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [172597405] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:41,536 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:41,537 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:24:41,537 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1958930627] [2024-11-13 15:24:41,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:41,537 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:24:41,537 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:41,538 INFO L85 PathProgramCache]: Analyzing trace with hash 237958982, now seen corresponding path program 1 times [2024-11-13 15:24:41,538 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:41,538 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [7696028] [2024-11-13 15:24:41,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:41,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:41,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:41,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:41,624 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:41,624 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [7696028] [2024-11-13 15:24:41,625 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [7696028] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:41,625 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:41,625 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:24:41,625 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1930027828] [2024-11-13 15:24:41,626 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:41,626 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:24:41,626 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:24:41,626 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:24:41,626 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:24:41,627 INFO L87 Difference]: Start difference. First operand 61735 states and 88309 transitions. cyclomatic complexity: 26638 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:42,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:24:42,213 INFO L93 Difference]: Finished difference Result 117490 states and 167414 transitions. [2024-11-13 15:24:42,213 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117490 states and 167414 transitions. [2024-11-13 15:24:42,781 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 116832 [2024-11-13 15:24:43,212 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117490 states to 117490 states and 167414 transitions. [2024-11-13 15:24:43,212 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117490 [2024-11-13 15:24:43,291 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117490 [2024-11-13 15:24:43,291 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117490 states and 167414 transitions. [2024-11-13 15:24:43,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:24:43,396 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117490 states and 167414 transitions. [2024-11-13 15:24:43,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117490 states and 167414 transitions. [2024-11-13 15:24:44,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117490 to 117362. [2024-11-13 15:24:44,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117362 states, 117362 states have (on average 1.4253847071454133) internal successors, (167286), 117361 states have internal predecessors, (167286), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:45,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117362 states to 117362 states and 167286 transitions. [2024-11-13 15:24:45,190 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117362 states and 167286 transitions. [2024-11-13 15:24:45,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:24:45,191 INFO L424 stractBuchiCegarLoop]: Abstraction has 117362 states and 167286 transitions. [2024-11-13 15:24:45,191 INFO L331 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-13 15:24:45,191 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117362 states and 167286 transitions. [2024-11-13 15:24:45,466 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 116704 [2024-11-13 15:24:45,466 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:24:45,466 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:24:45,468 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:45,468 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:45,468 INFO L745 eck$LassoCheckResult]: Stem: 516348#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 516349#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 517314#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 517315#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 517403#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 517320#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 517262#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 517263#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 517307#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 516280#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 516281#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 516392#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 516640#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 516564#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 516282#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 515943#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 515944#L1036 assume !(0 == ~M_E~0); 516039#L1036-2 assume !(0 == ~T1_E~0); 516969#L1041-1 assume !(0 == ~T2_E~0); 516970#L1046-1 assume !(0 == ~T3_E~0); 516323#L1051-1 assume !(0 == ~T4_E~0); 516324#L1056-1 assume !(0 == ~T5_E~0); 517120#L1061-1 assume !(0 == ~T6_E~0); 516212#L1066-1 assume !(0 == ~T7_E~0); 516213#L1071-1 assume !(0 == ~T8_E~0); 517098#L1076-1 assume !(0 == ~T9_E~0); 516102#L1081-1 assume !(0 == ~T10_E~0); 516103#L1086-1 assume !(0 == ~E_M~0); 516508#L1091-1 assume !(0 == ~E_1~0); 517330#L1096-1 assume !(0 == ~E_2~0); 517331#L1101-1 assume !(0 == ~E_3~0); 516578#L1106-1 assume !(0 == ~E_4~0); 516579#L1111-1 assume !(0 == ~E_5~0); 516751#L1116-1 assume !(0 == ~E_6~0); 516752#L1121-1 assume !(0 == ~E_7~0); 516568#L1126-1 assume !(0 == ~E_8~0); 516569#L1131-1 assume !(0 == ~E_9~0); 516857#L1136-1 assume !(0 == ~E_10~0); 516980#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 517152#L514 assume !(1 == ~m_pc~0); 517153#L514-2 is_master_triggered_~__retres1~0#1 := 0; 516587#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 516588#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 517226#L1285 assume !(0 != activate_threads_~tmp~1#1); 517380#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 516232#L533 assume !(1 == ~t1_pc~0); 516233#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 516768#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 515995#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 515996#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 517004#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 517005#L552 assume !(1 == ~t2_pc~0); 516710#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 516711#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 516572#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 516573#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 516600#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 516601#L571 assume !(1 == ~t3_pc~0); 516826#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 516909#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 515941#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 515942#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 516757#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 516025#L590 assume !(1 == ~t4_pc~0); 516026#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 516825#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 517470#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 517386#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 517036#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 516753#L609 assume !(1 == ~t5_pc~0); 516754#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 517378#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 517229#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 517230#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 516745#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 516746#L628 assume !(1 == ~t6_pc~0); 516673#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 516672#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 516545#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 516546#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 517076#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 517077#L647 assume 1 == ~t7_pc~0; 516580#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 516581#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 517242#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 516583#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 516584#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 517423#L666 assume !(1 == ~t8_pc~0); 516370#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 516371#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 516599#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 516779#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 516505#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 516506#L685 assume 1 == ~t9_pc~0; 517392#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 517251#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 516634#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 516536#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 516537#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 516940#L704 assume !(1 == ~t10_pc~0); 516526#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 516525#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 516797#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 516074#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 516075#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 516332#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 517061#L1154-2 assume !(1 == ~T1_E~0); 520869#L1159-1 assume !(1 == ~T2_E~0); 520867#L1164-1 assume !(1 == ~T3_E~0); 520865#L1169-1 assume !(1 == ~T4_E~0); 520864#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 520861#L1179-1 assume !(1 == ~T6_E~0); 520860#L1184-1 assume !(1 == ~T7_E~0); 520857#L1189-1 assume !(1 == ~T8_E~0); 520856#L1194-1 assume !(1 == ~T9_E~0); 520855#L1199-1 assume !(1 == ~T10_E~0); 520853#L1204-1 assume !(1 == ~E_M~0); 520850#L1209-1 assume !(1 == ~E_1~0); 520848#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 520846#L1219-1 assume !(1 == ~E_3~0); 520844#L1224-1 assume !(1 == ~E_4~0); 520842#L1229-1 assume !(1 == ~E_5~0); 520840#L1234-1 assume !(1 == ~E_6~0); 520837#L1239-1 assume !(1 == ~E_7~0); 520835#L1244-1 assume !(1 == ~E_8~0); 520832#L1249-1 assume !(1 == ~E_9~0); 520830#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 520829#L1259-1 assume { :end_inline_reset_delta_events } true; 520825#L1565-2 [2024-11-13 15:24:45,469 INFO L747 eck$LassoCheckResult]: Loop: 520825#L1565-2 assume !false; 520421#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 520418#L1011-1 assume !false; 520417#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 519681#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 519669#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 519666#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 519663#L866 assume !(0 != eval_~tmp~0#1); 519664#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 537448#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 537446#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 537444#L1036-5 assume !(0 == ~T1_E~0); 537442#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 537440#L1046-3 assume !(0 == ~T3_E~0); 537438#L1051-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 537436#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 536853#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 527563#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 522927#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 522924#L1076-3 assume !(0 == ~T9_E~0); 522922#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 522920#L1086-3 assume !(0 == ~E_M~0); 522918#L1091-3 assume 0 == ~E_1~0;~E_1~0 := 1; 522916#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 522914#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 522911#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 522909#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 522907#L1116-3 assume !(0 == ~E_6~0); 522905#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 522903#L1126-3 assume !(0 == ~E_8~0); 522901#L1131-3 assume 0 == ~E_9~0;~E_9~0 := 1; 522899#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 522897#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 522894#L514-36 assume !(1 == ~m_pc~0); 522892#L514-38 is_master_triggered_~__retres1~0#1 := 0; 522890#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 522888#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 522886#L1285-36 assume !(0 != activate_threads_~tmp~1#1); 522884#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 522882#L533-36 assume !(1 == ~t1_pc~0); 522880#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 522876#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 522874#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 522872#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 522870#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 522868#L552-36 assume !(1 == ~t2_pc~0); 522866#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 522864#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 522862#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 522860#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 522858#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 522856#L571-36 assume !(1 == ~t3_pc~0); 522854#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 522852#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 522850#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 522848#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 522846#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 522844#L590-36 assume 1 == ~t4_pc~0; 522842#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 522843#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 527334#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 522832#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 522831#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 522828#L609-36 assume !(1 == ~t5_pc~0); 522826#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 522824#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 522822#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 522820#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 522818#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 522816#L628-36 assume 1 == ~t6_pc~0; 522814#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 522811#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 522808#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 522806#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 522804#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 522802#L647-36 assume !(1 == ~t7_pc~0); 522799#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 522795#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 522793#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 522791#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 522789#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 522787#L666-36 assume 1 == ~t8_pc~0; 522785#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 522781#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 522779#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 522777#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 522775#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 522773#L685-36 assume !(1 == ~t9_pc~0); 522771#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 522767#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 522765#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 522763#L1357-36 assume !(0 != activate_threads_~tmp___8~0#1); 522761#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 522759#L704-36 assume !(1 == ~t10_pc~0); 522757#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 522753#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 522751#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 522749#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 522747#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 522745#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 521538#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 522740#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 522736#L1164-3 assume !(1 == ~T3_E~0); 522735#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 522734#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 522733#L1179-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 522732#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 522731#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 522730#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 522729#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 522725#L1204-3 assume !(1 == ~E_M~0); 522723#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 522721#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 522719#L1219-3 assume 1 == ~E_3~0;~E_3~0 := 2; 522717#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 522714#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 522712#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 522710#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 521492#L1244-3 assume !(1 == ~E_8~0); 521490#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 521488#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 521486#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 521473#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 521465#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 521463#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 521462#L1584 assume !(0 == start_simulation_~tmp~3#1); 521460#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 521457#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 521446#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 521444#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 521443#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 521442#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 521436#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 520828#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 520825#L1565-2 [2024-11-13 15:24:45,469 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:45,469 INFO L85 PathProgramCache]: Analyzing trace with hash -671092981, now seen corresponding path program 1 times [2024-11-13 15:24:45,469 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:45,469 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [728660265] [2024-11-13 15:24:45,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:45,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:45,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:45,562 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:45,562 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:45,562 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [728660265] [2024-11-13 15:24:45,562 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [728660265] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:45,562 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:45,562 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:45,562 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2076215409] [2024-11-13 15:24:45,562 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:45,563 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:24:45,563 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:45,563 INFO L85 PathProgramCache]: Analyzing trace with hash 1446955075, now seen corresponding path program 1 times [2024-11-13 15:24:45,563 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:45,563 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1322362578] [2024-11-13 15:24:45,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:45,564 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:45,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:45,983 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:45,984 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:45,984 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1322362578] [2024-11-13 15:24:45,984 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1322362578] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:45,984 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:45,984 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:45,984 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2095865986] [2024-11-13 15:24:45,984 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:45,985 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:24:45,985 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:24:45,985 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:24:45,985 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:24:45,985 INFO L87 Difference]: Start difference. First operand 117362 states and 167286 transitions. cyclomatic complexity: 50052 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:47,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:24:47,609 INFO L93 Difference]: Finished difference Result 282357 states and 399839 transitions. [2024-11-13 15:24:47,609 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 282357 states and 399839 transitions. [2024-11-13 15:24:48,567 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 280612 [2024-11-13 15:24:49,517 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 282357 states to 282357 states and 399839 transitions. [2024-11-13 15:24:49,517 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 282357 [2024-11-13 15:24:49,654 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 282357 [2024-11-13 15:24:49,654 INFO L73 IsDeterministic]: Start isDeterministic. Operand 282357 states and 399839 transitions. [2024-11-13 15:24:49,746 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:24:49,746 INFO L218 hiAutomatonCegarLoop]: Abstraction has 282357 states and 399839 transitions. [2024-11-13 15:24:49,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282357 states and 399839 transitions. [2024-11-13 15:24:51,743 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282357 to 227905. [2024-11-13 15:24:51,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 227905 states, 227905 states have (on average 1.4191307781751168) internal successors, (323427), 227904 states have internal predecessors, (323427), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:52,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227905 states to 227905 states and 323427 transitions. [2024-11-13 15:24:52,980 INFO L240 hiAutomatonCegarLoop]: Abstraction has 227905 states and 323427 transitions. [2024-11-13 15:24:52,981 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:24:52,981 INFO L424 stractBuchiCegarLoop]: Abstraction has 227905 states and 323427 transitions. [2024-11-13 15:24:52,982 INFO L331 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-13 15:24:52,982 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 227905 states and 323427 transitions. [2024-11-13 15:24:53,529 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 226800 [2024-11-13 15:24:53,529 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:24:53,529 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:24:53,531 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:53,531 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:24:53,532 INFO L745 eck$LassoCheckResult]: Stem: 916070#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 916071#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 917116#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 917117#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 917224#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 917123#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 917058#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 917059#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 917103#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 916002#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 916003#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 916118#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 916379#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 916297#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 916004#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 915672#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 915673#L1036 assume !(0 == ~M_E~0); 915768#L1036-2 assume !(0 == ~T1_E~0); 916729#L1041-1 assume !(0 == ~T2_E~0); 916730#L1046-1 assume !(0 == ~T3_E~0); 916045#L1051-1 assume !(0 == ~T4_E~0); 916046#L1056-1 assume !(0 == ~T5_E~0); 916900#L1061-1 assume !(0 == ~T6_E~0); 915937#L1066-1 assume !(0 == ~T7_E~0); 915938#L1071-1 assume !(0 == ~T8_E~0); 916880#L1076-1 assume !(0 == ~T9_E~0); 915828#L1081-1 assume !(0 == ~T10_E~0); 915829#L1086-1 assume !(0 == ~E_M~0); 916238#L1091-1 assume !(0 == ~E_1~0); 917136#L1096-1 assume !(0 == ~E_2~0); 917137#L1101-1 assume !(0 == ~E_3~0); 916312#L1106-1 assume !(0 == ~E_4~0); 916313#L1111-1 assume !(0 == ~E_5~0); 916501#L1116-1 assume !(0 == ~E_6~0); 916502#L1121-1 assume !(0 == ~E_7~0); 916301#L1126-1 assume !(0 == ~E_8~0); 916302#L1131-1 assume !(0 == ~E_9~0); 916612#L1136-1 assume !(0 == ~E_10~0); 916737#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 916935#L514 assume !(1 == ~m_pc~0); 916936#L514-2 is_master_triggered_~__retres1~0#1 := 0; 916318#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 916319#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 917015#L1285 assume !(0 != activate_threads_~tmp~1#1); 917192#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 915956#L533 assume !(1 == ~t1_pc~0); 915957#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 916517#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 915724#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 915725#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 916766#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 916767#L552 assume !(1 == ~t2_pc~0); 916460#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 916461#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 916305#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 916306#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 916331#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 916332#L571 assume !(1 == ~t3_pc~0); 916581#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 916666#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 915670#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 915671#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 916506#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 915754#L590 assume !(1 == ~t4_pc~0); 915755#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 916580#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 917342#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 917199#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 916803#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 916503#L609 assume !(1 == ~t5_pc~0); 916504#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 917190#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 917019#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 917020#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 916495#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 916496#L628 assume !(1 == ~t6_pc~0); 916411#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 916410#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 916277#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 916278#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 916853#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 916854#L647 assume !(1 == ~t7_pc~0); 916996#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 917032#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 917033#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 916314#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 916315#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 917266#L666 assume !(1 == ~t8_pc~0); 916096#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 916097#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 916330#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 916529#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 916235#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 916236#L685 assume 1 == ~t9_pc~0; 917206#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 917041#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 916371#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 916266#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 916267#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 916698#L704 assume !(1 == ~t10_pc~0); 916257#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 916256#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 916548#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 915801#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 915802#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 916054#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 916834#L1154-2 assume !(1 == ~T1_E~0); 917235#L1159-1 assume !(1 == ~T2_E~0); 917305#L1164-1 assume !(1 == ~T3_E~0); 917306#L1169-1 assume !(1 == ~T4_E~0); 916372#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 916373#L1179-1 assume !(1 == ~T6_E~0); 916008#L1184-1 assume !(1 == ~T7_E~0); 916009#L1189-1 assume !(1 == ~T8_E~0); 916220#L1194-1 assume !(1 == ~T9_E~0); 916221#L1199-1 assume !(1 == ~T10_E~0); 916174#L1204-1 assume !(1 == ~E_M~0); 916175#L1209-1 assume !(1 == ~E_1~0); 916797#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 916798#L1219-1 assume !(1 == ~E_3~0); 917242#L1224-1 assume !(1 == ~E_4~0); 916553#L1229-1 assume !(1 == ~E_5~0); 915896#L1234-1 assume !(1 == ~E_6~0); 915897#L1239-1 assume !(1 == ~E_7~0); 915952#L1244-1 assume !(1 == ~E_8~0); 915953#L1249-1 assume !(1 == ~E_9~0); 1020548#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1020547#L1259-1 assume { :end_inline_reset_delta_events } true; 1020534#L1565-2 [2024-11-13 15:24:53,532 INFO L747 eck$LassoCheckResult]: Loop: 1020534#L1565-2 assume !false; 1020523#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1020305#L1011-1 assume !false; 1020279#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1003534#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1003523#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1003522#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1003520#L866 assume !(0 != eval_~tmp~0#1); 1003521#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1024036#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1024034#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1024031#L1036-5 assume !(0 == ~T1_E~0); 1024029#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1024027#L1046-3 assume !(0 == ~T3_E~0); 1024021#L1051-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1024015#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1024010#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1024005#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1024000#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1023995#L1076-3 assume !(0 == ~T9_E~0); 1023989#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1023984#L1086-3 assume !(0 == ~E_M~0); 1023979#L1091-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1023972#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1023966#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1023960#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1023955#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1023950#L1116-3 assume !(0 == ~E_6~0); 1023945#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1023941#L1126-3 assume !(0 == ~E_8~0); 1023936#L1131-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1023931#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1023925#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1023919#L514-36 assume !(1 == ~m_pc~0); 1023913#L514-38 is_master_triggered_~__retres1~0#1 := 0; 1023905#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1023899#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1023895#L1285-36 assume !(0 != activate_threads_~tmp~1#1); 1023890#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1023886#L533-36 assume !(1 == ~t1_pc~0); 1023881#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1023875#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1023870#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1023865#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1023859#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1023853#L552-36 assume !(1 == ~t2_pc~0); 1023848#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1023841#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1023836#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1023829#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1023825#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1023823#L571-36 assume !(1 == ~t3_pc~0); 1023822#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1023821#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1023820#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1023819#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1023818#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1023817#L590-36 assume 1 == ~t4_pc~0; 1023815#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1023816#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1023814#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1023808#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1023806#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1023804#L609-36 assume !(1 == ~t5_pc~0); 1023802#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1023800#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1023798#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1023796#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1023793#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1023791#L628-36 assume 1 == ~t6_pc~0; 1023787#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1023784#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1023782#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1023780#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1023778#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1023776#L647-36 assume !(1 == ~t7_pc~0); 943833#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1023773#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1023771#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1023768#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1023753#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1023749#L666-36 assume 1 == ~t8_pc~0; 1023745#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1023740#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1021931#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1021930#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1021929#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1021928#L685-36 assume !(1 == ~t9_pc~0); 1021926#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1021923#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1021921#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1021919#L1357-36 assume !(0 != activate_threads_~tmp___8~0#1); 1021916#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1021914#L704-36 assume !(1 == ~t10_pc~0); 1021912#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1021909#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1021907#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1021905#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1021902#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1021900#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 984489#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1021897#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1021895#L1164-3 assume !(1 == ~T3_E~0); 1021477#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1021892#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1021890#L1179-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1021888#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1021886#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1021884#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1021882#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1021880#L1204-3 assume !(1 == ~E_M~0); 994230#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1021877#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1021875#L1219-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1021873#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1021871#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1021869#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1021867#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1021865#L1244-3 assume !(1 == ~E_8~0); 984445#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1021862#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1021051#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1020959#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1020946#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1020941#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1020934#L1584 assume !(0 == start_simulation_~tmp~3#1); 1020928#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1020573#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1020561#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1020558#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1020556#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1020554#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1020552#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1020546#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 1020534#L1565-2 [2024-11-13 15:24:53,533 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:53,533 INFO L85 PathProgramCache]: Analyzing trace with hash 1730432140, now seen corresponding path program 1 times [2024-11-13 15:24:53,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:53,533 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1592292311] [2024-11-13 15:24:53,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:53,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:53,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:53,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:53,635 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:53,635 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1592292311] [2024-11-13 15:24:53,635 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1592292311] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:53,635 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:53,635 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:24:53,635 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [677678319] [2024-11-13 15:24:53,635 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:53,636 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:24:53,637 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:24:53,637 INFO L85 PathProgramCache]: Analyzing trace with hash 1446955075, now seen corresponding path program 2 times [2024-11-13 15:24:53,637 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:24:53,637 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [114318543] [2024-11-13 15:24:53,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:24:53,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:24:53,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:24:53,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:24:53,711 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:24:53,711 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [114318543] [2024-11-13 15:24:53,711 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [114318543] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:24:53,711 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:24:53,711 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:24:53,711 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2007064737] [2024-11-13 15:24:53,711 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:24:53,712 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:24:53,712 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:24:53,713 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:24:53,714 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:24:53,714 INFO L87 Difference]: Start difference. First operand 227905 states and 323427 transitions. cyclomatic complexity: 95650 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:24:55,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:24:55,877 INFO L93 Difference]: Finished difference Result 432976 states and 612432 transitions. [2024-11-13 15:24:55,877 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 432976 states and 612432 transitions. [2024-11-13 15:24:58,049 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 430464 [2024-11-13 15:24:59,581 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 432976 states to 432976 states and 612432 transitions. [2024-11-13 15:24:59,581 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 432976 [2024-11-13 15:24:59,740 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 432976 [2024-11-13 15:24:59,740 INFO L73 IsDeterministic]: Start isDeterministic. Operand 432976 states and 612432 transitions. [2024-11-13 15:24:59,909 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:24:59,909 INFO L218 hiAutomatonCegarLoop]: Abstraction has 432976 states and 612432 transitions. [2024-11-13 15:25:00,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 432976 states and 612432 transitions. [2024-11-13 15:25:03,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 432976 to 432464. [2024-11-13 15:25:03,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 432464 states, 432464 states have (on average 1.414961707795331) internal successors, (611920), 432463 states have internal predecessors, (611920), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:25:05,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 432464 states to 432464 states and 611920 transitions. [2024-11-13 15:25:05,707 INFO L240 hiAutomatonCegarLoop]: Abstraction has 432464 states and 611920 transitions. [2024-11-13 15:25:05,708 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:25:05,708 INFO L424 stractBuchiCegarLoop]: Abstraction has 432464 states and 611920 transitions. [2024-11-13 15:25:05,708 INFO L331 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-13 15:25:05,708 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 432464 states and 611920 transitions. [2024-11-13 15:25:07,258 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 429952 [2024-11-13 15:25:07,258 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:25:07,258 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:25:07,260 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:25:07,260 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:25:07,261 INFO L745 eck$LassoCheckResult]: Stem: 1576959#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1576960#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1578026#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1578027#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1578155#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 1578037#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1577963#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1577964#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1578014#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1576893#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1576894#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1577006#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1577259#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1577181#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1576895#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1576560#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1576561#L1036 assume !(0 == ~M_E~0); 1576656#L1036-2 assume !(0 == ~T1_E~0); 1577609#L1041-1 assume !(0 == ~T2_E~0); 1577610#L1046-1 assume !(0 == ~T3_E~0); 1576934#L1051-1 assume !(0 == ~T4_E~0); 1576935#L1056-1 assume !(0 == ~T5_E~0); 1577779#L1061-1 assume !(0 == ~T6_E~0); 1576828#L1066-1 assume !(0 == ~T7_E~0); 1576829#L1071-1 assume !(0 == ~T8_E~0); 1577759#L1076-1 assume !(0 == ~T9_E~0); 1576715#L1081-1 assume !(0 == ~T10_E~0); 1576716#L1086-1 assume !(0 == ~E_M~0); 1577126#L1091-1 assume !(0 == ~E_1~0); 1578047#L1096-1 assume !(0 == ~E_2~0); 1578048#L1101-1 assume !(0 == ~E_3~0); 1577195#L1106-1 assume !(0 == ~E_4~0); 1577196#L1111-1 assume !(0 == ~E_5~0); 1577378#L1116-1 assume !(0 == ~E_6~0); 1577379#L1121-1 assume !(0 == ~E_7~0); 1577185#L1126-1 assume !(0 == ~E_8~0); 1577186#L1131-1 assume !(0 == ~E_9~0); 1577489#L1136-1 assume !(0 == ~E_10~0); 1577623#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1577823#L514 assume !(1 == ~m_pc~0); 1577824#L514-2 is_master_triggered_~__retres1~0#1 := 0; 1577201#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1577202#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1577911#L1285 assume !(0 != activate_threads_~tmp~1#1); 1578124#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1576847#L533 assume !(1 == ~t1_pc~0); 1576848#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1577394#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1576612#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1576613#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 1577654#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1577655#L552 assume !(1 == ~t2_pc~0); 1577332#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1577333#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1577189#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1577190#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 1577216#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1577217#L571 assume !(1 == ~t3_pc~0); 1577454#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1577546#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1576558#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1576559#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 1577382#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1576641#L590 assume !(1 == ~t4_pc~0); 1576642#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1577453#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1578263#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1578131#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 1577687#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1577380#L609 assume !(1 == ~t5_pc~0); 1577381#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1578122#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1577915#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1577916#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 1577371#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1577372#L628 assume !(1 == ~t6_pc~0); 1577292#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1577291#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1577162#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1577163#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 1577733#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1577734#L647 assume !(1 == ~t7_pc~0); 1577893#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1577928#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1577929#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1577197#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 1577198#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1578185#L666 assume !(1 == ~t8_pc~0); 1576983#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1576984#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1577215#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1577406#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 1577121#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1577122#L685 assume !(1 == ~t9_pc~0); 1578139#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1577944#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1577252#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1577152#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 1577153#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1577578#L704 assume !(1 == ~t10_pc~0); 1577144#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1577143#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1577426#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1576688#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 1576689#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1576943#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 1577716#L1154-2 assume !(1 == ~T1_E~0); 1578165#L1159-1 assume !(1 == ~T2_E~0); 1578233#L1164-1 assume !(1 == ~T3_E~0); 1577404#L1169-1 assume !(1 == ~T4_E~0); 1577253#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1577047#L1179-1 assume !(1 == ~T6_E~0); 1576899#L1184-1 assume !(1 == ~T7_E~0); 1576900#L1189-1 assume !(1 == ~T8_E~0); 1576981#L1194-1 assume !(1 == ~T9_E~0); 1577106#L1199-1 assume !(1 == ~T10_E~0); 1577060#L1204-1 assume !(1 == ~E_M~0); 1577061#L1209-1 assume !(1 == ~E_1~0); 1577681#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1577682#L1219-1 assume !(1 == ~E_3~0); 1578171#L1224-1 assume !(1 == ~E_4~0); 1577430#L1229-1 assume !(1 == ~E_5~0); 1576785#L1234-1 assume !(1 == ~E_6~0); 1576786#L1239-1 assume !(1 == ~E_7~0); 1576843#L1244-1 assume !(1 == ~E_8~0); 1576844#L1249-1 assume !(1 == ~E_9~0); 1577769#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1576683#L1259-1 assume { :end_inline_reset_delta_events } true; 1576684#L1565-2 [2024-11-13 15:25:07,261 INFO L747 eck$LassoCheckResult]: Loop: 1576684#L1565-2 assume !false; 1744474#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1744468#L1011-1 assume !false; 1744463#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1744277#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1744260#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1744252#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1744245#L866 assume !(0 != eval_~tmp~0#1); 1744246#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1783134#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1783129#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1783122#L1036-5 assume !(0 == ~T1_E~0); 1783118#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1783116#L1046-3 assume !(0 == ~T3_E~0); 1783112#L1051-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1783108#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1783103#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1783098#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1783094#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1783090#L1076-3 assume !(0 == ~T9_E~0); 1783086#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1783081#L1086-3 assume !(0 == ~E_M~0); 1783077#L1091-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1783073#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1783069#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1783065#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1783062#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1783058#L1116-3 assume !(0 == ~E_6~0); 1783054#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1783051#L1126-3 assume !(0 == ~E_8~0); 1783048#L1131-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1783045#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1783042#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1783039#L514-36 assume !(1 == ~m_pc~0); 1783035#L514-38 is_master_triggered_~__retres1~0#1 := 0; 1783031#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1783027#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1783023#L1285-36 assume !(0 != activate_threads_~tmp~1#1); 1783019#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1783016#L533-36 assume !(1 == ~t1_pc~0); 1783013#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1783008#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1783004#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1783001#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1782997#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1782993#L552-36 assume !(1 == ~t2_pc~0); 1782990#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1782986#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1782982#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1782979#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1782976#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1782973#L571-36 assume !(1 == ~t3_pc~0); 1782970#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1782966#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1782961#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1782956#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1782952#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1782948#L590-36 assume 1 == ~t4_pc~0; 1782943#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1782937#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1782931#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1782924#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1782919#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1782915#L609-36 assume !(1 == ~t5_pc~0); 1782911#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1782905#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1782899#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1782894#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1782887#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1782882#L628-36 assume 1 == ~t6_pc~0; 1782877#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1782869#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1782867#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1782864#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1782861#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1782416#L647-36 assume !(1 == ~t7_pc~0); 1742346#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1774034#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1774033#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1774032#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1774031#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1774030#L666-36 assume 1 == ~t8_pc~0; 1774029#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1774027#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1774025#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1774024#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1774023#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1774022#L685-36 assume !(1 == ~t9_pc~0); 1774021#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1774020#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1774019#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1774017#L1357-36 assume !(0 != activate_threads_~tmp___8~0#1); 1774014#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1774012#L704-36 assume !(1 == ~t10_pc~0); 1774010#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1774007#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1774005#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1774003#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1774000#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1773998#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1670118#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1773995#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1773993#L1164-3 assume !(1 == ~T3_E~0); 1685500#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1773990#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1773988#L1179-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1773986#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1773984#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1773982#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1773980#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1773978#L1204-3 assume !(1 == ~E_M~0); 1721207#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1773975#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1773973#L1219-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1773971#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1773967#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1773965#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1773963#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1773961#L1244-3 assume !(1 == ~E_8~0); 1679856#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1773957#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1773955#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1773940#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1773932#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1770206#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1578356#L1584 assume !(0 == start_simulation_~tmp~3#1); 1578357#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1744652#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1744640#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1744637#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1744633#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1744538#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1744534#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1744498#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 1576684#L1565-2 [2024-11-13 15:25:07,261 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:25:07,262 INFO L85 PathProgramCache]: Analyzing trace with hash -1513086067, now seen corresponding path program 1 times [2024-11-13 15:25:07,262 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:25:07,262 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670869577] [2024-11-13 15:25:07,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:25:07,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:25:07,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:25:07,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:25:07,356 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:25:07,356 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1670869577] [2024-11-13 15:25:07,357 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1670869577] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:25:07,357 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:25:07,357 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:25:07,357 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1603639668] [2024-11-13 15:25:07,357 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:25:07,357 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:25:07,358 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:25:07,358 INFO L85 PathProgramCache]: Analyzing trace with hash 1446955075, now seen corresponding path program 3 times [2024-11-13 15:25:07,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:25:07,358 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [743177629] [2024-11-13 15:25:07,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:25:07,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:25:07,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:25:07,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:25:07,416 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:25:07,416 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [743177629] [2024-11-13 15:25:07,416 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [743177629] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:25:07,416 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:25:07,416 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:25:07,416 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [489258041] [2024-11-13 15:25:07,416 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:25:07,417 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:25:07,417 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:25:07,417 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:25:07,417 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:25:07,417 INFO L87 Difference]: Start difference. First operand 432464 states and 611920 transitions. cyclomatic complexity: 179712 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)