./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.10.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d393d146-4356-4a11-b661-5d5a295f61d2/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d393d146-4356-4a11-b661-5d5a295f61d2/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d393d146-4356-4a11-b661-5d5a295f61d2/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d393d146-4356-4a11-b661-5d5a295f61d2/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.10.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d393d146-4356-4a11-b661-5d5a295f61d2/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d393d146-4356-4a11-b661-5d5a295f61d2/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 6ba9401cadb8fecd59a1a331c94e3215cc972a92f03516bfd6c95164e3ec98a9 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 15:14:20,602 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 15:14:20,691 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d393d146-4356-4a11-b661-5d5a295f61d2/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 15:14:20,695 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 15:14:20,696 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 15:14:20,721 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 15:14:20,721 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 15:14:20,722 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 15:14:20,722 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 15:14:20,722 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 15:14:20,722 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 15:14:20,722 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 15:14:20,723 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 15:14:20,723 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 15:14:20,723 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 15:14:20,723 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 15:14:20,723 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 15:14:20,723 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 15:14:20,723 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 15:14:20,723 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 15:14:20,723 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 15:14:20,724 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 15:14:20,724 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 15:14:20,724 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 15:14:20,724 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 15:14:20,724 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 15:14:20,724 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 15:14:20,724 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 15:14:20,724 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 15:14:20,724 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 15:14:20,724 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 15:14:20,724 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 15:14:20,724 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 15:14:20,725 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 15:14:20,725 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 15:14:20,725 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 15:14:20,725 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 15:14:20,725 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 15:14:20,725 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 15:14:20,725 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d393d146-4356-4a11-b661-5d5a295f61d2/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 6ba9401cadb8fecd59a1a331c94e3215cc972a92f03516bfd6c95164e3ec98a9 [2024-11-13 15:14:21,047 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 15:14:21,055 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 15:14:21,058 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 15:14:21,059 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 15:14:21,059 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 15:14:21,060 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d393d146-4356-4a11-b661-5d5a295f61d2/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/token_ring.10.cil-2.c Unable to find full path for "g++" [2024-11-13 15:14:22,908 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 15:14:23,220 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 15:14:23,225 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d393d146-4356-4a11-b661-5d5a295f61d2/sv-benchmarks/c/systemc/token_ring.10.cil-2.c [2024-11-13 15:14:23,243 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d393d146-4356-4a11-b661-5d5a295f61d2/bin/uautomizer-verify-qhAvR1uOyd/data/5c95d8de5/2bed7967e5734cf7922cc93b06b50ec8/FLAG20fab57eb [2024-11-13 15:14:23,259 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d393d146-4356-4a11-b661-5d5a295f61d2/bin/uautomizer-verify-qhAvR1uOyd/data/5c95d8de5/2bed7967e5734cf7922cc93b06b50ec8 [2024-11-13 15:14:23,262 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 15:14:23,264 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 15:14:23,266 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 15:14:23,267 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 15:14:23,271 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 15:14:23,272 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:14:23" (1/1) ... [2024-11-13 15:14:23,275 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@55f09b85 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:14:23, skipping insertion in model container [2024-11-13 15:14:23,276 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:14:23" (1/1) ... [2024-11-13 15:14:23,325 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 15:14:23,646 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:14:23,664 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 15:14:23,736 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:14:23,766 INFO L204 MainTranslator]: Completed translation [2024-11-13 15:14:23,766 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:14:23 WrapperNode [2024-11-13 15:14:23,767 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 15:14:23,767 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 15:14:23,767 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 15:14:23,768 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 15:14:23,773 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:14:23" (1/1) ... [2024-11-13 15:14:23,784 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:14:23" (1/1) ... [2024-11-13 15:14:23,872 INFO L138 Inliner]: procedures = 48, calls = 62, calls flagged for inlining = 57, calls inlined = 210, statements flattened = 3196 [2024-11-13 15:14:23,873 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 15:14:23,873 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 15:14:23,873 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 15:14:23,873 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 15:14:23,892 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:14:23" (1/1) ... [2024-11-13 15:14:23,892 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:14:23" (1/1) ... [2024-11-13 15:14:23,905 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:14:23" (1/1) ... [2024-11-13 15:14:23,957 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 15:14:23,958 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:14:23" (1/1) ... [2024-11-13 15:14:23,958 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:14:23" (1/1) ... [2024-11-13 15:14:23,998 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:14:23" (1/1) ... [2024-11-13 15:14:24,048 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:14:23" (1/1) ... [2024-11-13 15:14:24,056 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:14:23" (1/1) ... [2024-11-13 15:14:24,069 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:14:23" (1/1) ... [2024-11-13 15:14:24,085 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 15:14:24,086 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 15:14:24,086 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 15:14:24,086 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 15:14:24,087 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:14:23" (1/1) ... [2024-11-13 15:14:24,095 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:14:24,108 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d393d146-4356-4a11-b661-5d5a295f61d2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:14:24,123 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d393d146-4356-4a11-b661-5d5a295f61d2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:14:24,126 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d393d146-4356-4a11-b661-5d5a295f61d2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 15:14:24,154 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 15:14:24,154 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 15:14:24,154 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 15:14:24,154 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 15:14:24,312 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 15:14:24,314 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 15:14:27,387 INFO L? ?]: Removed 662 outVars from TransFormulas that were not future-live. [2024-11-13 15:14:27,387 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 15:14:27,429 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 15:14:27,429 INFO L316 CfgBuilder]: Removed 13 assume(true) statements. [2024-11-13 15:14:27,430 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:14:27 BoogieIcfgContainer [2024-11-13 15:14:27,430 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 15:14:27,431 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 15:14:27,431 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 15:14:27,436 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 15:14:27,436 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:14:27,437 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 03:14:23" (1/3) ... [2024-11-13 15:14:27,438 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@68d02a30 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:14:27, skipping insertion in model container [2024-11-13 15:14:27,438 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:14:27,438 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:14:23" (2/3) ... [2024-11-13 15:14:27,438 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@68d02a30 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:14:27, skipping insertion in model container [2024-11-13 15:14:27,438 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:14:27,438 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:14:27" (3/3) ... [2024-11-13 15:14:27,440 INFO L333 chiAutomizerObserver]: Analyzing ICFG token_ring.10.cil-2.c [2024-11-13 15:14:27,535 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 15:14:27,535 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 15:14:27,535 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 15:14:27,535 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 15:14:27,535 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 15:14:27,535 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 15:14:27,535 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 15:14:27,536 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 15:14:27,548 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1379 states, 1378 states have (on average 1.5014513788098693) internal successors, (2069), 1378 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:27,617 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1236 [2024-11-13 15:14:27,618 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:14:27,618 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:14:27,635 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:27,638 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:27,638 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 15:14:27,641 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1379 states, 1378 states have (on average 1.5014513788098693) internal successors, (2069), 1378 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:27,665 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1236 [2024-11-13 15:14:27,665 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:14:27,665 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:14:27,675 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:27,675 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:27,693 INFO L745 eck$LassoCheckResult]: Stem: 188#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1260#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 998#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1256#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 589#L719true assume !(1 == ~m_i~0);~m_st~0 := 2; 358#L719-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 563#L724-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 730#L729-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1246#L734-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 477#L739-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 848#L744-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 392#L749-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 683#L754-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 869#L759-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 639#L764-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 571#L769-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 857#L1024true assume !(0 == ~M_E~0); 960#L1024-2true assume !(0 == ~T1_E~0); 186#L1029-1true assume !(0 == ~T2_E~0); 245#L1034-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1328#L1039-1true assume !(0 == ~T4_E~0); 1035#L1044-1true assume !(0 == ~T5_E~0); 407#L1049-1true assume !(0 == ~T6_E~0); 1342#L1054-1true assume !(0 == ~T7_E~0); 588#L1059-1true assume !(0 == ~T8_E~0); 214#L1064-1true assume !(0 == ~T9_E~0); 822#L1069-1true assume !(0 == ~T10_E~0); 1239#L1074-1true assume 0 == ~E_M~0;~E_M~0 := 1; 899#L1079-1true assume !(0 == ~E_1~0); 860#L1084-1true assume !(0 == ~E_2~0); 1059#L1089-1true assume !(0 == ~E_3~0); 933#L1094-1true assume !(0 == ~E_4~0); 469#L1099-1true assume !(0 == ~E_5~0); 1074#L1104-1true assume !(0 == ~E_6~0); 702#L1109-1true assume !(0 == ~E_7~0); 320#L1114-1true assume 0 == ~E_8~0;~E_8~0 := 1; 1291#L1119-1true assume !(0 == ~E_9~0); 365#L1124-1true assume !(0 == ~E_10~0); 39#L1129-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 721#L502true assume 1 == ~m_pc~0; 586#L503true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 100#L513true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 851#is_master_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 636#L1273true assume !(0 != activate_threads_~tmp~1#1); 1378#L1273-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1143#L521true assume !(1 == ~t1_pc~0); 1070#L521-2true is_transmit1_triggered_~__retres1~1#1 := 0; 63#L532true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 652#L1281true assume !(0 != activate_threads_~tmp___0~0#1); 56#L1281-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 875#L540true assume 1 == ~t2_pc~0; 1125#L541true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 879#L551true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 318#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1240#L1289true assume !(0 != activate_threads_~tmp___1~0#1); 968#L1289-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 203#L559true assume 1 == ~t3_pc~0; 1044#L560true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 377#L570true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 665#L1297true assume !(0 != activate_threads_~tmp___2~0#1); 108#L1297-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1267#L578true assume !(1 == ~t4_pc~0); 828#L578-2true is_transmit4_triggered_~__retres1~4#1 := 0; 854#L589true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1111#L1305true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 619#L1305-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1179#L597true assume 1 == ~t5_pc~0; 1347#L598true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 73#L608true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 855#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1366#L1313true assume !(0 != activate_threads_~tmp___4~0#1); 572#L1313-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 633#L616true assume !(1 == ~t6_pc~0); 1191#L616-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1087#L627true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 304#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 509#L1321true assume !(0 != activate_threads_~tmp___5~0#1); 462#L1321-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 697#L635true assume 1 == ~t7_pc~0; 622#L636true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 255#L646true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1276#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 928#L1329true assume !(0 != activate_threads_~tmp___6~0#1); 567#L1329-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 816#L654true assume !(1 == ~t8_pc~0); 426#L654-2true is_transmit8_triggered_~__retres1~8#1 := 0; 969#L665true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 764#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 819#L1337true assume !(0 != activate_threads_~tmp___7~0#1); 1021#L1337-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 185#L673true assume 1 == ~t9_pc~0; 1038#L674true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1215#L684true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 355#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 768#L1345true assume !(0 != activate_threads_~tmp___8~0#1); 715#L1345-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 888#L692true assume !(1 == ~t10_pc~0); 701#L692-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1028#L703true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 464#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 472#L1353true assume !(0 != activate_threads_~tmp___9~0#1); 792#L1353-2true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1325#L1142true assume !(1 == ~M_E~0); 138#L1142-2true assume !(1 == ~T1_E~0); 769#L1147-1true assume !(1 == ~T2_E~0); 1324#L1152-1true assume !(1 == ~T3_E~0); 382#L1157-1true assume !(1 == ~T4_E~0); 868#L1162-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 491#L1167-1true assume !(1 == ~T6_E~0); 952#L1172-1true assume !(1 == ~T7_E~0); 982#L1177-1true assume !(1 == ~T8_E~0); 604#L1182-1true assume !(1 == ~T9_E~0); 708#L1187-1true assume !(1 == ~T10_E~0); 758#L1192-1true assume !(1 == ~E_M~0); 288#L1197-1true assume !(1 == ~E_1~0); 773#L1202-1true assume 1 == ~E_2~0;~E_2~0 := 2; 555#L1207-1true assume !(1 == ~E_3~0); 539#L1212-1true assume !(1 == ~E_4~0); 66#L1217-1true assume !(1 == ~E_5~0); 1380#L1222-1true assume !(1 == ~E_6~0); 536#L1227-1true assume !(1 == ~E_7~0); 601#L1232-1true assume !(1 == ~E_8~0); 7#L1237-1true assume !(1 == ~E_9~0); 1079#L1242-1true assume 1 == ~E_10~0;~E_10~0 := 2; 587#L1247-1true assume { :end_inline_reset_delta_events } true; 88#L1553-2true [2024-11-13 15:14:27,695 INFO L747 eck$LassoCheckResult]: Loop: 88#L1553-2true assume !false; 755#L1554true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 235#L999-1true assume false; 779#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 481#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1305#L1024-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1025#L1024-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 459#L1029-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 435#L1034-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 735#L1039-3true assume !(0 == ~T4_E~0); 788#L1044-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 183#L1049-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 664#L1054-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 64#L1059-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1350#L1064-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 415#L1069-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 710#L1074-3true assume 0 == ~E_M~0;~E_M~0 := 1; 1001#L1079-3true assume !(0 == ~E_1~0); 595#L1084-3true assume 0 == ~E_2~0;~E_2~0 := 1; 504#L1089-3true assume 0 == ~E_3~0;~E_3~0 := 1; 662#L1094-3true assume 0 == ~E_4~0;~E_4~0 := 1; 448#L1099-3true assume 0 == ~E_5~0;~E_5~0 := 1; 733#L1104-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1085#L1109-3true assume 0 == ~E_7~0;~E_7~0 := 1; 719#L1114-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1204#L1119-3true assume !(0 == ~E_9~0); 1344#L1124-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1237#L1129-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1118#L502-36true assume 1 == ~m_pc~0; 736#L503-12true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2#L513-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1003#is_master_triggered_returnLabel#13true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 215#L1273-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 703#L1273-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 394#L521-36true assume !(1 == ~t1_pc~0); 1098#L521-38true is_transmit1_triggered_~__retres1~1#1 := 0; 528#L532-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 999#is_transmit1_triggered_returnLabel#13true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1209#L1281-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 826#L1281-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1128#L540-36true assume !(1 == ~t2_pc~0); 42#L540-38true is_transmit2_triggered_~__retres1~2#1 := 0; 258#L551-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 827#is_transmit2_triggered_returnLabel#13true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1351#L1289-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 488#L1289-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6#L559-36true assume 1 == ~t3_pc~0; 726#L560-12true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 756#L570-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 353#is_transmit3_triggered_returnLabel#13true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 606#L1297-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 894#L1297-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1250#L578-36true assume 1 == ~t4_pc~0; 579#L579-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1259#L589-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 496#is_transmit4_triggered_returnLabel#13true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1323#L1305-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 419#L1305-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 594#L597-36true assume !(1 == ~t5_pc~0); 1141#L597-38true is_transmit5_triggered_~__retres1~5#1 := 0; 1078#L608-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 967#is_transmit5_triggered_returnLabel#13true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 556#L1313-36true assume !(0 != activate_threads_~tmp___4~0#1); 289#L1313-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1130#L616-36true assume 1 == ~t6_pc~0; 1349#L617-12true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37#L627-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 338#is_transmit6_triggered_returnLabel#13true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 456#L1321-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 754#L1321-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1362#L635-36true assume 1 == ~t7_pc~0; 1030#L636-12true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 838#L646-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 932#is_transmit7_triggered_returnLabel#13true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1284#L1329-36true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 446#L1329-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1297#L654-36true assume 1 == ~t8_pc~0; 1218#L655-12true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1346#L665-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 576#is_transmit8_triggered_returnLabel#13true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1190#L1337-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1145#L1337-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 231#L673-36true assume !(1 == ~t9_pc~0); 740#L673-38true is_transmit9_triggered_~__retres1~9#1 := 0; 478#L684-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 380#is_transmit9_triggered_returnLabel#13true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1050#L1345-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10#L1345-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1201#L692-36true assume !(1 == ~t10_pc~0); 112#L692-38true is_transmit10_triggered_~__retres1~10#1 := 0; 455#L703-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 278#is_transmit10_triggered_returnLabel#13true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 212#L1353-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 454#L1353-38true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 573#L1142-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1185#L1142-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1034#L1147-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1090#L1152-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 513#L1157-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 834#L1162-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1088#L1167-3true assume !(1 == ~T6_E~0); 1011#L1172-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 444#L1177-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 374#L1182-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 867#L1187-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 384#L1192-3true assume 1 == ~E_M~0;~E_M~0 := 2; 266#L1197-3true assume 1 == ~E_1~0;~E_1~0 := 2; 433#L1202-3true assume 1 == ~E_2~0;~E_2~0 := 2; 522#L1207-3true assume !(1 == ~E_3~0); 1126#L1212-3true assume 1 == ~E_4~0;~E_4~0 := 2; 731#L1217-3true assume 1 == ~E_5~0;~E_5~0 := 2; 207#L1222-3true assume 1 == ~E_6~0;~E_6~0 := 2; 48#L1227-3true assume 1 == ~E_7~0;~E_7~0 := 2; 900#L1232-3true assume 1 == ~E_8~0;~E_8~0 := 2; 870#L1237-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1310#L1242-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1264#L1247-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 945#L782-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 120#L839-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 271#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 580#L1572true assume !(0 == start_simulation_~tmp~3#1); 395#L1572-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1231#L782-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1103#L839-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 43#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 1301#L1527true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4#L1534true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 499#stop_simulation_returnLabel#1true start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1371#L1585true assume !(0 != start_simulation_~tmp___0~1#1); 88#L1553-2true [2024-11-13 15:14:27,705 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:27,707 INFO L85 PathProgramCache]: Analyzing trace with hash 121410427, now seen corresponding path program 1 times [2024-11-13 15:14:27,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:27,715 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1902932643] [2024-11-13 15:14:27,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:27,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:27,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:28,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:28,128 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:28,128 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1902932643] [2024-11-13 15:14:28,129 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1902932643] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:28,129 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:28,129 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:28,133 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [921043093] [2024-11-13 15:14:28,133 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:28,138 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:14:28,139 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:28,140 INFO L85 PathProgramCache]: Analyzing trace with hash 636953815, now seen corresponding path program 1 times [2024-11-13 15:14:28,140 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:28,140 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1272219415] [2024-11-13 15:14:28,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:28,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:28,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:28,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:28,253 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:28,253 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1272219415] [2024-11-13 15:14:28,253 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1272219415] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:28,253 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:28,260 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:14:28,261 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [536371560] [2024-11-13 15:14:28,261 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:28,262 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:14:28,267 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:14:28,299 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:14:28,300 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:14:28,306 INFO L87 Difference]: Start difference. First operand has 1379 states, 1378 states have (on average 1.5014513788098693) internal successors, (2069), 1378 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:28,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:14:28,425 INFO L93 Difference]: Finished difference Result 1377 states and 2039 transitions. [2024-11-13 15:14:28,426 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2039 transitions. [2024-11-13 15:14:28,443 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-11-13 15:14:28,464 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1372 states and 2034 transitions. [2024-11-13 15:14:28,465 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2024-11-13 15:14:28,468 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2024-11-13 15:14:28,468 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2034 transitions. [2024-11-13 15:14:28,475 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:14:28,475 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2034 transitions. [2024-11-13 15:14:28,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2034 transitions. [2024-11-13 15:14:28,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2024-11-13 15:14:28,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4825072886297377) internal successors, (2034), 1371 states have internal predecessors, (2034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:28,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2034 transitions. [2024-11-13 15:14:28,579 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2034 transitions. [2024-11-13 15:14:28,580 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:14:28,585 INFO L424 stractBuchiCegarLoop]: Abstraction has 1372 states and 2034 transitions. [2024-11-13 15:14:28,585 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 15:14:28,585 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2034 transitions. [2024-11-13 15:14:28,595 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-11-13 15:14:28,596 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:14:28,596 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:14:28,601 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:28,601 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:28,602 INFO L745 eck$LassoCheckResult]: Stem: 3147#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3148#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4049#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4050#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3729#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 3418#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3419#L724-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3699#L729-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3869#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3587#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3588#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3469#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3470#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3823#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3783#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 3707#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3708#L1024 assume !(0 == ~M_E~0); 3963#L1024-2 assume !(0 == ~T1_E~0); 3143#L1029-1 assume !(0 == ~T2_E~0); 3144#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3246#L1039-1 assume !(0 == ~T4_E~0); 4073#L1044-1 assume !(0 == ~T5_E~0); 3491#L1049-1 assume !(0 == ~T6_E~0); 3492#L1054-1 assume !(0 == ~T7_E~0); 3728#L1059-1 assume !(0 == ~T8_E~0); 3193#L1064-1 assume !(0 == ~T9_E~0); 3194#L1069-1 assume !(0 == ~T10_E~0); 3932#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3992#L1079-1 assume !(0 == ~E_1~0); 3965#L1084-1 assume !(0 == ~E_2~0); 3966#L1089-1 assume !(0 == ~E_3~0); 4010#L1094-1 assume !(0 == ~E_4~0); 3577#L1099-1 assume !(0 == ~E_5~0); 3578#L1104-1 assume !(0 == ~E_6~0); 3841#L1109-1 assume !(0 == ~E_7~0); 3360#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 3361#L1119-1 assume !(0 == ~E_9~0); 3431#L1124-1 assume !(0 == ~E_10~0); 2847#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2848#L502 assume 1 == ~m_pc~0; 3726#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2973#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2974#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3779#L1273 assume !(0 != activate_threads_~tmp~1#1); 3780#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4103#L521 assume !(1 == ~t1_pc~0); 4038#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2898#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2863#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2864#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 2884#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2885#L540 assume 1 == ~t2_pc~0; 3976#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3688#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3356#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3357#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 4034#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3171#L559 assume 1 == ~t3_pc~0; 3172#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3449#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2800#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2801#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 2991#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2992#L578 assume !(1 == ~t4_pc~0); 3115#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3114#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2931#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2932#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3760#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3761#L597 assume 1 == ~t5_pc~0; 4119#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2918#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2919#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3961#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 3709#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3710#L616 assume !(1 == ~t6_pc~0); 3725#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3724#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3332#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3333#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 3567#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3568#L635 assume 1 == ~t7_pc~0; 3764#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2887#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3264#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4006#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 3701#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3702#L654 assume !(1 == ~t8_pc~0); 3518#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3519#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3894#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3895#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 3930#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3141#L673 assume 1 == ~t9_pc~0; 3142#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2838#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3413#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3414#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 3853#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3854#L692 assume !(1 == ~t10_pc~0); 3798#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3797#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3569#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3570#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 3581#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3909#L1142 assume !(1 == ~M_E~0); 3052#L1142-2 assume !(1 == ~T1_E~0); 3053#L1147-1 assume !(1 == ~T2_E~0); 3898#L1152-1 assume !(1 == ~T3_E~0); 3455#L1157-1 assume !(1 == ~T4_E~0); 3456#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3605#L1167-1 assume !(1 == ~T6_E~0); 3606#L1172-1 assume !(1 == ~T7_E~0); 4028#L1177-1 assume !(1 == ~T8_E~0); 3746#L1182-1 assume !(1 == ~T9_E~0); 3747#L1187-1 assume !(1 == ~T10_E~0); 3846#L1192-1 assume !(1 == ~E_M~0); 3312#L1197-1 assume !(1 == ~E_1~0); 3313#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3691#L1207-1 assume !(1 == ~E_3~0); 3666#L1212-1 assume !(1 == ~E_4~0); 2903#L1217-1 assume !(1 == ~E_5~0); 2904#L1222-1 assume !(1 == ~E_6~0); 3663#L1227-1 assume !(1 == ~E_7~0); 3664#L1232-1 assume !(1 == ~E_8~0); 2777#L1237-1 assume !(1 == ~E_9~0); 2778#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3727#L1247-1 assume { :end_inline_reset_delta_events } true; 2948#L1553-2 [2024-11-13 15:14:28,603 INFO L747 eck$LassoCheckResult]: Loop: 2948#L1553-2 assume !false; 2949#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3088#L999-1 assume !false; 3229#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3036#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2921#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3393#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3394#L854 assume !(0 != eval_~tmp~0#1); 3803#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3590#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3591#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4063#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3563#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3531#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3532#L1039-3 assume !(0 == ~T4_E~0); 3874#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3137#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3138#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2899#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2900#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3501#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3502#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3848#L1079-3 assume !(0 == ~E_1~0); 3739#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3624#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3625#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3550#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3551#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3872#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3860#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3861#L1119-3 assume !(0 == ~E_9~0); 4124#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4131#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4097#L502-36 assume !(1 == ~m_pc~0); 3280#L502-38 is_master_triggered_~__retres1~0#1 := 0; 2765#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2766#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3195#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3196#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3474#L521-36 assume 1 == ~t1_pc~0; 3475#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3485#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3655#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4051#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3934#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3935#L540-36 assume !(1 == ~t2_pc~0); 2849#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2850#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3267#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3936#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3600#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2771#L559-36 assume 1 == ~t3_pc~0; 2772#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3230#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3408#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3409#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3748#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3988#L578-36 assume 1 == ~t4_pc~0; 3717#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3673#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3611#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3612#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3507#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3508#L597-36 assume !(1 == ~t5_pc~0); 3736#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4089#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4033#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3690#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 3310#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3311#L616-36 assume 1 == ~t6_pc~0; 4100#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2843#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2844#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3388#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3560#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3889#L635-36 assume 1 == ~t7_pc~0; 4064#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3946#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3947#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4009#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3546#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3547#L654-36 assume !(1 == ~t8_pc~0); 4069#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 4070#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3713#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3714#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4104#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3221#L673-36 assume !(1 == ~t9_pc~0); 3222#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 3586#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3451#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3452#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2784#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2785#L692-36 assume !(1 == ~t10_pc~0); 2999#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3000#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3294#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3188#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3189#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3557#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3706#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4071#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4072#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3637#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3638#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3942#L1167-3 assume !(1 == ~T6_E~0); 4055#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3545#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3443#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3444#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3458#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3277#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3278#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3528#L1207-3 assume !(1 == ~E_3~0); 3646#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3870#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3181#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2868#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2869#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3971#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3972#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4134#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4020#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3019#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3020#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3284#L1572 assume !(0 == start_simulation_~tmp~3#1); 3315#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3477#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2798#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2856#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 2857#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2769#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2770#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3617#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 2948#L1553-2 [2024-11-13 15:14:28,604 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:28,604 INFO L85 PathProgramCache]: Analyzing trace with hash -825627459, now seen corresponding path program 1 times [2024-11-13 15:14:28,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:28,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1808780915] [2024-11-13 15:14:28,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:28,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:28,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:28,803 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:28,803 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:28,803 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1808780915] [2024-11-13 15:14:28,803 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1808780915] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:28,803 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:28,803 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:28,803 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [924325477] [2024-11-13 15:14:28,804 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:28,804 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:14:28,804 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:28,805 INFO L85 PathProgramCache]: Analyzing trace with hash -681160105, now seen corresponding path program 1 times [2024-11-13 15:14:28,805 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:28,805 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [587602546] [2024-11-13 15:14:28,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:28,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:28,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:29,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:29,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:29,032 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [587602546] [2024-11-13 15:14:29,033 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [587602546] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:29,033 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:29,033 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:29,033 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [381164843] [2024-11-13 15:14:29,033 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:29,033 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:14:29,034 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:14:29,034 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:14:29,034 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:14:29,036 INFO L87 Difference]: Start difference. First operand 1372 states and 2034 transitions. cyclomatic complexity: 663 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:29,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:14:29,097 INFO L93 Difference]: Finished difference Result 1372 states and 2033 transitions. [2024-11-13 15:14:29,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2033 transitions. [2024-11-13 15:14:29,111 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-11-13 15:14:29,125 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2033 transitions. [2024-11-13 15:14:29,126 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2024-11-13 15:14:29,127 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2024-11-13 15:14:29,128 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2033 transitions. [2024-11-13 15:14:29,133 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:14:29,133 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2033 transitions. [2024-11-13 15:14:29,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2033 transitions. [2024-11-13 15:14:29,197 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2024-11-13 15:14:29,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4817784256559767) internal successors, (2033), 1371 states have internal predecessors, (2033), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:29,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2033 transitions. [2024-11-13 15:14:29,206 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2033 transitions. [2024-11-13 15:14:29,207 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:14:29,208 INFO L424 stractBuchiCegarLoop]: Abstraction has 1372 states and 2033 transitions. [2024-11-13 15:14:29,211 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 15:14:29,212 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2033 transitions. [2024-11-13 15:14:29,219 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-11-13 15:14:29,219 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:14:29,219 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:14:29,221 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:29,221 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:29,222 INFO L745 eck$LassoCheckResult]: Stem: 5898#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 5899#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6800#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6801#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6480#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 6168#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6169#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6450#L729-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6620#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6337#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6338#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6220#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6221#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6574#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6534#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6457#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6458#L1024 assume !(0 == ~M_E~0); 6714#L1024-2 assume !(0 == ~T1_E~0); 5894#L1029-1 assume !(0 == ~T2_E~0); 5895#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5997#L1039-1 assume !(0 == ~T4_E~0); 6824#L1044-1 assume !(0 == ~T5_E~0); 6240#L1049-1 assume !(0 == ~T6_E~0); 6241#L1054-1 assume !(0 == ~T7_E~0); 6479#L1059-1 assume !(0 == ~T8_E~0); 5944#L1064-1 assume !(0 == ~T9_E~0); 5945#L1069-1 assume !(0 == ~T10_E~0); 6683#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6743#L1079-1 assume !(0 == ~E_1~0); 6716#L1084-1 assume !(0 == ~E_2~0); 6717#L1089-1 assume !(0 == ~E_3~0); 6761#L1094-1 assume !(0 == ~E_4~0); 6328#L1099-1 assume !(0 == ~E_5~0); 6329#L1104-1 assume !(0 == ~E_6~0); 6592#L1109-1 assume !(0 == ~E_7~0); 6111#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 6112#L1119-1 assume !(0 == ~E_9~0); 6178#L1124-1 assume !(0 == ~E_10~0); 5598#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5599#L502 assume 1 == ~m_pc~0; 6477#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5724#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5725#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6528#L1273 assume !(0 != activate_threads_~tmp~1#1); 6529#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6854#L521 assume !(1 == ~t1_pc~0); 6789#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5649#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5614#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5615#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 5635#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5636#L540 assume 1 == ~t2_pc~0; 6727#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6439#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6107#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6108#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 6785#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5922#L559 assume 1 == ~t3_pc~0; 5923#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6199#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5551#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5552#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 5742#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5743#L578 assume !(1 == ~t4_pc~0); 5861#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5860#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5681#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5682#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6509#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6510#L597 assume 1 == ~t5_pc~0; 6869#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5669#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5670#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6712#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 6459#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6460#L616 assume !(1 == ~t6_pc~0); 6474#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6473#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6083#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6084#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 6317#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6318#L635 assume 1 == ~t7_pc~0; 6514#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5638#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6013#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6757#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 6452#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6453#L654 assume !(1 == ~t8_pc~0); 6269#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6270#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6642#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6643#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 6681#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5892#L673 assume 1 == ~t9_pc~0; 5893#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5589#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6162#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6163#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 6604#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6605#L692 assume !(1 == ~t10_pc~0); 6549#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6548#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6320#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6321#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 6332#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6660#L1142 assume !(1 == ~M_E~0); 5803#L1142-2 assume !(1 == ~T1_E~0); 5804#L1147-1 assume !(1 == ~T2_E~0); 6649#L1152-1 assume !(1 == ~T3_E~0); 6206#L1157-1 assume !(1 == ~T4_E~0); 6207#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6356#L1167-1 assume !(1 == ~T6_E~0); 6357#L1172-1 assume !(1 == ~T7_E~0); 6778#L1177-1 assume !(1 == ~T8_E~0); 6497#L1182-1 assume !(1 == ~T9_E~0); 6498#L1187-1 assume !(1 == ~T10_E~0); 6597#L1192-1 assume !(1 == ~E_M~0); 6061#L1197-1 assume !(1 == ~E_1~0); 6062#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6441#L1207-1 assume !(1 == ~E_3~0); 6417#L1212-1 assume !(1 == ~E_4~0); 5654#L1217-1 assume !(1 == ~E_5~0); 5655#L1222-1 assume !(1 == ~E_6~0); 6414#L1227-1 assume !(1 == ~E_7~0); 6415#L1232-1 assume !(1 == ~E_8~0); 5528#L1237-1 assume !(1 == ~E_9~0); 5529#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 6478#L1247-1 assume { :end_inline_reset_delta_events } true; 5699#L1553-2 [2024-11-13 15:14:29,222 INFO L747 eck$LassoCheckResult]: Loop: 5699#L1553-2 assume !false; 5700#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5839#L999-1 assume !false; 5980#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5787#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5672#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6144#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6145#L854 assume !(0 != eval_~tmp~0#1); 6554#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6341#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6342#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6814#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6314#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6282#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6283#L1039-3 assume !(0 == ~T4_E~0); 6625#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5888#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5889#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5650#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5651#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6252#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6253#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6599#L1079-3 assume !(0 == ~E_1~0); 6489#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6375#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6376#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6301#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6302#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6623#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6611#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6612#L1119-3 assume !(0 == ~E_9~0); 6875#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6882#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6848#L502-36 assume 1 == ~m_pc~0; 6626#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5516#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5517#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5946#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5947#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6225#L521-36 assume 1 == ~t1_pc~0; 6226#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6236#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6406#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6802#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6685#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6686#L540-36 assume 1 == ~t2_pc~0; 6850#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5606#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6018#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6687#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6351#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5525#L559-36 assume 1 == ~t3_pc~0; 5526#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5984#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6159#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6160#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6499#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6739#L578-36 assume 1 == ~t4_pc~0; 6468#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6427#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6363#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6364#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6260#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6261#L597-36 assume !(1 == ~t5_pc~0); 6487#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 6840#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6784#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6442#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 6063#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6064#L616-36 assume 1 == ~t6_pc~0; 6851#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5594#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5595#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6139#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6311#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6640#L635-36 assume !(1 == ~t7_pc~0); 6816#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 6697#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6698#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6760#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6297#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6298#L654-36 assume !(1 == ~t8_pc~0); 6820#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 6821#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6464#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6465#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6855#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5972#L673-36 assume !(1 == ~t9_pc~0); 5973#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 6339#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6202#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6203#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5535#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5536#L692-36 assume !(1 == ~t10_pc~0); 5750#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 5751#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6045#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5939#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5940#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6310#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6461#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6822#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6823#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6388#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6389#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6693#L1167-3 assume !(1 == ~T6_E~0); 6806#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6296#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6194#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6195#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6209#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6028#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6029#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6279#L1207-3 assume !(1 == ~E_3~0); 6397#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6621#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5932#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5619#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5620#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6722#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6723#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6885#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6771#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5770#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5771#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 6035#L1572 assume !(0 == start_simulation_~tmp~3#1); 6066#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6228#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5549#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5607#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 5608#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5520#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5521#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6368#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 5699#L1553-2 [2024-11-13 15:14:29,227 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:29,227 INFO L85 PathProgramCache]: Analyzing trace with hash 1224781439, now seen corresponding path program 1 times [2024-11-13 15:14:29,227 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:29,227 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2758088] [2024-11-13 15:14:29,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:29,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:29,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:29,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:29,327 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:29,327 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2758088] [2024-11-13 15:14:29,327 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2758088] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:29,327 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:29,328 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:29,328 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [50239613] [2024-11-13 15:14:29,328 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:29,328 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:14:29,328 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:29,329 INFO L85 PathProgramCache]: Analyzing trace with hash 704182102, now seen corresponding path program 1 times [2024-11-13 15:14:29,329 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:29,329 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1461176161] [2024-11-13 15:14:29,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:29,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:29,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:29,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:29,442 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:29,443 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1461176161] [2024-11-13 15:14:29,443 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1461176161] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:29,443 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:29,443 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:29,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [653584152] [2024-11-13 15:14:29,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:29,444 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:14:29,444 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:14:29,445 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:14:29,445 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:14:29,445 INFO L87 Difference]: Start difference. First operand 1372 states and 2033 transitions. cyclomatic complexity: 662 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:29,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:14:29,482 INFO L93 Difference]: Finished difference Result 1372 states and 2032 transitions. [2024-11-13 15:14:29,482 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2032 transitions. [2024-11-13 15:14:29,492 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-11-13 15:14:29,500 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2032 transitions. [2024-11-13 15:14:29,501 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2024-11-13 15:14:29,503 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2024-11-13 15:14:29,504 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2032 transitions. [2024-11-13 15:14:29,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:14:29,511 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2032 transitions. [2024-11-13 15:14:29,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2032 transitions. [2024-11-13 15:14:29,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2024-11-13 15:14:29,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4810495626822158) internal successors, (2032), 1371 states have internal predecessors, (2032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:29,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2032 transitions. [2024-11-13 15:14:29,542 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2032 transitions. [2024-11-13 15:14:29,543 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:14:29,544 INFO L424 stractBuchiCegarLoop]: Abstraction has 1372 states and 2032 transitions. [2024-11-13 15:14:29,544 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 15:14:29,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2032 transitions. [2024-11-13 15:14:29,553 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-11-13 15:14:29,553 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:14:29,553 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:14:29,556 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:29,556 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:29,557 INFO L745 eck$LassoCheckResult]: Stem: 8649#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 8650#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 9551#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9552#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9231#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 8919#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8920#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9201#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9371#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9088#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9089#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8971#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8972#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9325#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9285#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9208#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9209#L1024 assume !(0 == ~M_E~0); 9465#L1024-2 assume !(0 == ~T1_E~0); 8645#L1029-1 assume !(0 == ~T2_E~0); 8646#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8748#L1039-1 assume !(0 == ~T4_E~0); 9575#L1044-1 assume !(0 == ~T5_E~0); 8991#L1049-1 assume !(0 == ~T6_E~0); 8992#L1054-1 assume !(0 == ~T7_E~0); 9230#L1059-1 assume !(0 == ~T8_E~0); 8695#L1064-1 assume !(0 == ~T9_E~0); 8696#L1069-1 assume !(0 == ~T10_E~0); 9434#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 9494#L1079-1 assume !(0 == ~E_1~0); 9467#L1084-1 assume !(0 == ~E_2~0); 9468#L1089-1 assume !(0 == ~E_3~0); 9512#L1094-1 assume !(0 == ~E_4~0); 9079#L1099-1 assume !(0 == ~E_5~0); 9080#L1104-1 assume !(0 == ~E_6~0); 9343#L1109-1 assume !(0 == ~E_7~0); 8862#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 8863#L1119-1 assume !(0 == ~E_9~0); 8929#L1124-1 assume !(0 == ~E_10~0); 8349#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8350#L502 assume 1 == ~m_pc~0; 9228#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8475#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8476#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9279#L1273 assume !(0 != activate_threads_~tmp~1#1); 9280#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9605#L521 assume !(1 == ~t1_pc~0); 9540#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8400#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8365#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8366#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 8386#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8387#L540 assume 1 == ~t2_pc~0; 9478#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9190#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8858#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8859#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 9536#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8673#L559 assume 1 == ~t3_pc~0; 8674#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8950#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8302#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8303#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 8493#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8494#L578 assume !(1 == ~t4_pc~0); 8614#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8613#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8433#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8434#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9262#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9263#L597 assume 1 == ~t5_pc~0; 9620#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8420#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8421#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9463#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 9210#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9211#L616 assume !(1 == ~t6_pc~0); 9225#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9224#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8834#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8835#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 9068#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9069#L635 assume 1 == ~t7_pc~0; 9265#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8389#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8764#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9508#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 9203#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9204#L654 assume !(1 == ~t8_pc~0); 9020#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 9021#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9395#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9396#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 9432#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8643#L673 assume 1 == ~t9_pc~0; 8644#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8340#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8915#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8916#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 9355#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9356#L692 assume !(1 == ~t10_pc~0); 9300#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 9299#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9071#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9072#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 9083#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9411#L1142 assume !(1 == ~M_E~0); 8554#L1142-2 assume !(1 == ~T1_E~0); 8555#L1147-1 assume !(1 == ~T2_E~0); 9400#L1152-1 assume !(1 == ~T3_E~0); 8957#L1157-1 assume !(1 == ~T4_E~0); 8958#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9107#L1167-1 assume !(1 == ~T6_E~0); 9108#L1172-1 assume !(1 == ~T7_E~0); 9529#L1177-1 assume !(1 == ~T8_E~0); 9248#L1182-1 assume !(1 == ~T9_E~0); 9249#L1187-1 assume !(1 == ~T10_E~0); 9348#L1192-1 assume !(1 == ~E_M~0); 8812#L1197-1 assume !(1 == ~E_1~0); 8813#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9192#L1207-1 assume !(1 == ~E_3~0); 9168#L1212-1 assume !(1 == ~E_4~0); 8405#L1217-1 assume !(1 == ~E_5~0); 8406#L1222-1 assume !(1 == ~E_6~0); 9165#L1227-1 assume !(1 == ~E_7~0); 9166#L1232-1 assume !(1 == ~E_8~0); 8279#L1237-1 assume !(1 == ~E_9~0); 8280#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 9229#L1247-1 assume { :end_inline_reset_delta_events } true; 8450#L1553-2 [2024-11-13 15:14:29,558 INFO L747 eck$LassoCheckResult]: Loop: 8450#L1553-2 assume !false; 8451#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8590#L999-1 assume !false; 8731#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8538#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8423#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8895#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8896#L854 assume !(0 != eval_~tmp~0#1); 9305#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9092#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9093#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9565#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9065#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9033#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9034#L1039-3 assume !(0 == ~T4_E~0); 9376#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8639#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8640#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8401#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8402#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9003#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9004#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9350#L1079-3 assume !(0 == ~E_1~0); 9240#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9126#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9127#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9052#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9053#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9374#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9362#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9363#L1119-3 assume !(0 == ~E_9~0); 9626#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9633#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9599#L502-36 assume 1 == ~m_pc~0; 9377#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8267#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8268#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8697#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8698#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8976#L521-36 assume 1 == ~t1_pc~0; 8977#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8987#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9157#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9553#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9436#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9437#L540-36 assume 1 == ~t2_pc~0; 9601#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8357#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8769#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9438#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9102#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8276#L559-36 assume 1 == ~t3_pc~0; 8277#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8735#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8910#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8911#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9250#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9490#L578-36 assume 1 == ~t4_pc~0; 9219#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9178#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9114#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9115#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9011#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9012#L597-36 assume !(1 == ~t5_pc~0); 9238#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 9591#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9535#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9193#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 8814#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8815#L616-36 assume 1 == ~t6_pc~0; 9602#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8345#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8346#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8890#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9062#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9391#L635-36 assume 1 == ~t7_pc~0; 9566#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9448#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9449#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9511#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9048#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9049#L654-36 assume !(1 == ~t8_pc~0); 9571#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 9572#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9215#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9216#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9606#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8723#L673-36 assume !(1 == ~t9_pc~0); 8724#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 9090#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8953#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8954#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8286#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8287#L692-36 assume !(1 == ~t10_pc~0); 8501#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 8502#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8796#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8690#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8691#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9061#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9212#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9573#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9574#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9139#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9140#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9444#L1167-3 assume !(1 == ~T6_E~0); 9557#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9047#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8947#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8948#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8960#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8779#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8780#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9030#L1207-3 assume !(1 == ~E_3~0); 9148#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9372#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8683#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8370#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8371#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9473#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9474#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9636#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9522#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8521#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8522#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 8786#L1572 assume !(0 == start_simulation_~tmp~3#1); 8817#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8979#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8300#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8358#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 8359#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8271#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8272#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 9119#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 8450#L1553-2 [2024-11-13 15:14:29,559 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:29,559 INFO L85 PathProgramCache]: Analyzing trace with hash 736734333, now seen corresponding path program 1 times [2024-11-13 15:14:29,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:29,559 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [782890505] [2024-11-13 15:14:29,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:29,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:29,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:29,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:29,630 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:29,631 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [782890505] [2024-11-13 15:14:29,632 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [782890505] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:29,632 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:29,632 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:29,632 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1358637592] [2024-11-13 15:14:29,632 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:29,633 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:14:29,633 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:29,633 INFO L85 PathProgramCache]: Analyzing trace with hash 1735512917, now seen corresponding path program 1 times [2024-11-13 15:14:29,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:29,634 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [966131744] [2024-11-13 15:14:29,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:29,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:29,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:29,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:29,742 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:29,742 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [966131744] [2024-11-13 15:14:29,743 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [966131744] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:29,743 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:29,743 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:29,743 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1847058856] [2024-11-13 15:14:29,743 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:29,743 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:14:29,743 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:14:29,744 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:14:29,744 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:14:29,744 INFO L87 Difference]: Start difference. First operand 1372 states and 2032 transitions. cyclomatic complexity: 661 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:29,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:14:29,779 INFO L93 Difference]: Finished difference Result 1372 states and 2031 transitions. [2024-11-13 15:14:29,779 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2031 transitions. [2024-11-13 15:14:29,788 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-11-13 15:14:29,796 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2031 transitions. [2024-11-13 15:14:29,796 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2024-11-13 15:14:29,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2024-11-13 15:14:29,797 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2031 transitions. [2024-11-13 15:14:29,801 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:14:29,801 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2031 transitions. [2024-11-13 15:14:29,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2031 transitions. [2024-11-13 15:14:29,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2024-11-13 15:14:29,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4803206997084548) internal successors, (2031), 1371 states have internal predecessors, (2031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:29,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2031 transitions. [2024-11-13 15:14:29,831 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2031 transitions. [2024-11-13 15:14:29,831 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:14:29,832 INFO L424 stractBuchiCegarLoop]: Abstraction has 1372 states and 2031 transitions. [2024-11-13 15:14:29,832 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 15:14:29,832 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2031 transitions. [2024-11-13 15:14:29,839 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-11-13 15:14:29,840 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:14:29,841 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:14:29,842 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:29,844 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:29,844 INFO L745 eck$LassoCheckResult]: Stem: 11400#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 11401#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 12303#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12304#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11982#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 11671#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11672#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11952#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12122#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11840#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11841#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11722#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11723#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12076#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12036#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11960#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11961#L1024 assume !(0 == ~M_E~0); 12216#L1024-2 assume !(0 == ~T1_E~0); 11396#L1029-1 assume !(0 == ~T2_E~0); 11397#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11499#L1039-1 assume !(0 == ~T4_E~0); 12326#L1044-1 assume !(0 == ~T5_E~0); 11744#L1049-1 assume !(0 == ~T6_E~0); 11745#L1054-1 assume !(0 == ~T7_E~0); 11981#L1059-1 assume !(0 == ~T8_E~0); 11446#L1064-1 assume !(0 == ~T9_E~0); 11447#L1069-1 assume !(0 == ~T10_E~0); 12185#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 12245#L1079-1 assume !(0 == ~E_1~0); 12218#L1084-1 assume !(0 == ~E_2~0); 12219#L1089-1 assume !(0 == ~E_3~0); 12263#L1094-1 assume !(0 == ~E_4~0); 11830#L1099-1 assume !(0 == ~E_5~0); 11831#L1104-1 assume !(0 == ~E_6~0); 12094#L1109-1 assume !(0 == ~E_7~0); 11613#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 11614#L1119-1 assume !(0 == ~E_9~0); 11684#L1124-1 assume !(0 == ~E_10~0); 11100#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11101#L502 assume 1 == ~m_pc~0; 11979#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11226#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11227#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12032#L1273 assume !(0 != activate_threads_~tmp~1#1); 12033#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12356#L521 assume !(1 == ~t1_pc~0); 12291#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11151#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11116#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11117#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 11137#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11138#L540 assume 1 == ~t2_pc~0; 12229#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11941#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11609#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11610#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 12287#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11424#L559 assume 1 == ~t3_pc~0; 11425#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11702#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11053#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11054#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 11244#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11245#L578 assume !(1 == ~t4_pc~0); 11368#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11367#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11184#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11185#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12013#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12014#L597 assume 1 == ~t5_pc~0; 12372#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11171#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11172#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12214#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 11962#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11963#L616 assume !(1 == ~t6_pc~0); 11978#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11977#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11585#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11586#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 11820#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11821#L635 assume 1 == ~t7_pc~0; 12017#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11140#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11517#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12259#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 11954#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11955#L654 assume !(1 == ~t8_pc~0); 11771#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11772#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12147#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12148#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 12183#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11394#L673 assume 1 == ~t9_pc~0; 11395#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11091#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11666#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11667#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 12106#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12107#L692 assume !(1 == ~t10_pc~0); 12051#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12050#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11822#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11823#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 11834#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12162#L1142 assume !(1 == ~M_E~0); 11305#L1142-2 assume !(1 == ~T1_E~0); 11306#L1147-1 assume !(1 == ~T2_E~0); 12151#L1152-1 assume !(1 == ~T3_E~0); 11708#L1157-1 assume !(1 == ~T4_E~0); 11709#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11858#L1167-1 assume !(1 == ~T6_E~0); 11859#L1172-1 assume !(1 == ~T7_E~0); 12281#L1177-1 assume !(1 == ~T8_E~0); 11999#L1182-1 assume !(1 == ~T9_E~0); 12000#L1187-1 assume !(1 == ~T10_E~0); 12099#L1192-1 assume !(1 == ~E_M~0); 11565#L1197-1 assume !(1 == ~E_1~0); 11566#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 11944#L1207-1 assume !(1 == ~E_3~0); 11919#L1212-1 assume !(1 == ~E_4~0); 11156#L1217-1 assume !(1 == ~E_5~0); 11157#L1222-1 assume !(1 == ~E_6~0); 11916#L1227-1 assume !(1 == ~E_7~0); 11917#L1232-1 assume !(1 == ~E_8~0); 11030#L1237-1 assume !(1 == ~E_9~0); 11031#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 11980#L1247-1 assume { :end_inline_reset_delta_events } true; 11201#L1553-2 [2024-11-13 15:14:29,845 INFO L747 eck$LassoCheckResult]: Loop: 11201#L1553-2 assume !false; 11202#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11341#L999-1 assume !false; 11482#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11289#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11174#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11646#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11647#L854 assume !(0 != eval_~tmp~0#1); 12056#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11843#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11844#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12316#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11816#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11784#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11785#L1039-3 assume !(0 == ~T4_E~0); 12127#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11390#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11391#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11152#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11153#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11754#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11755#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12101#L1079-3 assume !(0 == ~E_1~0); 11992#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11877#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11878#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11803#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11804#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12125#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12113#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12114#L1119-3 assume !(0 == ~E_9~0); 12377#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12384#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12350#L502-36 assume 1 == ~m_pc~0; 12128#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11018#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11019#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11448#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11449#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11727#L521-36 assume 1 == ~t1_pc~0; 11728#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11738#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11908#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12302#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12187#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12188#L540-36 assume 1 == ~t2_pc~0; 12352#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11103#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11520#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12189#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11853#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11024#L559-36 assume 1 == ~t3_pc~0; 11025#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11483#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11661#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11662#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12001#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12241#L578-36 assume 1 == ~t4_pc~0; 11970#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11927#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11865#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11866#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11762#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11763#L597-36 assume !(1 == ~t5_pc~0); 11989#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 12342#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12286#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11943#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 11563#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11564#L616-36 assume 1 == ~t6_pc~0; 12353#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11096#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11097#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11641#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11813#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12142#L635-36 assume 1 == ~t7_pc~0; 12317#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12199#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12200#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12262#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11799#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11800#L654-36 assume !(1 == ~t8_pc~0); 12322#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 12323#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11966#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11967#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12357#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11474#L673-36 assume !(1 == ~t9_pc~0); 11475#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 11839#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11704#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11705#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11037#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11038#L692-36 assume !(1 == ~t10_pc~0); 11252#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 11253#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11547#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11441#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11442#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11810#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11959#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12324#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12325#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11890#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11891#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12195#L1167-3 assume !(1 == ~T6_E~0); 12308#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11798#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11696#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11697#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11711#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11530#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11531#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11781#L1207-3 assume !(1 == ~E_3~0); 11899#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12123#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11434#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11121#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11122#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12224#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12225#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12387#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 12273#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11272#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11273#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 11537#L1572 assume !(0 == start_simulation_~tmp~3#1); 11568#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11730#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11051#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11109#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 11110#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11022#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11023#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 11870#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 11201#L1553-2 [2024-11-13 15:14:29,845 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:29,846 INFO L85 PathProgramCache]: Analyzing trace with hash 1829369535, now seen corresponding path program 1 times [2024-11-13 15:14:29,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:29,846 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [122945331] [2024-11-13 15:14:29,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:29,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:29,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:29,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:29,925 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:29,925 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [122945331] [2024-11-13 15:14:29,925 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [122945331] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:29,925 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:29,926 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:29,926 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [587023273] [2024-11-13 15:14:29,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:29,926 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:14:29,926 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:29,926 INFO L85 PathProgramCache]: Analyzing trace with hash 1735512917, now seen corresponding path program 2 times [2024-11-13 15:14:29,926 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:29,926 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [856354509] [2024-11-13 15:14:29,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:29,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:29,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:30,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:30,016 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:30,016 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [856354509] [2024-11-13 15:14:30,016 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [856354509] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:30,016 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:30,016 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:30,016 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2044088592] [2024-11-13 15:14:30,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:30,017 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:14:30,017 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:14:30,018 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:14:30,018 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:14:30,018 INFO L87 Difference]: Start difference. First operand 1372 states and 2031 transitions. cyclomatic complexity: 660 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:30,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:14:30,051 INFO L93 Difference]: Finished difference Result 1372 states and 2030 transitions. [2024-11-13 15:14:30,051 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2030 transitions. [2024-11-13 15:14:30,060 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-11-13 15:14:30,066 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2030 transitions. [2024-11-13 15:14:30,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2024-11-13 15:14:30,067 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2024-11-13 15:14:30,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2030 transitions. [2024-11-13 15:14:30,070 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:14:30,070 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2030 transitions. [2024-11-13 15:14:30,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2030 transitions. [2024-11-13 15:14:30,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2024-11-13 15:14:30,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4795918367346939) internal successors, (2030), 1371 states have internal predecessors, (2030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:30,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2030 transitions. [2024-11-13 15:14:30,096 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2030 transitions. [2024-11-13 15:14:30,097 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:14:30,099 INFO L424 stractBuchiCegarLoop]: Abstraction has 1372 states and 2030 transitions. [2024-11-13 15:14:30,099 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 15:14:30,099 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2030 transitions. [2024-11-13 15:14:30,106 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-11-13 15:14:30,106 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:14:30,106 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:14:30,108 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:30,109 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:30,109 INFO L745 eck$LassoCheckResult]: Stem: 14151#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 14152#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 15053#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15054#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14733#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 14421#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14422#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14703#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14873#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14590#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14591#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14473#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14474#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14827#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14787#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14710#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14711#L1024 assume !(0 == ~M_E~0); 14967#L1024-2 assume !(0 == ~T1_E~0); 14147#L1029-1 assume !(0 == ~T2_E~0); 14148#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14250#L1039-1 assume !(0 == ~T4_E~0); 15077#L1044-1 assume !(0 == ~T5_E~0); 14493#L1049-1 assume !(0 == ~T6_E~0); 14494#L1054-1 assume !(0 == ~T7_E~0); 14732#L1059-1 assume !(0 == ~T8_E~0); 14197#L1064-1 assume !(0 == ~T9_E~0); 14198#L1069-1 assume !(0 == ~T10_E~0); 14936#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 14996#L1079-1 assume !(0 == ~E_1~0); 14969#L1084-1 assume !(0 == ~E_2~0); 14970#L1089-1 assume !(0 == ~E_3~0); 15014#L1094-1 assume !(0 == ~E_4~0); 14581#L1099-1 assume !(0 == ~E_5~0); 14582#L1104-1 assume !(0 == ~E_6~0); 14845#L1109-1 assume !(0 == ~E_7~0); 14364#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 14365#L1119-1 assume !(0 == ~E_9~0); 14431#L1124-1 assume !(0 == ~E_10~0); 13851#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13852#L502 assume 1 == ~m_pc~0; 14730#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13977#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13978#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14781#L1273 assume !(0 != activate_threads_~tmp~1#1); 14782#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15107#L521 assume !(1 == ~t1_pc~0); 15042#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13902#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13867#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13868#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 13888#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13889#L540 assume 1 == ~t2_pc~0; 14980#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14692#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14360#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14361#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 15038#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14175#L559 assume 1 == ~t3_pc~0; 14176#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14452#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13804#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13805#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 13995#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13996#L578 assume !(1 == ~t4_pc~0); 14114#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14113#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13934#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13935#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14762#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14763#L597 assume 1 == ~t5_pc~0; 15122#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13922#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13923#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14965#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 14712#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14713#L616 assume !(1 == ~t6_pc~0); 14727#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14726#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14336#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14337#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 14570#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14571#L635 assume 1 == ~t7_pc~0; 14767#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13891#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14266#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15010#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 14705#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14706#L654 assume !(1 == ~t8_pc~0); 14522#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14523#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14895#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14896#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 14934#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14145#L673 assume 1 == ~t9_pc~0; 14146#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13842#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14415#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14416#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 14857#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14858#L692 assume !(1 == ~t10_pc~0); 14802#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14801#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14573#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14574#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 14585#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14913#L1142 assume !(1 == ~M_E~0); 14056#L1142-2 assume !(1 == ~T1_E~0); 14057#L1147-1 assume !(1 == ~T2_E~0); 14902#L1152-1 assume !(1 == ~T3_E~0); 14459#L1157-1 assume !(1 == ~T4_E~0); 14460#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14609#L1167-1 assume !(1 == ~T6_E~0); 14610#L1172-1 assume !(1 == ~T7_E~0); 15031#L1177-1 assume !(1 == ~T8_E~0); 14750#L1182-1 assume !(1 == ~T9_E~0); 14751#L1187-1 assume !(1 == ~T10_E~0); 14850#L1192-1 assume !(1 == ~E_M~0); 14314#L1197-1 assume !(1 == ~E_1~0); 14315#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 14694#L1207-1 assume !(1 == ~E_3~0); 14670#L1212-1 assume !(1 == ~E_4~0); 13907#L1217-1 assume !(1 == ~E_5~0); 13908#L1222-1 assume !(1 == ~E_6~0); 14667#L1227-1 assume !(1 == ~E_7~0); 14668#L1232-1 assume !(1 == ~E_8~0); 13781#L1237-1 assume !(1 == ~E_9~0); 13782#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 14731#L1247-1 assume { :end_inline_reset_delta_events } true; 13952#L1553-2 [2024-11-13 15:14:30,109 INFO L747 eck$LassoCheckResult]: Loop: 13952#L1553-2 assume !false; 13953#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14092#L999-1 assume !false; 14233#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14040#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13925#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14397#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14398#L854 assume !(0 != eval_~tmp~0#1); 14807#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14594#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14595#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15067#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14567#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14535#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14536#L1039-3 assume !(0 == ~T4_E~0); 14878#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14141#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14142#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13903#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13904#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14505#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14506#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14852#L1079-3 assume !(0 == ~E_1~0); 14742#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14628#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14629#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14554#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14555#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14876#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14864#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14865#L1119-3 assume !(0 == ~E_9~0); 15128#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15135#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15101#L502-36 assume !(1 == ~m_pc~0); 14284#L502-38 is_master_triggered_~__retres1~0#1 := 0; 13769#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13770#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14199#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14200#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14478#L521-36 assume !(1 == ~t1_pc~0); 14480#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 14489#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14659#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15055#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14938#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14939#L540-36 assume !(1 == ~t2_pc~0); 13858#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 13859#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14271#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14940#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14604#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13778#L559-36 assume 1 == ~t3_pc~0; 13779#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14237#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14412#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14413#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14752#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14992#L578-36 assume 1 == ~t4_pc~0; 14721#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14680#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14616#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14617#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14513#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14514#L597-36 assume !(1 == ~t5_pc~0); 14740#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 15093#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15037#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14695#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 14316#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14317#L616-36 assume 1 == ~t6_pc~0; 15104#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13847#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13848#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14392#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14564#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14893#L635-36 assume 1 == ~t7_pc~0; 15068#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14950#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14951#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15013#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14550#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14551#L654-36 assume !(1 == ~t8_pc~0); 15073#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 15074#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14717#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14718#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15108#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14225#L673-36 assume !(1 == ~t9_pc~0); 14226#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 14592#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14455#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14456#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13788#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13789#L692-36 assume !(1 == ~t10_pc~0); 14003#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 14004#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14298#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14192#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14193#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14563#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14714#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15075#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15076#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14641#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14642#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14946#L1167-3 assume !(1 == ~T6_E~0); 15059#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14549#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14447#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14448#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14462#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14281#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14282#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14532#L1207-3 assume !(1 == ~E_3~0); 14650#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14874#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14185#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13872#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13873#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14975#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14976#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15138#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 15024#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 14023#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14024#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 14288#L1572 assume !(0 == start_simulation_~tmp~3#1); 14319#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14481#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13802#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13860#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 13861#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13773#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13774#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 14621#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 13952#L1553-2 [2024-11-13 15:14:30,110 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:30,110 INFO L85 PathProgramCache]: Analyzing trace with hash -1183425475, now seen corresponding path program 1 times [2024-11-13 15:14:30,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:30,111 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2031285437] [2024-11-13 15:14:30,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:30,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:30,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:30,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:30,176 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:30,176 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2031285437] [2024-11-13 15:14:30,177 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2031285437] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:30,177 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:30,177 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:30,177 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [83976446] [2024-11-13 15:14:30,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:30,177 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:14:30,178 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:30,178 INFO L85 PathProgramCache]: Analyzing trace with hash -808236584, now seen corresponding path program 1 times [2024-11-13 15:14:30,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:30,178 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [777415281] [2024-11-13 15:14:30,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:30,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:30,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:30,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:30,251 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:30,252 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [777415281] [2024-11-13 15:14:30,252 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [777415281] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:30,252 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:30,252 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:30,252 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1115668456] [2024-11-13 15:14:30,252 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:30,253 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:14:30,253 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:14:30,253 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:14:30,253 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:14:30,253 INFO L87 Difference]: Start difference. First operand 1372 states and 2030 transitions. cyclomatic complexity: 659 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:30,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:14:30,290 INFO L93 Difference]: Finished difference Result 1372 states and 2029 transitions. [2024-11-13 15:14:30,290 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2029 transitions. [2024-11-13 15:14:30,299 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-11-13 15:14:30,306 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2029 transitions. [2024-11-13 15:14:30,306 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2024-11-13 15:14:30,307 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2024-11-13 15:14:30,307 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2029 transitions. [2024-11-13 15:14:30,310 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:14:30,310 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2029 transitions. [2024-11-13 15:14:30,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2029 transitions. [2024-11-13 15:14:30,328 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2024-11-13 15:14:30,330 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.478862973760933) internal successors, (2029), 1371 states have internal predecessors, (2029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:30,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2029 transitions. [2024-11-13 15:14:30,335 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2029 transitions. [2024-11-13 15:14:30,337 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:14:30,338 INFO L424 stractBuchiCegarLoop]: Abstraction has 1372 states and 2029 transitions. [2024-11-13 15:14:30,340 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 15:14:30,340 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2029 transitions. [2024-11-13 15:14:30,348 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-11-13 15:14:30,348 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:14:30,348 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:14:30,351 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:30,351 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:30,351 INFO L745 eck$LassoCheckResult]: Stem: 16902#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 16903#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 17804#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17805#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17484#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 17172#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17173#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17454#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17624#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17341#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17342#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17224#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17225#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17578#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17538#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17461#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17462#L1024 assume !(0 == ~M_E~0); 17718#L1024-2 assume !(0 == ~T1_E~0); 16898#L1029-1 assume !(0 == ~T2_E~0); 16899#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17001#L1039-1 assume !(0 == ~T4_E~0); 17828#L1044-1 assume !(0 == ~T5_E~0); 17244#L1049-1 assume !(0 == ~T6_E~0); 17245#L1054-1 assume !(0 == ~T7_E~0); 17483#L1059-1 assume !(0 == ~T8_E~0); 16948#L1064-1 assume !(0 == ~T9_E~0); 16949#L1069-1 assume !(0 == ~T10_E~0); 17687#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 17747#L1079-1 assume !(0 == ~E_1~0); 17720#L1084-1 assume !(0 == ~E_2~0); 17721#L1089-1 assume !(0 == ~E_3~0); 17765#L1094-1 assume !(0 == ~E_4~0); 17332#L1099-1 assume !(0 == ~E_5~0); 17333#L1104-1 assume !(0 == ~E_6~0); 17596#L1109-1 assume !(0 == ~E_7~0); 17115#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 17116#L1119-1 assume !(0 == ~E_9~0); 17182#L1124-1 assume !(0 == ~E_10~0); 16602#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16603#L502 assume 1 == ~m_pc~0; 17481#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16728#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16729#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17532#L1273 assume !(0 != activate_threads_~tmp~1#1); 17533#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17858#L521 assume !(1 == ~t1_pc~0); 17793#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16653#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16618#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16619#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 16639#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16640#L540 assume 1 == ~t2_pc~0; 17731#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17443#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17111#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17112#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 17789#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16926#L559 assume 1 == ~t3_pc~0; 16927#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17203#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16555#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16556#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 16746#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16747#L578 assume !(1 == ~t4_pc~0); 16868#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16867#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16686#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16687#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17515#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17516#L597 assume 1 == ~t5_pc~0; 17873#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16673#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16674#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17716#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 17463#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17464#L616 assume !(1 == ~t6_pc~0); 17478#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17477#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17087#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17088#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 17321#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17322#L635 assume 1 == ~t7_pc~0; 17518#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16642#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17017#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17761#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 17456#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17457#L654 assume !(1 == ~t8_pc~0); 17273#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17274#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17648#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17649#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 17685#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16896#L673 assume 1 == ~t9_pc~0; 16897#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16593#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17168#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17169#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 17608#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17609#L692 assume !(1 == ~t10_pc~0); 17553#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17552#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17324#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17325#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 17336#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17664#L1142 assume !(1 == ~M_E~0); 16807#L1142-2 assume !(1 == ~T1_E~0); 16808#L1147-1 assume !(1 == ~T2_E~0); 17653#L1152-1 assume !(1 == ~T3_E~0); 17210#L1157-1 assume !(1 == ~T4_E~0); 17211#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17360#L1167-1 assume !(1 == ~T6_E~0); 17361#L1172-1 assume !(1 == ~T7_E~0); 17782#L1177-1 assume !(1 == ~T8_E~0); 17501#L1182-1 assume !(1 == ~T9_E~0); 17502#L1187-1 assume !(1 == ~T10_E~0); 17601#L1192-1 assume !(1 == ~E_M~0); 17065#L1197-1 assume !(1 == ~E_1~0); 17066#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 17445#L1207-1 assume !(1 == ~E_3~0); 17421#L1212-1 assume !(1 == ~E_4~0); 16658#L1217-1 assume !(1 == ~E_5~0); 16659#L1222-1 assume !(1 == ~E_6~0); 17418#L1227-1 assume !(1 == ~E_7~0); 17419#L1232-1 assume !(1 == ~E_8~0); 16532#L1237-1 assume !(1 == ~E_9~0); 16533#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 17482#L1247-1 assume { :end_inline_reset_delta_events } true; 16703#L1553-2 [2024-11-13 15:14:30,352 INFO L747 eck$LassoCheckResult]: Loop: 16703#L1553-2 assume !false; 16704#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16843#L999-1 assume !false; 16984#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16791#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16676#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17148#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17149#L854 assume !(0 != eval_~tmp~0#1); 17558#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17345#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17346#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17818#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17318#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17286#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17287#L1039-3 assume !(0 == ~T4_E~0); 17629#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16892#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16893#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16654#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16655#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17256#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17257#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17603#L1079-3 assume !(0 == ~E_1~0); 17493#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17379#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17380#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17305#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17306#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17627#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17615#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17616#L1119-3 assume !(0 == ~E_9~0); 17879#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17886#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17852#L502-36 assume !(1 == ~m_pc~0); 17035#L502-38 is_master_triggered_~__retres1~0#1 := 0; 16520#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16521#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16950#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16951#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17229#L521-36 assume 1 == ~t1_pc~0; 17230#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17240#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17410#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17806#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17689#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17690#L540-36 assume !(1 == ~t2_pc~0); 16609#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 16610#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17022#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17691#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17355#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16529#L559-36 assume 1 == ~t3_pc~0; 16530#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16988#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17163#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17164#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17503#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17743#L578-36 assume 1 == ~t4_pc~0; 17473#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17431#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17367#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17368#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17264#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17265#L597-36 assume !(1 == ~t5_pc~0); 17491#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 17844#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17788#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17446#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 17067#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17068#L616-36 assume !(1 == ~t6_pc~0); 17814#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 16598#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16599#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17143#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17315#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17644#L635-36 assume 1 == ~t7_pc~0; 17819#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17701#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17702#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17764#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17301#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17302#L654-36 assume !(1 == ~t8_pc~0); 17824#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 17825#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17468#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17469#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17859#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16976#L673-36 assume !(1 == ~t9_pc~0); 16977#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 17343#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17206#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17207#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16539#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16540#L692-36 assume !(1 == ~t10_pc~0); 16754#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 16755#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17049#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16943#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16944#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17314#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17465#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17826#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17827#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17392#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17393#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17697#L1167-3 assume !(1 == ~T6_E~0); 17811#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17300#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17200#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17201#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17213#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17032#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17033#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17283#L1207-3 assume !(1 == ~E_3~0); 17401#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17626#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16936#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16623#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16624#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17726#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17727#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17889#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17775#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16774#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16775#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 17039#L1572 assume !(0 == start_simulation_~tmp~3#1); 17070#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17232#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16553#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16611#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 16612#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16524#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16525#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 17372#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 16703#L1553-2 [2024-11-13 15:14:30,352 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:30,353 INFO L85 PathProgramCache]: Analyzing trace with hash 659050239, now seen corresponding path program 1 times [2024-11-13 15:14:30,353 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:30,353 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1231697522] [2024-11-13 15:14:30,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:30,353 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:30,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:30,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:30,453 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:30,453 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1231697522] [2024-11-13 15:14:30,453 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1231697522] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:30,453 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:30,453 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:30,453 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [545297703] [2024-11-13 15:14:30,453 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:30,454 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:14:30,454 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:30,454 INFO L85 PathProgramCache]: Analyzing trace with hash -303517288, now seen corresponding path program 1 times [2024-11-13 15:14:30,454 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:30,454 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [256498095] [2024-11-13 15:14:30,454 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:30,454 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:30,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:30,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:30,524 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:30,524 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [256498095] [2024-11-13 15:14:30,524 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [256498095] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:30,524 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:30,524 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:30,524 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [494563677] [2024-11-13 15:14:30,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:30,524 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:14:30,525 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:14:30,525 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:14:30,525 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:14:30,525 INFO L87 Difference]: Start difference. First operand 1372 states and 2029 transitions. cyclomatic complexity: 658 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:30,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:14:30,558 INFO L93 Difference]: Finished difference Result 1372 states and 2028 transitions. [2024-11-13 15:14:30,558 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2028 transitions. [2024-11-13 15:14:30,568 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-11-13 15:14:30,575 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2028 transitions. [2024-11-13 15:14:30,575 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2024-11-13 15:14:30,576 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2024-11-13 15:14:30,576 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2028 transitions. [2024-11-13 15:14:30,578 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:14:30,578 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2028 transitions. [2024-11-13 15:14:30,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2028 transitions. [2024-11-13 15:14:30,598 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2024-11-13 15:14:30,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.478134110787172) internal successors, (2028), 1371 states have internal predecessors, (2028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:30,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2028 transitions. [2024-11-13 15:14:30,606 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2028 transitions. [2024-11-13 15:14:30,607 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:14:30,609 INFO L424 stractBuchiCegarLoop]: Abstraction has 1372 states and 2028 transitions. [2024-11-13 15:14:30,609 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 15:14:30,609 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2028 transitions. [2024-11-13 15:14:30,615 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-11-13 15:14:30,615 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:14:30,615 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:14:30,617 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:30,617 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:30,620 INFO L745 eck$LassoCheckResult]: Stem: 19653#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 19654#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 20556#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20557#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20235#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 19924#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19925#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20206#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20375#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20093#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20094#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19978#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19979#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20329#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20289#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20213#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20214#L1024 assume !(0 == ~M_E~0); 20469#L1024-2 assume !(0 == ~T1_E~0); 19649#L1029-1 assume !(0 == ~T2_E~0); 19650#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19752#L1039-1 assume !(0 == ~T4_E~0); 20580#L1044-1 assume !(0 == ~T5_E~0); 19997#L1049-1 assume !(0 == ~T6_E~0); 19998#L1054-1 assume !(0 == ~T7_E~0); 20234#L1059-1 assume !(0 == ~T8_E~0); 19699#L1064-1 assume !(0 == ~T9_E~0); 19700#L1069-1 assume !(0 == ~T10_E~0); 20438#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 20498#L1079-1 assume !(0 == ~E_1~0); 20471#L1084-1 assume !(0 == ~E_2~0); 20472#L1089-1 assume !(0 == ~E_3~0); 20516#L1094-1 assume !(0 == ~E_4~0); 20083#L1099-1 assume !(0 == ~E_5~0); 20084#L1104-1 assume !(0 == ~E_6~0); 20347#L1109-1 assume !(0 == ~E_7~0); 19866#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 19867#L1119-1 assume !(0 == ~E_9~0); 19937#L1124-1 assume !(0 == ~E_10~0); 19353#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19354#L502 assume 1 == ~m_pc~0; 20232#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19479#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19480#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20285#L1273 assume !(0 != activate_threads_~tmp~1#1); 20286#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20609#L521 assume !(1 == ~t1_pc~0); 20544#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19404#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19369#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19370#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 19390#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19391#L540 assume 1 == ~t2_pc~0; 20482#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20194#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19864#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19865#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 20540#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19677#L559 assume 1 == ~t3_pc~0; 19678#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19955#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19306#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19307#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 19497#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19498#L578 assume !(1 == ~t4_pc~0); 19621#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19620#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19437#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19438#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20266#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20267#L597 assume 1 == ~t5_pc~0; 20625#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19424#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19425#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20467#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 20215#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20216#L616 assume !(1 == ~t6_pc~0); 20231#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 20230#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19838#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19839#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 20073#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20074#L635 assume 1 == ~t7_pc~0; 20270#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19393#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19770#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20512#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 20207#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20208#L654 assume !(1 == ~t8_pc~0); 20024#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 20025#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20400#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20401#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 20436#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19647#L673 assume 1 == ~t9_pc~0; 19648#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19344#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19919#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19920#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 20359#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20360#L692 assume !(1 == ~t10_pc~0); 20304#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20303#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20075#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20076#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 20087#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20415#L1142 assume !(1 == ~M_E~0); 19558#L1142-2 assume !(1 == ~T1_E~0); 19559#L1147-1 assume !(1 == ~T2_E~0); 20404#L1152-1 assume !(1 == ~T3_E~0); 19961#L1157-1 assume !(1 == ~T4_E~0); 19962#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20111#L1167-1 assume !(1 == ~T6_E~0); 20112#L1172-1 assume !(1 == ~T7_E~0); 20534#L1177-1 assume !(1 == ~T8_E~0); 20252#L1182-1 assume !(1 == ~T9_E~0); 20253#L1187-1 assume !(1 == ~T10_E~0); 20352#L1192-1 assume !(1 == ~E_M~0); 19818#L1197-1 assume !(1 == ~E_1~0); 19819#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 20197#L1207-1 assume !(1 == ~E_3~0); 20172#L1212-1 assume !(1 == ~E_4~0); 19409#L1217-1 assume !(1 == ~E_5~0); 19410#L1222-1 assume !(1 == ~E_6~0); 20169#L1227-1 assume !(1 == ~E_7~0); 20170#L1232-1 assume !(1 == ~E_8~0); 19283#L1237-1 assume !(1 == ~E_9~0); 19284#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 20233#L1247-1 assume { :end_inline_reset_delta_events } true; 19454#L1553-2 [2024-11-13 15:14:30,621 INFO L747 eck$LassoCheckResult]: Loop: 19454#L1553-2 assume !false; 19455#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19594#L999-1 assume !false; 19735#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19542#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19427#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19899#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19900#L854 assume !(0 != eval_~tmp~0#1); 20309#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20096#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20097#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20569#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20069#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20037#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20038#L1039-3 assume !(0 == ~T4_E~0); 20380#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19643#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19644#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19405#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19406#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 20007#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 20008#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20354#L1079-3 assume !(0 == ~E_1~0); 20245#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20130#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20131#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20056#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20057#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20378#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20366#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20367#L1119-3 assume !(0 == ~E_9~0); 20630#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20637#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20603#L502-36 assume !(1 == ~m_pc~0); 19786#L502-38 is_master_triggered_~__retres1~0#1 := 0; 19271#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19272#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19701#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19702#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19975#L521-36 assume 1 == ~t1_pc~0; 19976#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19991#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20161#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20555#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20440#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20441#L540-36 assume !(1 == ~t2_pc~0); 19357#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 19358#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19773#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20442#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20106#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19277#L559-36 assume 1 == ~t3_pc~0; 19278#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19739#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19914#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19915#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20254#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20494#L578-36 assume !(1 == ~t4_pc~0); 20179#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 20180#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20118#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20119#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20015#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20016#L597-36 assume !(1 == ~t5_pc~0); 20242#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 20595#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20539#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20196#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 19816#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19817#L616-36 assume !(1 == ~t6_pc~0); 20565#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 19349#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19350#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19894#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20066#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20395#L635-36 assume 1 == ~t7_pc~0; 20570#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20452#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20453#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20515#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20052#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20053#L654-36 assume 1 == ~t8_pc~0; 20633#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20576#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20219#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20220#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20610#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19727#L673-36 assume !(1 == ~t9_pc~0); 19728#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 20092#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19957#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19958#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19290#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19291#L692-36 assume !(1 == ~t10_pc~0); 19505#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 19506#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19800#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19694#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19695#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20063#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20212#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20577#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20578#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20143#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20144#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20448#L1167-3 assume !(1 == ~T6_E~0); 20561#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20051#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19949#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19950#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19964#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19783#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19784#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20034#L1207-3 assume !(1 == ~E_3~0); 20152#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20376#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19687#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19374#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19375#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20477#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20478#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20640#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 20526#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19525#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19526#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 19790#L1572 assume !(0 == start_simulation_~tmp~3#1); 19821#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19983#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19304#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19362#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 19363#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19275#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19276#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 20123#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 19454#L1553-2 [2024-11-13 15:14:30,621 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:30,621 INFO L85 PathProgramCache]: Analyzing trace with hash -1913914371, now seen corresponding path program 1 times [2024-11-13 15:14:30,621 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:30,622 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1288281368] [2024-11-13 15:14:30,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:30,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:30,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:30,678 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:30,678 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:30,678 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1288281368] [2024-11-13 15:14:30,678 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1288281368] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:30,679 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:30,679 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:30,679 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [84426144] [2024-11-13 15:14:30,679 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:30,679 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:14:30,679 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:30,680 INFO L85 PathProgramCache]: Analyzing trace with hash -1872052584, now seen corresponding path program 1 times [2024-11-13 15:14:30,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:30,682 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [121070037] [2024-11-13 15:14:30,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:30,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:30,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:30,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:30,771 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:30,771 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [121070037] [2024-11-13 15:14:30,771 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [121070037] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:30,771 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:30,771 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:30,771 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1179021813] [2024-11-13 15:14:30,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:30,772 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:14:30,772 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:14:30,772 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:14:30,772 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:14:30,772 INFO L87 Difference]: Start difference. First operand 1372 states and 2028 transitions. cyclomatic complexity: 657 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:30,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:14:30,811 INFO L93 Difference]: Finished difference Result 1372 states and 2027 transitions. [2024-11-13 15:14:30,812 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2027 transitions. [2024-11-13 15:14:30,820 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-11-13 15:14:30,827 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2027 transitions. [2024-11-13 15:14:30,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2024-11-13 15:14:30,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2024-11-13 15:14:30,829 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2027 transitions. [2024-11-13 15:14:30,831 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:14:30,831 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2027 transitions. [2024-11-13 15:14:30,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2027 transitions. [2024-11-13 15:14:30,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2024-11-13 15:14:30,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.477405247813411) internal successors, (2027), 1371 states have internal predecessors, (2027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:30,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2027 transitions. [2024-11-13 15:14:30,859 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2027 transitions. [2024-11-13 15:14:30,860 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:14:30,862 INFO L424 stractBuchiCegarLoop]: Abstraction has 1372 states and 2027 transitions. [2024-11-13 15:14:30,862 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 15:14:30,862 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2027 transitions. [2024-11-13 15:14:30,868 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-11-13 15:14:30,868 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:14:30,868 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:14:30,870 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:30,871 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:30,871 INFO L745 eck$LassoCheckResult]: Stem: 22404#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 22405#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 23306#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23307#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22986#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 22674#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22675#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22956#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23126#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22843#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22844#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22726#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22727#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 23080#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 23040#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22963#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22964#L1024 assume !(0 == ~M_E~0); 23220#L1024-2 assume !(0 == ~T1_E~0); 22400#L1029-1 assume !(0 == ~T2_E~0); 22401#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22503#L1039-1 assume !(0 == ~T4_E~0); 23330#L1044-1 assume !(0 == ~T5_E~0); 22746#L1049-1 assume !(0 == ~T6_E~0); 22747#L1054-1 assume !(0 == ~T7_E~0); 22985#L1059-1 assume !(0 == ~T8_E~0); 22450#L1064-1 assume !(0 == ~T9_E~0); 22451#L1069-1 assume !(0 == ~T10_E~0); 23189#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 23249#L1079-1 assume !(0 == ~E_1~0); 23222#L1084-1 assume !(0 == ~E_2~0); 23223#L1089-1 assume !(0 == ~E_3~0); 23267#L1094-1 assume !(0 == ~E_4~0); 22834#L1099-1 assume !(0 == ~E_5~0); 22835#L1104-1 assume !(0 == ~E_6~0); 23098#L1109-1 assume !(0 == ~E_7~0); 22617#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 22618#L1119-1 assume !(0 == ~E_9~0); 22684#L1124-1 assume !(0 == ~E_10~0); 22104#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22105#L502 assume 1 == ~m_pc~0; 22983#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22230#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22231#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23034#L1273 assume !(0 != activate_threads_~tmp~1#1); 23035#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23360#L521 assume !(1 == ~t1_pc~0); 23295#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22155#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22120#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22121#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 22141#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22142#L540 assume 1 == ~t2_pc~0; 23233#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22945#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22613#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22614#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 23291#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22428#L559 assume 1 == ~t3_pc~0; 22429#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22705#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22057#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22058#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 22248#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22249#L578 assume !(1 == ~t4_pc~0); 22367#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22366#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22187#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22188#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23015#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23016#L597 assume 1 == ~t5_pc~0; 23375#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22175#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22176#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23218#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 22965#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22966#L616 assume !(1 == ~t6_pc~0); 22980#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22979#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22589#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22590#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 22823#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22824#L635 assume 1 == ~t7_pc~0; 23020#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22144#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22519#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23263#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 22958#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22959#L654 assume !(1 == ~t8_pc~0); 22775#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22776#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23148#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23149#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 23187#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22398#L673 assume 1 == ~t9_pc~0; 22399#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22095#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22668#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22669#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 23110#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23111#L692 assume !(1 == ~t10_pc~0); 23055#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 23054#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22826#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22827#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 22838#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23166#L1142 assume !(1 == ~M_E~0); 22309#L1142-2 assume !(1 == ~T1_E~0); 22310#L1147-1 assume !(1 == ~T2_E~0); 23155#L1152-1 assume !(1 == ~T3_E~0); 22712#L1157-1 assume !(1 == ~T4_E~0); 22713#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22862#L1167-1 assume !(1 == ~T6_E~0); 22863#L1172-1 assume !(1 == ~T7_E~0); 23284#L1177-1 assume !(1 == ~T8_E~0); 23003#L1182-1 assume !(1 == ~T9_E~0); 23004#L1187-1 assume !(1 == ~T10_E~0); 23103#L1192-1 assume !(1 == ~E_M~0); 22567#L1197-1 assume !(1 == ~E_1~0); 22568#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22947#L1207-1 assume !(1 == ~E_3~0); 22923#L1212-1 assume !(1 == ~E_4~0); 22160#L1217-1 assume !(1 == ~E_5~0); 22161#L1222-1 assume !(1 == ~E_6~0); 22920#L1227-1 assume !(1 == ~E_7~0); 22921#L1232-1 assume !(1 == ~E_8~0); 22034#L1237-1 assume !(1 == ~E_9~0); 22035#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22984#L1247-1 assume { :end_inline_reset_delta_events } true; 22205#L1553-2 [2024-11-13 15:14:30,871 INFO L747 eck$LassoCheckResult]: Loop: 22205#L1553-2 assume !false; 22206#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22345#L999-1 assume !false; 22486#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22293#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22178#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22650#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22651#L854 assume !(0 != eval_~tmp~0#1); 23060#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22847#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22848#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23320#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22820#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22788#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22789#L1039-3 assume !(0 == ~T4_E~0); 23131#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22394#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22395#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22156#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22157#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22758#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22759#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23105#L1079-3 assume !(0 == ~E_1~0); 22995#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22881#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22882#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22807#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22808#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23129#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23117#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23118#L1119-3 assume !(0 == ~E_9~0); 23381#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23388#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23354#L502-36 assume !(1 == ~m_pc~0); 22537#L502-38 is_master_triggered_~__retres1~0#1 := 0; 22022#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22023#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22452#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22453#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22731#L521-36 assume 1 == ~t1_pc~0; 22732#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22742#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22912#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23308#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23191#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23192#L540-36 assume 1 == ~t2_pc~0; 23356#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22112#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22524#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23193#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22857#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22031#L559-36 assume 1 == ~t3_pc~0; 22032#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22490#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22665#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22666#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23005#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23245#L578-36 assume !(1 == ~t4_pc~0); 22932#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 22933#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22869#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22870#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22766#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22767#L597-36 assume !(1 == ~t5_pc~0); 22993#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 23346#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23290#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22948#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 22569#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22570#L616-36 assume !(1 == ~t6_pc~0); 23316#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 22100#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22101#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22645#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22817#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23146#L635-36 assume 1 == ~t7_pc~0; 23321#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23203#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23204#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23266#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22803#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22804#L654-36 assume 1 == ~t8_pc~0; 23384#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23327#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22970#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22971#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 23361#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22478#L673-36 assume 1 == ~t9_pc~0; 22480#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22845#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22708#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22709#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22041#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22042#L692-36 assume !(1 == ~t10_pc~0); 22256#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 22257#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22551#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22445#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22446#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22816#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22967#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23328#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23329#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22894#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22895#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23199#L1167-3 assume !(1 == ~T6_E~0); 23312#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22802#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22700#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22701#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22715#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22534#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22535#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22785#L1207-3 assume !(1 == ~E_3~0); 22903#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23127#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22438#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22125#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22126#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23228#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23229#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23391#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 23277#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22276#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22277#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 22541#L1572 assume !(0 == start_simulation_~tmp~3#1); 22572#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22734#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22055#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22113#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 22114#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22026#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22027#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 22874#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 22205#L1553-2 [2024-11-13 15:14:30,871 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:30,872 INFO L85 PathProgramCache]: Analyzing trace with hash -1581271233, now seen corresponding path program 1 times [2024-11-13 15:14:30,872 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:30,872 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1686164289] [2024-11-13 15:14:30,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:30,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:30,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:30,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:30,932 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:30,932 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1686164289] [2024-11-13 15:14:30,932 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1686164289] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:30,933 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:30,933 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:30,933 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1169610202] [2024-11-13 15:14:30,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:30,933 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:14:30,934 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:30,934 INFO L85 PathProgramCache]: Analyzing trace with hash 1408070870, now seen corresponding path program 1 times [2024-11-13 15:14:30,934 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:30,934 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203341896] [2024-11-13 15:14:30,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:30,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:30,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:31,014 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:31,015 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:31,015 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1203341896] [2024-11-13 15:14:31,015 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1203341896] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:31,015 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:31,015 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:31,015 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [39544282] [2024-11-13 15:14:31,015 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:31,015 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:14:31,015 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:14:31,016 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:14:31,016 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:14:31,016 INFO L87 Difference]: Start difference. First operand 1372 states and 2027 transitions. cyclomatic complexity: 656 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:31,053 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:14:31,053 INFO L93 Difference]: Finished difference Result 1372 states and 2026 transitions. [2024-11-13 15:14:31,053 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2026 transitions. [2024-11-13 15:14:31,061 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-11-13 15:14:31,068 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2026 transitions. [2024-11-13 15:14:31,068 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2024-11-13 15:14:31,069 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2024-11-13 15:14:31,069 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2026 transitions. [2024-11-13 15:14:31,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:14:31,072 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2026 transitions. [2024-11-13 15:14:31,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2026 transitions. [2024-11-13 15:14:31,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2024-11-13 15:14:31,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4766763848396502) internal successors, (2026), 1371 states have internal predecessors, (2026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:31,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2026 transitions. [2024-11-13 15:14:31,097 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2026 transitions. [2024-11-13 15:14:31,098 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:14:31,098 INFO L424 stractBuchiCegarLoop]: Abstraction has 1372 states and 2026 transitions. [2024-11-13 15:14:31,098 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 15:14:31,099 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2026 transitions. [2024-11-13 15:14:31,104 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2024-11-13 15:14:31,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:14:31,104 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:14:31,106 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:31,106 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:31,107 INFO L745 eck$LassoCheckResult]: Stem: 25155#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 25156#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 26057#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26058#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25737#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 25425#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25426#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25707#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25877#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25595#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25596#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25477#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25478#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 25831#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25791#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 25715#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25716#L1024 assume !(0 == ~M_E~0); 25971#L1024-2 assume !(0 == ~T1_E~0); 25151#L1029-1 assume !(0 == ~T2_E~0); 25152#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25254#L1039-1 assume !(0 == ~T4_E~0); 26081#L1044-1 assume !(0 == ~T5_E~0); 25497#L1049-1 assume !(0 == ~T6_E~0); 25498#L1054-1 assume !(0 == ~T7_E~0); 25736#L1059-1 assume !(0 == ~T8_E~0); 25201#L1064-1 assume !(0 == ~T9_E~0); 25202#L1069-1 assume !(0 == ~T10_E~0); 25940#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 26000#L1079-1 assume !(0 == ~E_1~0); 25973#L1084-1 assume !(0 == ~E_2~0); 25974#L1089-1 assume !(0 == ~E_3~0); 26018#L1094-1 assume !(0 == ~E_4~0); 25585#L1099-1 assume !(0 == ~E_5~0); 25586#L1104-1 assume !(0 == ~E_6~0); 25849#L1109-1 assume !(0 == ~E_7~0); 25368#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 25369#L1119-1 assume !(0 == ~E_9~0); 25435#L1124-1 assume !(0 == ~E_10~0); 24855#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24856#L502 assume 1 == ~m_pc~0; 25734#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 24981#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24982#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25785#L1273 assume !(0 != activate_threads_~tmp~1#1); 25786#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26111#L521 assume !(1 == ~t1_pc~0); 26046#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 24906#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24871#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24872#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 24892#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24893#L540 assume 1 == ~t2_pc~0; 25984#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25696#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25364#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25365#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 26042#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25179#L559 assume 1 == ~t3_pc~0; 25180#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25456#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24808#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24809#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 24999#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25000#L578 assume !(1 == ~t4_pc~0); 25121#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 25120#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24939#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24940#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25768#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25769#L597 assume 1 == ~t5_pc~0; 26126#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24926#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24927#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25969#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 25717#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25718#L616 assume !(1 == ~t6_pc~0); 25731#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25730#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25340#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25341#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 25574#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25575#L635 assume 1 == ~t7_pc~0; 25771#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24895#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25270#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26014#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 25709#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25710#L654 assume !(1 == ~t8_pc~0); 25526#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25527#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25901#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25902#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 25938#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25149#L673 assume 1 == ~t9_pc~0; 25150#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24846#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25421#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25422#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 25861#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25862#L692 assume !(1 == ~t10_pc~0); 25806#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25805#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25577#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25578#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 25589#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25917#L1142 assume !(1 == ~M_E~0); 25060#L1142-2 assume !(1 == ~T1_E~0); 25061#L1147-1 assume !(1 == ~T2_E~0); 25906#L1152-1 assume !(1 == ~T3_E~0); 25463#L1157-1 assume !(1 == ~T4_E~0); 25464#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25613#L1167-1 assume !(1 == ~T6_E~0); 25614#L1172-1 assume !(1 == ~T7_E~0); 26035#L1177-1 assume !(1 == ~T8_E~0); 25754#L1182-1 assume !(1 == ~T9_E~0); 25755#L1187-1 assume !(1 == ~T10_E~0); 25854#L1192-1 assume !(1 == ~E_M~0); 25318#L1197-1 assume !(1 == ~E_1~0); 25319#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25698#L1207-1 assume !(1 == ~E_3~0); 25674#L1212-1 assume !(1 == ~E_4~0); 24911#L1217-1 assume !(1 == ~E_5~0); 24912#L1222-1 assume !(1 == ~E_6~0); 25671#L1227-1 assume !(1 == ~E_7~0); 25672#L1232-1 assume !(1 == ~E_8~0); 24785#L1237-1 assume !(1 == ~E_9~0); 24786#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 25735#L1247-1 assume { :end_inline_reset_delta_events } true; 24956#L1553-2 [2024-11-13 15:14:31,109 INFO L747 eck$LassoCheckResult]: Loop: 24956#L1553-2 assume !false; 24957#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25096#L999-1 assume !false; 25237#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25044#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24929#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25401#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25402#L854 assume !(0 != eval_~tmp~0#1); 25811#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25598#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25599#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26071#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25571#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25539#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25540#L1039-3 assume !(0 == ~T4_E~0); 25882#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25145#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25146#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24907#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24908#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25509#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25510#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25856#L1079-3 assume !(0 == ~E_1~0); 25747#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25632#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25633#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25558#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25559#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25880#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25868#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25869#L1119-3 assume !(0 == ~E_9~0); 26132#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26139#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26105#L502-36 assume !(1 == ~m_pc~0); 25288#L502-38 is_master_triggered_~__retres1~0#1 := 0; 24773#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24774#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25203#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25204#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25482#L521-36 assume 1 == ~t1_pc~0; 25483#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25493#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25663#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26059#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25942#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25943#L540-36 assume 1 == ~t2_pc~0; 26107#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24863#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25275#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25944#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25608#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24782#L559-36 assume !(1 == ~t3_pc~0); 24784#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 25241#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25416#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25417#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25756#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25996#L578-36 assume !(1 == ~t4_pc~0); 25683#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 25684#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25620#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25621#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25517#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25518#L597-36 assume !(1 == ~t5_pc~0); 25744#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 26097#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26041#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25699#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 25320#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25321#L616-36 assume !(1 == ~t6_pc~0); 26067#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 24851#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24852#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25396#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25568#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25897#L635-36 assume 1 == ~t7_pc~0; 26072#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25954#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25955#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26017#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25554#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25555#L654-36 assume 1 == ~t8_pc~0; 26135#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26080#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25721#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25722#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26112#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25226#L673-36 assume !(1 == ~t9_pc~0); 25227#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 25594#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25459#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25460#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24792#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24793#L692-36 assume 1 == ~t10_pc~0; 25746#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25005#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25302#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25194#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25195#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25565#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25714#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26075#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26076#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25645#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25646#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25950#L1167-3 assume !(1 == ~T6_E~0); 26062#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25551#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25451#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25452#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25466#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25284#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25285#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25532#L1207-3 assume !(1 == ~E_3~0); 25653#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25878#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25189#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24876#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24877#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25979#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25980#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26142#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 26028#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 25027#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25028#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 25292#L1572 assume !(0 == start_simulation_~tmp~3#1); 25323#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25485#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24806#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24864#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 24865#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24777#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24778#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 25625#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 24956#L1553-2 [2024-11-13 15:14:31,110 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:31,110 INFO L85 PathProgramCache]: Analyzing trace with hash 711809793, now seen corresponding path program 1 times [2024-11-13 15:14:31,110 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:31,110 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1030968755] [2024-11-13 15:14:31,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:31,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:31,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:31,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:31,227 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:31,227 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1030968755] [2024-11-13 15:14:31,227 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1030968755] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:31,227 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:31,227 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:31,227 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [920860236] [2024-11-13 15:14:31,227 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:31,228 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:14:31,228 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:31,228 INFO L85 PathProgramCache]: Analyzing trace with hash -1400344297, now seen corresponding path program 1 times [2024-11-13 15:14:31,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:31,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1651639077] [2024-11-13 15:14:31,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:31,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:31,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:31,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:31,299 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:31,299 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1651639077] [2024-11-13 15:14:31,299 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1651639077] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:31,299 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:31,299 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:31,299 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [728804140] [2024-11-13 15:14:31,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:31,300 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:14:31,300 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:14:31,300 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:14:31,300 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:14:31,300 INFO L87 Difference]: Start difference. First operand 1372 states and 2026 transitions. cyclomatic complexity: 655 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:31,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:14:31,483 INFO L93 Difference]: Finished difference Result 2526 states and 3716 transitions. [2024-11-13 15:14:31,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2526 states and 3716 transitions. [2024-11-13 15:14:31,498 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2365 [2024-11-13 15:14:31,511 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2526 states to 2526 states and 3716 transitions. [2024-11-13 15:14:31,511 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2526 [2024-11-13 15:14:31,514 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2526 [2024-11-13 15:14:31,514 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2526 states and 3716 transitions. [2024-11-13 15:14:31,518 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:14:31,519 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2526 states and 3716 transitions. [2024-11-13 15:14:31,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2526 states and 3716 transitions. [2024-11-13 15:14:31,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2526 to 2526. [2024-11-13 15:14:31,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2526 states, 2526 states have (on average 1.471100554235946) internal successors, (3716), 2525 states have internal predecessors, (3716), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:31,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2526 states to 2526 states and 3716 transitions. [2024-11-13 15:14:31,633 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2526 states and 3716 transitions. [2024-11-13 15:14:31,634 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:14:31,634 INFO L424 stractBuchiCegarLoop]: Abstraction has 2526 states and 3716 transitions. [2024-11-13 15:14:31,634 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 15:14:31,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2526 states and 3716 transitions. [2024-11-13 15:14:31,646 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2365 [2024-11-13 15:14:31,646 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:14:31,646 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:14:31,648 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:31,648 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:31,648 INFO L745 eck$LassoCheckResult]: Stem: 29063#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 29064#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 29982#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29983#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29649#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 29335#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29336#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29619#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29793#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29505#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29506#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29387#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29388#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29747#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29705#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 29626#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29627#L1024 assume !(0 == ~M_E~0); 29891#L1024-2 assume !(0 == ~T1_E~0); 29059#L1029-1 assume !(0 == ~T2_E~0); 29060#L1034-1 assume !(0 == ~T3_E~0); 29163#L1039-1 assume !(0 == ~T4_E~0); 30009#L1044-1 assume !(0 == ~T5_E~0); 29407#L1049-1 assume !(0 == ~T6_E~0); 29408#L1054-1 assume !(0 == ~T7_E~0); 29648#L1059-1 assume !(0 == ~T8_E~0); 29110#L1064-1 assume !(0 == ~T9_E~0); 29111#L1069-1 assume !(0 == ~T10_E~0); 29860#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 29921#L1079-1 assume !(0 == ~E_1~0); 29893#L1084-1 assume !(0 == ~E_2~0); 29894#L1089-1 assume !(0 == ~E_3~0); 29942#L1094-1 assume !(0 == ~E_4~0); 29496#L1099-1 assume !(0 == ~E_5~0); 29497#L1104-1 assume !(0 == ~E_6~0); 29765#L1109-1 assume !(0 == ~E_7~0); 29278#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 29279#L1119-1 assume !(0 == ~E_9~0); 29345#L1124-1 assume !(0 == ~E_10~0); 28763#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28764#L502 assume 1 == ~m_pc~0; 29646#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28889#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28890#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29699#L1273 assume !(0 != activate_threads_~tmp~1#1); 29700#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30049#L521 assume !(1 == ~t1_pc~0); 29971#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28814#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28779#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28780#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 28800#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28801#L540 assume 1 == ~t2_pc~0; 29905#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29608#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29274#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29275#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 29967#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29087#L559 assume 1 == ~t3_pc~0; 29088#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29366#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28716#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28717#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 28907#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28908#L578 assume !(1 == ~t4_pc~0); 29028#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 29027#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28846#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28847#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29681#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29682#L597 assume 1 == ~t5_pc~0; 30065#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28834#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28835#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29889#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 29628#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29629#L616 assume !(1 == ~t6_pc~0); 29643#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29642#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29250#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29251#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 29485#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29486#L635 assume 1 == ~t7_pc~0; 29684#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28803#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29179#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29938#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 29621#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29622#L654 assume !(1 == ~t8_pc~0); 29436#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29437#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29818#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29819#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 29858#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29057#L673 assume 1 == ~t9_pc~0; 29058#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28754#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29329#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29330#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 29777#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29778#L692 assume !(1 == ~t10_pc~0); 29721#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29720#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29488#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29489#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 29500#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29836#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 30087#L1142-2 assume !(1 == ~T1_E~0); 30244#L1147-1 assume !(1 == ~T2_E~0); 30242#L1152-1 assume !(1 == ~T3_E~0); 30086#L1157-1 assume !(1 == ~T4_E~0); 30238#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30236#L1167-1 assume !(1 == ~T6_E~0); 30234#L1172-1 assume !(1 == ~T7_E~0); 30232#L1177-1 assume !(1 == ~T8_E~0); 30230#L1182-1 assume !(1 == ~T9_E~0); 30229#L1187-1 assume !(1 == ~T10_E~0); 30228#L1192-1 assume !(1 == ~E_M~0); 29228#L1197-1 assume !(1 == ~E_1~0); 29229#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 29610#L1207-1 assume !(1 == ~E_3~0); 29586#L1212-1 assume !(1 == ~E_4~0); 28819#L1217-1 assume !(1 == ~E_5~0); 28820#L1222-1 assume !(1 == ~E_6~0); 29583#L1227-1 assume !(1 == ~E_7~0); 29584#L1232-1 assume !(1 == ~E_8~0); 28693#L1237-1 assume !(1 == ~E_9~0); 28694#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 30127#L1247-1 assume { :end_inline_reset_delta_events } true; 30120#L1553-2 [2024-11-13 15:14:31,649 INFO L747 eck$LassoCheckResult]: Loop: 30120#L1553-2 assume !false; 30114#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30110#L999-1 assume !false; 30109#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30108#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30097#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30096#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30094#L854 assume !(0 != eval_~tmp~0#1); 30093#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30092#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30091#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29998#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29482#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29449#L1034-3 assume !(0 == ~T3_E~0); 29450#L1039-3 assume !(0 == ~T4_E~0); 29798#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29053#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29054#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28815#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28816#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29419#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29420#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29772#L1079-3 assume !(0 == ~E_1~0); 29658#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29544#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29545#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29468#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29469#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29796#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29784#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29785#L1119-3 assume !(0 == ~E_9~0); 30072#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 30079#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30042#L502-36 assume 1 == ~m_pc~0; 29799#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28681#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28682#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29112#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29113#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29392#L521-36 assume 1 == ~t1_pc~0; 29393#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29403#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29575#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29984#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29862#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29863#L540-36 assume !(1 == ~t2_pc~0); 28770#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 28771#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29184#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29864#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29519#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28690#L559-36 assume 1 == ~t3_pc~0; 28691#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29150#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29326#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29327#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29669#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29917#L578-36 assume 1 == ~t4_pc~0; 29637#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29596#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29531#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29532#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29427#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29428#L597-36 assume !(1 == ~t5_pc~0); 29656#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 30029#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29966#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29611#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 29230#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29231#L616-36 assume !(1 == ~t6_pc~0); 29992#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 28759#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28760#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29306#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29479#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29814#L635-36 assume 1 == ~t7_pc~0; 30000#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29874#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29875#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29941#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29464#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29465#L654-36 assume !(1 == ~t8_pc~0); 30005#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 30006#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29633#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29634#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30050#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29138#L673-36 assume !(1 == ~t9_pc~0); 29139#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 29507#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29369#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29370#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28700#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28701#L692-36 assume !(1 == ~t10_pc~0); 28915#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 28916#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29212#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29105#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29106#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29478#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29630#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30007#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30008#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29557#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29558#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29870#L1167-3 assume !(1 == ~T6_E~0); 29988#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29463#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29361#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29362#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29376#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29194#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29195#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29446#L1207-3 assume !(1 == ~E_3~0); 29566#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29794#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29097#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28784#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28785#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29899#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29900#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30083#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 29952#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28935#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28936#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 29202#L1572 assume !(0 == start_simulation_~tmp~3#1); 29233#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 29395#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28714#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30159#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 30146#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30139#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30132#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 30128#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 30120#L1553-2 [2024-11-13 15:14:31,649 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:31,649 INFO L85 PathProgramCache]: Analyzing trace with hash 1478663553, now seen corresponding path program 1 times [2024-11-13 15:14:31,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:31,650 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [687129427] [2024-11-13 15:14:31,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:31,650 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:31,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:31,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:31,742 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:31,742 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [687129427] [2024-11-13 15:14:31,742 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [687129427] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:31,742 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:31,742 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:31,742 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1440962136] [2024-11-13 15:14:31,742 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:31,743 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:14:31,743 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:31,743 INFO L85 PathProgramCache]: Analyzing trace with hash 1214521561, now seen corresponding path program 1 times [2024-11-13 15:14:31,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:31,743 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1942638510] [2024-11-13 15:14:31,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:31,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:31,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:31,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:31,823 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:31,823 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1942638510] [2024-11-13 15:14:31,823 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1942638510] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:31,823 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:31,823 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:31,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765527717] [2024-11-13 15:14:31,823 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:31,824 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:14:31,824 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:14:31,824 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:14:31,824 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:14:31,825 INFO L87 Difference]: Start difference. First operand 2526 states and 3716 transitions. cyclomatic complexity: 1192 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:32,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:14:32,078 INFO L93 Difference]: Finished difference Result 4664 states and 6847 transitions. [2024-11-13 15:14:32,078 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4664 states and 6847 transitions. [2024-11-13 15:14:32,105 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4471 [2024-11-13 15:14:32,136 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4664 states to 4664 states and 6847 transitions. [2024-11-13 15:14:32,136 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4664 [2024-11-13 15:14:32,141 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4664 [2024-11-13 15:14:32,141 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4664 states and 6847 transitions. [2024-11-13 15:14:32,148 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:14:32,148 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4664 states and 6847 transitions. [2024-11-13 15:14:32,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4664 states and 6847 transitions. [2024-11-13 15:14:32,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4664 to 4662. [2024-11-13 15:14:32,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4662 states, 4662 states have (on average 1.4682539682539681) internal successors, (6845), 4661 states have internal predecessors, (6845), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:32,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4662 states to 4662 states and 6845 transitions. [2024-11-13 15:14:32,244 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4662 states and 6845 transitions. [2024-11-13 15:14:32,244 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:14:32,244 INFO L424 stractBuchiCegarLoop]: Abstraction has 4662 states and 6845 transitions. [2024-11-13 15:14:32,244 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 15:14:32,245 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4662 states and 6845 transitions. [2024-11-13 15:14:32,266 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4471 [2024-11-13 15:14:32,266 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:14:32,266 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:14:32,268 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:32,268 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:32,268 INFO L745 eck$LassoCheckResult]: Stem: 36263#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 36264#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 37194#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37195#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36855#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 36536#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36537#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36825#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36997#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36709#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36710#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36591#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36592#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36950#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36910#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36833#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36834#L1024 assume !(0 == ~M_E~0); 37096#L1024-2 assume !(0 == ~T1_E~0); 36259#L1029-1 assume !(0 == ~T2_E~0); 36260#L1034-1 assume !(0 == ~T3_E~0); 36363#L1039-1 assume !(0 == ~T4_E~0); 37221#L1044-1 assume !(0 == ~T5_E~0); 36611#L1049-1 assume !(0 == ~T6_E~0); 36612#L1054-1 assume !(0 == ~T7_E~0); 36854#L1059-1 assume !(0 == ~T8_E~0); 36309#L1064-1 assume !(0 == ~T9_E~0); 36310#L1069-1 assume !(0 == ~T10_E~0); 37064#L1074-1 assume !(0 == ~E_M~0); 37130#L1079-1 assume !(0 == ~E_1~0); 37098#L1084-1 assume !(0 == ~E_2~0); 37099#L1089-1 assume !(0 == ~E_3~0); 37149#L1094-1 assume !(0 == ~E_4~0); 36699#L1099-1 assume !(0 == ~E_5~0); 36700#L1104-1 assume !(0 == ~E_6~0); 36968#L1109-1 assume !(0 == ~E_7~0); 36477#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 36478#L1119-1 assume !(0 == ~E_9~0); 36551#L1124-1 assume !(0 == ~E_10~0); 35963#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35964#L502 assume 1 == ~m_pc~0; 36852#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36089#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36090#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36906#L1273 assume !(0 != activate_threads_~tmp~1#1); 36907#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37255#L521 assume !(1 == ~t1_pc~0); 37180#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36014#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35979#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35980#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 36000#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36001#L540 assume 1 == ~t2_pc~0; 37113#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36813#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36475#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36476#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 37174#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36287#L559 assume 1 == ~t3_pc~0; 36288#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36567#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35916#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35917#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 36107#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36108#L578 assume !(1 == ~t4_pc~0); 36231#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36230#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36047#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36048#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36886#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36887#L597 assume 1 == ~t5_pc~0; 37276#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36034#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36035#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37094#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 36835#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36836#L616 assume !(1 == ~t6_pc~0); 36851#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36850#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36449#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36450#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 36689#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36690#L635 assume 1 == ~t7_pc~0; 36890#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36003#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36381#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37145#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 36826#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36827#L654 assume !(1 == ~t8_pc~0); 36638#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36639#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37025#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37026#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 37062#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36257#L673 assume 1 == ~t9_pc~0; 36258#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35956#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36531#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36532#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 36980#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36981#L692 assume !(1 == ~t10_pc~0); 36927#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36926#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36691#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36692#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 36703#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37041#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 37297#L1142-2 assume !(1 == ~T1_E~0); 37914#L1147-1 assume !(1 == ~T2_E~0); 37911#L1152-1 assume !(1 == ~T3_E~0); 37481#L1157-1 assume !(1 == ~T4_E~0); 37479#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37477#L1167-1 assume !(1 == ~T6_E~0); 37475#L1172-1 assume !(1 == ~T7_E~0); 37473#L1177-1 assume !(1 == ~T8_E~0); 37472#L1182-1 assume !(1 == ~T9_E~0); 37396#L1187-1 assume !(1 == ~T10_E~0); 37393#L1192-1 assume !(1 == ~E_M~0); 37390#L1197-1 assume !(1 == ~E_1~0); 37388#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 37386#L1207-1 assume !(1 == ~E_3~0); 37384#L1212-1 assume !(1 == ~E_4~0); 37372#L1217-1 assume !(1 == ~E_5~0); 37370#L1222-1 assume !(1 == ~E_6~0); 37368#L1227-1 assume !(1 == ~E_7~0); 37356#L1232-1 assume !(1 == ~E_8~0); 37347#L1237-1 assume !(1 == ~E_9~0); 37339#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 37332#L1247-1 assume { :end_inline_reset_delta_events } true; 37328#L1553-2 [2024-11-13 15:14:32,269 INFO L747 eck$LassoCheckResult]: Loop: 37328#L1553-2 assume !false; 37324#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37320#L999-1 assume !false; 37319#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37318#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37307#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37306#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 37304#L854 assume !(0 != eval_~tmp~0#1); 37303#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37302#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37300#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37301#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38516#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38514#L1034-3 assume !(0 == ~T3_E~0); 38512#L1039-3 assume !(0 == ~T4_E~0); 38509#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 38507#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38505#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38503#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 38501#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38499#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38496#L1074-3 assume !(0 == ~E_M~0); 38494#L1079-3 assume !(0 == ~E_1~0); 38492#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38490#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38488#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38486#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38483#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38481#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38479#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38477#L1119-3 assume !(0 == ~E_9~0); 38475#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38473#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38470#L502-36 assume !(1 == ~m_pc~0); 38467#L502-38 is_master_triggered_~__retres1~0#1 := 0; 38465#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38463#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38461#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38459#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38456#L521-36 assume 1 == ~t1_pc~0; 38453#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38451#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38449#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38447#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38445#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38442#L540-36 assume !(1 == ~t2_pc~0); 38439#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 38437#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38435#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38433#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38432#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38428#L559-36 assume 1 == ~t3_pc~0; 38425#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38423#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38422#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38419#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38418#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38417#L578-36 assume 1 == ~t4_pc~0; 38416#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38414#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38413#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38412#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38411#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38410#L597-36 assume 1 == ~t5_pc~0; 38408#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38407#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38406#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38405#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 38404#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38403#L616-36 assume 1 == ~t6_pc~0; 38401#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38400#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38399#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38398#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38397#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38396#L635-36 assume 1 == ~t7_pc~0; 38394#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38393#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38392#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38391#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38389#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38388#L654-36 assume 1 == ~t8_pc~0; 38385#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38383#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38381#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38378#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 38376#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38374#L673-36 assume !(1 == ~t9_pc~0); 37661#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 37658#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37654#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37651#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37649#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37647#L692-36 assume 1 == ~t10_pc~0; 37644#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37642#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37640#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37637#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37635#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37633#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36831#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37630#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37628#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37624#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37622#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37620#L1167-3 assume !(1 == ~T6_E~0); 37618#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37616#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37614#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37611#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37609#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37605#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37603#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37601#L1207-3 assume !(1 == ~E_3~0); 37599#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37596#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37594#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37592#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37590#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37588#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37586#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37583#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37456#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37455#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37454#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 37453#L1572 assume !(0 == start_simulation_~tmp~3#1); 36432#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37382#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37371#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37369#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 37357#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37348#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37340#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 37333#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 37328#L1553-2 [2024-11-13 15:14:32,269 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:32,269 INFO L85 PathProgramCache]: Analyzing trace with hash 171521155, now seen corresponding path program 1 times [2024-11-13 15:14:32,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:32,270 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [792181809] [2024-11-13 15:14:32,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:32,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:32,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:32,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:32,365 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:32,366 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [792181809] [2024-11-13 15:14:32,366 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [792181809] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:32,366 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:32,366 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:32,366 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [939997181] [2024-11-13 15:14:32,366 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:32,366 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:14:32,367 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:32,367 INFO L85 PathProgramCache]: Analyzing trace with hash -46660904, now seen corresponding path program 1 times [2024-11-13 15:14:32,367 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:32,367 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1990809529] [2024-11-13 15:14:32,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:32,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:32,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:32,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:32,432 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:32,432 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1990809529] [2024-11-13 15:14:32,432 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1990809529] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:32,432 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:32,432 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:32,433 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [199538344] [2024-11-13 15:14:32,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:32,433 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:14:32,433 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:14:32,433 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:14:32,433 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:14:32,433 INFO L87 Difference]: Start difference. First operand 4662 states and 6845 transitions. cyclomatic complexity: 2187 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:32,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:14:32,688 INFO L93 Difference]: Finished difference Result 8740 states and 12800 transitions. [2024-11-13 15:14:32,688 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8740 states and 12800 transitions. [2024-11-13 15:14:32,729 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8525 [2024-11-13 15:14:32,834 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8740 states to 8740 states and 12800 transitions. [2024-11-13 15:14:32,835 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8740 [2024-11-13 15:14:32,843 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8740 [2024-11-13 15:14:32,843 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8740 states and 12800 transitions. [2024-11-13 15:14:32,858 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:14:32,858 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8740 states and 12800 transitions. [2024-11-13 15:14:32,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8740 states and 12800 transitions. [2024-11-13 15:14:33,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8740 to 8736. [2024-11-13 15:14:33,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8736 states, 8736 states have (on average 1.4647435897435896) internal successors, (12796), 8735 states have internal predecessors, (12796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:33,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8736 states to 8736 states and 12796 transitions. [2024-11-13 15:14:33,088 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8736 states and 12796 transitions. [2024-11-13 15:14:33,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:14:33,089 INFO L424 stractBuchiCegarLoop]: Abstraction has 8736 states and 12796 transitions. [2024-11-13 15:14:33,089 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 15:14:33,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8736 states and 12796 transitions. [2024-11-13 15:14:33,131 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8525 [2024-11-13 15:14:33,132 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:14:33,132 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:14:33,134 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:33,134 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:33,135 INFO L745 eck$LassoCheckResult]: Stem: 49678#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 49679#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 50608#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50609#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50271#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 49951#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49952#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50240#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50418#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50123#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50124#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50004#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50005#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50371#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50328#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50247#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50248#L1024 assume !(0 == ~M_E~0); 50516#L1024-2 assume !(0 == ~T1_E~0); 49674#L1029-1 assume !(0 == ~T2_E~0); 49675#L1034-1 assume !(0 == ~T3_E~0); 49777#L1039-1 assume !(0 == ~T4_E~0); 50632#L1044-1 assume !(0 == ~T5_E~0); 50025#L1049-1 assume !(0 == ~T6_E~0); 50026#L1054-1 assume !(0 == ~T7_E~0); 50270#L1059-1 assume !(0 == ~T8_E~0); 49724#L1064-1 assume !(0 == ~T9_E~0); 49725#L1069-1 assume !(0 == ~T10_E~0); 50484#L1074-1 assume !(0 == ~E_M~0); 50548#L1079-1 assume !(0 == ~E_1~0); 50518#L1084-1 assume !(0 == ~E_2~0); 50519#L1089-1 assume !(0 == ~E_3~0); 50568#L1094-1 assume !(0 == ~E_4~0); 50114#L1099-1 assume !(0 == ~E_5~0); 50115#L1104-1 assume !(0 == ~E_6~0); 50389#L1109-1 assume !(0 == ~E_7~0); 49892#L1114-1 assume !(0 == ~E_8~0); 49893#L1119-1 assume !(0 == ~E_9~0); 49961#L1124-1 assume !(0 == ~E_10~0); 49375#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49376#L502 assume 1 == ~m_pc~0; 50268#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49501#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49502#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 50322#L1273 assume !(0 != activate_threads_~tmp~1#1); 50323#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50668#L521 assume !(1 == ~t1_pc~0); 50597#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49426#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49391#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49392#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 49412#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49413#L540 assume 1 == ~t2_pc~0; 50531#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50228#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49888#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49889#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 50593#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49702#L559 assume 1 == ~t3_pc~0; 49703#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49983#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49328#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49329#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 49519#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49520#L578 assume !(1 == ~t4_pc~0); 49642#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49641#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49459#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49460#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50304#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50305#L597 assume 1 == ~t5_pc~0; 50686#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49446#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49447#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50514#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 50249#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50250#L616 assume !(1 == ~t6_pc~0); 50265#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50264#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49864#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49865#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 50103#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50104#L635 assume 1 == ~t7_pc~0; 50307#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49415#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49793#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50564#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 50242#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50243#L654 assume !(1 == ~t8_pc~0); 50054#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 50055#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50443#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50444#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 50481#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49672#L673 assume 1 == ~t9_pc~0; 49673#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49366#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49947#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49948#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 50402#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50403#L692 assume !(1 == ~t10_pc~0); 50343#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50342#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50106#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50107#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 50118#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50460#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 50712#L1142-2 assume !(1 == ~T1_E~0); 53314#L1147-1 assume !(1 == ~T2_E~0); 53313#L1152-1 assume !(1 == ~T3_E~0); 53312#L1157-1 assume !(1 == ~T4_E~0); 53310#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53308#L1167-1 assume !(1 == ~T6_E~0); 53306#L1172-1 assume !(1 == ~T7_E~0); 53305#L1177-1 assume !(1 == ~T8_E~0); 53304#L1182-1 assume !(1 == ~T9_E~0); 50394#L1187-1 assume !(1 == ~T10_E~0); 50395#L1192-1 assume !(1 == ~E_M~0); 49842#L1197-1 assume !(1 == ~E_1~0); 49843#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 50451#L1207-1 assume !(1 == ~E_3~0); 50855#L1212-1 assume !(1 == ~E_4~0); 50854#L1217-1 assume !(1 == ~E_5~0); 50819#L1222-1 assume !(1 == ~E_6~0); 50800#L1227-1 assume !(1 == ~E_7~0); 50779#L1232-1 assume !(1 == ~E_8~0); 50763#L1237-1 assume !(1 == ~E_9~0); 50761#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 50752#L1247-1 assume { :end_inline_reset_delta_events } true; 50745#L1553-2 [2024-11-13 15:14:33,135 INFO L747 eck$LassoCheckResult]: Loop: 50745#L1553-2 assume !false; 50739#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50735#L999-1 assume !false; 50734#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50733#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50722#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50721#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 50719#L854 assume !(0 != eval_~tmp~0#1); 50718#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50717#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50716#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50622#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50100#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50067#L1034-3 assume !(0 == ~T3_E~0); 50068#L1039-3 assume !(0 == ~T4_E~0); 50423#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49668#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49669#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49427#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49428#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50037#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 50038#L1074-3 assume !(0 == ~E_M~0); 50397#L1079-3 assume !(0 == ~E_1~0); 50280#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50161#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50162#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 50086#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50087#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50421#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50409#L1114-3 assume !(0 == ~E_8~0); 50410#L1119-3 assume !(0 == ~E_9~0); 50692#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50700#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50662#L502-36 assume !(1 == ~m_pc~0); 49811#L502-38 is_master_triggered_~__retres1~0#1 := 0; 49293#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49294#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49726#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49727#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50009#L521-36 assume 1 == ~t1_pc~0; 50010#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50021#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50193#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50610#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50486#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50487#L540-36 assume !(1 == ~t2_pc~0); 49382#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 49383#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49798#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50488#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50137#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49302#L559-36 assume 1 == ~t3_pc~0; 49303#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49764#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49942#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49943#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50292#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50544#L578-36 assume 1 == ~t4_pc~0; 50258#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50214#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50149#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50150#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50045#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50046#L597-36 assume !(1 == ~t5_pc~0); 50278#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 50650#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50592#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50232#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 49844#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49845#L616-36 assume 1 == ~t6_pc~0; 50665#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49371#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49372#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49920#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50096#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50438#L635-36 assume !(1 == ~t7_pc~0); 50624#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 50499#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50500#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50567#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50082#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50083#L654-36 assume !(1 == ~t8_pc~0); 50628#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 50629#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50254#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50255#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50669#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49752#L673-36 assume !(1 == ~t9_pc~0); 49753#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 50125#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49986#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49987#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49312#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49313#L692-36 assume !(1 == ~t10_pc~0); 49527#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 49528#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49825#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49719#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49720#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50095#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50251#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50630#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50631#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 51541#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 51539#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 51513#L1167-3 assume !(1 == ~T6_E~0); 51496#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 51471#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 51469#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 51467#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51451#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 51434#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51432#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 51420#L1207-3 assume !(1 == ~E_3~0); 51411#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51402#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51394#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 51386#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 51374#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 51370#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51368#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51366#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 51354#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 51352#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 51349#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 51347#L1572 assume !(0 == start_simulation_~tmp~3#1); 49847#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50841#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50830#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50811#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 50794#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50777#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50762#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 50753#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 50745#L1553-2 [2024-11-13 15:14:33,136 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:33,136 INFO L85 PathProgramCache]: Analyzing trace with hash -711987835, now seen corresponding path program 1 times [2024-11-13 15:14:33,136 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:33,137 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1309718608] [2024-11-13 15:14:33,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:33,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:33,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:33,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:33,223 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:33,223 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1309718608] [2024-11-13 15:14:33,223 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1309718608] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:33,223 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:33,223 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:14:33,224 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1986840647] [2024-11-13 15:14:33,224 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:33,224 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:14:33,224 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:33,225 INFO L85 PathProgramCache]: Analyzing trace with hash 621142622, now seen corresponding path program 1 times [2024-11-13 15:14:33,225 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:33,225 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023239648] [2024-11-13 15:14:33,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:33,225 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:33,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:33,319 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:33,320 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:33,320 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2023239648] [2024-11-13 15:14:33,320 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2023239648] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:33,320 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:33,320 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:33,320 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [601490089] [2024-11-13 15:14:33,320 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:33,321 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:14:33,321 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:14:33,321 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:14:33,322 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:14:33,322 INFO L87 Difference]: Start difference. First operand 8736 states and 12796 transitions. cyclomatic complexity: 4068 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:33,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:14:33,532 INFO L93 Difference]: Finished difference Result 17155 states and 24947 transitions. [2024-11-13 15:14:33,533 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17155 states and 24947 transitions. [2024-11-13 15:14:33,611 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16929 [2024-11-13 15:14:33,675 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17155 states to 17155 states and 24947 transitions. [2024-11-13 15:14:33,675 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17155 [2024-11-13 15:14:33,692 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17155 [2024-11-13 15:14:33,692 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17155 states and 24947 transitions. [2024-11-13 15:14:33,716 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:14:33,716 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17155 states and 24947 transitions. [2024-11-13 15:14:33,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17155 states and 24947 transitions. [2024-11-13 15:14:33,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17155 to 16547. [2024-11-13 15:14:33,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16547 states, 16547 states have (on average 1.455913458632985) internal successors, (24091), 16546 states have internal predecessors, (24091), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:34,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16547 states to 16547 states and 24091 transitions. [2024-11-13 15:14:34,201 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16547 states and 24091 transitions. [2024-11-13 15:14:34,201 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:14:34,202 INFO L424 stractBuchiCegarLoop]: Abstraction has 16547 states and 24091 transitions. [2024-11-13 15:14:34,202 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 15:14:34,202 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16547 states and 24091 transitions. [2024-11-13 15:14:34,245 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16321 [2024-11-13 15:14:34,245 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:14:34,245 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:14:34,247 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:34,247 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:34,248 INFO L745 eck$LassoCheckResult]: Stem: 75581#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 75582#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 76581#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76582#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76197#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 75863#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75864#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76165#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76358#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76045#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76046#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 75923#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 75924#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 76306#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 76257#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 76175#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76176#L1024 assume !(0 == ~M_E~0); 76473#L1024-2 assume !(0 == ~T1_E~0); 75576#L1029-1 assume !(0 == ~T2_E~0); 75577#L1034-1 assume !(0 == ~T3_E~0); 75686#L1039-1 assume !(0 == ~T4_E~0); 76611#L1044-1 assume !(0 == ~T5_E~0); 75943#L1049-1 assume !(0 == ~T6_E~0); 75944#L1054-1 assume !(0 == ~T7_E~0); 76196#L1059-1 assume !(0 == ~T8_E~0); 75633#L1064-1 assume !(0 == ~T9_E~0); 75634#L1069-1 assume !(0 == ~T10_E~0); 76436#L1074-1 assume !(0 == ~E_M~0); 76508#L1079-1 assume !(0 == ~E_1~0); 76476#L1084-1 assume !(0 == ~E_2~0); 76477#L1089-1 assume !(0 == ~E_3~0); 76533#L1094-1 assume !(0 == ~E_4~0); 76034#L1099-1 assume !(0 == ~E_5~0); 76035#L1104-1 assume !(0 == ~E_6~0); 76327#L1109-1 assume !(0 == ~E_7~0); 75802#L1114-1 assume !(0 == ~E_8~0); 75803#L1119-1 assume !(0 == ~E_9~0); 75878#L1124-1 assume !(0 == ~E_10~0); 75273#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75274#L502 assume !(1 == ~m_pc~0); 75474#L502-2 is_master_triggered_~__retres1~0#1 := 0; 75404#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75405#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 76253#L1273 assume !(0 != activate_threads_~tmp~1#1); 76254#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76676#L521 assume !(1 == ~t1_pc~0); 76567#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 75326#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75289#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 75290#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 75310#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75311#L540 assume 1 == ~t2_pc~0; 76488#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 76149#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75800#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 75801#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 76563#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75611#L559 assume 1 == ~t3_pc~0; 75612#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 75894#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75226#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75227#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 75420#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75421#L578 assume !(1 == ~t4_pc~0); 75546#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 75545#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75358#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75359#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 76233#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76234#L597 assume 1 == ~t5_pc~0; 76707#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 75344#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75345#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76471#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 76177#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76178#L616 assume !(1 == ~t6_pc~0); 76194#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 76193#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75774#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75775#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 76024#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76025#L635 assume 1 == ~t7_pc~0; 76236#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 75313#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75703#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76529#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 76167#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76168#L654 assume !(1 == ~t8_pc~0); 75971#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 75972#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76391#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76392#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 76433#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75574#L673 assume 1 == ~t9_pc~0; 75575#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 75266#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75858#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75859#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 76339#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76340#L692 assume !(1 == ~t10_pc~0); 76276#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 76275#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76026#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76027#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 76038#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76408#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 75482#L1142-2 assume !(1 == ~T1_E~0); 75483#L1147-1 assume !(1 == ~T2_E~0); 76395#L1152-1 assume !(1 == ~T3_E~0); 76747#L1157-1 assume !(1 == ~T4_E~0); 76482#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 76063#L1167-1 assume !(1 == ~T6_E~0); 76064#L1172-1 assume !(1 == ~T7_E~0); 76555#L1177-1 assume !(1 == ~T8_E~0); 76216#L1182-1 assume !(1 == ~T9_E~0); 76217#L1187-1 assume !(1 == ~T10_E~0); 76332#L1192-1 assume !(1 == ~E_M~0); 75753#L1197-1 assume !(1 == ~E_1~0); 75754#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 76154#L1207-1 assume !(1 == ~E_3~0); 76155#L1212-1 assume !(1 == ~E_4~0); 87977#L1217-1 assume !(1 == ~E_5~0); 87975#L1222-1 assume !(1 == ~E_6~0); 87972#L1227-1 assume !(1 == ~E_7~0); 87970#L1232-1 assume !(1 == ~E_8~0); 85126#L1237-1 assume !(1 == ~E_9~0); 87967#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 86781#L1247-1 assume { :end_inline_reset_delta_events } true; 86777#L1553-2 [2024-11-13 15:14:34,248 INFO L747 eck$LassoCheckResult]: Loop: 86777#L1553-2 assume !false; 86776#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 86772#L999-1 assume !false; 86771#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 86770#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 86759#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 86758#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 86757#L854 assume !(0 != eval_~tmp~0#1); 76400#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 76048#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 76049#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 76599#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 76020#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 75984#L1034-3 assume !(0 == ~T3_E~0); 75985#L1039-3 assume !(0 == ~T4_E~0); 76363#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 75570#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 75571#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 75324#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 75325#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 75953#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 75954#L1074-3 assume !(0 == ~E_M~0); 76334#L1079-3 assume !(0 == ~E_1~0); 76207#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 76082#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 76083#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 76007#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 76008#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 76361#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 76347#L1114-3 assume !(0 == ~E_8~0); 76348#L1119-3 assume !(0 == ~E_9~0); 76715#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 76724#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76665#L502-36 assume !(1 == ~m_pc~0); 75721#L502-38 is_master_triggered_~__retres1~0#1 := 0; 75191#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75192#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 75635#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 75636#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75920#L521-36 assume 1 == ~t1_pc~0; 75921#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 75934#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76114#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 76580#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 76439#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76440#L540-36 assume !(1 == ~t2_pc~0); 75280#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 75281#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75706#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 76441#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 76058#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75200#L559-36 assume 1 == ~t3_pc~0; 75201#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 75675#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75853#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75854#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 76218#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76504#L578-36 assume !(1 == ~t4_pc~0); 76136#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 76137#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76070#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76071#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 75961#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75962#L597-36 assume 1 == ~t5_pc~0; 76205#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 76645#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76562#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76151#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 75751#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75752#L616-36 assume 1 == ~t6_pc~0; 86945#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 86943#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86941#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86938#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 86936#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86934#L635-36 assume 1 == ~t7_pc~0; 86931#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 86929#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86927#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 86926#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 86923#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86921#L654-36 assume !(1 == ~t8_pc~0); 86919#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 86916#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 86914#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 86912#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 86909#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 86907#L673-36 assume 1 == ~t9_pc~0; 86905#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 86902#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86900#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86898#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 86895#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86893#L692-36 assume !(1 == ~t10_pc~0); 86891#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 86888#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86886#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 86884#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 86881#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86879#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 76173#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 86876#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86874#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86070#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86870#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 86868#L1167-3 assume !(1 == ~T6_E~0); 86866#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 86864#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 86862#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 86860#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 86857#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 75904#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 86854#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 86852#L1207-3 assume !(1 == ~E_3~0); 86850#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 86849#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 86845#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 86843#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 86841#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 85117#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 86838#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 86837#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 86826#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 86825#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 86824#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 86823#L1572 assume !(0 == start_simulation_~tmp~3#1); 75756#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 86815#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 86802#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 86798#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 86794#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86790#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86786#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 86782#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 86777#L1553-2 [2024-11-13 15:14:34,249 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:34,249 INFO L85 PathProgramCache]: Analyzing trace with hash -2098669114, now seen corresponding path program 1 times [2024-11-13 15:14:34,249 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:34,249 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183918719] [2024-11-13 15:14:34,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:34,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:34,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:34,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:34,321 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:34,322 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1183918719] [2024-11-13 15:14:34,322 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1183918719] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:34,322 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:34,322 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:14:34,322 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1902128417] [2024-11-13 15:14:34,322 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:34,322 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:14:34,323 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:34,323 INFO L85 PathProgramCache]: Analyzing trace with hash -636044260, now seen corresponding path program 1 times [2024-11-13 15:14:34,323 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:34,323 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [671131416] [2024-11-13 15:14:34,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:34,323 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:34,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:34,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:34,384 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:34,384 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [671131416] [2024-11-13 15:14:34,384 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [671131416] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:34,384 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:34,385 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:34,385 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [592448814] [2024-11-13 15:14:34,385 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:34,385 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:14:34,385 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:14:34,386 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:14:34,386 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:14:34,386 INFO L87 Difference]: Start difference. First operand 16547 states and 24091 transitions. cyclomatic complexity: 7560 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:34,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:14:34,742 INFO L93 Difference]: Finished difference Result 31457 states and 45569 transitions. [2024-11-13 15:14:34,742 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31457 states and 45569 transitions. [2024-11-13 15:14:34,856 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 31184 [2024-11-13 15:14:34,983 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31457 states to 31457 states and 45569 transitions. [2024-11-13 15:14:34,984 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31457 [2024-11-13 15:14:35,022 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31457 [2024-11-13 15:14:35,022 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31457 states and 45569 transitions. [2024-11-13 15:14:35,064 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:14:35,064 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31457 states and 45569 transitions. [2024-11-13 15:14:35,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31457 states and 45569 transitions. [2024-11-13 15:14:35,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31457 to 31425. [2024-11-13 15:14:35,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31425 states, 31425 states have (on average 1.4490692124105011) internal successors, (45537), 31424 states have internal predecessors, (45537), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:35,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31425 states to 31425 states and 45537 transitions. [2024-11-13 15:14:35,837 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31425 states and 45537 transitions. [2024-11-13 15:14:35,837 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:14:35,837 INFO L424 stractBuchiCegarLoop]: Abstraction has 31425 states and 45537 transitions. [2024-11-13 15:14:35,838 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 15:14:35,838 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31425 states and 45537 transitions. [2024-11-13 15:14:35,947 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 31152 [2024-11-13 15:14:35,947 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:14:35,947 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:14:35,950 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:35,950 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:35,950 INFO L745 eck$LassoCheckResult]: Stem: 123586#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 123587#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 124550#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 124551#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 124197#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 123867#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 123868#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 124161#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 124346#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 124044#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 124045#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 123919#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 123920#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 124298#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 124254#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 124171#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 124172#L1024 assume !(0 == ~M_E~0); 124453#L1024-2 assume !(0 == ~T1_E~0); 123582#L1029-1 assume !(0 == ~T2_E~0); 123583#L1034-1 assume !(0 == ~T3_E~0); 123693#L1039-1 assume !(0 == ~T4_E~0); 124578#L1044-1 assume !(0 == ~T5_E~0); 123940#L1049-1 assume !(0 == ~T6_E~0); 123941#L1054-1 assume !(0 == ~T7_E~0); 124196#L1059-1 assume !(0 == ~T8_E~0); 123638#L1064-1 assume !(0 == ~T9_E~0); 123639#L1069-1 assume !(0 == ~T10_E~0); 124418#L1074-1 assume !(0 == ~E_M~0); 124484#L1079-1 assume !(0 == ~E_1~0); 124456#L1084-1 assume !(0 == ~E_2~0); 124457#L1089-1 assume !(0 == ~E_3~0); 124505#L1094-1 assume !(0 == ~E_4~0); 124034#L1099-1 assume !(0 == ~E_5~0); 124035#L1104-1 assume !(0 == ~E_6~0); 124317#L1109-1 assume !(0 == ~E_7~0); 123809#L1114-1 assume !(0 == ~E_8~0); 123810#L1119-1 assume !(0 == ~E_9~0); 123877#L1124-1 assume !(0 == ~E_10~0); 123284#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 123285#L502 assume !(1 == ~m_pc~0); 123479#L502-2 is_master_triggered_~__retres1~0#1 := 0; 123410#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 123411#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 124248#L1273 assume !(0 != activate_threads_~tmp~1#1); 124249#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 124631#L521 assume !(1 == ~t1_pc~0); 124537#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 123335#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123300#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 123301#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 123321#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123322#L540 assume !(1 == ~t2_pc~0); 124148#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 124149#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 123805#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 123806#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 124532#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 123615#L559 assume 1 == ~t3_pc~0; 123616#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 123897#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123237#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 123238#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 123428#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123429#L578 assume !(1 == ~t4_pc~0); 123548#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 123547#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123367#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 123368#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 124228#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 124229#L597 assume 1 == ~t5_pc~0; 124651#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 123355#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 123356#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 124451#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 124173#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 124174#L616 assume !(1 == ~t6_pc~0); 124191#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 124190#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 123779#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 123780#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 124023#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 124024#L635 assume 1 == ~t7_pc~0; 124233#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 123324#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 123709#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 124500#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 124166#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 124167#L654 assume !(1 == ~t8_pc~0); 123971#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 123972#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 124372#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 124373#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 124416#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 123580#L673 assume 1 == ~t9_pc~0; 123581#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 123275#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 123861#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 123862#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 124329#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 124330#L692 assume !(1 == ~t10_pc~0); 124269#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 124268#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 124026#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 124027#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 124038#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124394#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 123489#L1142-2 assume !(1 == ~T1_E~0); 123490#L1147-1 assume !(1 == ~T2_E~0); 124379#L1152-1 assume !(1 == ~T3_E~0); 124684#L1157-1 assume !(1 == ~T4_E~0); 150382#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 150381#L1167-1 assume !(1 == ~T6_E~0); 150380#L1172-1 assume !(1 == ~T7_E~0); 150379#L1177-1 assume !(1 == ~T8_E~0); 150378#L1182-1 assume !(1 == ~T9_E~0); 150377#L1187-1 assume !(1 == ~T10_E~0); 124370#L1192-1 assume !(1 == ~E_M~0); 124371#L1197-1 assume !(1 == ~E_1~0); 151710#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 151709#L1207-1 assume !(1 == ~E_3~0); 151705#L1212-1 assume !(1 == ~E_4~0); 151701#L1217-1 assume !(1 == ~E_5~0); 151697#L1222-1 assume !(1 == ~E_6~0); 151693#L1227-1 assume !(1 == ~E_7~0); 151689#L1232-1 assume !(1 == ~E_8~0); 124212#L1237-1 assume !(1 == ~E_9~0); 151682#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 151364#L1247-1 assume { :end_inline_reset_delta_events } true; 151362#L1553-2 [2024-11-13 15:14:35,951 INFO L747 eck$LassoCheckResult]: Loop: 151362#L1553-2 assume !false; 151360#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 151354#L999-1 assume !false; 151352#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 151345#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 151333#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 151331#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 151328#L854 assume !(0 != eval_~tmp~0#1); 151329#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 154290#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 154288#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 154286#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 154284#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 154282#L1034-3 assume !(0 == ~T3_E~0); 154280#L1039-3 assume !(0 == ~T4_E~0); 154277#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 154275#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 154273#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 154271#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 154269#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 154267#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 154264#L1074-3 assume !(0 == ~E_M~0); 154262#L1079-3 assume !(0 == ~E_1~0); 154260#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 154258#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 154256#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 154254#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 154251#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 154249#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 154247#L1114-3 assume !(0 == ~E_8~0); 154245#L1119-3 assume !(0 == ~E_9~0); 154243#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 154241#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 154238#L502-36 assume !(1 == ~m_pc~0); 154236#L502-38 is_master_triggered_~__retres1~0#1 := 0; 154234#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 154232#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 153317#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 152991#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 152634#L521-36 assume 1 == ~t1_pc~0; 152630#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 152628#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 152626#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 152624#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 152622#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 152620#L540-36 assume !(1 == ~t2_pc~0); 152618#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 152616#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 152614#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 152612#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 152610#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 152608#L559-36 assume 1 == ~t3_pc~0; 152604#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 152602#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 152600#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 152598#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 152596#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 152594#L578-36 assume !(1 == ~t4_pc~0); 152590#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 152588#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 152586#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 152584#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 152582#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 152580#L597-36 assume 1 == ~t5_pc~0; 152576#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 152574#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 152572#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 152570#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 152568#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 152566#L616-36 assume 1 == ~t6_pc~0; 152562#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 152560#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 152558#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 152556#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 152554#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 152552#L635-36 assume 1 == ~t7_pc~0; 152548#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 152546#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 152544#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 152542#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 152540#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 152538#L654-36 assume 1 == ~t8_pc~0; 152534#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 152532#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 152530#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 152528#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 152526#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 152524#L673-36 assume !(1 == ~t9_pc~0); 152520#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 152518#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 152516#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 152514#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 152512#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 152510#L692-36 assume 1 == ~t10_pc~0; 152506#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 152504#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 152502#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 152500#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 152498#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 152497#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 140512#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 152493#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 152491#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 143118#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 152489#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 152487#L1167-3 assume !(1 == ~T6_E~0); 152485#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 152483#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 152481#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 152479#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 152477#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 151458#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 152475#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 152473#L1207-3 assume !(1 == ~E_3~0); 152471#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 152469#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 152467#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 152465#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 152464#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 152459#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 152457#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 152455#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 152444#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 152441#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 152440#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 152439#L1572 assume !(0 == start_simulation_~tmp~3#1); 123763#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 151387#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 151376#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 151374#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 151371#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 151369#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 151367#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 151365#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 151362#L1553-2 [2024-11-13 15:14:35,951 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:35,952 INFO L85 PathProgramCache]: Analyzing trace with hash 353984391, now seen corresponding path program 1 times [2024-11-13 15:14:35,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:35,952 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1916077603] [2024-11-13 15:14:35,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:35,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:35,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:36,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:36,052 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:36,053 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1916077603] [2024-11-13 15:14:36,053 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1916077603] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:36,053 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:36,053 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:14:36,053 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1547761522] [2024-11-13 15:14:36,053 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:36,054 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:14:36,054 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:36,054 INFO L85 PathProgramCache]: Analyzing trace with hash -1770533221, now seen corresponding path program 1 times [2024-11-13 15:14:36,054 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:36,054 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1336532681] [2024-11-13 15:14:36,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:36,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:36,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:36,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:36,211 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:36,211 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1336532681] [2024-11-13 15:14:36,211 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1336532681] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:36,212 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:36,212 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:36,212 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [145129909] [2024-11-13 15:14:36,212 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:36,212 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:14:36,212 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:14:36,213 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:14:36,213 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:14:36,214 INFO L87 Difference]: Start difference. First operand 31425 states and 45537 transitions. cyclomatic complexity: 14144 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:36,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:14:36,510 INFO L93 Difference]: Finished difference Result 59788 states and 86234 transitions. [2024-11-13 15:14:36,511 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59788 states and 86234 transitions. [2024-11-13 15:14:36,844 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 59420 [2024-11-13 15:14:37,207 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59788 states to 59788 states and 86234 transitions. [2024-11-13 15:14:37,208 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 59788 [2024-11-13 15:14:37,254 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 59788 [2024-11-13 15:14:37,255 INFO L73 IsDeterministic]: Start isDeterministic. Operand 59788 states and 86234 transitions. [2024-11-13 15:14:37,302 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:14:37,302 INFO L218 hiAutomatonCegarLoop]: Abstraction has 59788 states and 86234 transitions. [2024-11-13 15:14:37,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59788 states and 86234 transitions. [2024-11-13 15:14:38,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59788 to 59724. [2024-11-13 15:14:38,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59724 states, 59724 states have (on average 1.4428035630567275) internal successors, (86170), 59723 states have internal predecessors, (86170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:38,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59724 states to 59724 states and 86170 transitions. [2024-11-13 15:14:38,375 INFO L240 hiAutomatonCegarLoop]: Abstraction has 59724 states and 86170 transitions. [2024-11-13 15:14:38,378 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:14:38,378 INFO L424 stractBuchiCegarLoop]: Abstraction has 59724 states and 86170 transitions. [2024-11-13 15:14:38,378 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 15:14:38,378 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59724 states and 86170 transitions. [2024-11-13 15:14:38,561 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 59356 [2024-11-13 15:14:38,561 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:14:38,561 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:14:38,568 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:38,568 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:38,569 INFO L745 eck$LassoCheckResult]: Stem: 214808#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 214809#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 215799#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 215800#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 215420#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 215092#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 215093#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 215389#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 215586#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 215269#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 215270#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 215148#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 215149#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 215530#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 215480#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 215396#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 215397#L1024 assume !(0 == ~M_E~0); 215697#L1024-2 assume !(0 == ~T1_E~0); 214804#L1029-1 assume !(0 == ~T2_E~0); 214805#L1034-1 assume !(0 == ~T3_E~0); 214909#L1039-1 assume !(0 == ~T4_E~0); 215827#L1044-1 assume !(0 == ~T5_E~0); 215170#L1049-1 assume !(0 == ~T6_E~0); 215171#L1054-1 assume !(0 == ~T7_E~0); 215419#L1059-1 assume !(0 == ~T8_E~0); 214856#L1064-1 assume !(0 == ~T9_E~0); 214857#L1069-1 assume !(0 == ~T10_E~0); 215664#L1074-1 assume !(0 == ~E_M~0); 215731#L1079-1 assume !(0 == ~E_1~0); 215699#L1084-1 assume !(0 == ~E_2~0); 215700#L1089-1 assume !(0 == ~E_3~0); 215750#L1094-1 assume !(0 == ~E_4~0); 215259#L1099-1 assume !(0 == ~E_5~0); 215260#L1104-1 assume !(0 == ~E_6~0); 215550#L1109-1 assume !(0 == ~E_7~0); 215029#L1114-1 assume !(0 == ~E_8~0); 215030#L1119-1 assume !(0 == ~E_9~0); 215102#L1124-1 assume !(0 == ~E_10~0); 214503#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 214504#L502 assume !(1 == ~m_pc~0); 214700#L502-2 is_master_triggered_~__retres1~0#1 := 0; 214629#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 214630#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 215474#L1273 assume !(0 != activate_threads_~tmp~1#1); 215475#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 215863#L521 assume !(1 == ~t1_pc~0); 215786#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 214554#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 214519#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 214520#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 214540#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 214541#L540 assume !(1 == ~t2_pc~0); 215374#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 215375#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 215025#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 215026#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 215780#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 214835#L559 assume !(1 == ~t3_pc~0); 214836#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 215125#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 214456#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 214457#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 214647#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 214648#L578 assume !(1 == ~t4_pc~0); 214770#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 214769#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 214586#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 214587#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 215451#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 215452#L597 assume 1 == ~t5_pc~0; 215883#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 214574#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 214575#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 215695#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 215398#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 215399#L616 assume !(1 == ~t6_pc~0); 215414#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 215413#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 214999#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 215000#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 215248#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 215249#L635 assume 1 == ~t7_pc~0; 215457#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 214543#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 214925#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 215746#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 215391#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 215392#L654 assume !(1 == ~t8_pc~0); 215200#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 215201#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 215616#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 215617#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 215662#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 214802#L673 assume 1 == ~t9_pc~0; 214803#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 214494#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 215086#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 215087#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 215565#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 215566#L692 assume !(1 == ~t10_pc~0); 215497#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 215496#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 215251#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 215252#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 215264#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 215640#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 214710#L1142-2 assume !(1 == ~T1_E~0); 214711#L1147-1 assume !(1 == ~T2_E~0); 215922#L1152-1 assume !(1 == ~T3_E~0); 215132#L1157-1 assume !(1 == ~T4_E~0); 215133#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 215288#L1167-1 assume !(1 == ~T6_E~0); 215289#L1172-1 assume !(1 == ~T7_E~0); 215768#L1177-1 assume !(1 == ~T8_E~0); 215438#L1182-1 assume !(1 == ~T9_E~0); 215439#L1187-1 assume !(1 == ~T10_E~0); 215558#L1192-1 assume !(1 == ~E_M~0); 215613#L1197-1 assume !(1 == ~E_1~0); 269642#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 269641#L1207-1 assume !(1 == ~E_3~0); 269638#L1212-1 assume !(1 == ~E_4~0); 269634#L1217-1 assume !(1 == ~E_5~0); 269630#L1222-1 assume !(1 == ~E_6~0); 269626#L1227-1 assume !(1 == ~E_7~0); 269622#L1232-1 assume !(1 == ~E_8~0); 215435#L1237-1 assume !(1 == ~E_9~0); 269615#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 268883#L1247-1 assume { :end_inline_reset_delta_events } true; 268881#L1553-2 [2024-11-13 15:14:38,569 INFO L747 eck$LassoCheckResult]: Loop: 268881#L1553-2 assume !false; 268879#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 268874#L999-1 assume !false; 268872#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 268867#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 268856#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 268855#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 268853#L854 assume !(0 != eval_~tmp~0#1); 268854#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 269167#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 269165#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 269163#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 269161#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 269159#L1034-3 assume !(0 == ~T3_E~0); 269157#L1039-3 assume !(0 == ~T4_E~0); 269155#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 269153#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 269151#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 269149#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 269147#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 269145#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 269143#L1074-3 assume !(0 == ~E_M~0); 269141#L1079-3 assume !(0 == ~E_1~0); 269139#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 269137#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 269135#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 269133#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 269131#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 269129#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 269127#L1114-3 assume !(0 == ~E_8~0); 269125#L1119-3 assume !(0 == ~E_9~0); 269123#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 269121#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 269119#L502-36 assume !(1 == ~m_pc~0); 269117#L502-38 is_master_triggered_~__retres1~0#1 := 0; 269115#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 269113#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 269111#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 269109#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 269107#L521-36 assume !(1 == ~t1_pc~0); 269104#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 269101#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 269099#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 269097#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 269095#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 269093#L540-36 assume !(1 == ~t2_pc~0); 269091#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 269089#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 269087#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 269085#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 269083#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 269081#L559-36 assume !(1 == ~t3_pc~0); 269079#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 269077#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 269075#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 269073#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 269071#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 269069#L578-36 assume !(1 == ~t4_pc~0); 269065#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 269063#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 269061#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 269059#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 269057#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 269055#L597-36 assume !(1 == ~t5_pc~0); 269052#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 269049#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 269047#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 269045#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 269043#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 269041#L616-36 assume 1 == ~t6_pc~0; 269037#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 269035#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 269033#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 269031#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 269029#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 269027#L635-36 assume !(1 == ~t7_pc~0); 269024#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 269021#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 269019#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 269017#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 269015#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 269013#L654-36 assume 1 == ~t8_pc~0; 269009#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 269007#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 269005#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 269003#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 269001#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 268999#L673-36 assume 1 == ~t9_pc~0; 268996#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 268993#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 268991#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 268989#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 268987#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 268985#L692-36 assume 1 == ~t10_pc~0; 268981#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 268979#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 268977#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 268975#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 268973#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 268972#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 242877#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 268968#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 268966#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 254331#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 268964#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 268962#L1167-3 assume !(1 == ~T6_E~0); 268960#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 268958#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 268956#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 268954#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 268952#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 248147#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 268950#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 268948#L1207-3 assume !(1 == ~E_3~0); 268946#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 268944#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 268942#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 268940#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 268939#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 268936#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 268935#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 268934#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 268923#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 268921#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 268918#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 268916#L1572 assume !(0 == start_simulation_~tmp~3#1); 214978#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 268906#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 268895#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 268893#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 268891#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 268888#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 268886#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 268884#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 268881#L1553-2 [2024-11-13 15:14:38,570 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:38,570 INFO L85 PathProgramCache]: Analyzing trace with hash -1601336824, now seen corresponding path program 1 times [2024-11-13 15:14:38,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:38,570 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [109529296] [2024-11-13 15:14:38,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:38,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:38,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:38,813 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:38,814 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:38,814 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [109529296] [2024-11-13 15:14:38,814 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [109529296] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:38,814 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:38,814 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:14:38,814 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1317555751] [2024-11-13 15:14:38,814 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:38,815 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:14:38,815 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:38,815 INFO L85 PathProgramCache]: Analyzing trace with hash -95999970, now seen corresponding path program 1 times [2024-11-13 15:14:38,815 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:38,815 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1483491852] [2024-11-13 15:14:38,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:38,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:38,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:38,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:38,886 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:38,886 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1483491852] [2024-11-13 15:14:38,886 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1483491852] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:38,886 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:38,886 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:38,886 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1248812058] [2024-11-13 15:14:38,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:38,887 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:14:38,887 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:14:38,887 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:14:38,887 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:14:38,888 INFO L87 Difference]: Start difference. First operand 59724 states and 86170 transitions. cyclomatic complexity: 26510 Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:39,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:14:39,547 INFO L93 Difference]: Finished difference Result 61575 states and 88021 transitions. [2024-11-13 15:14:39,548 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61575 states and 88021 transitions. [2024-11-13 15:14:39,777 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 61204 [2024-11-13 15:14:40,097 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61575 states to 61575 states and 88021 transitions. [2024-11-13 15:14:40,098 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61575 [2024-11-13 15:14:40,121 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61575 [2024-11-13 15:14:40,121 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61575 states and 88021 transitions. [2024-11-13 15:14:40,164 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:14:40,164 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61575 states and 88021 transitions. [2024-11-13 15:14:40,203 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61575 states and 88021 transitions. [2024-11-13 15:14:40,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61575 to 61575. [2024-11-13 15:14:40,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61575 states, 61575 states have (on average 1.4294924888347544) internal successors, (88021), 61574 states have internal predecessors, (88021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:41,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61575 states to 61575 states and 88021 transitions. [2024-11-13 15:14:41,320 INFO L240 hiAutomatonCegarLoop]: Abstraction has 61575 states and 88021 transitions. [2024-11-13 15:14:41,320 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:14:41,321 INFO L424 stractBuchiCegarLoop]: Abstraction has 61575 states and 88021 transitions. [2024-11-13 15:14:41,321 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 15:14:41,321 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61575 states and 88021 transitions. [2024-11-13 15:14:41,445 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 61204 [2024-11-13 15:14:41,445 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:14:41,446 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:14:41,447 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:41,447 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:41,447 INFO L745 eck$LassoCheckResult]: Stem: 336119#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 336120#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 337124#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 337125#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 336740#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 336397#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 336398#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 336705#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 336896#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 336579#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 336580#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 336452#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 336453#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 336841#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 336798#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 336712#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 336713#L1024 assume !(0 == ~M_E~0); 337006#L1024-2 assume !(0 == ~T1_E~0); 336115#L1029-1 assume !(0 == ~T2_E~0); 336116#L1034-1 assume !(0 == ~T3_E~0); 336224#L1039-1 assume !(0 == ~T4_E~0); 337156#L1044-1 assume !(0 == ~T5_E~0); 336474#L1049-1 assume !(0 == ~T6_E~0); 336475#L1054-1 assume !(0 == ~T7_E~0); 336739#L1059-1 assume !(0 == ~T8_E~0); 336169#L1064-1 assume !(0 == ~T9_E~0); 336170#L1069-1 assume !(0 == ~T10_E~0); 336970#L1074-1 assume !(0 == ~E_M~0); 337046#L1079-1 assume !(0 == ~E_1~0); 337009#L1084-1 assume !(0 == ~E_2~0); 337010#L1089-1 assume !(0 == ~E_3~0); 337072#L1094-1 assume !(0 == ~E_4~0); 336569#L1099-1 assume !(0 == ~E_5~0); 336570#L1104-1 assume !(0 == ~E_6~0); 336863#L1109-1 assume !(0 == ~E_7~0); 336339#L1114-1 assume !(0 == ~E_8~0); 336340#L1119-1 assume !(0 == ~E_9~0); 336408#L1124-1 assume !(0 == ~E_10~0); 335812#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 335813#L502 assume !(1 == ~m_pc~0); 336009#L502-2 is_master_triggered_~__retres1~0#1 := 0; 335941#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 335942#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 336792#L1273 assume !(0 != activate_threads_~tmp~1#1); 336793#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 337221#L521 assume !(1 == ~t1_pc~0); 337109#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 335862#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 335828#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 335829#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 335848#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 335849#L540 assume !(1 == ~t2_pc~0); 336692#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 336693#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 336335#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 336336#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 337103#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 336148#L559 assume !(1 == ~t3_pc~0); 336149#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 336429#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 335765#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 335766#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 335959#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 335960#L578 assume !(1 == ~t4_pc~0); 336079#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 336975#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 335895#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 335896#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 336772#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 336773#L597 assume 1 == ~t5_pc~0; 337248#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 335883#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 335884#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 337004#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 336714#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 336715#L616 assume !(1 == ~t6_pc~0); 336734#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 336733#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 336312#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 336313#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 336557#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 336558#L635 assume 1 == ~t7_pc~0; 336777#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 335851#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 336241#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 337068#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 336707#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 336708#L654 assume !(1 == ~t8_pc~0); 336505#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 336506#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 336923#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 336924#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 336968#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 336113#L673 assume 1 == ~t9_pc~0; 336114#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 335803#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 336391#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 336392#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 336876#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 336877#L692 assume !(1 == ~t10_pc~0); 336814#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 336813#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 336560#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 336561#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 336573#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 336944#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 336019#L1142-2 assume !(1 == ~T1_E~0); 336020#L1147-1 assume !(1 == ~T2_E~0); 336931#L1152-1 assume !(1 == ~T3_E~0); 336436#L1157-1 assume !(1 == ~T4_E~0); 336437#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 336599#L1167-1 assume !(1 == ~T6_E~0); 336600#L1172-1 assume !(1 == ~T7_E~0); 337093#L1177-1 assume !(1 == ~T8_E~0); 336757#L1182-1 assume !(1 == ~T9_E~0); 336758#L1187-1 assume !(1 == ~T10_E~0); 336869#L1192-1 assume !(1 == ~E_M~0); 336290#L1197-1 assume !(1 == ~E_1~0); 336291#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 336696#L1207-1 assume !(1 == ~E_3~0); 336668#L1212-1 assume !(1 == ~E_4~0); 335867#L1217-1 assume !(1 == ~E_5~0); 335868#L1222-1 assume !(1 == ~E_6~0); 336664#L1227-1 assume !(1 == ~E_7~0); 336665#L1232-1 assume !(1 == ~E_8~0); 335742#L1237-1 assume !(1 == ~E_9~0); 335743#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 336737#L1247-1 assume { :end_inline_reset_delta_events } true; 336738#L1553-2 [2024-11-13 15:14:41,448 INFO L747 eck$LassoCheckResult]: Loop: 336738#L1553-2 assume !false; 364566#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 364560#L999-1 assume !false; 361151#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 345373#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 345361#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 345359#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 345356#L854 assume !(0 != eval_~tmp~0#1); 345357#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 366706#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 366705#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 366704#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 366703#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 366702#L1034-3 assume !(0 == ~T3_E~0); 366701#L1039-3 assume !(0 == ~T4_E~0); 366700#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 366699#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 366698#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 366697#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 366696#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 366695#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 366694#L1074-3 assume !(0 == ~E_M~0); 366693#L1079-3 assume !(0 == ~E_1~0); 366692#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 366691#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 366690#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 366689#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 366688#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 366687#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 366686#L1114-3 assume !(0 == ~E_8~0); 366685#L1119-3 assume !(0 == ~E_9~0); 366684#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 366683#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 366682#L502-36 assume !(1 == ~m_pc~0); 366681#L502-38 is_master_triggered_~__retres1~0#1 := 0; 366680#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 366679#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 366678#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 366677#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 366676#L521-36 assume !(1 == ~t1_pc~0); 366675#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 366673#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 366672#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 366671#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 366670#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 366669#L540-36 assume !(1 == ~t2_pc~0); 366668#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 366667#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 366666#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 366665#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 366664#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 366663#L559-36 assume !(1 == ~t3_pc~0); 366662#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 366661#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 366660#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 366659#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 366658#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 366657#L578-36 assume !(1 == ~t4_pc~0); 366656#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 366654#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 366652#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 366650#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 366648#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 366647#L597-36 assume 1 == ~t5_pc~0; 366645#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 366644#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 366643#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 366642#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 366641#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 366640#L616-36 assume !(1 == ~t6_pc~0); 366639#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 366637#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 366636#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 366635#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 366634#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 366633#L635-36 assume 1 == ~t7_pc~0; 366631#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 366630#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 366629#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 366628#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 366627#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 366626#L654-36 assume !(1 == ~t8_pc~0); 366625#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 366623#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 366622#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 366621#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 366620#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 366619#L673-36 assume !(1 == ~t9_pc~0); 366617#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 366616#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 366615#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 366614#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 366613#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 366612#L692-36 assume !(1 == ~t10_pc~0); 366611#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 366609#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 366608#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 366607#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 366606#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 366605#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 346963#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 366604#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 366602#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 357379#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 366599#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 366597#L1167-3 assume !(1 == ~T6_E~0); 366595#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 366593#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 366591#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 366590#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 366588#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 353909#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 366575#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 366573#L1207-3 assume !(1 == ~E_3~0); 337736#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 337734#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 337732#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 337730#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 337728#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 337726#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 337724#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 337722#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 337700#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 337698#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 337696#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 337413#L1572 assume !(0 == start_simulation_~tmp~3#1); 337414#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 364591#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 364580#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 364578#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 364575#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 364573#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 364571#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 364569#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 336738#L1553-2 [2024-11-13 15:14:41,448 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:41,448 INFO L85 PathProgramCache]: Analyzing trace with hash 360237834, now seen corresponding path program 1 times [2024-11-13 15:14:41,448 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:41,448 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1056717754] [2024-11-13 15:14:41,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:41,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:41,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:41,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:41,523 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:41,523 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1056717754] [2024-11-13 15:14:41,523 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1056717754] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:41,523 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:41,523 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:14:41,523 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1839096769] [2024-11-13 15:14:41,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:41,524 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:14:41,524 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:41,524 INFO L85 PathProgramCache]: Analyzing trace with hash -1295143070, now seen corresponding path program 1 times [2024-11-13 15:14:41,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:41,524 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1459404999] [2024-11-13 15:14:41,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:41,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:41,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:41,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:41,581 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:41,582 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1459404999] [2024-11-13 15:14:41,582 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1459404999] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:41,582 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:41,582 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:41,582 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1453008742] [2024-11-13 15:14:41,582 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:41,582 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:14:41,582 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:14:41,583 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:14:41,583 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:14:41,583 INFO L87 Difference]: Start difference. First operand 61575 states and 88021 transitions. cyclomatic complexity: 26510 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:42,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:14:42,024 INFO L93 Difference]: Finished difference Result 117170 states and 166838 transitions. [2024-11-13 15:14:42,024 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117170 states and 166838 transitions. [2024-11-13 15:14:42,677 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 116512 [2024-11-13 15:14:42,902 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117170 states to 117170 states and 166838 transitions. [2024-11-13 15:14:42,902 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117170 [2024-11-13 15:14:42,967 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117170 [2024-11-13 15:14:42,968 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117170 states and 166838 transitions. [2024-11-13 15:14:43,315 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:14:43,315 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117170 states and 166838 transitions. [2024-11-13 15:14:43,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117170 states and 166838 transitions. [2024-11-13 15:14:44,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117170 to 117042. [2024-11-13 15:14:44,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117042 states, 117042 states have (on average 1.424360485979392) internal successors, (166710), 117041 states have internal predecessors, (166710), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:44,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117042 states to 117042 states and 166710 transitions. [2024-11-13 15:14:44,881 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117042 states and 166710 transitions. [2024-11-13 15:14:44,882 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:14:44,882 INFO L424 stractBuchiCegarLoop]: Abstraction has 117042 states and 166710 transitions. [2024-11-13 15:14:44,882 INFO L331 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-13 15:14:44,883 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117042 states and 166710 transitions. [2024-11-13 15:14:45,292 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 116384 [2024-11-13 15:14:45,293 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:14:45,293 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:14:45,295 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:45,295 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:45,295 INFO L745 eck$LassoCheckResult]: Stem: 514868#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 514869#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 515889#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 515890#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 515501#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 515159#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 515160#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 515463#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 515657#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 515340#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 515341#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 515213#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 515214#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 515606#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 515562#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 515474#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 515475#L1024 assume !(0 == ~M_E~0); 515786#L1024-2 assume !(0 == ~T1_E~0); 514864#L1029-1 assume !(0 == ~T2_E~0); 514865#L1034-1 assume !(0 == ~T3_E~0); 514973#L1039-1 assume !(0 == ~T4_E~0); 515916#L1044-1 assume !(0 == ~T5_E~0); 515234#L1049-1 assume !(0 == ~T6_E~0); 515235#L1054-1 assume !(0 == ~T7_E~0); 515500#L1059-1 assume !(0 == ~T8_E~0); 514918#L1064-1 assume !(0 == ~T9_E~0); 514919#L1069-1 assume !(0 == ~T10_E~0); 515745#L1074-1 assume !(0 == ~E_M~0); 515820#L1079-1 assume !(0 == ~E_1~0); 515788#L1084-1 assume !(0 == ~E_2~0); 515789#L1089-1 assume !(0 == ~E_3~0); 515842#L1094-1 assume !(0 == ~E_4~0); 515331#L1099-1 assume !(0 == ~E_5~0); 515332#L1104-1 assume !(0 == ~E_6~0); 515626#L1109-1 assume !(0 == ~E_7~0); 515093#L1114-1 assume !(0 == ~E_8~0); 515094#L1119-1 assume !(0 == ~E_9~0); 515170#L1124-1 assume !(0 == ~E_10~0); 514564#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 514565#L502 assume !(1 == ~m_pc~0); 514760#L502-2 is_master_triggered_~__retres1~0#1 := 0; 514691#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 514692#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 515556#L1273 assume !(0 != activate_threads_~tmp~1#1); 515557#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 515977#L521 assume !(1 == ~t1_pc~0); 515876#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 514615#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 514580#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 514581#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 514601#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 514602#L540 assume !(1 == ~t2_pc~0); 515448#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 515449#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 515089#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 515090#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 515869#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 514897#L559 assume !(1 == ~t3_pc~0); 514898#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 515191#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 514517#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 514518#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 514709#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 514710#L578 assume !(1 == ~t4_pc~0); 514828#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 515750#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 514648#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 514649#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 515536#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 515537#L597 assume !(1 == ~t5_pc~0); 515485#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 514636#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 514637#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 515783#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 515476#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 515477#L616 assume !(1 == ~t6_pc~0); 515495#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 515494#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 515065#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 515066#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 515319#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 515320#L635 assume 1 == ~t7_pc~0; 515541#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 514604#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 514989#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 515837#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 515469#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 515470#L654 assume !(1 == ~t8_pc~0); 515265#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 515266#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 515692#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 515693#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 515742#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 514862#L673 assume 1 == ~t9_pc~0; 514863#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 514555#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 515153#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 515154#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 515640#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 515641#L692 assume !(1 == ~t10_pc~0); 515578#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 515577#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 515323#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 515324#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 515335#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 515718#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 514770#L1142-2 assume !(1 == ~T1_E~0); 514771#L1147-1 assume !(1 == ~T2_E~0); 515699#L1152-1 assume !(1 == ~T3_E~0); 515198#L1157-1 assume !(1 == ~T4_E~0); 515199#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 515359#L1167-1 assume !(1 == ~T6_E~0); 515360#L1172-1 assume !(1 == ~T7_E~0); 515860#L1177-1 assume !(1 == ~T8_E~0); 515521#L1182-1 assume !(1 == ~T9_E~0); 515522#L1187-1 assume !(1 == ~T10_E~0); 515633#L1192-1 assume !(1 == ~E_M~0); 515039#L1197-1 assume !(1 == ~E_1~0); 515040#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 515452#L1207-1 assume !(1 == ~E_3~0); 515426#L1212-1 assume !(1 == ~E_4~0); 514620#L1217-1 assume !(1 == ~E_5~0); 514621#L1222-1 assume !(1 == ~E_6~0); 515423#L1227-1 assume !(1 == ~E_7~0); 515424#L1232-1 assume !(1 == ~E_8~0); 515517#L1237-1 assume !(1 == ~E_9~0); 546713#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 546645#L1247-1 assume { :end_inline_reset_delta_events } true; 546630#L1553-2 [2024-11-13 15:14:45,296 INFO L747 eck$LassoCheckResult]: Loop: 546630#L1553-2 assume !false; 542882#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 542877#L999-1 assume !false; 542875#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 541553#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 541539#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 541537#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 541534#L854 assume !(0 != eval_~tmp~0#1); 541535#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 566597#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 566591#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 566586#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 566580#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 566575#L1034-3 assume !(0 == ~T3_E~0); 566570#L1039-3 assume !(0 == ~T4_E~0); 566566#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 566562#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 566556#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 566550#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 566544#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 566539#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 566534#L1074-3 assume !(0 == ~E_M~0); 566529#L1079-3 assume !(0 == ~E_1~0); 566524#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 566518#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 566512#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 566507#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 566503#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 566499#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 566493#L1114-3 assume !(0 == ~E_8~0); 566488#L1119-3 assume !(0 == ~E_9~0); 566482#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 566477#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 566472#L502-36 assume !(1 == ~m_pc~0); 566468#L502-38 is_master_triggered_~__retres1~0#1 := 0; 566463#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 566457#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 566189#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 551981#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 551980#L521-36 assume 1 == ~t1_pc~0; 551978#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 551977#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 551976#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 547185#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 547182#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 547180#L540-36 assume !(1 == ~t2_pc~0); 547178#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 547176#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 547174#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 547172#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 547169#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 547167#L559-36 assume !(1 == ~t3_pc~0); 547165#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 547163#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 547161#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 547160#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 547158#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 547156#L578-36 assume !(1 == ~t4_pc~0); 547152#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 547150#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 547148#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 547146#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 547143#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 547141#L597-36 assume !(1 == ~t5_pc~0); 547139#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 547137#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 547135#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 547133#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 547131#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 547129#L616-36 assume 1 == ~t6_pc~0; 547126#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 547122#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 547120#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 547118#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 547116#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 547113#L635-36 assume 1 == ~t7_pc~0; 547110#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 547108#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 547106#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 547104#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 547102#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 547100#L654-36 assume 1 == ~t8_pc~0; 547097#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 547095#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 547092#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 547090#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 547088#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 547086#L673-36 assume !(1 == ~t9_pc~0); 547083#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 547081#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 547078#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 547076#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 547074#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 547072#L692-36 assume 1 == ~t10_pc~0; 547069#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 547067#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 547064#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 547062#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 547060#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 547058#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 516440#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 547055#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 547052#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 516433#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 547049#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 547047#L1167-3 assume !(1 == ~T6_E~0); 547045#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 547043#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 547040#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 547038#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 547036#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 543742#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 547033#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 547031#L1207-3 assume !(1 == ~E_3~0); 547029#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 547027#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 547025#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 547023#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 547021#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 545907#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 547018#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 547016#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 546994#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 546992#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 546990#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 546989#L1572 assume !(0 == start_simulation_~tmp~3#1); 546987#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 546668#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 546657#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 546654#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 546652#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 546650#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 546648#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 546646#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 546630#L1553-2 [2024-11-13 15:14:45,296 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:45,297 INFO L85 PathProgramCache]: Analyzing trace with hash -671092981, now seen corresponding path program 1 times [2024-11-13 15:14:45,297 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:45,297 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1528219259] [2024-11-13 15:14:45,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:45,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:45,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:45,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:45,421 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:45,422 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1528219259] [2024-11-13 15:14:45,422 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1528219259] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:45,422 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:45,422 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:45,422 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [787051972] [2024-11-13 15:14:45,422 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:45,422 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:14:45,422 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:45,423 INFO L85 PathProgramCache]: Analyzing trace with hash 1552889887, now seen corresponding path program 1 times [2024-11-13 15:14:45,423 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:45,423 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1773961353] [2024-11-13 15:14:45,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:45,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:45,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:45,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:45,500 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:45,501 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1773961353] [2024-11-13 15:14:45,501 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1773961353] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:45,501 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:45,501 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:45,501 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [38104575] [2024-11-13 15:14:45,501 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:45,502 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:14:45,502 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:14:45,502 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:14:45,502 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:14:45,503 INFO L87 Difference]: Start difference. First operand 117042 states and 166710 transitions. cyclomatic complexity: 49796 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:46,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:14:46,880 INFO L93 Difference]: Finished difference Result 281557 states and 398399 transitions. [2024-11-13 15:14:46,881 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 281557 states and 398399 transitions. [2024-11-13 15:14:48,343 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 279812 [2024-11-13 15:14:49,378 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 281557 states to 281557 states and 398399 transitions. [2024-11-13 15:14:49,378 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 281557 [2024-11-13 15:14:49,508 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 281557 [2024-11-13 15:14:49,508 INFO L73 IsDeterministic]: Start isDeterministic. Operand 281557 states and 398399 transitions. [2024-11-13 15:14:49,706 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:14:49,706 INFO L218 hiAutomatonCegarLoop]: Abstraction has 281557 states and 398399 transitions. [2024-11-13 15:14:49,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281557 states and 398399 transitions. [2024-11-13 15:14:52,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281557 to 227265. [2024-11-13 15:14:52,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 227265 states, 227265 states have (on average 1.4180582139792752) internal successors, (322275), 227264 states have internal predecessors, (322275), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:52,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227265 states to 227265 states and 322275 transitions. [2024-11-13 15:14:52,661 INFO L240 hiAutomatonCegarLoop]: Abstraction has 227265 states and 322275 transitions. [2024-11-13 15:14:52,663 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:14:52,663 INFO L424 stractBuchiCegarLoop]: Abstraction has 227265 states and 322275 transitions. [2024-11-13 15:14:52,664 INFO L331 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-13 15:14:52,664 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 227265 states and 322275 transitions. [2024-11-13 15:14:53,717 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 226160 [2024-11-13 15:14:53,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:14:53,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:14:53,718 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:53,718 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:14:53,719 INFO L745 eck$LassoCheckResult]: Stem: 913475#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 913476#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 914473#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 914474#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 914087#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 913752#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 913753#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 914055#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 914251#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 913933#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 913934#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 913807#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 913808#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 914197#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 914147#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 914062#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 914063#L1024 assume !(0 == ~M_E~0); 914374#L1024-2 assume !(0 == ~T1_E~0); 913471#L1029-1 assume !(0 == ~T2_E~0); 913472#L1034-1 assume !(0 == ~T3_E~0); 913576#L1039-1 assume !(0 == ~T4_E~0); 914503#L1044-1 assume !(0 == ~T5_E~0); 913829#L1049-1 assume !(0 == ~T6_E~0); 913830#L1054-1 assume !(0 == ~T7_E~0); 914086#L1059-1 assume !(0 == ~T8_E~0); 913525#L1064-1 assume !(0 == ~T9_E~0); 913526#L1069-1 assume !(0 == ~T10_E~0); 914335#L1074-1 assume !(0 == ~E_M~0); 914408#L1079-1 assume !(0 == ~E_1~0); 914376#L1084-1 assume !(0 == ~E_2~0); 914377#L1089-1 assume !(0 == ~E_3~0); 914430#L1094-1 assume !(0 == ~E_4~0); 913924#L1099-1 assume !(0 == ~E_5~0); 913925#L1104-1 assume !(0 == ~E_6~0); 914217#L1109-1 assume !(0 == ~E_7~0); 913693#L1114-1 assume !(0 == ~E_8~0); 913694#L1119-1 assume !(0 == ~E_9~0); 913763#L1124-1 assume !(0 == ~E_10~0); 913172#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 913173#L502 assume !(1 == ~m_pc~0); 913368#L502-2 is_master_triggered_~__retres1~0#1 := 0; 913299#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 913300#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 914141#L1273 assume !(0 != activate_threads_~tmp~1#1); 914142#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 914557#L521 assume !(1 == ~t1_pc~0); 914459#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 913223#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 913188#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 913189#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 913209#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 913210#L540 assume !(1 == ~t2_pc~0); 914042#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 914043#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 913689#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 913690#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 914455#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 913503#L559 assume !(1 == ~t3_pc~0); 913504#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 913784#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 913125#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 913126#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 913317#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 913318#L578 assume !(1 == ~t4_pc~0); 913436#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 914341#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 914371#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 914542#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 914118#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 914119#L597 assume !(1 == ~t5_pc~0); 914072#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 913243#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 913244#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 914372#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 914064#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 914065#L616 assume !(1 == ~t6_pc~0); 914081#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 914080#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 913665#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 913666#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 913912#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 913913#L635 assume !(1 == ~t7_pc~0); 913211#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 913212#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 913593#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 914426#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 914057#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 914058#L654 assume !(1 == ~t8_pc~0); 913859#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 913860#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 914281#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 914282#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 914333#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 913469#L673 assume 1 == ~t9_pc~0; 913470#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 913163#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 913746#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 913747#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 914233#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 914234#L692 assume !(1 == ~t10_pc~0); 914166#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 914165#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 913915#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 913916#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 913928#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 914311#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 913378#L1142-2 assume !(1 == ~T1_E~0); 913379#L1147-1 assume !(1 == ~T2_E~0); 914632#L1152-1 assume !(1 == ~T3_E~0); 914633#L1157-1 assume !(1 == ~T4_E~0); 914383#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 914384#L1167-1 assume !(1 == ~T6_E~0); 914447#L1172-1 assume !(1 == ~T7_E~0); 914448#L1177-1 assume !(1 == ~T8_E~0); 914104#L1182-1 assume !(1 == ~T9_E~0); 914105#L1187-1 assume !(1 == ~T10_E~0); 914278#L1192-1 assume !(1 == ~E_M~0); 914279#L1197-1 assume !(1 == ~E_1~0); 997751#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 997750#L1207-1 assume !(1 == ~E_3~0); 997749#L1212-1 assume !(1 == ~E_4~0); 997748#L1217-1 assume !(1 == ~E_5~0); 997747#L1222-1 assume !(1 == ~E_6~0); 997746#L1227-1 assume !(1 == ~E_7~0); 997745#L1232-1 assume !(1 == ~E_8~0); 997742#L1237-1 assume !(1 == ~E_9~0); 997741#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 997739#L1247-1 assume { :end_inline_reset_delta_events } true; 997735#L1553-2 [2024-11-13 15:14:53,719 INFO L747 eck$LassoCheckResult]: Loop: 997735#L1553-2 assume !false; 997731#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 997727#L999-1 assume !false; 997726#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 997323#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 997312#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 995053#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 995048#L854 assume !(0 != eval_~tmp~0#1); 995049#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1007805#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1007803#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1007801#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1007798#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1007796#L1034-3 assume !(0 == ~T3_E~0); 1007794#L1039-3 assume !(0 == ~T4_E~0); 1007792#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1007790#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1007788#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1007785#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1007783#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1007781#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1007779#L1074-3 assume !(0 == ~E_M~0); 1007777#L1079-3 assume !(0 == ~E_1~0); 1007775#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1007773#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1007771#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1007770#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1007769#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1007768#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1007767#L1114-3 assume !(0 == ~E_8~0); 1007766#L1119-3 assume !(0 == ~E_9~0); 1007765#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1007764#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1007763#L502-36 assume !(1 == ~m_pc~0); 1007762#L502-38 is_master_triggered_~__retres1~0#1 := 0; 1007761#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1007760#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1007758#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1007757#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1007756#L521-36 assume !(1 == ~t1_pc~0); 1007753#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1007750#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1007747#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1007745#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1007743#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1007741#L540-36 assume !(1 == ~t2_pc~0); 1007739#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1007737#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1007735#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1007733#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1007731#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1007729#L559-36 assume !(1 == ~t3_pc~0); 1007727#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1007725#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1007723#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1007721#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1007719#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1007717#L578-36 assume !(1 == ~t4_pc~0); 1007715#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1015594#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1011545#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1007705#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 1007701#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1007699#L597-36 assume !(1 == ~t5_pc~0); 1007697#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1007695#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1007693#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1007691#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 1007689#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1007687#L616-36 assume !(1 == ~t6_pc~0); 1007685#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1007681#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1007679#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1007677#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1007675#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1007673#L635-36 assume !(1 == ~t7_pc~0); 964864#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1007671#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1007669#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1007667#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1007665#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1007663#L654-36 assume !(1 == ~t8_pc~0); 1007661#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1007657#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1007655#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1007653#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1007651#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1007649#L673-36 assume 1 == ~t9_pc~0; 1007647#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1007643#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1007641#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1007639#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1007637#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1007635#L692-36 assume !(1 == ~t10_pc~0); 1007633#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1007629#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1007627#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1007625#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1007623#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1007621#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 994079#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1007616#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1007614#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1007610#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1007608#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1007606#L1167-3 assume !(1 == ~T6_E~0); 1007604#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1007602#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1007600#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1007598#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1007596#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1007592#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1007590#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1007588#L1207-3 assume !(1 == ~E_3~0); 1007586#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1007584#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1007582#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1007580#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1007578#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1001882#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1007575#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1007573#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1007560#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1007558#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1007556#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1007554#L1572 assume !(0 == start_simulation_~tmp~3#1); 1007551#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1007543#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1007533#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1007531#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 1004938#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1004936#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 997752#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 997740#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 997735#L1553-2 [2024-11-13 15:14:53,719 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:53,719 INFO L85 PathProgramCache]: Analyzing trace with hash 1730432140, now seen corresponding path program 1 times [2024-11-13 15:14:53,720 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:53,720 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1361600823] [2024-11-13 15:14:53,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:53,720 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:53,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:53,782 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:53,782 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:53,782 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1361600823] [2024-11-13 15:14:53,782 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1361600823] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:53,783 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:53,783 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:14:53,783 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [344497128] [2024-11-13 15:14:53,783 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:53,783 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:14:53,784 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:14:53,784 INFO L85 PathProgramCache]: Analyzing trace with hash 1906614371, now seen corresponding path program 1 times [2024-11-13 15:14:53,784 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:14:53,784 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [629258710] [2024-11-13 15:14:53,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:14:53,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:14:53,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:14:53,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:14:53,832 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:14:53,832 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [629258710] [2024-11-13 15:14:53,833 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [629258710] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:14:53,833 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:14:53,833 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:14:53,833 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1272485684] [2024-11-13 15:14:53,833 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:14:53,834 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:14:53,834 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:14:53,834 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:14:53,835 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:14:53,835 INFO L87 Difference]: Start difference. First operand 227265 states and 322275 transitions. cyclomatic complexity: 95138 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:14:55,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:14:55,722 INFO L93 Difference]: Finished difference Result 431696 states and 610128 transitions. [2024-11-13 15:14:55,722 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 431696 states and 610128 transitions. [2024-11-13 15:14:57,945 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 429184 [2024-11-13 15:14:59,697 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 431696 states to 431696 states and 610128 transitions. [2024-11-13 15:14:59,698 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 431696 [2024-11-13 15:14:59,832 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 431696 [2024-11-13 15:14:59,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 431696 states and 610128 transitions. [2024-11-13 15:14:59,981 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:14:59,982 INFO L218 hiAutomatonCegarLoop]: Abstraction has 431696 states and 610128 transitions. [2024-11-13 15:15:00,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 431696 states and 610128 transitions. [2024-11-13 15:15:03,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 431696 to 431184. [2024-11-13 15:15:04,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 431184 states, 431184 states have (on average 1.4138186945712272) internal successors, (609616), 431183 states have internal predecessors, (609616), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:15:05,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 431184 states to 431184 states and 609616 transitions. [2024-11-13 15:15:05,125 INFO L240 hiAutomatonCegarLoop]: Abstraction has 431184 states and 609616 transitions. [2024-11-13 15:15:05,125 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:15:05,126 INFO L424 stractBuchiCegarLoop]: Abstraction has 431184 states and 609616 transitions. [2024-11-13 15:15:05,126 INFO L331 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-13 15:15:05,126 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 431184 states and 609616 transitions.