./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.11.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ab2f671-61f7-4a2e-bd6c-0ed978efcb7d/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ab2f671-61f7-4a2e-bd6c-0ed978efcb7d/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ab2f671-61f7-4a2e-bd6c-0ed978efcb7d/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ab2f671-61f7-4a2e-bd6c-0ed978efcb7d/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.11.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ab2f671-61f7-4a2e-bd6c-0ed978efcb7d/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ab2f671-61f7-4a2e-bd6c-0ed978efcb7d/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c5f603027c62ff37561a520351662dbe2fd253b52e04e36028cb9a624978ef8e --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 15:57:29,394 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 15:57:29,490 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ab2f671-61f7-4a2e-bd6c-0ed978efcb7d/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 15:57:29,497 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 15:57:29,497 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 15:57:29,534 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 15:57:29,536 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 15:57:29,536 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 15:57:29,537 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 15:57:29,537 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 15:57:29,539 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 15:57:29,539 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 15:57:29,539 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 15:57:29,539 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 15:57:29,540 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 15:57:29,541 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 15:57:29,541 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 15:57:29,541 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 15:57:29,541 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 15:57:29,541 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 15:57:29,541 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 15:57:29,541 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 15:57:29,542 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 15:57:29,542 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 15:57:29,542 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 15:57:29,542 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 15:57:29,542 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 15:57:29,542 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 15:57:29,542 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 15:57:29,542 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 15:57:29,542 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 15:57:29,543 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 15:57:29,543 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 15:57:29,543 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 15:57:29,543 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 15:57:29,543 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 15:57:29,543 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 15:57:29,543 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 15:57:29,544 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 15:57:29,544 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ab2f671-61f7-4a2e-bd6c-0ed978efcb7d/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c5f603027c62ff37561a520351662dbe2fd253b52e04e36028cb9a624978ef8e [2024-11-13 15:57:29,853 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 15:57:29,864 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 15:57:29,866 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 15:57:29,868 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 15:57:29,868 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 15:57:29,869 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ab2f671-61f7-4a2e-bd6c-0ed978efcb7d/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/token_ring.11.cil-2.c Unable to find full path for "g++" [2024-11-13 15:57:31,751 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 15:57:32,098 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 15:57:32,098 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ab2f671-61f7-4a2e-bd6c-0ed978efcb7d/sv-benchmarks/c/systemc/token_ring.11.cil-2.c [2024-11-13 15:57:32,112 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ab2f671-61f7-4a2e-bd6c-0ed978efcb7d/bin/uautomizer-verify-qhAvR1uOyd/data/8d0b93a52/7e51941381074eafb26c6f158bc24ca4/FLAG5473bf4ca [2024-11-13 15:57:32,127 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ab2f671-61f7-4a2e-bd6c-0ed978efcb7d/bin/uautomizer-verify-qhAvR1uOyd/data/8d0b93a52/7e51941381074eafb26c6f158bc24ca4 [2024-11-13 15:57:32,130 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 15:57:32,131 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 15:57:32,132 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 15:57:32,133 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 15:57:32,137 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 15:57:32,138 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:57:32" (1/1) ... [2024-11-13 15:57:32,139 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6aaf8e42 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:57:32, skipping insertion in model container [2024-11-13 15:57:32,139 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:57:32" (1/1) ... [2024-11-13 15:57:32,173 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 15:57:32,528 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:57:32,544 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 15:57:32,614 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:57:32,634 INFO L204 MainTranslator]: Completed translation [2024-11-13 15:57:32,634 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:57:32 WrapperNode [2024-11-13 15:57:32,634 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 15:57:32,635 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 15:57:32,635 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 15:57:32,635 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 15:57:32,642 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:57:32" (1/1) ... [2024-11-13 15:57:32,652 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:57:32" (1/1) ... [2024-11-13 15:57:32,777 INFO L138 Inliner]: procedures = 50, calls = 65, calls flagged for inlining = 60, calls inlined = 239, statements flattened = 3656 [2024-11-13 15:57:32,779 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 15:57:32,779 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 15:57:32,779 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 15:57:32,779 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 15:57:32,790 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:57:32" (1/1) ... [2024-11-13 15:57:32,790 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:57:32" (1/1) ... [2024-11-13 15:57:32,800 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:57:32" (1/1) ... [2024-11-13 15:57:32,836 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 15:57:32,837 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:57:32" (1/1) ... [2024-11-13 15:57:32,837 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:57:32" (1/1) ... [2024-11-13 15:57:32,873 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:57:32" (1/1) ... [2024-11-13 15:57:32,937 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:57:32" (1/1) ... [2024-11-13 15:57:32,948 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:57:32" (1/1) ... [2024-11-13 15:57:32,956 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:57:32" (1/1) ... [2024-11-13 15:57:32,968 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 15:57:32,968 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 15:57:32,968 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 15:57:32,969 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 15:57:32,970 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:57:32" (1/1) ... [2024-11-13 15:57:32,975 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:57:32,988 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ab2f671-61f7-4a2e-bd6c-0ed978efcb7d/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:57:33,003 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ab2f671-61f7-4a2e-bd6c-0ed978efcb7d/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:57:33,007 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ab2f671-61f7-4a2e-bd6c-0ed978efcb7d/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 15:57:33,040 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 15:57:33,040 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 15:57:33,040 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 15:57:33,040 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 15:57:33,190 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 15:57:33,192 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 15:57:36,422 INFO L? ?]: Removed 768 outVars from TransFormulas that were not future-live. [2024-11-13 15:57:36,423 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 15:57:36,493 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 15:57:36,495 INFO L316 CfgBuilder]: Removed 14 assume(true) statements. [2024-11-13 15:57:36,495 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:57:36 BoogieIcfgContainer [2024-11-13 15:57:36,496 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 15:57:36,497 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 15:57:36,497 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 15:57:36,505 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 15:57:36,505 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:57:36,505 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 03:57:32" (1/3) ... [2024-11-13 15:57:36,507 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@587a9efc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:57:36, skipping insertion in model container [2024-11-13 15:57:36,507 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:57:36,507 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:57:32" (2/3) ... [2024-11-13 15:57:36,507 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@587a9efc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:57:36, skipping insertion in model container [2024-11-13 15:57:36,507 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:57:36,507 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:57:36" (3/3) ... [2024-11-13 15:57:36,509 INFO L333 chiAutomizerObserver]: Analyzing ICFG token_ring.11.cil-2.c [2024-11-13 15:57:36,609 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 15:57:36,609 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 15:57:36,609 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 15:57:36,609 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 15:57:36,609 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 15:57:36,609 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 15:57:36,609 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 15:57:36,610 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 15:57:36,622 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1585 states, 1584 states have (on average 1.4981060606060606) internal successors, (2373), 1584 states have internal predecessors, (2373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:36,720 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1430 [2024-11-13 15:57:36,720 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:36,721 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:36,733 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:36,734 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:36,734 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 15:57:36,738 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1585 states, 1584 states have (on average 1.4981060606060606) internal successors, (2373), 1584 states have internal predecessors, (2373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:36,780 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1430 [2024-11-13 15:57:36,781 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:36,781 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:36,788 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:36,789 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:36,799 INFO L745 eck$LassoCheckResult]: Stem: 123#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1525#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 608#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1521#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 109#L780true assume !(1 == ~m_i~0);~m_st~0 := 2; 1157#L780-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1415#L785-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1091#L790-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1413#L795-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 302#L800-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 581#L805-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1101#L810-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1030#L815-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 250#L820-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 730#L825-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 193#L830-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 921#L835-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1471#L1109true assume !(0 == ~M_E~0); 956#L1109-2true assume !(0 == ~T1_E~0); 198#L1114-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1542#L1119-1true assume !(0 == ~T3_E~0); 1035#L1124-1true assume !(0 == ~T4_E~0); 21#L1129-1true assume !(0 == ~T5_E~0); 353#L1134-1true assume !(0 == ~T6_E~0); 940#L1139-1true assume !(0 == ~T7_E~0); 1013#L1144-1true assume !(0 == ~T8_E~0); 780#L1149-1true assume !(0 == ~T9_E~0); 72#L1154-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 915#L1159-1true assume !(0 == ~T11_E~0); 769#L1164-1true assume !(0 == ~E_M~0); 279#L1169-1true assume !(0 == ~E_1~0); 224#L1174-1true assume !(0 == ~E_2~0); 151#L1179-1true assume !(0 == ~E_3~0); 112#L1184-1true assume !(0 == ~E_4~0); 130#L1189-1true assume !(0 == ~E_5~0); 174#L1194-1true assume 0 == ~E_6~0;~E_6~0 := 1; 788#L1199-1true assume !(0 == ~E_7~0); 964#L1204-1true assume !(0 == ~E_8~0); 726#L1209-1true assume !(0 == ~E_9~0); 1183#L1214-1true assume !(0 == ~E_10~0); 1544#L1219-1true assume !(0 == ~E_11~0); 1489#L1224-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 290#L544true assume 1 == ~m_pc~0; 1026#L545true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1193#L555true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 516#is_master_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 92#L1379true assume !(0 != activate_threads_~tmp~1#1); 1408#L1379-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 567#L563true assume !(1 == ~t1_pc~0); 1189#L563-2true is_transmit1_triggered_~__retres1~1#1 := 0; 26#L574true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 825#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 671#L1387true assume !(0 != activate_threads_~tmp___0~0#1); 24#L1387-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 414#L582true assume 1 == ~t2_pc~0; 884#L583true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 679#L593true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 196#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 838#L1395true assume !(0 != activate_threads_~tmp___1~0#1); 40#L1395-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 759#L601true assume !(1 == ~t3_pc~0); 473#L601-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1008#L612true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 806#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 708#L1403true assume !(0 != activate_threads_~tmp___2~0#1); 1426#L1403-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 660#L620true assume 1 == ~t4_pc~0; 31#L621true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 370#L631true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 578#L1411true assume !(0 != activate_threads_~tmp___3~0#1); 760#L1411-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 743#L639true assume 1 == ~t5_pc~0; 637#L640true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 177#L650true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1281#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 593#L1419true assume !(0 != activate_threads_~tmp___4~0#1); 846#L1419-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 537#L658true assume !(1 == ~t6_pc~0); 288#L658-2true is_transmit6_triggered_~__retres1~6#1 := 0; 700#L669true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 191#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1497#L1427true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 712#L1427-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 203#L677true assume 1 == ~t7_pc~0; 1251#L678true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 887#L688true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1536#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1076#L1435true assume !(0 != activate_threads_~tmp___6~0#1); 1234#L1435-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1314#L696true assume !(1 == ~t8_pc~0); 325#L696-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1154#L707true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1237#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1360#L1443true assume !(0 != activate_threads_~tmp___7~0#1); 1540#L1443-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 628#L715true assume 1 == ~t9_pc~0; 1225#L716true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 387#L726true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 223#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 613#L1451true assume !(0 != activate_threads_~tmp___8~0#1); 1406#L1451-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 885#L734true assume !(1 == ~t10_pc~0); 1036#L734-2true is_transmit10_triggered_~__retres1~10#1 := 0; 264#L745true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1088#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 810#L1459true assume !(0 != activate_threads_~tmp___9~0#1); 1263#L1459-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 310#L753true assume 1 == ~t11_pc~0; 718#L754true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1583#L764true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1171#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 486#L1467true assume !(0 != activate_threads_~tmp___10~0#1); 774#L1467-2true havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 521#L1237true assume !(1 == ~M_E~0); 1307#L1237-2true assume !(1 == ~T1_E~0); 1438#L1242-1true assume !(1 == ~T2_E~0); 367#L1247-1true assume !(1 == ~T3_E~0); 1072#L1252-1true assume !(1 == ~T4_E~0); 232#L1257-1true assume !(1 == ~T5_E~0); 905#L1262-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1058#L1267-1true assume !(1 == ~T7_E~0); 1059#L1272-1true assume !(1 == ~T8_E~0); 421#L1277-1true assume !(1 == ~T9_E~0); 818#L1282-1true assume !(1 == ~T10_E~0); 754#L1287-1true assume !(1 == ~T11_E~0); 789#L1292-1true assume !(1 == ~E_M~0); 711#L1297-1true assume !(1 == ~E_1~0); 304#L1302-1true assume 1 == ~E_2~0;~E_2~0 := 2; 1039#L1307-1true assume !(1 == ~E_3~0); 1371#L1312-1true assume !(1 == ~E_4~0); 449#L1317-1true assume !(1 == ~E_5~0); 622#L1322-1true assume !(1 == ~E_6~0); 272#L1327-1true assume !(1 == ~E_7~0); 670#L1332-1true assume !(1 == ~E_8~0); 1350#L1337-1true assume !(1 == ~E_9~0); 617#L1342-1true assume 1 == ~E_10~0;~E_10~0 := 2; 1240#L1347-1true assume !(1 == ~E_11~0); 1038#L1352-1true assume { :end_inline_reset_delta_events } true; 1580#L1678-2true [2024-11-13 15:57:36,802 INFO L747 eck$LassoCheckResult]: Loop: 1580#L1678-2true assume !false; 662#L1679true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1286#L1084-1true assume !true; 477#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 301#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1442#L1109-3true assume 0 == ~M_E~0;~M_E~0 := 1; 32#L1109-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1218#L1114-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 713#L1119-3true assume !(0 == ~T3_E~0); 1575#L1124-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 740#L1129-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 948#L1134-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1122#L1139-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1024#L1144-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 295#L1149-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1569#L1154-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 453#L1159-3true assume !(0 == ~T11_E~0); 1553#L1164-3true assume 0 == ~E_M~0;~E_M~0 := 1; 657#L1169-3true assume 0 == ~E_1~0;~E_1~0 := 1; 980#L1174-3true assume 0 == ~E_2~0;~E_2~0 := 1; 702#L1179-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1316#L1184-3true assume 0 == ~E_4~0;~E_4~0 := 1; 865#L1189-3true assume 0 == ~E_5~0;~E_5~0 := 1; 561#L1194-3true assume 0 == ~E_6~0;~E_6~0 := 1; 163#L1199-3true assume !(0 == ~E_7~0); 791#L1204-3true assume 0 == ~E_8~0;~E_8~0 := 1; 284#L1209-3true assume 0 == ~E_9~0;~E_9~0 := 1; 10#L1214-3true assume 0 == ~E_10~0;~E_10~0 := 1; 607#L1219-3true assume 0 == ~E_11~0;~E_11~0 := 1; 395#L1224-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 650#L544-39true assume !(1 == ~m_pc~0); 4#L544-41true is_master_triggered_~__retres1~0#1 := 0; 742#L555-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 629#is_master_triggered_returnLabel#14true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 207#L1379-39true assume !(0 != activate_threads_~tmp~1#1); 845#L1379-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1327#L563-39true assume !(1 == ~t1_pc~0); 70#L563-41true is_transmit1_triggered_~__retres1~1#1 := 0; 1554#L574-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1419#is_transmit1_triggered_returnLabel#14true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1453#L1387-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1464#L1387-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 994#L582-39true assume !(1 == ~t2_pc~0); 1248#L582-41true is_transmit2_triggered_~__retres1~2#1 := 0; 761#L593-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 434#is_transmit2_triggered_returnLabel#14true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 966#L1395-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 117#L1395-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15#L601-39true assume !(1 == ~t3_pc~0); 37#L601-41true is_transmit3_triggered_~__retres1~3#1 := 0; 803#L612-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1565#is_transmit3_triggered_returnLabel#14true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1510#L1403-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 853#L1403-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 535#L620-39true assume !(1 == ~t4_pc~0); 1560#L620-41true is_transmit4_triggered_~__retres1~4#1 := 0; 934#L631-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 553#is_transmit4_triggered_returnLabel#14true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 814#L1411-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1563#L1411-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1558#L639-39true assume !(1 == ~t5_pc~0); 1295#L639-41true is_transmit5_triggered_~__retres1~5#1 := 0; 371#L650-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 570#is_transmit5_triggered_returnLabel#14true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27#L1419-39true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1391#L1419-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 565#L658-39true assume !(1 == ~t6_pc~0); 1447#L658-41true is_transmit6_triggered_~__retres1~6#1 := 0; 1070#L669-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1494#is_transmit6_triggered_returnLabel#14true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 723#L1427-39true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 696#L1427-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1244#L677-39true assume 1 == ~t7_pc~0; 664#L678-13true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 111#L688-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 815#is_transmit7_triggered_returnLabel#14true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 141#L1435-39true assume !(0 != activate_threads_~tmp___6~0#1); 1381#L1435-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 488#L696-39true assume 1 == ~t8_pc~0; 460#L697-13true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 382#L707-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 935#is_transmit8_triggered_returnLabel#14true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 588#L1443-39true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 557#L1443-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 471#L715-39true assume 1 == ~t9_pc~0; 17#L716-13true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 812#L726-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53#is_transmit9_triggered_returnLabel#14true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1582#L1451-39true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 746#L1451-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1146#L734-39true assume !(1 == ~t10_pc~0); 278#L734-41true is_transmit10_triggered_~__retres1~10#1 := 0; 490#L745-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1167#is_transmit10_triggered_returnLabel#14true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 87#L1459-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1476#L1459-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1097#L753-39true assume !(1 == ~t11_pc~0); 51#L753-41true is_transmit11_triggered_~__retres1~11#1 := 0; 1010#L764-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 586#is_transmit11_triggered_returnLabel#14true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 464#L1467-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 753#L1467-41true havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 533#L1237-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1092#L1237-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 771#L1242-3true assume !(1 == ~T2_E~0); 1529#L1247-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1057#L1252-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 692#L1257-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1016#L1262-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1104#L1267-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1545#L1272-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1348#L1277-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 126#L1282-3true assume !(1 == ~T10_E~0); 672#L1287-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 79#L1292-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1507#L1297-3true assume 1 == ~E_1~0;~E_1~0 := 2; 899#L1302-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1231#L1307-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1527#L1312-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1518#L1317-3true assume 1 == ~E_5~0;~E_5~0 := 2; 792#L1322-3true assume !(1 == ~E_6~0); 1573#L1327-3true assume 1 == ~E_7~0;~E_7~0 := 2; 107#L1332-3true assume 1 == ~E_8~0;~E_8~0 := 2; 95#L1337-3true assume 1 == ~E_9~0;~E_9~0 := 2; 512#L1342-3true assume 1 == ~E_10~0;~E_10~0 := 2; 938#L1347-3true assume 1 == ~E_11~0;~E_11~0 := 2; 612#L1352-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 889#L848-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 212#L910-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 178#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 744#L1697true assume !(0 == start_simulation_~tmp~3#1); 528#L1697-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1319#L848-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 854#L910-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 1126#L1652true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 584#L1659true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1107#stop_simulation_returnLabel#1true start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 886#L1710true assume !(0 != start_simulation_~tmp___0~1#1); 1580#L1678-2true [2024-11-13 15:57:36,808 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:36,808 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 1 times [2024-11-13 15:57:36,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:36,817 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [873852200] [2024-11-13 15:57:36,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:36,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:36,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:37,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:37,231 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:37,231 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [873852200] [2024-11-13 15:57:37,232 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [873852200] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:37,232 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:37,232 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:37,234 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [396041869] [2024-11-13 15:57:37,235 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:37,238 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:37,239 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:37,239 INFO L85 PathProgramCache]: Analyzing trace with hash 787865133, now seen corresponding path program 1 times [2024-11-13 15:57:37,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:37,239 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1485243225] [2024-11-13 15:57:37,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:37,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:37,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:37,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:37,320 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:37,320 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1485243225] [2024-11-13 15:57:37,321 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1485243225] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:37,321 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:37,321 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:57:37,321 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1339850059] [2024-11-13 15:57:37,321 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:37,322 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:37,323 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:37,372 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-13 15:57:37,373 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-13 15:57:37,379 INFO L87 Difference]: Start difference. First operand has 1585 states, 1584 states have (on average 1.4981060606060606) internal successors, (2373), 1584 states have internal predecessors, (2373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 69.5) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:37,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:37,469 INFO L93 Difference]: Finished difference Result 1583 states and 2342 transitions. [2024-11-13 15:57:37,470 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1583 states and 2342 transitions. [2024-11-13 15:57:37,489 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:37,513 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1583 states to 1578 states and 2337 transitions. [2024-11-13 15:57:37,516 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-13 15:57:37,520 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-13 15:57:37,520 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2337 transitions. [2024-11-13 15:57:37,533 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:37,533 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2337 transitions. [2024-11-13 15:57:37,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2337 transitions. [2024-11-13 15:57:37,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-13 15:57:37,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4809885931558935) internal successors, (2337), 1577 states have internal predecessors, (2337), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:37,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2337 transitions. [2024-11-13 15:57:37,657 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2337 transitions. [2024-11-13 15:57:37,658 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-13 15:57:37,664 INFO L424 stractBuchiCegarLoop]: Abstraction has 1578 states and 2337 transitions. [2024-11-13 15:57:37,665 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 15:57:37,665 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2337 transitions. [2024-11-13 15:57:37,676 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:37,676 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:37,677 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:37,682 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:37,684 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:37,685 INFO L745 eck$LassoCheckResult]: Stem: 3433#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 3434#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4214#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4215#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3407#L780 assume !(1 == ~m_i~0);~m_st~0 := 2; 3408#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4648#L785-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4617#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4618#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3766#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3767#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4182#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4584#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3670#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3671#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 3561#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 3562#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4515#L1109 assume !(0 == ~M_E~0); 4532#L1109-2 assume !(0 == ~T1_E~0); 3570#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3571#L1119-1 assume !(0 == ~T3_E~0); 4587#L1124-1 assume !(0 == ~T4_E~0); 3221#L1129-1 assume !(0 == ~T5_E~0); 3222#L1134-1 assume !(0 == ~T6_E~0); 3853#L1139-1 assume !(0 == ~T7_E~0); 4523#L1144-1 assume !(0 == ~T8_E~0); 4393#L1149-1 assume !(0 == ~T9_E~0); 3332#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3333#L1159-1 assume !(0 == ~T11_E~0); 4383#L1164-1 assume !(0 == ~E_M~0); 3728#L1169-1 assume !(0 == ~E_1~0); 3622#L1174-1 assume !(0 == ~E_2~0); 3486#L1179-1 assume !(0 == ~E_3~0); 3413#L1184-1 assume !(0 == ~E_4~0); 3414#L1189-1 assume !(0 == ~E_5~0); 3446#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3529#L1199-1 assume !(0 == ~E_7~0); 4402#L1204-1 assume !(0 == ~E_8~0); 4343#L1209-1 assume !(0 == ~E_9~0); 4344#L1214-1 assume !(0 == ~E_10~0); 4661#L1219-1 assume !(0 == ~E_11~0); 4748#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3745#L544 assume 1 == ~m_pc~0; 3746#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4571#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4101#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3375#L1379 assume !(0 != activate_threads_~tmp~1#1); 3376#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4169#L563 assume !(1 == ~t1_pc~0); 3975#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3231#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3232#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4291#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 3227#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3228#L582 assume 1 == ~t2_pc~0; 3953#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4296#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3566#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3567#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 3260#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3261#L601 assume !(1 == ~t3_pc~0); 3970#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3969#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4423#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4328#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 4329#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4277#L620 assume 1 == ~t4_pc~0; 3241#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3242#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3274#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3275#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 4179#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4361#L639 assume 1 == ~t5_pc~0; 4251#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3534#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3535#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4199#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 4200#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4134#L658 assume !(1 == ~t6_pc~0); 3742#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3743#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3558#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3559#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4332#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3581#L677 assume 1 == ~t7_pc~0; 3582#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3479#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4489#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4610#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 4611#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4681#L696 assume !(1 == ~t8_pc~0); 3806#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3807#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4646#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4684#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 4729#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4238#L715 assume 1 == ~t9_pc~0; 4239#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3906#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3620#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3621#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 4221#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4484#L734 assume !(1 == ~t10_pc~0); 4485#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3698#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3699#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4427#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 4428#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3780#L753 assume 1 == ~t11_pc~0; 3781#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4337#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4655#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4056#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 4057#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4108#L1237 assume !(1 == ~M_E~0); 4109#L1237-2 assume !(1 == ~T1_E~0); 4712#L1242-1 assume !(1 == ~T2_E~0); 3874#L1247-1 assume !(1 == ~T3_E~0); 3875#L1252-1 assume !(1 == ~T4_E~0); 3639#L1257-1 assume !(1 == ~T5_E~0); 3640#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4504#L1267-1 assume !(1 == ~T7_E~0); 4602#L1272-1 assume !(1 == ~T8_E~0); 3964#L1277-1 assume !(1 == ~T9_E~0); 3965#L1282-1 assume !(1 == ~T10_E~0); 4370#L1287-1 assume !(1 == ~T11_E~0); 4371#L1292-1 assume !(1 == ~E_M~0); 4331#L1297-1 assume !(1 == ~E_1~0); 3771#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3772#L1307-1 assume !(1 == ~E_3~0); 4591#L1312-1 assume !(1 == ~E_4~0); 4010#L1317-1 assume !(1 == ~E_5~0); 4011#L1322-1 assume !(1 == ~E_6~0); 3715#L1327-1 assume !(1 == ~E_7~0); 3716#L1332-1 assume !(1 == ~E_8~0); 4290#L1337-1 assume !(1 == ~E_9~0); 4224#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 4225#L1347-1 assume !(1 == ~E_11~0); 4590#L1352-1 assume { :end_inline_reset_delta_events } true; 4488#L1678-2 [2024-11-13 15:57:37,686 INFO L747 eck$LassoCheckResult]: Loop: 4488#L1678-2 assume !false; 4280#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4281#L1084-1 assume !false; 4077#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4078#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3352#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4576#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3271#L925 assume !(0 != eval_~tmp~0#1); 3273#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3764#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3765#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3244#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3245#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4333#L1119-3 assume !(0 == ~T3_E~0); 4334#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4358#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4359#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4528#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4579#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3755#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3756#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4017#L1159-3 assume !(0 == ~T11_E~0); 4018#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4273#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4274#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4321#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4322#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4467#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4163#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3508#L1199-3 assume !(0 == ~E_7~0); 3509#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3735#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3194#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3195#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3918#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3919#L544-39 assume 1 == ~m_pc~0; 4265#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3183#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4241#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3589#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 3590#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4454#L563-39 assume 1 == ~t1_pc~0; 4460#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3328#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4739#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4740#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4743#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4562#L582-39 assume 1 == ~t2_pc~0; 3651#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3653#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3987#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3988#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3422#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3206#L601-39 assume 1 == ~t3_pc~0; 3207#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3255#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4421#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4750#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4458#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4129#L620-39 assume !(1 == ~t4_pc~0); 4130#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 4319#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4154#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4155#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4431#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4754#L639-39 assume 1 == ~t5_pc~0; 4545#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3877#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3878#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3233#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3234#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4166#L658-39 assume 1 == ~t6_pc~0; 4149#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4150#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4606#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4342#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4316#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4317#L677-39 assume !(1 == ~t7_pc~0); 3962#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 3411#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3412#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3467#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 3468#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4059#L696-39 assume 1 == ~t8_pc~0; 4025#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3900#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3901#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4191#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4159#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4039#L715-39 assume 1 == ~t9_pc~0; 3211#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3212#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3288#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3289#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4364#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4365#L734-39 assume 1 == ~t10_pc~0; 4294#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3727#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4062#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3365#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3366#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4620#L753-39 assume !(1 == ~t11_pc~0); 3284#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 3285#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4188#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4030#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4031#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4126#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4127#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4385#L1242-3 assume !(1 == ~T2_E~0); 4386#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4601#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4309#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4310#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4574#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4623#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4726#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3438#L1282-3 assume !(1 == ~T10_E~0); 3439#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3348#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3349#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4497#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4498#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4678#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4751#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4405#L1322-3 assume !(1 == ~E_6~0); 4406#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3404#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3381#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3382#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4097#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4219#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4220#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3330#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3536#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3537#L1697 assume !(0 == start_simulation_~tmp~3#1); 4116#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4117#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3455#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3223#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 3224#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4185#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4186#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 4487#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 4488#L1678-2 [2024-11-13 15:57:37,687 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:37,687 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 2 times [2024-11-13 15:57:37,687 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:37,689 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [593876196] [2024-11-13 15:57:37,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:37,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:37,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:37,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:37,902 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:37,903 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [593876196] [2024-11-13 15:57:37,903 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [593876196] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:37,903 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:37,904 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:37,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1947848886] [2024-11-13 15:57:37,904 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:37,906 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:37,907 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:37,907 INFO L85 PathProgramCache]: Analyzing trace with hash -950442133, now seen corresponding path program 1 times [2024-11-13 15:57:37,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:37,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1318428097] [2024-11-13 15:57:37,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:37,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:37,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:38,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:38,132 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:38,132 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1318428097] [2024-11-13 15:57:38,132 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1318428097] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:38,132 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:38,132 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:38,132 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1154136968] [2024-11-13 15:57:38,132 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:38,133 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:38,133 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:38,133 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:38,134 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:38,134 INFO L87 Difference]: Start difference. First operand 1578 states and 2337 transitions. cyclomatic complexity: 760 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:38,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:38,195 INFO L93 Difference]: Finished difference Result 1578 states and 2336 transitions. [2024-11-13 15:57:38,196 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2336 transitions. [2024-11-13 15:57:38,209 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:38,221 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2336 transitions. [2024-11-13 15:57:38,221 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-13 15:57:38,222 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-13 15:57:38,223 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2336 transitions. [2024-11-13 15:57:38,226 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:38,226 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2336 transitions. [2024-11-13 15:57:38,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2336 transitions. [2024-11-13 15:57:38,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-13 15:57:38,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4803548795944232) internal successors, (2336), 1577 states have internal predecessors, (2336), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:38,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2336 transitions. [2024-11-13 15:57:38,264 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2336 transitions. [2024-11-13 15:57:38,264 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:38,265 INFO L424 stractBuchiCegarLoop]: Abstraction has 1578 states and 2336 transitions. [2024-11-13 15:57:38,265 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 15:57:38,265 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2336 transitions. [2024-11-13 15:57:38,277 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:38,277 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:38,277 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:38,279 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:38,280 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:38,283 INFO L745 eck$LassoCheckResult]: Stem: 6596#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 6597#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7377#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7378#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6570#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 6571#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7811#L785-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7780#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7781#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6929#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6930#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7345#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7747#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6833#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6834#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6724#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 6725#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7678#L1109 assume !(0 == ~M_E~0); 7695#L1109-2 assume !(0 == ~T1_E~0); 6733#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6734#L1119-1 assume !(0 == ~T3_E~0); 7750#L1124-1 assume !(0 == ~T4_E~0); 6384#L1129-1 assume !(0 == ~T5_E~0); 6385#L1134-1 assume !(0 == ~T6_E~0); 7016#L1139-1 assume !(0 == ~T7_E~0); 7686#L1144-1 assume !(0 == ~T8_E~0); 7556#L1149-1 assume !(0 == ~T9_E~0); 6495#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6496#L1159-1 assume !(0 == ~T11_E~0); 7546#L1164-1 assume !(0 == ~E_M~0); 6891#L1169-1 assume !(0 == ~E_1~0); 6785#L1174-1 assume !(0 == ~E_2~0); 6649#L1179-1 assume !(0 == ~E_3~0); 6576#L1184-1 assume !(0 == ~E_4~0); 6577#L1189-1 assume !(0 == ~E_5~0); 6609#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 6692#L1199-1 assume !(0 == ~E_7~0); 7565#L1204-1 assume !(0 == ~E_8~0); 7506#L1209-1 assume !(0 == ~E_9~0); 7507#L1214-1 assume !(0 == ~E_10~0); 7824#L1219-1 assume !(0 == ~E_11~0); 7911#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6908#L544 assume 1 == ~m_pc~0; 6909#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7734#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7264#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6538#L1379 assume !(0 != activate_threads_~tmp~1#1); 6539#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7332#L563 assume !(1 == ~t1_pc~0); 7138#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6394#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6395#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7454#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 6390#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6391#L582 assume 1 == ~t2_pc~0; 7116#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7459#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6729#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6730#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 6423#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6424#L601 assume !(1 == ~t3_pc~0); 7133#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7132#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7586#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7491#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 7492#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7440#L620 assume 1 == ~t4_pc~0; 6404#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6405#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6437#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6438#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 7342#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7524#L639 assume 1 == ~t5_pc~0; 7414#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6697#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6698#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7362#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 7363#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7297#L658 assume !(1 == ~t6_pc~0); 6905#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6906#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6721#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6722#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7495#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6744#L677 assume 1 == ~t7_pc~0; 6745#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6642#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7652#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7773#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 7774#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7844#L696 assume !(1 == ~t8_pc~0); 6969#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6970#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7809#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7847#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 7892#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7401#L715 assume 1 == ~t9_pc~0; 7402#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7069#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6783#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6784#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 7384#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7647#L734 assume !(1 == ~t10_pc~0); 7648#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6861#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6862#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7590#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 7591#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6943#L753 assume 1 == ~t11_pc~0; 6944#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7500#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7818#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7219#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 7220#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7271#L1237 assume !(1 == ~M_E~0); 7272#L1237-2 assume !(1 == ~T1_E~0); 7875#L1242-1 assume !(1 == ~T2_E~0); 7037#L1247-1 assume !(1 == ~T3_E~0); 7038#L1252-1 assume !(1 == ~T4_E~0); 6802#L1257-1 assume !(1 == ~T5_E~0); 6803#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7667#L1267-1 assume !(1 == ~T7_E~0); 7765#L1272-1 assume !(1 == ~T8_E~0); 7127#L1277-1 assume !(1 == ~T9_E~0); 7128#L1282-1 assume !(1 == ~T10_E~0); 7533#L1287-1 assume !(1 == ~T11_E~0); 7534#L1292-1 assume !(1 == ~E_M~0); 7494#L1297-1 assume !(1 == ~E_1~0); 6934#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6935#L1307-1 assume !(1 == ~E_3~0); 7754#L1312-1 assume !(1 == ~E_4~0); 7173#L1317-1 assume !(1 == ~E_5~0); 7174#L1322-1 assume !(1 == ~E_6~0); 6878#L1327-1 assume !(1 == ~E_7~0); 6879#L1332-1 assume !(1 == ~E_8~0); 7453#L1337-1 assume !(1 == ~E_9~0); 7387#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 7388#L1347-1 assume !(1 == ~E_11~0); 7753#L1352-1 assume { :end_inline_reset_delta_events } true; 7651#L1678-2 [2024-11-13 15:57:38,284 INFO L747 eck$LassoCheckResult]: Loop: 7651#L1678-2 assume !false; 7443#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7444#L1084-1 assume !false; 7240#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7241#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6515#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7739#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6434#L925 assume !(0 != eval_~tmp~0#1); 6436#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6927#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6928#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6407#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6408#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7496#L1119-3 assume !(0 == ~T3_E~0); 7497#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7521#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7522#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7691#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7742#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6918#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6919#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7180#L1159-3 assume !(0 == ~T11_E~0); 7181#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7436#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7437#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7484#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7485#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7630#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7326#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6671#L1199-3 assume !(0 == ~E_7~0); 6672#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6898#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6357#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6358#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7081#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7082#L544-39 assume 1 == ~m_pc~0; 7428#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6346#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7404#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6752#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 6753#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7617#L563-39 assume 1 == ~t1_pc~0; 7623#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6491#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7902#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7903#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7906#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7725#L582-39 assume 1 == ~t2_pc~0; 6814#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6816#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7150#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7151#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6585#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6369#L601-39 assume 1 == ~t3_pc~0; 6370#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6418#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7584#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7913#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7621#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7292#L620-39 assume !(1 == ~t4_pc~0); 7293#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 7482#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7317#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7318#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7594#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7917#L639-39 assume 1 == ~t5_pc~0; 7708#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7040#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7041#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6396#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6397#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7329#L658-39 assume 1 == ~t6_pc~0; 7312#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7313#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7769#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7505#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7479#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7480#L677-39 assume !(1 == ~t7_pc~0); 7125#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 6574#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6575#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6630#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 6631#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7222#L696-39 assume 1 == ~t8_pc~0; 7188#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7063#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7064#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7354#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7322#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7202#L715-39 assume 1 == ~t9_pc~0; 6374#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6375#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6451#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6452#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7527#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7528#L734-39 assume 1 == ~t10_pc~0; 7457#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 6890#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7225#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6528#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6529#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7783#L753-39 assume !(1 == ~t11_pc~0); 6447#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 6448#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7351#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7193#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7194#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7289#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7290#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7548#L1242-3 assume !(1 == ~T2_E~0); 7549#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7764#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7472#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7473#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7737#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7786#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7889#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6601#L1282-3 assume !(1 == ~T10_E~0); 6602#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 6511#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6512#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7660#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7661#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7841#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7914#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7568#L1322-3 assume !(1 == ~E_6~0); 7569#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6567#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6544#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6545#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7260#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7382#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7383#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6493#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6699#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 6700#L1697 assume !(0 == start_simulation_~tmp~3#1); 7279#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7280#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6618#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6386#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 6387#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7348#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7349#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 7650#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 7651#L1678-2 [2024-11-13 15:57:38,284 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:38,284 INFO L85 PathProgramCache]: Analyzing trace with hash -968871490, now seen corresponding path program 1 times [2024-11-13 15:57:38,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:38,285 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1284442258] [2024-11-13 15:57:38,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:38,285 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:38,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:38,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:38,395 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:38,395 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1284442258] [2024-11-13 15:57:38,395 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1284442258] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:38,396 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:38,396 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:38,396 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [475903187] [2024-11-13 15:57:38,396 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:38,396 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:38,397 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:38,397 INFO L85 PathProgramCache]: Analyzing trace with hash -950442133, now seen corresponding path program 2 times [2024-11-13 15:57:38,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:38,401 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1305547992] [2024-11-13 15:57:38,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:38,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:38,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:38,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:38,501 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:38,501 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1305547992] [2024-11-13 15:57:38,501 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1305547992] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:38,501 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:38,501 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:38,502 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1618154966] [2024-11-13 15:57:38,502 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:38,502 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:38,502 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:38,503 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:38,503 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:38,503 INFO L87 Difference]: Start difference. First operand 1578 states and 2336 transitions. cyclomatic complexity: 759 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:38,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:38,543 INFO L93 Difference]: Finished difference Result 1578 states and 2335 transitions. [2024-11-13 15:57:38,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2335 transitions. [2024-11-13 15:57:38,554 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:38,562 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2335 transitions. [2024-11-13 15:57:38,562 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-13 15:57:38,564 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-13 15:57:38,565 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2335 transitions. [2024-11-13 15:57:38,568 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:38,568 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2335 transitions. [2024-11-13 15:57:38,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2335 transitions. [2024-11-13 15:57:38,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-13 15:57:38,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.479721166032953) internal successors, (2335), 1577 states have internal predecessors, (2335), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:38,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2335 transitions. [2024-11-13 15:57:38,601 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2335 transitions. [2024-11-13 15:57:38,602 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:38,602 INFO L424 stractBuchiCegarLoop]: Abstraction has 1578 states and 2335 transitions. [2024-11-13 15:57:38,602 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 15:57:38,603 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2335 transitions. [2024-11-13 15:57:38,612 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:38,612 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:38,612 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:38,614 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:38,615 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:38,615 INFO L745 eck$LassoCheckResult]: Stem: 9759#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 9760#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10541#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10542#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9733#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 9734#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10974#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10943#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10944#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10092#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10093#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10508#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10910#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9998#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9999#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9887#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9888#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10843#L1109 assume !(0 == ~M_E~0); 10858#L1109-2 assume !(0 == ~T1_E~0); 9896#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9897#L1119-1 assume !(0 == ~T3_E~0); 10913#L1124-1 assume !(0 == ~T4_E~0); 9547#L1129-1 assume !(0 == ~T5_E~0); 9548#L1134-1 assume !(0 == ~T6_E~0); 10179#L1139-1 assume !(0 == ~T7_E~0); 10849#L1144-1 assume !(0 == ~T8_E~0); 10719#L1149-1 assume !(0 == ~T9_E~0); 9660#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9661#L1159-1 assume !(0 == ~T11_E~0); 10709#L1164-1 assume !(0 == ~E_M~0); 10054#L1169-1 assume !(0 == ~E_1~0); 9948#L1174-1 assume !(0 == ~E_2~0); 9817#L1179-1 assume !(0 == ~E_3~0); 9739#L1184-1 assume !(0 == ~E_4~0); 9740#L1189-1 assume !(0 == ~E_5~0); 9772#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 9859#L1199-1 assume !(0 == ~E_7~0); 10728#L1204-1 assume !(0 == ~E_8~0); 10670#L1209-1 assume !(0 == ~E_9~0); 10671#L1214-1 assume !(0 == ~E_10~0); 10987#L1219-1 assume !(0 == ~E_11~0); 11074#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10073#L544 assume 1 == ~m_pc~0; 10074#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10897#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10427#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9701#L1379 assume !(0 != activate_threads_~tmp~1#1); 9702#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10497#L563 assume !(1 == ~t1_pc~0); 10301#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9557#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9558#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10617#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 9553#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9554#L582 assume 1 == ~t2_pc~0; 10279#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10622#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9892#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9893#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 9586#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9587#L601 assume !(1 == ~t3_pc~0); 10296#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10295#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10749#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10654#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 10655#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10603#L620 assume 1 == ~t4_pc~0; 9567#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9568#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9600#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9601#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 10505#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10688#L639 assume 1 == ~t5_pc~0; 10577#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9862#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9863#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10525#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 10526#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10462#L658 assume !(1 == ~t6_pc~0); 10068#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10069#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9884#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9885#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10658#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9909#L677 assume 1 == ~t7_pc~0; 9910#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9808#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10815#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10936#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 10937#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11007#L696 assume !(1 == ~t8_pc~0); 10133#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10134#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10972#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11010#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 11055#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10564#L715 assume 1 == ~t9_pc~0; 10565#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10232#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9946#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9947#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 10547#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10812#L734 assume !(1 == ~t10_pc~0); 10813#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10024#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10025#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10753#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 10754#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10106#L753 assume 1 == ~t11_pc~0; 10107#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10663#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10981#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10384#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 10385#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10436#L1237 assume !(1 == ~M_E~0); 10437#L1237-2 assume !(1 == ~T1_E~0); 11039#L1242-1 assume !(1 == ~T2_E~0); 10200#L1247-1 assume !(1 == ~T3_E~0); 10201#L1252-1 assume !(1 == ~T4_E~0); 9965#L1257-1 assume !(1 == ~T5_E~0); 9966#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10830#L1267-1 assume !(1 == ~T7_E~0); 10928#L1272-1 assume !(1 == ~T8_E~0); 10290#L1277-1 assume !(1 == ~T9_E~0); 10291#L1282-1 assume !(1 == ~T10_E~0); 10696#L1287-1 assume !(1 == ~T11_E~0); 10697#L1292-1 assume !(1 == ~E_M~0); 10657#L1297-1 assume !(1 == ~E_1~0); 10097#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 10098#L1307-1 assume !(1 == ~E_3~0); 10917#L1312-1 assume !(1 == ~E_4~0); 10336#L1317-1 assume !(1 == ~E_5~0); 10337#L1322-1 assume !(1 == ~E_6~0); 10043#L1327-1 assume !(1 == ~E_7~0); 10044#L1332-1 assume !(1 == ~E_8~0); 10616#L1337-1 assume !(1 == ~E_9~0); 10550#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 10551#L1347-1 assume !(1 == ~E_11~0); 10916#L1352-1 assume { :end_inline_reset_delta_events } true; 10811#L1678-2 [2024-11-13 15:57:38,615 INFO L747 eck$LassoCheckResult]: Loop: 10811#L1678-2 assume !false; 10608#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10609#L1084-1 assume !false; 10403#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10404#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9678#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10902#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9597#L925 assume !(0 != eval_~tmp~0#1); 9599#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10090#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10091#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9570#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9571#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10659#L1119-3 assume !(0 == ~T3_E~0); 10660#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10685#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10686#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10854#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10905#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10081#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10082#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10343#L1159-3 assume !(0 == ~T11_E~0); 10344#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10599#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10600#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10647#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10648#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10793#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10489#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9834#L1199-3 assume !(0 == ~E_7~0); 9835#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10061#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9520#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9521#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10244#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10245#L544-39 assume !(1 == ~m_pc~0); 9508#L544-41 is_master_triggered_~__retres1~0#1 := 0; 9509#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10567#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9915#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 9916#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10780#L563-39 assume 1 == ~t1_pc~0; 10786#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9654#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11065#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11066#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11069#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10888#L582-39 assume 1 == ~t2_pc~0; 9977#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9979#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10313#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10314#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9748#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9532#L601-39 assume 1 == ~t3_pc~0; 9533#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9581#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10747#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11076#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10784#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10455#L620-39 assume !(1 == ~t4_pc~0); 10456#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 10645#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10480#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10481#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10757#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11080#L639-39 assume 1 == ~t5_pc~0; 10871#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10203#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10204#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9559#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9560#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10492#L658-39 assume 1 == ~t6_pc~0; 10475#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10476#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10932#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10668#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10642#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10643#L677-39 assume !(1 == ~t7_pc~0); 10288#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 9737#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9738#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9793#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 9794#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10383#L696-39 assume !(1 == ~t8_pc~0); 10352#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 10226#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10227#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10517#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10485#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10365#L715-39 assume 1 == ~t9_pc~0; 9537#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9538#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9614#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9615#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10690#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10691#L734-39 assume !(1 == ~t10_pc~0); 10052#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 10053#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10388#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9691#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9692#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10946#L753-39 assume !(1 == ~t11_pc~0); 9610#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 9611#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10514#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10356#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10357#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10452#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10453#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10711#L1242-3 assume !(1 == ~T2_E~0); 10712#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10927#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10635#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10636#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10900#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10949#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11052#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9764#L1282-3 assume !(1 == ~T10_E~0); 9765#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9674#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9675#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10823#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10824#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11004#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11077#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10731#L1322-3 assume !(1 == ~E_6~0); 10732#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9730#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9707#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9708#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10423#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 10545#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10546#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9656#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9860#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 9861#L1697 assume !(0 == start_simulation_~tmp~3#1); 10442#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10443#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9781#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9549#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 9550#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10511#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10512#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 10810#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 10811#L1678-2 [2024-11-13 15:57:38,616 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:38,616 INFO L85 PathProgramCache]: Analyzing trace with hash -1332337988, now seen corresponding path program 1 times [2024-11-13 15:57:38,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:38,616 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [135571106] [2024-11-13 15:57:38,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:38,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:38,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:38,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:38,711 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:38,711 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [135571106] [2024-11-13 15:57:38,711 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [135571106] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:38,711 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:38,711 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:38,711 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1523574778] [2024-11-13 15:57:38,712 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:38,712 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:38,712 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:38,712 INFO L85 PathProgramCache]: Analyzing trace with hash 581685806, now seen corresponding path program 1 times [2024-11-13 15:57:38,712 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:38,713 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1740170428] [2024-11-13 15:57:38,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:38,713 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:38,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:38,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:38,851 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:38,851 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1740170428] [2024-11-13 15:57:38,851 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1740170428] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:38,852 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:38,852 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:38,852 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [937287691] [2024-11-13 15:57:38,852 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:38,853 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:38,853 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:38,853 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:38,853 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:38,854 INFO L87 Difference]: Start difference. First operand 1578 states and 2335 transitions. cyclomatic complexity: 758 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:38,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:38,893 INFO L93 Difference]: Finished difference Result 1578 states and 2334 transitions. [2024-11-13 15:57:38,893 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2334 transitions. [2024-11-13 15:57:38,903 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:38,911 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2334 transitions. [2024-11-13 15:57:38,911 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-13 15:57:38,913 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-13 15:57:38,913 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2334 transitions. [2024-11-13 15:57:38,916 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:38,916 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2334 transitions. [2024-11-13 15:57:38,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2334 transitions. [2024-11-13 15:57:38,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-13 15:57:38,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.479087452471483) internal successors, (2334), 1577 states have internal predecessors, (2334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:38,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2334 transitions. [2024-11-13 15:57:38,950 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2334 transitions. [2024-11-13 15:57:38,951 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:38,951 INFO L424 stractBuchiCegarLoop]: Abstraction has 1578 states and 2334 transitions. [2024-11-13 15:57:38,951 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 15:57:38,951 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2334 transitions. [2024-11-13 15:57:38,961 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:38,961 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:38,961 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:38,963 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:38,963 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:38,964 INFO L745 eck$LassoCheckResult]: Stem: 12922#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 12923#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 13703#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13704#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12896#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 12897#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14137#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14106#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14107#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13255#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13256#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13671#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14073#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13159#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13160#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13050#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13051#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14004#L1109 assume !(0 == ~M_E~0); 14021#L1109-2 assume !(0 == ~T1_E~0); 13059#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13060#L1119-1 assume !(0 == ~T3_E~0); 14076#L1124-1 assume !(0 == ~T4_E~0); 12710#L1129-1 assume !(0 == ~T5_E~0); 12711#L1134-1 assume !(0 == ~T6_E~0); 13342#L1139-1 assume !(0 == ~T7_E~0); 14012#L1144-1 assume !(0 == ~T8_E~0); 13882#L1149-1 assume !(0 == ~T9_E~0); 12821#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12822#L1159-1 assume !(0 == ~T11_E~0); 13872#L1164-1 assume !(0 == ~E_M~0); 13217#L1169-1 assume !(0 == ~E_1~0); 13111#L1174-1 assume !(0 == ~E_2~0); 12977#L1179-1 assume !(0 == ~E_3~0); 12902#L1184-1 assume !(0 == ~E_4~0); 12903#L1189-1 assume !(0 == ~E_5~0); 12935#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 13018#L1199-1 assume !(0 == ~E_7~0); 13891#L1204-1 assume !(0 == ~E_8~0); 13832#L1209-1 assume !(0 == ~E_9~0); 13833#L1214-1 assume !(0 == ~E_10~0); 14150#L1219-1 assume !(0 == ~E_11~0); 14237#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13234#L544 assume 1 == ~m_pc~0; 13235#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14060#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13590#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12864#L1379 assume !(0 != activate_threads_~tmp~1#1); 12865#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13658#L563 assume !(1 == ~t1_pc~0); 13464#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12720#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12721#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13780#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 12716#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12717#L582 assume 1 == ~t2_pc~0; 13442#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13785#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13055#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13056#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 12749#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12750#L601 assume !(1 == ~t3_pc~0); 13459#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13458#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13912#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13817#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 13818#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13766#L620 assume 1 == ~t4_pc~0; 12730#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12731#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12763#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12764#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 13668#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13851#L639 assume 1 == ~t5_pc~0; 13740#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13025#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13026#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13688#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 13689#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13623#L658 assume !(1 == ~t6_pc~0); 13231#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 13232#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13047#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13048#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13821#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13070#L677 assume 1 == ~t7_pc~0; 13071#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12968#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13978#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14099#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 14100#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14170#L696 assume !(1 == ~t8_pc~0); 13295#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 13296#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14135#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14173#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 14218#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13727#L715 assume 1 == ~t9_pc~0; 13728#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13395#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13109#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13110#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 13710#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13975#L734 assume !(1 == ~t10_pc~0); 13976#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 13187#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13188#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13916#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 13917#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13269#L753 assume 1 == ~t11_pc~0; 13270#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13826#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14144#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13546#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 13547#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13597#L1237 assume !(1 == ~M_E~0); 13598#L1237-2 assume !(1 == ~T1_E~0); 14201#L1242-1 assume !(1 == ~T2_E~0); 13363#L1247-1 assume !(1 == ~T3_E~0); 13364#L1252-1 assume !(1 == ~T4_E~0); 13128#L1257-1 assume !(1 == ~T5_E~0); 13129#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13993#L1267-1 assume !(1 == ~T7_E~0); 14091#L1272-1 assume !(1 == ~T8_E~0); 13453#L1277-1 assume !(1 == ~T9_E~0); 13454#L1282-1 assume !(1 == ~T10_E~0); 13859#L1287-1 assume !(1 == ~T11_E~0); 13860#L1292-1 assume !(1 == ~E_M~0); 13820#L1297-1 assume !(1 == ~E_1~0); 13260#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 13261#L1307-1 assume !(1 == ~E_3~0); 14080#L1312-1 assume !(1 == ~E_4~0); 13499#L1317-1 assume !(1 == ~E_5~0); 13500#L1322-1 assume !(1 == ~E_6~0); 13204#L1327-1 assume !(1 == ~E_7~0); 13205#L1332-1 assume !(1 == ~E_8~0); 13779#L1337-1 assume !(1 == ~E_9~0); 13713#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 13714#L1347-1 assume !(1 == ~E_11~0); 14079#L1352-1 assume { :end_inline_reset_delta_events } true; 13974#L1678-2 [2024-11-13 15:57:38,964 INFO L747 eck$LassoCheckResult]: Loop: 13974#L1678-2 assume !false; 13769#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13770#L1084-1 assume !false; 13566#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13567#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12841#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 14065#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12760#L925 assume !(0 != eval_~tmp~0#1); 12762#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13253#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13254#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12733#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12734#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13822#L1119-3 assume !(0 == ~T3_E~0); 13823#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13847#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13848#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14017#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14068#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13244#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13245#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13506#L1159-3 assume !(0 == ~T11_E~0); 13507#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13762#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13763#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13810#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13811#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13956#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13652#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13000#L1199-3 assume !(0 == ~E_7~0); 13001#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13226#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12686#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12687#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13407#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13408#L544-39 assume 1 == ~m_pc~0; 13755#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12672#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13730#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13078#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 13079#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13943#L563-39 assume !(1 == ~t1_pc~0); 12819#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 12820#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14228#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14229#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14232#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14051#L582-39 assume 1 == ~t2_pc~0; 13140#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13142#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13476#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13477#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12911#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12695#L601-39 assume 1 == ~t3_pc~0; 12696#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12744#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13910#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14239#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13947#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13620#L620-39 assume !(1 == ~t4_pc~0); 13621#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 13808#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13643#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13644#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13920#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14243#L639-39 assume 1 == ~t5_pc~0; 14034#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13366#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13367#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12722#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12723#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13655#L658-39 assume 1 == ~t6_pc~0; 13638#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13639#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14095#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13831#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13805#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13806#L677-39 assume !(1 == ~t7_pc~0); 13448#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 12898#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12899#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12956#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 12957#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13545#L696-39 assume 1 == ~t8_pc~0; 13514#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13389#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13390#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13680#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13648#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13526#L715-39 assume 1 == ~t9_pc~0; 12698#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12699#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12775#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12776#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13853#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13854#L734-39 assume 1 == ~t10_pc~0; 13783#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13216#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13551#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12854#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12855#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14109#L753-39 assume !(1 == ~t11_pc~0); 12773#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 12774#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13677#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13519#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13520#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13611#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13612#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13874#L1242-3 assume !(1 == ~T2_E~0); 13875#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14089#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13798#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13799#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14062#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14112#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14215#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12926#L1282-3 assume !(1 == ~T10_E~0); 12927#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12837#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12838#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13983#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13984#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14167#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14240#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13894#L1322-3 assume !(1 == ~E_6~0); 13895#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12893#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12870#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12871#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13586#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13706#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13707#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12814#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13023#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 13024#L1697 assume !(0 == start_simulation_~tmp~3#1); 13605#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13606#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12944#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12712#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 12713#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13674#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13675#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 13973#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 13974#L1678-2 [2024-11-13 15:57:38,964 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:38,964 INFO L85 PathProgramCache]: Analyzing trace with hash -1621157378, now seen corresponding path program 1 times [2024-11-13 15:57:38,964 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:38,964 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [906653401] [2024-11-13 15:57:38,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:38,965 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:38,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:39,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:39,057 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:39,057 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [906653401] [2024-11-13 15:57:39,057 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [906653401] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:39,057 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:39,058 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:39,058 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1684670273] [2024-11-13 15:57:39,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:39,058 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:39,058 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:39,059 INFO L85 PathProgramCache]: Analyzing trace with hash 1364938220, now seen corresponding path program 1 times [2024-11-13 15:57:39,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:39,060 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1906794364] [2024-11-13 15:57:39,060 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:39,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:39,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:39,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:39,171 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:39,171 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1906794364] [2024-11-13 15:57:39,171 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1906794364] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:39,171 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:39,171 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:39,171 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1861845839] [2024-11-13 15:57:39,171 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:39,172 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:39,172 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:39,172 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:39,172 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:39,172 INFO L87 Difference]: Start difference. First operand 1578 states and 2334 transitions. cyclomatic complexity: 757 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:39,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:39,213 INFO L93 Difference]: Finished difference Result 1578 states and 2333 transitions. [2024-11-13 15:57:39,213 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2333 transitions. [2024-11-13 15:57:39,223 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:39,230 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2333 transitions. [2024-11-13 15:57:39,230 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-13 15:57:39,232 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-13 15:57:39,232 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2333 transitions. [2024-11-13 15:57:39,235 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:39,235 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2333 transitions. [2024-11-13 15:57:39,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2333 transitions. [2024-11-13 15:57:39,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-13 15:57:39,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4784537389100127) internal successors, (2333), 1577 states have internal predecessors, (2333), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:39,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2333 transitions. [2024-11-13 15:57:39,265 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2333 transitions. [2024-11-13 15:57:39,265 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:39,268 INFO L424 stractBuchiCegarLoop]: Abstraction has 1578 states and 2333 transitions. [2024-11-13 15:57:39,269 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 15:57:39,269 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2333 transitions. [2024-11-13 15:57:39,279 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:39,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:39,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:39,281 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:39,281 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:39,282 INFO L745 eck$LassoCheckResult]: Stem: 16085#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 16086#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 16866#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16867#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16059#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 16060#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17300#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17269#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17270#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16418#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16419#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16834#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17236#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16322#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16323#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16213#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16214#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17167#L1109 assume !(0 == ~M_E~0); 17184#L1109-2 assume !(0 == ~T1_E~0); 16222#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16223#L1119-1 assume !(0 == ~T3_E~0); 17239#L1124-1 assume !(0 == ~T4_E~0); 15873#L1129-1 assume !(0 == ~T5_E~0); 15874#L1134-1 assume !(0 == ~T6_E~0); 16505#L1139-1 assume !(0 == ~T7_E~0); 17175#L1144-1 assume !(0 == ~T8_E~0); 17045#L1149-1 assume !(0 == ~T9_E~0); 15984#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15985#L1159-1 assume !(0 == ~T11_E~0); 17035#L1164-1 assume !(0 == ~E_M~0); 16380#L1169-1 assume !(0 == ~E_1~0); 16274#L1174-1 assume !(0 == ~E_2~0); 16138#L1179-1 assume !(0 == ~E_3~0); 16065#L1184-1 assume !(0 == ~E_4~0); 16066#L1189-1 assume !(0 == ~E_5~0); 16098#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 16181#L1199-1 assume !(0 == ~E_7~0); 17054#L1204-1 assume !(0 == ~E_8~0); 16995#L1209-1 assume !(0 == ~E_9~0); 16996#L1214-1 assume !(0 == ~E_10~0); 17313#L1219-1 assume !(0 == ~E_11~0); 17400#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16397#L544 assume 1 == ~m_pc~0; 16398#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17223#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16753#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16027#L1379 assume !(0 != activate_threads_~tmp~1#1); 16028#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16821#L563 assume !(1 == ~t1_pc~0); 16627#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15883#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15884#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16943#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 15879#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15880#L582 assume 1 == ~t2_pc~0; 16605#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16948#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16218#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16219#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 15912#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15913#L601 assume !(1 == ~t3_pc~0); 16622#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16621#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17075#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16980#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 16981#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16929#L620 assume 1 == ~t4_pc~0; 15893#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15894#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15926#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15927#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 16831#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17013#L639 assume 1 == ~t5_pc~0; 16903#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16186#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16187#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16851#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 16852#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16786#L658 assume !(1 == ~t6_pc~0); 16394#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16395#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16210#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16211#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16984#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16233#L677 assume 1 == ~t7_pc~0; 16234#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16131#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17141#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17262#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 17263#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17333#L696 assume !(1 == ~t8_pc~0); 16458#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16459#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17298#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17336#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 17381#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16890#L715 assume 1 == ~t9_pc~0; 16891#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16558#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16272#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16273#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 16873#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17136#L734 assume !(1 == ~t10_pc~0); 17137#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16350#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16351#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17079#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 17080#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16432#L753 assume 1 == ~t11_pc~0; 16433#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16989#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17307#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16708#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 16709#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16760#L1237 assume !(1 == ~M_E~0); 16761#L1237-2 assume !(1 == ~T1_E~0); 17364#L1242-1 assume !(1 == ~T2_E~0); 16526#L1247-1 assume !(1 == ~T3_E~0); 16527#L1252-1 assume !(1 == ~T4_E~0); 16291#L1257-1 assume !(1 == ~T5_E~0); 16292#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17156#L1267-1 assume !(1 == ~T7_E~0); 17254#L1272-1 assume !(1 == ~T8_E~0); 16616#L1277-1 assume !(1 == ~T9_E~0); 16617#L1282-1 assume !(1 == ~T10_E~0); 17022#L1287-1 assume !(1 == ~T11_E~0); 17023#L1292-1 assume !(1 == ~E_M~0); 16983#L1297-1 assume !(1 == ~E_1~0); 16423#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 16424#L1307-1 assume !(1 == ~E_3~0); 17243#L1312-1 assume !(1 == ~E_4~0); 16662#L1317-1 assume !(1 == ~E_5~0); 16663#L1322-1 assume !(1 == ~E_6~0); 16367#L1327-1 assume !(1 == ~E_7~0); 16368#L1332-1 assume !(1 == ~E_8~0); 16942#L1337-1 assume !(1 == ~E_9~0); 16876#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 16877#L1347-1 assume !(1 == ~E_11~0); 17242#L1352-1 assume { :end_inline_reset_delta_events } true; 17140#L1678-2 [2024-11-13 15:57:39,283 INFO L747 eck$LassoCheckResult]: Loop: 17140#L1678-2 assume !false; 16932#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16933#L1084-1 assume !false; 16729#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16730#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 16004#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 17228#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15923#L925 assume !(0 != eval_~tmp~0#1); 15925#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16416#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16417#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15896#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15897#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16985#L1119-3 assume !(0 == ~T3_E~0); 16986#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17010#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17011#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17180#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17231#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16407#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16408#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16669#L1159-3 assume !(0 == ~T11_E~0); 16670#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16925#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16926#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16973#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16974#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17119#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16815#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16160#L1199-3 assume !(0 == ~E_7~0); 16161#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16387#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15846#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15847#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16570#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16571#L544-39 assume 1 == ~m_pc~0; 16917#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15835#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16893#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16241#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 16242#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17106#L563-39 assume 1 == ~t1_pc~0; 17112#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15980#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17391#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17392#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17395#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17214#L582-39 assume !(1 == ~t2_pc~0); 16304#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 16305#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16639#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16640#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16074#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15858#L601-39 assume 1 == ~t3_pc~0; 15859#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15907#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17073#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17402#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17110#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16781#L620-39 assume !(1 == ~t4_pc~0); 16782#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 16971#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16806#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16807#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17083#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17406#L639-39 assume 1 == ~t5_pc~0; 17197#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16529#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16530#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15885#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15886#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16818#L658-39 assume 1 == ~t6_pc~0; 16801#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16802#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17258#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16994#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16968#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16969#L677-39 assume !(1 == ~t7_pc~0); 16614#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 16063#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16064#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16119#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 16120#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16711#L696-39 assume 1 == ~t8_pc~0; 16677#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16552#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16553#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16843#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16811#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16691#L715-39 assume 1 == ~t9_pc~0; 15863#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15864#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15940#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15941#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17016#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17017#L734-39 assume 1 == ~t10_pc~0; 16946#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16379#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16714#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16017#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16018#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17272#L753-39 assume !(1 == ~t11_pc~0); 15936#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 15937#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16840#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16682#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16683#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16778#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16779#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17037#L1242-3 assume !(1 == ~T2_E~0); 17038#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17253#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16961#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16962#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17226#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17275#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17378#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16090#L1282-3 assume !(1 == ~T10_E~0); 16091#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16000#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16001#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17149#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17150#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17330#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17403#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17057#L1322-3 assume !(1 == ~E_6~0); 17058#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16056#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16033#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16034#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16749#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16871#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16872#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15982#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16188#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 16189#L1697 assume !(0 == start_simulation_~tmp~3#1); 16768#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16769#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 16107#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15875#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 15876#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16837#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16838#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 17139#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 17140#L1678-2 [2024-11-13 15:57:39,284 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:39,284 INFO L85 PathProgramCache]: Analyzing trace with hash -1076284804, now seen corresponding path program 1 times [2024-11-13 15:57:39,284 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:39,284 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [357190426] [2024-11-13 15:57:39,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:39,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:39,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:39,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:39,387 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:39,387 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [357190426] [2024-11-13 15:57:39,387 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [357190426] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:39,387 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:39,388 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:39,389 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [614825516] [2024-11-13 15:57:39,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:39,389 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:39,389 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:39,390 INFO L85 PathProgramCache]: Analyzing trace with hash 1483113132, now seen corresponding path program 1 times [2024-11-13 15:57:39,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:39,390 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [258819764] [2024-11-13 15:57:39,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:39,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:39,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:39,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:39,484 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:39,484 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [258819764] [2024-11-13 15:57:39,484 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [258819764] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:39,484 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:39,484 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:39,485 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1461507295] [2024-11-13 15:57:39,485 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:39,485 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:39,486 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:39,486 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:39,486 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:39,486 INFO L87 Difference]: Start difference. First operand 1578 states and 2333 transitions. cyclomatic complexity: 756 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:39,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:39,526 INFO L93 Difference]: Finished difference Result 1578 states and 2332 transitions. [2024-11-13 15:57:39,526 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2332 transitions. [2024-11-13 15:57:39,536 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:39,543 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2332 transitions. [2024-11-13 15:57:39,544 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-13 15:57:39,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-13 15:57:39,545 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2332 transitions. [2024-11-13 15:57:39,548 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:39,548 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2332 transitions. [2024-11-13 15:57:39,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2332 transitions. [2024-11-13 15:57:39,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-13 15:57:39,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4778200253485425) internal successors, (2332), 1577 states have internal predecessors, (2332), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:39,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2332 transitions. [2024-11-13 15:57:39,580 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2332 transitions. [2024-11-13 15:57:39,584 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:39,584 INFO L424 stractBuchiCegarLoop]: Abstraction has 1578 states and 2332 transitions. [2024-11-13 15:57:39,584 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 15:57:39,585 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2332 transitions. [2024-11-13 15:57:39,594 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:39,594 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:39,594 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:39,596 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:39,599 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:39,599 INFO L745 eck$LassoCheckResult]: Stem: 19248#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 19249#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 20029#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20030#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19222#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 19223#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20463#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20432#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20433#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19581#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19582#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19997#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20399#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19485#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19486#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19376#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19377#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20330#L1109 assume !(0 == ~M_E~0); 20347#L1109-2 assume !(0 == ~T1_E~0); 19385#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19386#L1119-1 assume !(0 == ~T3_E~0); 20402#L1124-1 assume !(0 == ~T4_E~0); 19036#L1129-1 assume !(0 == ~T5_E~0); 19037#L1134-1 assume !(0 == ~T6_E~0); 19668#L1139-1 assume !(0 == ~T7_E~0); 20338#L1144-1 assume !(0 == ~T8_E~0); 20208#L1149-1 assume !(0 == ~T9_E~0); 19147#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19148#L1159-1 assume !(0 == ~T11_E~0); 20198#L1164-1 assume !(0 == ~E_M~0); 19543#L1169-1 assume !(0 == ~E_1~0); 19437#L1174-1 assume !(0 == ~E_2~0); 19301#L1179-1 assume !(0 == ~E_3~0); 19228#L1184-1 assume !(0 == ~E_4~0); 19229#L1189-1 assume !(0 == ~E_5~0); 19261#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 19344#L1199-1 assume !(0 == ~E_7~0); 20217#L1204-1 assume !(0 == ~E_8~0); 20158#L1209-1 assume !(0 == ~E_9~0); 20159#L1214-1 assume !(0 == ~E_10~0); 20476#L1219-1 assume !(0 == ~E_11~0); 20563#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19560#L544 assume 1 == ~m_pc~0; 19561#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20386#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19916#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19190#L1379 assume !(0 != activate_threads_~tmp~1#1); 19191#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19984#L563 assume !(1 == ~t1_pc~0); 19790#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19046#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19047#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20106#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 19042#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19043#L582 assume 1 == ~t2_pc~0; 19768#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20111#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19381#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19382#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 19075#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19076#L601 assume !(1 == ~t3_pc~0); 19785#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19784#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20238#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20143#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 20144#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20092#L620 assume 1 == ~t4_pc~0; 19056#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19057#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19089#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19090#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 19994#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20176#L639 assume 1 == ~t5_pc~0; 20066#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19349#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19350#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20014#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 20015#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19949#L658 assume !(1 == ~t6_pc~0); 19557#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19558#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19373#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19374#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20147#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19396#L677 assume 1 == ~t7_pc~0; 19397#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19294#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20304#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20425#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 20426#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20496#L696 assume !(1 == ~t8_pc~0); 19621#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19622#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20461#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20499#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 20544#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20053#L715 assume 1 == ~t9_pc~0; 20054#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19721#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19435#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19436#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 20036#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20299#L734 assume !(1 == ~t10_pc~0); 20300#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19513#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19514#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20242#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 20243#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19595#L753 assume 1 == ~t11_pc~0; 19596#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20152#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20470#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19871#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 19872#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19923#L1237 assume !(1 == ~M_E~0); 19924#L1237-2 assume !(1 == ~T1_E~0); 20527#L1242-1 assume !(1 == ~T2_E~0); 19689#L1247-1 assume !(1 == ~T3_E~0); 19690#L1252-1 assume !(1 == ~T4_E~0); 19454#L1257-1 assume !(1 == ~T5_E~0); 19455#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20319#L1267-1 assume !(1 == ~T7_E~0); 20417#L1272-1 assume !(1 == ~T8_E~0); 19779#L1277-1 assume !(1 == ~T9_E~0); 19780#L1282-1 assume !(1 == ~T10_E~0); 20185#L1287-1 assume !(1 == ~T11_E~0); 20186#L1292-1 assume !(1 == ~E_M~0); 20146#L1297-1 assume !(1 == ~E_1~0); 19586#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 19587#L1307-1 assume !(1 == ~E_3~0); 20406#L1312-1 assume !(1 == ~E_4~0); 19825#L1317-1 assume !(1 == ~E_5~0); 19826#L1322-1 assume !(1 == ~E_6~0); 19530#L1327-1 assume !(1 == ~E_7~0); 19531#L1332-1 assume !(1 == ~E_8~0); 20105#L1337-1 assume !(1 == ~E_9~0); 20039#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 20040#L1347-1 assume !(1 == ~E_11~0); 20405#L1352-1 assume { :end_inline_reset_delta_events } true; 20303#L1678-2 [2024-11-13 15:57:39,599 INFO L747 eck$LassoCheckResult]: Loop: 20303#L1678-2 assume !false; 20095#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20096#L1084-1 assume !false; 19892#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19893#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19167#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 20391#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19086#L925 assume !(0 != eval_~tmp~0#1); 19088#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19579#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19580#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19059#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19060#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20148#L1119-3 assume !(0 == ~T3_E~0); 20149#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20173#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20174#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20343#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20394#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19570#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19571#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19832#L1159-3 assume !(0 == ~T11_E~0); 19833#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20088#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20089#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20136#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20137#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20282#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19978#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19323#L1199-3 assume !(0 == ~E_7~0); 19324#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19550#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19009#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19010#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19733#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19734#L544-39 assume 1 == ~m_pc~0; 20080#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18998#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20056#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19404#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 19405#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20269#L563-39 assume 1 == ~t1_pc~0; 20275#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19143#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20554#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20555#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20558#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20377#L582-39 assume 1 == ~t2_pc~0; 19466#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19468#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19802#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19803#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19237#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19021#L601-39 assume 1 == ~t3_pc~0; 19022#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19070#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20236#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20565#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20273#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19944#L620-39 assume !(1 == ~t4_pc~0); 19945#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 20134#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19969#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19970#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20246#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20569#L639-39 assume 1 == ~t5_pc~0; 20360#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19692#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19693#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19048#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19049#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19981#L658-39 assume 1 == ~t6_pc~0; 19964#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19965#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20421#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20157#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20131#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20132#L677-39 assume !(1 == ~t7_pc~0); 19777#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 19226#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19227#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19282#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 19283#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19874#L696-39 assume 1 == ~t8_pc~0; 19840#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19715#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19716#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20006#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19974#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19854#L715-39 assume 1 == ~t9_pc~0; 19026#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19027#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19103#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19104#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20179#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20180#L734-39 assume !(1 == ~t10_pc~0); 19541#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 19542#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19877#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19180#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19181#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20435#L753-39 assume !(1 == ~t11_pc~0); 19099#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 19100#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20003#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19845#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19846#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19941#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19942#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20200#L1242-3 assume !(1 == ~T2_E~0); 20201#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20416#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20124#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20125#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20389#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20438#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20541#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19253#L1282-3 assume !(1 == ~T10_E~0); 19254#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 19163#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19164#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20312#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20313#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20493#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20566#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20220#L1322-3 assume !(1 == ~E_6~0); 20221#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19219#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19196#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19197#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19912#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20034#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 20035#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19145#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19351#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 19352#L1697 assume !(0 == start_simulation_~tmp~3#1); 19931#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19932#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19270#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19038#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 19039#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20000#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20001#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 20302#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 20303#L1678-2 [2024-11-13 15:57:39,600 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:39,600 INFO L85 PathProgramCache]: Analyzing trace with hash -1751444930, now seen corresponding path program 1 times [2024-11-13 15:57:39,600 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:39,600 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1470844014] [2024-11-13 15:57:39,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:39,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:39,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:39,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:39,672 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:39,672 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1470844014] [2024-11-13 15:57:39,672 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1470844014] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:39,672 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:39,672 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:39,673 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1483894029] [2024-11-13 15:57:39,673 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:39,673 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:39,674 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:39,674 INFO L85 PathProgramCache]: Analyzing trace with hash 517761196, now seen corresponding path program 1 times [2024-11-13 15:57:39,674 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:39,674 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1025137388] [2024-11-13 15:57:39,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:39,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:39,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:39,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:39,757 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:39,757 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1025137388] [2024-11-13 15:57:39,757 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1025137388] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:39,757 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:39,757 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:39,757 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1792456543] [2024-11-13 15:57:39,757 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:39,758 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:39,758 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:39,758 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:39,758 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:39,758 INFO L87 Difference]: Start difference. First operand 1578 states and 2332 transitions. cyclomatic complexity: 755 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:39,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:39,798 INFO L93 Difference]: Finished difference Result 1578 states and 2331 transitions. [2024-11-13 15:57:39,798 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2331 transitions. [2024-11-13 15:57:39,807 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:39,814 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2331 transitions. [2024-11-13 15:57:39,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-13 15:57:39,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-13 15:57:39,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2331 transitions. [2024-11-13 15:57:39,819 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:39,819 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2331 transitions. [2024-11-13 15:57:39,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2331 transitions. [2024-11-13 15:57:39,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-13 15:57:39,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4771863117870723) internal successors, (2331), 1577 states have internal predecessors, (2331), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:39,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2331 transitions. [2024-11-13 15:57:39,851 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2331 transitions. [2024-11-13 15:57:39,852 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:39,854 INFO L424 stractBuchiCegarLoop]: Abstraction has 1578 states and 2331 transitions. [2024-11-13 15:57:39,854 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 15:57:39,854 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2331 transitions. [2024-11-13 15:57:39,861 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:39,861 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:39,861 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:39,863 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:39,863 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:39,864 INFO L745 eck$LassoCheckResult]: Stem: 22411#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 22412#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 23192#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23193#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22385#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 22386#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23626#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23595#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23596#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22744#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22745#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23160#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23562#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22648#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22649#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22539#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22540#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23493#L1109 assume !(0 == ~M_E~0); 23510#L1109-2 assume !(0 == ~T1_E~0); 22548#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22549#L1119-1 assume !(0 == ~T3_E~0); 23565#L1124-1 assume !(0 == ~T4_E~0); 22199#L1129-1 assume !(0 == ~T5_E~0); 22200#L1134-1 assume !(0 == ~T6_E~0); 22831#L1139-1 assume !(0 == ~T7_E~0); 23501#L1144-1 assume !(0 == ~T8_E~0); 23371#L1149-1 assume !(0 == ~T9_E~0); 22310#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22311#L1159-1 assume !(0 == ~T11_E~0); 23361#L1164-1 assume !(0 == ~E_M~0); 22706#L1169-1 assume !(0 == ~E_1~0); 22600#L1174-1 assume !(0 == ~E_2~0); 22464#L1179-1 assume !(0 == ~E_3~0); 22391#L1184-1 assume !(0 == ~E_4~0); 22392#L1189-1 assume !(0 == ~E_5~0); 22424#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 22507#L1199-1 assume !(0 == ~E_7~0); 23380#L1204-1 assume !(0 == ~E_8~0); 23321#L1209-1 assume !(0 == ~E_9~0); 23322#L1214-1 assume !(0 == ~E_10~0); 23639#L1219-1 assume !(0 == ~E_11~0); 23726#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22723#L544 assume 1 == ~m_pc~0; 22724#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23549#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23079#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22353#L1379 assume !(0 != activate_threads_~tmp~1#1); 22354#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23147#L563 assume !(1 == ~t1_pc~0); 22953#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22209#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22210#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23269#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 22205#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22206#L582 assume 1 == ~t2_pc~0; 22931#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23274#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22544#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22545#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 22238#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22239#L601 assume !(1 == ~t3_pc~0); 22948#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22947#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23401#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23306#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 23307#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23255#L620 assume 1 == ~t4_pc~0; 22219#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22220#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22252#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22253#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 23157#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23339#L639 assume 1 == ~t5_pc~0; 23229#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22512#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22513#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23177#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 23178#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23112#L658 assume !(1 == ~t6_pc~0); 22720#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22721#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22536#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22537#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23310#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22559#L677 assume 1 == ~t7_pc~0; 22560#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22457#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23467#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23588#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 23589#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23659#L696 assume !(1 == ~t8_pc~0); 22784#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22785#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23624#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23662#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 23707#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23216#L715 assume 1 == ~t9_pc~0; 23217#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22884#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22598#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22599#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 23199#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23462#L734 assume !(1 == ~t10_pc~0); 23463#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22676#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22677#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23405#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 23406#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22758#L753 assume 1 == ~t11_pc~0; 22759#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23315#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23633#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23034#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 23035#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23086#L1237 assume !(1 == ~M_E~0); 23087#L1237-2 assume !(1 == ~T1_E~0); 23690#L1242-1 assume !(1 == ~T2_E~0); 22852#L1247-1 assume !(1 == ~T3_E~0); 22853#L1252-1 assume !(1 == ~T4_E~0); 22617#L1257-1 assume !(1 == ~T5_E~0); 22618#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23482#L1267-1 assume !(1 == ~T7_E~0); 23580#L1272-1 assume !(1 == ~T8_E~0); 22942#L1277-1 assume !(1 == ~T9_E~0); 22943#L1282-1 assume !(1 == ~T10_E~0); 23348#L1287-1 assume !(1 == ~T11_E~0); 23349#L1292-1 assume !(1 == ~E_M~0); 23309#L1297-1 assume !(1 == ~E_1~0); 22749#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22750#L1307-1 assume !(1 == ~E_3~0); 23569#L1312-1 assume !(1 == ~E_4~0); 22988#L1317-1 assume !(1 == ~E_5~0); 22989#L1322-1 assume !(1 == ~E_6~0); 22693#L1327-1 assume !(1 == ~E_7~0); 22694#L1332-1 assume !(1 == ~E_8~0); 23268#L1337-1 assume !(1 == ~E_9~0); 23202#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 23203#L1347-1 assume !(1 == ~E_11~0); 23568#L1352-1 assume { :end_inline_reset_delta_events } true; 23466#L1678-2 [2024-11-13 15:57:39,865 INFO L747 eck$LassoCheckResult]: Loop: 23466#L1678-2 assume !false; 23258#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23259#L1084-1 assume !false; 23055#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 23056#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22330#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23554#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22249#L925 assume !(0 != eval_~tmp~0#1); 22251#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22742#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22743#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22222#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22223#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23311#L1119-3 assume !(0 == ~T3_E~0); 23312#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23336#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23337#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23506#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23557#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22733#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22734#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22995#L1159-3 assume !(0 == ~T11_E~0); 22996#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23251#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23252#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23299#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23300#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23445#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23141#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22486#L1199-3 assume !(0 == ~E_7~0); 22487#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22713#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22172#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22173#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22896#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22897#L544-39 assume !(1 == ~m_pc~0); 22160#L544-41 is_master_triggered_~__retres1~0#1 := 0; 22161#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23219#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22567#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 22568#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23432#L563-39 assume !(1 == ~t1_pc~0); 22305#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 22306#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23717#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23718#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23721#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23540#L582-39 assume 1 == ~t2_pc~0; 22629#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22631#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22965#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22966#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22400#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22184#L601-39 assume 1 == ~t3_pc~0; 22185#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22233#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23399#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23728#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23436#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23107#L620-39 assume !(1 == ~t4_pc~0); 23108#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 23297#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23132#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23133#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23409#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23732#L639-39 assume 1 == ~t5_pc~0; 23523#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22855#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22856#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22211#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22212#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23144#L658-39 assume 1 == ~t6_pc~0; 23127#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23128#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23584#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23320#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23294#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23295#L677-39 assume !(1 == ~t7_pc~0); 22940#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 22389#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22390#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22445#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 22446#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23037#L696-39 assume 1 == ~t8_pc~0; 23003#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22878#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22879#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23169#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 23137#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23017#L715-39 assume 1 == ~t9_pc~0; 22189#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22190#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22266#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22267#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 23342#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23343#L734-39 assume !(1 == ~t10_pc~0); 22704#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 22705#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23040#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22343#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22344#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23598#L753-39 assume !(1 == ~t11_pc~0); 22262#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 22263#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23166#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23008#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23009#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23104#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 23105#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23363#L1242-3 assume !(1 == ~T2_E~0); 23364#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23579#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23287#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23288#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23552#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23601#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23704#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22416#L1282-3 assume !(1 == ~T10_E~0); 22417#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22326#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22327#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23475#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23476#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23656#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23729#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23383#L1322-3 assume !(1 == ~E_6~0); 23384#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22382#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22359#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22360#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23075#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 23197#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 23198#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22308#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22514#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 22515#L1697 assume !(0 == start_simulation_~tmp~3#1); 23094#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 23095#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22433#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22201#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 22202#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23163#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23164#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 23465#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 23466#L1678-2 [2024-11-13 15:57:39,865 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:39,865 INFO L85 PathProgramCache]: Analyzing trace with hash -803392964, now seen corresponding path program 1 times [2024-11-13 15:57:39,866 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:39,866 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2020160692] [2024-11-13 15:57:39,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:39,866 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:39,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:39,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:39,968 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:39,968 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2020160692] [2024-11-13 15:57:39,968 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2020160692] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:39,968 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:39,968 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:39,968 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1559942731] [2024-11-13 15:57:39,968 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:39,969 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:39,969 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:39,969 INFO L85 PathProgramCache]: Analyzing trace with hash 1868533998, now seen corresponding path program 1 times [2024-11-13 15:57:39,969 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:39,969 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [313935013] [2024-11-13 15:57:39,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:39,969 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:39,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:40,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:40,057 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:40,057 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [313935013] [2024-11-13 15:57:40,057 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [313935013] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:40,057 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:40,057 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:40,057 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1161120273] [2024-11-13 15:57:40,057 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:40,058 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:40,058 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:40,058 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:40,058 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:40,058 INFO L87 Difference]: Start difference. First operand 1578 states and 2331 transitions. cyclomatic complexity: 754 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:40,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:40,099 INFO L93 Difference]: Finished difference Result 1578 states and 2330 transitions. [2024-11-13 15:57:40,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2330 transitions. [2024-11-13 15:57:40,108 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:40,115 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2330 transitions. [2024-11-13 15:57:40,115 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-13 15:57:40,117 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-13 15:57:40,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2330 transitions. [2024-11-13 15:57:40,120 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:40,120 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2330 transitions. [2024-11-13 15:57:40,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2330 transitions. [2024-11-13 15:57:40,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-13 15:57:40,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.476552598225602) internal successors, (2330), 1577 states have internal predecessors, (2330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:40,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2330 transitions. [2024-11-13 15:57:40,151 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2330 transitions. [2024-11-13 15:57:40,152 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:40,152 INFO L424 stractBuchiCegarLoop]: Abstraction has 1578 states and 2330 transitions. [2024-11-13 15:57:40,152 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 15:57:40,152 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2330 transitions. [2024-11-13 15:57:40,160 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:40,161 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:40,161 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:40,163 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:40,164 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:40,164 INFO L745 eck$LassoCheckResult]: Stem: 25574#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 25575#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 26355#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26356#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25548#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 25549#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26789#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26758#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26759#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25907#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25908#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26323#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26725#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25811#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25812#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25702#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25703#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26656#L1109 assume !(0 == ~M_E~0); 26673#L1109-2 assume !(0 == ~T1_E~0); 25711#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25712#L1119-1 assume !(0 == ~T3_E~0); 26728#L1124-1 assume !(0 == ~T4_E~0); 25362#L1129-1 assume !(0 == ~T5_E~0); 25363#L1134-1 assume !(0 == ~T6_E~0); 25994#L1139-1 assume !(0 == ~T7_E~0); 26664#L1144-1 assume !(0 == ~T8_E~0); 26534#L1149-1 assume !(0 == ~T9_E~0); 25475#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25476#L1159-1 assume !(0 == ~T11_E~0); 26524#L1164-1 assume !(0 == ~E_M~0); 25869#L1169-1 assume !(0 == ~E_1~0); 25763#L1174-1 assume !(0 == ~E_2~0); 25629#L1179-1 assume !(0 == ~E_3~0); 25554#L1184-1 assume !(0 == ~E_4~0); 25555#L1189-1 assume !(0 == ~E_5~0); 25587#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 25672#L1199-1 assume !(0 == ~E_7~0); 26543#L1204-1 assume !(0 == ~E_8~0); 26484#L1209-1 assume !(0 == ~E_9~0); 26485#L1214-1 assume !(0 == ~E_10~0); 26802#L1219-1 assume !(0 == ~E_11~0); 26889#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25886#L544 assume 1 == ~m_pc~0; 25887#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26712#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26242#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25516#L1379 assume !(0 != activate_threads_~tmp~1#1); 25517#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26312#L563 assume !(1 == ~t1_pc~0); 26116#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25372#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25373#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26432#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 25368#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25369#L582 assume 1 == ~t2_pc~0; 26094#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26437#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25707#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25708#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 25401#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25402#L601 assume !(1 == ~t3_pc~0); 26111#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26110#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26564#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26469#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 26470#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26418#L620 assume 1 == ~t4_pc~0; 25382#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25383#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25415#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25416#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 26320#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26503#L639 assume 1 == ~t5_pc~0; 26392#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25677#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25678#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26340#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 26341#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26275#L658 assume !(1 == ~t6_pc~0); 25883#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25884#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25699#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25700#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26473#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25724#L677 assume 1 == ~t7_pc~0; 25725#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25623#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26630#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26751#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 26752#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26822#L696 assume !(1 == ~t8_pc~0); 25948#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25949#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26787#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26825#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 26870#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26379#L715 assume 1 == ~t9_pc~0; 26380#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26047#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25761#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25762#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 26362#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26627#L734 assume !(1 == ~t10_pc~0); 26628#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25839#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25840#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26568#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 26569#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25921#L753 assume 1 == ~t11_pc~0; 25922#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26478#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26796#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26199#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 26200#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26251#L1237 assume !(1 == ~M_E~0); 26252#L1237-2 assume !(1 == ~T1_E~0); 26854#L1242-1 assume !(1 == ~T2_E~0); 26015#L1247-1 assume !(1 == ~T3_E~0); 26016#L1252-1 assume !(1 == ~T4_E~0); 25780#L1257-1 assume !(1 == ~T5_E~0); 25781#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26645#L1267-1 assume !(1 == ~T7_E~0); 26743#L1272-1 assume !(1 == ~T8_E~0); 26105#L1277-1 assume !(1 == ~T9_E~0); 26106#L1282-1 assume !(1 == ~T10_E~0); 26511#L1287-1 assume !(1 == ~T11_E~0); 26512#L1292-1 assume !(1 == ~E_M~0); 26472#L1297-1 assume !(1 == ~E_1~0); 25912#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25913#L1307-1 assume !(1 == ~E_3~0); 26732#L1312-1 assume !(1 == ~E_4~0); 26151#L1317-1 assume !(1 == ~E_5~0); 26152#L1322-1 assume !(1 == ~E_6~0); 25856#L1327-1 assume !(1 == ~E_7~0); 25857#L1332-1 assume !(1 == ~E_8~0); 26431#L1337-1 assume !(1 == ~E_9~0); 26365#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 26366#L1347-1 assume !(1 == ~E_11~0); 26731#L1352-1 assume { :end_inline_reset_delta_events } true; 26626#L1678-2 [2024-11-13 15:57:40,164 INFO L747 eck$LassoCheckResult]: Loop: 26626#L1678-2 assume !false; 26421#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26422#L1084-1 assume !false; 26218#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26219#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25493#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 26717#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25412#L925 assume !(0 != eval_~tmp~0#1); 25414#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25905#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25906#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25385#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25386#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26474#L1119-3 assume !(0 == ~T3_E~0); 26475#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26499#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26500#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26669#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26720#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25896#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25897#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26159#L1159-3 assume !(0 == ~T11_E~0); 26160#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26414#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26415#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26462#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26463#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26608#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26304#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25652#L1199-3 assume !(0 == ~E_7~0); 25653#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25880#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25338#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25339#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 26059#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26060#L544-39 assume 1 == ~m_pc~0; 26407#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25324#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26382#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25730#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 25731#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26595#L563-39 assume 1 == ~t1_pc~0; 26601#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25472#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26880#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26881#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26884#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26703#L582-39 assume 1 == ~t2_pc~0; 25792#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25794#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26128#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26129#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25565#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25347#L601-39 assume 1 == ~t3_pc~0; 25348#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25393#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26562#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26891#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26599#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26269#L620-39 assume !(1 == ~t4_pc~0); 26270#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 26460#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26295#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26296#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26572#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26894#L639-39 assume 1 == ~t5_pc~0; 26686#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26018#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26019#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25374#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25375#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26307#L658-39 assume 1 == ~t6_pc~0; 26290#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26291#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26747#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26483#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26457#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26458#L677-39 assume !(1 == ~t7_pc~0); 26101#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 25552#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25553#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25608#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 25609#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26198#L696-39 assume 1 == ~t8_pc~0; 26166#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26041#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26042#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26332#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26300#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26180#L715-39 assume 1 == ~t9_pc~0; 25350#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25351#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25429#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25430#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 26505#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26506#L734-39 assume 1 == ~t10_pc~0; 26435#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25868#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26203#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25506#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25507#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26761#L753-39 assume !(1 == ~t11_pc~0); 25425#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 25426#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26329#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26171#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 26172#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26263#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26264#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26526#L1242-3 assume !(1 == ~T2_E~0); 26527#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26742#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26450#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26451#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26714#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26764#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26867#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25579#L1282-3 assume !(1 == ~T10_E~0); 25580#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25489#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25490#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26638#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26639#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26819#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26892#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26546#L1322-3 assume !(1 == ~E_6~0); 26547#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25545#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25522#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25523#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26238#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 26360#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26361#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25466#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25675#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 25676#L1697 assume !(0 == start_simulation_~tmp~3#1); 26257#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26258#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25596#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25364#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 25365#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26326#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26327#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 26625#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 26626#L1678-2 [2024-11-13 15:57:40,164 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:40,165 INFO L85 PathProgramCache]: Analyzing trace with hash -218621314, now seen corresponding path program 1 times [2024-11-13 15:57:40,165 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:40,165 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2095843157] [2024-11-13 15:57:40,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:40,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:40,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:40,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:40,234 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:40,234 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2095843157] [2024-11-13 15:57:40,234 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2095843157] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:40,234 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:40,234 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:40,234 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1300844992] [2024-11-13 15:57:40,234 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:40,234 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:40,235 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:40,235 INFO L85 PathProgramCache]: Analyzing trace with hash -950442133, now seen corresponding path program 3 times [2024-11-13 15:57:40,235 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:40,235 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1705854542] [2024-11-13 15:57:40,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:40,235 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:40,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:40,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:40,314 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:40,314 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1705854542] [2024-11-13 15:57:40,314 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1705854542] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:40,314 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:40,314 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:40,314 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1932135946] [2024-11-13 15:57:40,314 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:40,315 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:40,315 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:40,315 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:40,315 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:40,315 INFO L87 Difference]: Start difference. First operand 1578 states and 2330 transitions. cyclomatic complexity: 753 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:40,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:40,358 INFO L93 Difference]: Finished difference Result 1578 states and 2329 transitions. [2024-11-13 15:57:40,358 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2329 transitions. [2024-11-13 15:57:40,367 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:40,374 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2329 transitions. [2024-11-13 15:57:40,374 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-13 15:57:40,376 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-13 15:57:40,376 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2329 transitions. [2024-11-13 15:57:40,379 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:40,379 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2329 transitions. [2024-11-13 15:57:40,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2329 transitions. [2024-11-13 15:57:40,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-13 15:57:40,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4759188846641318) internal successors, (2329), 1577 states have internal predecessors, (2329), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:40,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2329 transitions. [2024-11-13 15:57:40,409 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2329 transitions. [2024-11-13 15:57:40,409 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:40,410 INFO L424 stractBuchiCegarLoop]: Abstraction has 1578 states and 2329 transitions. [2024-11-13 15:57:40,410 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 15:57:40,410 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2329 transitions. [2024-11-13 15:57:40,417 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:40,417 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:40,417 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:40,419 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:40,419 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:40,420 INFO L745 eck$LassoCheckResult]: Stem: 28737#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 28738#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 29518#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29519#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28711#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 28712#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29952#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29921#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29922#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29070#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29071#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29486#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29888#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 28974#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28975#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28865#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28866#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29819#L1109 assume !(0 == ~M_E~0); 29836#L1109-2 assume !(0 == ~T1_E~0); 28874#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28875#L1119-1 assume !(0 == ~T3_E~0); 29891#L1124-1 assume !(0 == ~T4_E~0); 28525#L1129-1 assume !(0 == ~T5_E~0); 28526#L1134-1 assume !(0 == ~T6_E~0); 29157#L1139-1 assume !(0 == ~T7_E~0); 29827#L1144-1 assume !(0 == ~T8_E~0); 29697#L1149-1 assume !(0 == ~T9_E~0); 28636#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28637#L1159-1 assume !(0 == ~T11_E~0); 29687#L1164-1 assume !(0 == ~E_M~0); 29032#L1169-1 assume !(0 == ~E_1~0); 28926#L1174-1 assume !(0 == ~E_2~0); 28790#L1179-1 assume !(0 == ~E_3~0); 28717#L1184-1 assume !(0 == ~E_4~0); 28718#L1189-1 assume !(0 == ~E_5~0); 28750#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 28833#L1199-1 assume !(0 == ~E_7~0); 29706#L1204-1 assume !(0 == ~E_8~0); 29647#L1209-1 assume !(0 == ~E_9~0); 29648#L1214-1 assume !(0 == ~E_10~0); 29965#L1219-1 assume !(0 == ~E_11~0); 30052#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29049#L544 assume 1 == ~m_pc~0; 29050#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29875#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29405#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28679#L1379 assume !(0 != activate_threads_~tmp~1#1); 28680#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29473#L563 assume !(1 == ~t1_pc~0); 29279#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28535#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28536#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29595#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 28531#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28532#L582 assume 1 == ~t2_pc~0; 29257#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29600#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28870#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28871#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 28564#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28565#L601 assume !(1 == ~t3_pc~0); 29274#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29273#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29727#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29632#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 29633#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29581#L620 assume 1 == ~t4_pc~0; 28545#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28546#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28578#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28579#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 29483#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29665#L639 assume 1 == ~t5_pc~0; 29555#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28838#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28839#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29503#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 29504#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29438#L658 assume !(1 == ~t6_pc~0); 29046#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29047#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28862#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28863#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29636#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28885#L677 assume 1 == ~t7_pc~0; 28886#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28783#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29793#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29914#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 29915#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29985#L696 assume !(1 == ~t8_pc~0); 29110#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29111#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29950#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29988#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 30033#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29542#L715 assume 1 == ~t9_pc~0; 29543#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29210#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28924#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28925#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 29525#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29788#L734 assume !(1 == ~t10_pc~0); 29789#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29002#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29003#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29731#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 29732#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29084#L753 assume 1 == ~t11_pc~0; 29085#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29641#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29959#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29360#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 29361#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29412#L1237 assume !(1 == ~M_E~0); 29413#L1237-2 assume !(1 == ~T1_E~0); 30016#L1242-1 assume !(1 == ~T2_E~0); 29178#L1247-1 assume !(1 == ~T3_E~0); 29179#L1252-1 assume !(1 == ~T4_E~0); 28943#L1257-1 assume !(1 == ~T5_E~0); 28944#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29808#L1267-1 assume !(1 == ~T7_E~0); 29906#L1272-1 assume !(1 == ~T8_E~0); 29268#L1277-1 assume !(1 == ~T9_E~0); 29269#L1282-1 assume !(1 == ~T10_E~0); 29674#L1287-1 assume !(1 == ~T11_E~0); 29675#L1292-1 assume !(1 == ~E_M~0); 29635#L1297-1 assume !(1 == ~E_1~0); 29075#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 29076#L1307-1 assume !(1 == ~E_3~0); 29895#L1312-1 assume !(1 == ~E_4~0); 29314#L1317-1 assume !(1 == ~E_5~0); 29315#L1322-1 assume !(1 == ~E_6~0); 29019#L1327-1 assume !(1 == ~E_7~0); 29020#L1332-1 assume !(1 == ~E_8~0); 29594#L1337-1 assume !(1 == ~E_9~0); 29528#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 29529#L1347-1 assume !(1 == ~E_11~0); 29894#L1352-1 assume { :end_inline_reset_delta_events } true; 29792#L1678-2 [2024-11-13 15:57:40,420 INFO L747 eck$LassoCheckResult]: Loop: 29792#L1678-2 assume !false; 29584#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29585#L1084-1 assume !false; 29381#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29382#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28656#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29880#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 28575#L925 assume !(0 != eval_~tmp~0#1); 28577#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29068#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29069#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28548#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28549#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29637#L1119-3 assume !(0 == ~T3_E~0); 29638#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29662#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29663#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29832#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29883#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29059#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29060#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29321#L1159-3 assume !(0 == ~T11_E~0); 29322#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29577#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29578#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29625#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29626#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29771#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29467#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28812#L1199-3 assume !(0 == ~E_7~0); 28813#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29039#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28498#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28499#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 29222#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29223#L544-39 assume 1 == ~m_pc~0; 29569#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28487#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29545#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28893#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 28894#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29758#L563-39 assume 1 == ~t1_pc~0; 29764#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28632#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30043#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30044#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30047#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29866#L582-39 assume 1 == ~t2_pc~0; 28955#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28957#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29291#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29292#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28726#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28510#L601-39 assume !(1 == ~t3_pc~0); 28512#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 28559#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29725#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30054#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29762#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29433#L620-39 assume !(1 == ~t4_pc~0); 29434#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 29623#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29458#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29459#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29735#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30058#L639-39 assume 1 == ~t5_pc~0; 29849#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29181#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29182#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28537#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28538#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29470#L658-39 assume 1 == ~t6_pc~0; 29453#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29454#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29910#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29646#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29620#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29621#L677-39 assume !(1 == ~t7_pc~0); 29266#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 28715#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28716#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28771#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 28772#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29363#L696-39 assume 1 == ~t8_pc~0; 29329#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29204#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29205#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29495#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29463#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29343#L715-39 assume 1 == ~t9_pc~0; 28515#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28516#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28592#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28593#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29668#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29669#L734-39 assume !(1 == ~t10_pc~0); 29030#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 29031#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29366#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28669#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28670#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29924#L753-39 assume !(1 == ~t11_pc~0); 28588#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 28589#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29492#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29334#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29335#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29430#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29431#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29689#L1242-3 assume !(1 == ~T2_E~0); 29690#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29905#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29613#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29614#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29878#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29927#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30030#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28742#L1282-3 assume !(1 == ~T10_E~0); 28743#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28652#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28653#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29801#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29802#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29982#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30055#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29709#L1322-3 assume !(1 == ~E_6~0); 29710#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28708#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28685#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28686#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29401#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29523#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29524#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28634#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 28840#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 28841#L1697 assume !(0 == start_simulation_~tmp~3#1); 29420#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29421#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28759#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 28527#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 28528#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29489#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29490#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 29791#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 29792#L1678-2 [2024-11-13 15:57:40,420 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:40,420 INFO L85 PathProgramCache]: Analyzing trace with hash 215884284, now seen corresponding path program 1 times [2024-11-13 15:57:40,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:40,420 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [18824713] [2024-11-13 15:57:40,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:40,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:40,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:40,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:40,511 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:40,511 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [18824713] [2024-11-13 15:57:40,511 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [18824713] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:40,511 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:40,511 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:40,511 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [783161710] [2024-11-13 15:57:40,511 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:40,511 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:40,512 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:40,512 INFO L85 PathProgramCache]: Analyzing trace with hash -643086163, now seen corresponding path program 1 times [2024-11-13 15:57:40,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:40,512 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [978178312] [2024-11-13 15:57:40,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:40,512 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:40,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:40,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:40,601 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:40,601 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [978178312] [2024-11-13 15:57:40,602 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [978178312] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:40,602 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:40,602 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:40,602 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [433822937] [2024-11-13 15:57:40,602 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:40,602 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:40,602 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:40,603 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:40,603 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:40,603 INFO L87 Difference]: Start difference. First operand 1578 states and 2329 transitions. cyclomatic complexity: 752 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:40,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:40,657 INFO L93 Difference]: Finished difference Result 1578 states and 2328 transitions. [2024-11-13 15:57:40,657 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2328 transitions. [2024-11-13 15:57:40,668 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:40,677 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2328 transitions. [2024-11-13 15:57:40,677 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-13 15:57:40,679 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-13 15:57:40,679 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2328 transitions. [2024-11-13 15:57:40,682 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:40,682 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2328 transitions. [2024-11-13 15:57:40,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2328 transitions. [2024-11-13 15:57:40,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-13 15:57:40,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4752851711026616) internal successors, (2328), 1577 states have internal predecessors, (2328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:40,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2328 transitions. [2024-11-13 15:57:40,721 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2328 transitions. [2024-11-13 15:57:40,721 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:40,722 INFO L424 stractBuchiCegarLoop]: Abstraction has 1578 states and 2328 transitions. [2024-11-13 15:57:40,722 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 15:57:40,722 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2328 transitions. [2024-11-13 15:57:40,731 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:40,731 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:40,731 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:40,734 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:40,734 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:40,734 INFO L745 eck$LassoCheckResult]: Stem: 31900#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 31901#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 32681#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32682#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31874#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 31875#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33115#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33084#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33085#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32233#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32234#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32649#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33051#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32137#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 32138#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 32028#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32029#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32982#L1109 assume !(0 == ~M_E~0); 32999#L1109-2 assume !(0 == ~T1_E~0); 32037#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32038#L1119-1 assume !(0 == ~T3_E~0); 33054#L1124-1 assume !(0 == ~T4_E~0); 31688#L1129-1 assume !(0 == ~T5_E~0); 31689#L1134-1 assume !(0 == ~T6_E~0); 32320#L1139-1 assume !(0 == ~T7_E~0); 32990#L1144-1 assume !(0 == ~T8_E~0); 32860#L1149-1 assume !(0 == ~T9_E~0); 31799#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31800#L1159-1 assume !(0 == ~T11_E~0); 32850#L1164-1 assume !(0 == ~E_M~0); 32195#L1169-1 assume !(0 == ~E_1~0); 32089#L1174-1 assume !(0 == ~E_2~0); 31953#L1179-1 assume !(0 == ~E_3~0); 31880#L1184-1 assume !(0 == ~E_4~0); 31881#L1189-1 assume !(0 == ~E_5~0); 31913#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 31996#L1199-1 assume !(0 == ~E_7~0); 32869#L1204-1 assume !(0 == ~E_8~0); 32810#L1209-1 assume !(0 == ~E_9~0); 32811#L1214-1 assume !(0 == ~E_10~0); 33128#L1219-1 assume !(0 == ~E_11~0); 33215#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32212#L544 assume 1 == ~m_pc~0; 32213#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33038#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32568#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31842#L1379 assume !(0 != activate_threads_~tmp~1#1); 31843#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32636#L563 assume !(1 == ~t1_pc~0); 32442#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31698#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31699#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32758#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 31694#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31695#L582 assume 1 == ~t2_pc~0; 32420#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32763#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32033#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32034#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 31727#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31728#L601 assume !(1 == ~t3_pc~0); 32437#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 32436#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32890#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32795#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 32796#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32744#L620 assume 1 == ~t4_pc~0; 31708#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31709#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31741#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31742#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 32646#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32828#L639 assume 1 == ~t5_pc~0; 32718#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32001#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32002#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32666#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 32667#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32601#L658 assume !(1 == ~t6_pc~0); 32209#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 32210#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32025#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32026#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32799#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32048#L677 assume 1 == ~t7_pc~0; 32049#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31946#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32956#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33077#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 33078#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33148#L696 assume !(1 == ~t8_pc~0); 32273#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 32274#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33113#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33151#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 33196#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32705#L715 assume 1 == ~t9_pc~0; 32706#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32373#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32087#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32088#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 32688#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32951#L734 assume !(1 == ~t10_pc~0); 32952#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32165#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32166#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32894#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 32895#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32247#L753 assume 1 == ~t11_pc~0; 32248#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32804#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33122#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32523#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 32524#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32575#L1237 assume !(1 == ~M_E~0); 32576#L1237-2 assume !(1 == ~T1_E~0); 33179#L1242-1 assume !(1 == ~T2_E~0); 32341#L1247-1 assume !(1 == ~T3_E~0); 32342#L1252-1 assume !(1 == ~T4_E~0); 32106#L1257-1 assume !(1 == ~T5_E~0); 32107#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32971#L1267-1 assume !(1 == ~T7_E~0); 33069#L1272-1 assume !(1 == ~T8_E~0); 32431#L1277-1 assume !(1 == ~T9_E~0); 32432#L1282-1 assume !(1 == ~T10_E~0); 32837#L1287-1 assume !(1 == ~T11_E~0); 32838#L1292-1 assume !(1 == ~E_M~0); 32798#L1297-1 assume !(1 == ~E_1~0); 32238#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 32239#L1307-1 assume !(1 == ~E_3~0); 33058#L1312-1 assume !(1 == ~E_4~0); 32477#L1317-1 assume !(1 == ~E_5~0); 32478#L1322-1 assume !(1 == ~E_6~0); 32182#L1327-1 assume !(1 == ~E_7~0); 32183#L1332-1 assume !(1 == ~E_8~0); 32757#L1337-1 assume !(1 == ~E_9~0); 32691#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 32692#L1347-1 assume !(1 == ~E_11~0); 33057#L1352-1 assume { :end_inline_reset_delta_events } true; 32955#L1678-2 [2024-11-13 15:57:40,735 INFO L747 eck$LassoCheckResult]: Loop: 32955#L1678-2 assume !false; 32747#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32748#L1084-1 assume !false; 32544#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32545#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31819#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33043#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31738#L925 assume !(0 != eval_~tmp~0#1); 31740#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32231#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32232#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 31711#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31712#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32800#L1119-3 assume !(0 == ~T3_E~0); 32801#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32825#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32826#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32995#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33046#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32222#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32223#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32484#L1159-3 assume !(0 == ~T11_E~0); 32485#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32740#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32741#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32788#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32789#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32934#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32630#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31975#L1199-3 assume !(0 == ~E_7~0); 31976#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32202#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 31661#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31662#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32385#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32386#L544-39 assume !(1 == ~m_pc~0); 31649#L544-41 is_master_triggered_~__retres1~0#1 := 0; 31650#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32708#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32056#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 32057#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32921#L563-39 assume !(1 == ~t1_pc~0); 31794#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 31795#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33206#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33207#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33210#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33029#L582-39 assume 1 == ~t2_pc~0; 32118#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32120#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32454#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32455#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31889#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31673#L601-39 assume 1 == ~t3_pc~0; 31674#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31722#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32888#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33217#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32925#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32596#L620-39 assume !(1 == ~t4_pc~0); 32597#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 32786#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32621#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32622#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32898#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33221#L639-39 assume 1 == ~t5_pc~0; 33012#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32344#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32345#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31700#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31701#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32633#L658-39 assume 1 == ~t6_pc~0; 32616#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32617#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33073#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32809#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32783#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32784#L677-39 assume !(1 == ~t7_pc~0); 32429#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 31878#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31879#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31934#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 31935#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32526#L696-39 assume 1 == ~t8_pc~0; 32492#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32367#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32368#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32658#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32626#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32506#L715-39 assume !(1 == ~t9_pc~0); 31680#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 31679#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31755#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31756#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32831#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32832#L734-39 assume !(1 == ~t10_pc~0); 32193#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 32194#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32529#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31832#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 31833#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33087#L753-39 assume !(1 == ~t11_pc~0); 31751#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 31752#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32655#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32497#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32498#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32593#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32594#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32852#L1242-3 assume !(1 == ~T2_E~0); 32853#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33068#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32776#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32777#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33041#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33090#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33193#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31905#L1282-3 assume !(1 == ~T10_E~0); 31906#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31815#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 31816#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32964#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32965#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33145#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33218#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32872#L1322-3 assume !(1 == ~E_6~0); 32873#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31871#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31848#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 31849#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32564#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32686#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32687#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31797#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32003#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 32004#L1697 assume !(0 == start_simulation_~tmp~3#1); 32583#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32584#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31922#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 31690#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 31691#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32652#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32653#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 32954#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 32955#L1678-2 [2024-11-13 15:57:40,735 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:40,735 INFO L85 PathProgramCache]: Analyzing trace with hash 922480890, now seen corresponding path program 1 times [2024-11-13 15:57:40,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:40,735 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [226598735] [2024-11-13 15:57:40,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:40,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:40,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:40,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:40,808 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:40,808 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [226598735] [2024-11-13 15:57:40,808 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [226598735] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:40,808 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:40,808 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:40,808 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1336554963] [2024-11-13 15:57:40,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:40,809 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:40,809 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:40,809 INFO L85 PathProgramCache]: Analyzing trace with hash 760405359, now seen corresponding path program 1 times [2024-11-13 15:57:40,809 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:40,810 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1323527287] [2024-11-13 15:57:40,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:40,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:40,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:40,913 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:40,914 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:40,914 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1323527287] [2024-11-13 15:57:40,914 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1323527287] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:40,914 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:40,914 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:40,914 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1159742390] [2024-11-13 15:57:40,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:40,914 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:40,914 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:40,915 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:40,915 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:40,915 INFO L87 Difference]: Start difference. First operand 1578 states and 2328 transitions. cyclomatic complexity: 751 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:40,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:40,952 INFO L93 Difference]: Finished difference Result 1578 states and 2327 transitions. [2024-11-13 15:57:40,952 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2327 transitions. [2024-11-13 15:57:40,960 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:40,968 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2327 transitions. [2024-11-13 15:57:40,968 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-13 15:57:40,969 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-13 15:57:40,969 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2327 transitions. [2024-11-13 15:57:40,972 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:40,972 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2327 transitions. [2024-11-13 15:57:40,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2327 transitions. [2024-11-13 15:57:40,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-13 15:57:40,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4746514575411913) internal successors, (2327), 1577 states have internal predecessors, (2327), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:41,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2327 transitions. [2024-11-13 15:57:41,002 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2327 transitions. [2024-11-13 15:57:41,003 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:41,003 INFO L424 stractBuchiCegarLoop]: Abstraction has 1578 states and 2327 transitions. [2024-11-13 15:57:41,003 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 15:57:41,003 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2327 transitions. [2024-11-13 15:57:41,010 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-13 15:57:41,010 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:41,010 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:41,012 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:41,012 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:41,012 INFO L745 eck$LassoCheckResult]: Stem: 35063#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 35064#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 35844#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35845#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35037#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 35038#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36278#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36247#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36248#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35396#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35397#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35812#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36214#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35300#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35301#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 35191#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 35192#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36145#L1109 assume !(0 == ~M_E~0); 36162#L1109-2 assume !(0 == ~T1_E~0); 35200#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35201#L1119-1 assume !(0 == ~T3_E~0); 36217#L1124-1 assume !(0 == ~T4_E~0); 34851#L1129-1 assume !(0 == ~T5_E~0); 34852#L1134-1 assume !(0 == ~T6_E~0); 35483#L1139-1 assume !(0 == ~T7_E~0); 36153#L1144-1 assume !(0 == ~T8_E~0); 36023#L1149-1 assume !(0 == ~T9_E~0); 34962#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34963#L1159-1 assume !(0 == ~T11_E~0); 36013#L1164-1 assume !(0 == ~E_M~0); 35358#L1169-1 assume !(0 == ~E_1~0); 35252#L1174-1 assume !(0 == ~E_2~0); 35116#L1179-1 assume !(0 == ~E_3~0); 35043#L1184-1 assume !(0 == ~E_4~0); 35044#L1189-1 assume !(0 == ~E_5~0); 35076#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 35159#L1199-1 assume !(0 == ~E_7~0); 36032#L1204-1 assume !(0 == ~E_8~0); 35973#L1209-1 assume !(0 == ~E_9~0); 35974#L1214-1 assume !(0 == ~E_10~0); 36291#L1219-1 assume !(0 == ~E_11~0); 36378#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35375#L544 assume 1 == ~m_pc~0; 35376#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36201#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35731#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35005#L1379 assume !(0 != activate_threads_~tmp~1#1); 35006#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35799#L563 assume !(1 == ~t1_pc~0); 35605#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34861#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34862#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35921#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 34857#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34858#L582 assume 1 == ~t2_pc~0; 35583#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35926#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35196#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35197#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 34890#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34891#L601 assume !(1 == ~t3_pc~0); 35600#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 35599#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36053#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35958#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 35959#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35907#L620 assume 1 == ~t4_pc~0; 34871#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34872#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34904#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34905#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 35809#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35991#L639 assume 1 == ~t5_pc~0; 35881#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35164#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35165#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35829#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 35830#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35764#L658 assume !(1 == ~t6_pc~0); 35372#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 35373#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35188#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35189#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35962#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35211#L677 assume 1 == ~t7_pc~0; 35212#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35109#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36119#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36240#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 36241#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36311#L696 assume !(1 == ~t8_pc~0); 35436#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35437#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36276#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36314#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 36359#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35868#L715 assume 1 == ~t9_pc~0; 35869#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35536#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35250#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35251#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 35851#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36114#L734 assume !(1 == ~t10_pc~0); 36115#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35328#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35329#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36057#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 36058#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35410#L753 assume 1 == ~t11_pc~0; 35411#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35967#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36285#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35686#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 35687#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35738#L1237 assume !(1 == ~M_E~0); 35739#L1237-2 assume !(1 == ~T1_E~0); 36342#L1242-1 assume !(1 == ~T2_E~0); 35504#L1247-1 assume !(1 == ~T3_E~0); 35505#L1252-1 assume !(1 == ~T4_E~0); 35269#L1257-1 assume !(1 == ~T5_E~0); 35270#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36134#L1267-1 assume !(1 == ~T7_E~0); 36232#L1272-1 assume !(1 == ~T8_E~0); 35594#L1277-1 assume !(1 == ~T9_E~0); 35595#L1282-1 assume !(1 == ~T10_E~0); 36000#L1287-1 assume !(1 == ~T11_E~0); 36001#L1292-1 assume !(1 == ~E_M~0); 35961#L1297-1 assume !(1 == ~E_1~0); 35401#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 35402#L1307-1 assume !(1 == ~E_3~0); 36221#L1312-1 assume !(1 == ~E_4~0); 35640#L1317-1 assume !(1 == ~E_5~0); 35641#L1322-1 assume !(1 == ~E_6~0); 35345#L1327-1 assume !(1 == ~E_7~0); 35346#L1332-1 assume !(1 == ~E_8~0); 35920#L1337-1 assume !(1 == ~E_9~0); 35854#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 35855#L1347-1 assume !(1 == ~E_11~0); 36220#L1352-1 assume { :end_inline_reset_delta_events } true; 36118#L1678-2 [2024-11-13 15:57:41,012 INFO L747 eck$LassoCheckResult]: Loop: 36118#L1678-2 assume !false; 35910#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35911#L1084-1 assume !false; 35707#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35708#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34982#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36206#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34901#L925 assume !(0 != eval_~tmp~0#1); 34903#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35394#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35395#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34874#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34875#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35963#L1119-3 assume !(0 == ~T3_E~0); 35964#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35988#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35989#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36158#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36209#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 35385#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35386#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35647#L1159-3 assume !(0 == ~T11_E~0); 35648#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35903#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35904#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35951#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35952#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36097#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35793#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35138#L1199-3 assume !(0 == ~E_7~0); 35139#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35365#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 34824#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34825#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35548#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35549#L544-39 assume 1 == ~m_pc~0; 35895#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 34813#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35871#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35219#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 35220#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36084#L563-39 assume 1 == ~t1_pc~0; 36090#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34958#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36369#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36370#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36373#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36192#L582-39 assume 1 == ~t2_pc~0; 35281#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35283#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35617#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35618#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35052#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34836#L601-39 assume 1 == ~t3_pc~0; 34837#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34885#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36051#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36380#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36088#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35759#L620-39 assume !(1 == ~t4_pc~0); 35760#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 35949#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35784#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35785#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36061#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36384#L639-39 assume !(1 == ~t5_pc~0); 36176#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 35507#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35508#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34863#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34864#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35796#L658-39 assume 1 == ~t6_pc~0; 35779#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35780#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36236#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35972#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35946#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35947#L677-39 assume !(1 == ~t7_pc~0); 35592#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 35041#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35042#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35097#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 35098#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35689#L696-39 assume 1 == ~t8_pc~0; 35655#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35530#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35531#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35821#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35789#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35669#L715-39 assume 1 == ~t9_pc~0; 34841#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34842#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34918#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34919#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35994#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35995#L734-39 assume 1 == ~t10_pc~0; 35924#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35357#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35692#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34995#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34996#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36250#L753-39 assume !(1 == ~t11_pc~0); 34914#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 34915#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35818#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35660#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35661#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35756#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35757#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36015#L1242-3 assume !(1 == ~T2_E~0); 36016#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36231#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35939#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35940#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36204#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36253#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36356#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35068#L1282-3 assume !(1 == ~T10_E~0); 35069#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34978#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34979#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36127#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36128#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36308#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36381#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36035#L1322-3 assume !(1 == ~E_6~0); 36036#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35034#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35011#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35012#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35727#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35849#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35850#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34960#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35166#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 35167#L1697 assume !(0 == start_simulation_~tmp~3#1); 35746#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35747#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35085#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 34853#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 34854#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35815#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35816#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 36117#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 36118#L1678-2 [2024-11-13 15:57:41,013 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:41,013 INFO L85 PathProgramCache]: Analyzing trace with hash -24556996, now seen corresponding path program 1 times [2024-11-13 15:57:41,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:41,013 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [572793739] [2024-11-13 15:57:41,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:41,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:41,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:41,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:41,122 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:41,122 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [572793739] [2024-11-13 15:57:41,122 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [572793739] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:41,122 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:41,122 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:41,122 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [548411272] [2024-11-13 15:57:41,122 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:41,123 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:41,123 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:41,123 INFO L85 PathProgramCache]: Analyzing trace with hash -1887469332, now seen corresponding path program 1 times [2024-11-13 15:57:41,123 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:41,123 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1831618755] [2024-11-13 15:57:41,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:41,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:41,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:41,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:41,191 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:41,191 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1831618755] [2024-11-13 15:57:41,191 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1831618755] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:41,191 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:41,191 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:41,191 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1040180810] [2024-11-13 15:57:41,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:41,192 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:41,192 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:41,192 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:57:41,192 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:57:41,192 INFO L87 Difference]: Start difference. First operand 1578 states and 2327 transitions. cyclomatic complexity: 750 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:41,415 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:41,416 INFO L93 Difference]: Finished difference Result 2919 states and 4289 transitions. [2024-11-13 15:57:41,416 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2919 states and 4289 transitions. [2024-11-13 15:57:41,430 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2744 [2024-11-13 15:57:41,449 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2919 states to 2919 states and 4289 transitions. [2024-11-13 15:57:41,449 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2919 [2024-11-13 15:57:41,452 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2919 [2024-11-13 15:57:41,452 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2919 states and 4289 transitions. [2024-11-13 15:57:41,457 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:41,457 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2919 states and 4289 transitions. [2024-11-13 15:57:41,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2919 states and 4289 transitions. [2024-11-13 15:57:41,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2919 to 2919. [2024-11-13 15:57:41,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2919 states, 2919 states have (on average 1.4693388146625557) internal successors, (4289), 2918 states have internal predecessors, (4289), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:41,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2919 states to 2919 states and 4289 transitions. [2024-11-13 15:57:41,530 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2919 states and 4289 transitions. [2024-11-13 15:57:41,530 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:57:41,531 INFO L424 stractBuchiCegarLoop]: Abstraction has 2919 states and 4289 transitions. [2024-11-13 15:57:41,531 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 15:57:41,531 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2919 states and 4289 transitions. [2024-11-13 15:57:41,545 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2744 [2024-11-13 15:57:41,545 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:41,545 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:41,547 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:41,547 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:41,547 INFO L745 eck$LassoCheckResult]: Stem: 39571#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 39572#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 40369#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40370#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39544#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 39545#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40858#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40820#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40821#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39904#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39905#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40334#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40781#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 39810#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39811#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39699#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 39700#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40701#L1109 assume !(0 == ~M_E~0); 40720#L1109-2 assume !(0 == ~T1_E~0); 39708#L1114-1 assume !(0 == ~T2_E~0); 39709#L1119-1 assume !(0 == ~T3_E~0); 40784#L1124-1 assume !(0 == ~T4_E~0); 39358#L1129-1 assume !(0 == ~T5_E~0); 39359#L1134-1 assume !(0 == ~T6_E~0); 39992#L1139-1 assume !(0 == ~T7_E~0); 40708#L1144-1 assume !(0 == ~T8_E~0); 40557#L1149-1 assume !(0 == ~T9_E~0); 39471#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 39472#L1159-1 assume !(0 == ~T11_E~0); 40546#L1164-1 assume !(0 == ~E_M~0); 39866#L1169-1 assume !(0 == ~E_1~0); 39760#L1174-1 assume !(0 == ~E_2~0); 39629#L1179-1 assume !(0 == ~E_3~0); 39550#L1184-1 assume !(0 == ~E_4~0); 39551#L1189-1 assume !(0 == ~E_5~0); 39584#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 39671#L1199-1 assume !(0 == ~E_7~0); 40569#L1204-1 assume !(0 == ~E_8~0); 40506#L1209-1 assume !(0 == ~E_9~0); 40507#L1214-1 assume !(0 == ~E_10~0); 40874#L1219-1 assume !(0 == ~E_11~0); 40987#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39885#L544 assume 1 == ~m_pc~0; 39886#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40762#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40248#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39512#L1379 assume !(0 != activate_threads_~tmp~1#1); 39513#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40323#L563 assume !(1 == ~t1_pc~0); 40116#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39368#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39369#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40449#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 39364#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39365#L582 assume 1 == ~t2_pc~0; 40094#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40454#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39704#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39705#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 39397#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39398#L601 assume !(1 == ~t3_pc~0); 40111#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40110#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40590#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40488#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 40489#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40434#L620 assume 1 == ~t4_pc~0; 39378#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39379#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39411#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39412#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 40331#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40525#L639 assume 1 == ~t5_pc~0; 40408#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39674#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39675#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40351#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 40352#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40285#L658 assume !(1 == ~t6_pc~0); 39880#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 39881#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39696#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39697#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40493#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39721#L677 assume 1 == ~t7_pc~0; 39722#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39620#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40665#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40811#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 40812#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40899#L696 assume !(1 == ~t8_pc~0); 39945#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39946#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40856#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40902#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 40959#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40394#L715 assume 1 == ~t9_pc~0; 40395#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40047#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39758#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39759#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 40375#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40662#L734 assume !(1 == ~t10_pc~0); 40663#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39836#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39837#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40594#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 40595#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39918#L753 assume 1 == ~t11_pc~0; 39919#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 40498#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40868#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40203#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 40204#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40257#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 40258#L1237-2 assume !(1 == ~T1_E~0); 41111#L1242-1 assume !(1 == ~T2_E~0); 40976#L1247-1 assume !(1 == ~T3_E~0); 41110#L1252-1 assume !(1 == ~T4_E~0); 41109#L1257-1 assume !(1 == ~T5_E~0); 41108#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41107#L1267-1 assume !(1 == ~T7_E~0); 40801#L1272-1 assume !(1 == ~T8_E~0); 40105#L1277-1 assume !(1 == ~T9_E~0); 40106#L1282-1 assume !(1 == ~T10_E~0); 40600#L1287-1 assume !(1 == ~T11_E~0); 41068#L1292-1 assume !(1 == ~E_M~0); 41065#L1297-1 assume !(1 == ~E_1~0); 39909#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 39910#L1307-1 assume !(1 == ~E_3~0); 41044#L1312-1 assume !(1 == ~E_4~0); 41032#L1317-1 assume !(1 == ~E_5~0); 40388#L1322-1 assume !(1 == ~E_6~0); 39853#L1327-1 assume !(1 == ~E_7~0); 39854#L1332-1 assume !(1 == ~E_8~0); 40447#L1337-1 assume !(1 == ~E_9~0); 40956#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 41025#L1347-1 assume !(1 == ~E_11~0); 40787#L1352-1 assume { :end_inline_reset_delta_events } true; 40661#L1678-2 [2024-11-13 15:57:41,548 INFO L747 eck$LassoCheckResult]: Loop: 40661#L1678-2 assume !false; 41001#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41017#L1084-1 assume !false; 41016#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40891#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 39489#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40969#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 41003#L925 assume !(0 != eval_~tmp~0#1); 40190#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40191#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41002#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 39381#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39382#L1114-3 assume !(0 == ~T2_E~0); 40494#L1119-3 assume !(0 == ~T3_E~0); 40495#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40521#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40522#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40715#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40773#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 39893#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39894#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40158#L1159-3 assume !(0 == ~T11_E~0); 40159#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 40430#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40431#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40481#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40482#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40640#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40313#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 39646#L1199-3 assume !(0 == ~E_7~0); 39647#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39873#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39331#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39332#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40059#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40060#L544-39 assume 1 == ~m_pc~0; 40422#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39320#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40397#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39727#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 39728#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40623#L563-39 assume 1 == ~t1_pc~0; 40631#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 39465#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41995#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41994#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41993#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41992#L582-39 assume !(1 == ~t2_pc~0); 41990#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 41989#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41988#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41987#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41986#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41985#L601-39 assume !(1 == ~t3_pc~0); 41984#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 41982#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41981#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41980#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41979#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41978#L620-39 assume !(1 == ~t4_pc~0); 41976#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 41975#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41974#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41973#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41972#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41971#L639-39 assume 1 == ~t5_pc~0; 41969#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41968#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41967#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41966#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41965#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41964#L658-39 assume !(1 == ~t6_pc~0); 41962#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 41961#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41960#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41959#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41958#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41957#L677-39 assume 1 == ~t7_pc~0; 41955#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41954#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41953#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41952#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 41951#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41950#L696-39 assume 1 == ~t8_pc~0; 41948#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41947#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41946#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41945#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41944#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41943#L715-39 assume 1 == ~t9_pc~0; 41941#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41940#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41939#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41938#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41937#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41936#L734-39 assume 1 == ~t10_pc~0; 41934#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41933#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41932#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41931#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41524#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40824#L753-39 assume 1 == ~t11_pc~0; 40145#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39422#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40340#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40171#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40172#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40275#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40276#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41185#L1242-3 assume !(1 == ~T2_E~0); 40550#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41182#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41180#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41178#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41176#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41175#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 40955#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 39576#L1282-3 assume !(1 == ~T10_E~0); 39577#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40448#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41165#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40677#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40678#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40896#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40992#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40572#L1322-3 assume !(1 == ~E_6~0); 40573#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39541#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39518#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39519#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40244#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40707#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40667#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 39467#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 39672#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 39673#L1697 assume !(0 == start_simulation_~tmp~3#1); 40523#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40944#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 39593#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 41027#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 41026#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41024#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41023#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 40660#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 40661#L1678-2 [2024-11-13 15:57:41,548 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:41,548 INFO L85 PathProgramCache]: Analyzing trace with hash -1257740808, now seen corresponding path program 1 times [2024-11-13 15:57:41,548 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:41,548 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [349523670] [2024-11-13 15:57:41,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:41,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:41,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:41,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:41,647 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:41,647 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [349523670] [2024-11-13 15:57:41,647 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [349523670] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:41,647 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:41,647 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:41,647 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [116849051] [2024-11-13 15:57:41,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:41,648 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:41,649 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:41,649 INFO L85 PathProgramCache]: Analyzing trace with hash -1292951382, now seen corresponding path program 1 times [2024-11-13 15:57:41,649 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:41,649 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1689580655] [2024-11-13 15:57:41,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:41,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:41,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:41,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:41,722 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:41,722 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1689580655] [2024-11-13 15:57:41,722 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1689580655] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:41,722 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:41,722 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:41,723 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [930779742] [2024-11-13 15:57:41,723 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:41,723 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:41,723 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:41,723 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:57:41,723 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:57:41,724 INFO L87 Difference]: Start difference. First operand 2919 states and 4289 transitions. cyclomatic complexity: 1372 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:41,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:41,894 INFO L93 Difference]: Finished difference Result 5589 states and 8190 transitions. [2024-11-13 15:57:41,894 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5589 states and 8190 transitions. [2024-11-13 15:57:41,923 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5378 [2024-11-13 15:57:41,955 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5589 states to 5589 states and 8190 transitions. [2024-11-13 15:57:41,955 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5589 [2024-11-13 15:57:41,961 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5589 [2024-11-13 15:57:41,961 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5589 states and 8190 transitions. [2024-11-13 15:57:41,969 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:41,969 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5589 states and 8190 transitions. [2024-11-13 15:57:41,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5589 states and 8190 transitions. [2024-11-13 15:57:42,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5589 to 5589. [2024-11-13 15:57:42,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5589 states, 5589 states have (on average 1.465378421900161) internal successors, (8190), 5588 states have internal predecessors, (8190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:42,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5589 states to 5589 states and 8190 transitions. [2024-11-13 15:57:42,185 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5589 states and 8190 transitions. [2024-11-13 15:57:42,185 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:57:42,186 INFO L424 stractBuchiCegarLoop]: Abstraction has 5589 states and 8190 transitions. [2024-11-13 15:57:42,186 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 15:57:42,186 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5589 states and 8190 transitions. [2024-11-13 15:57:42,207 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5378 [2024-11-13 15:57:42,207 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:42,207 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:42,209 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:42,209 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:42,210 INFO L745 eck$LassoCheckResult]: Stem: 48089#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 48090#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 48885#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48886#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48062#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 48063#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49364#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49330#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49331#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48425#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48426#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48850#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49289#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48328#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 48329#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 48218#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 48219#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49206#L1109 assume !(0 == ~M_E~0); 49230#L1109-2 assume !(0 == ~T1_E~0); 48227#L1114-1 assume !(0 == ~T2_E~0); 48228#L1119-1 assume !(0 == ~T3_E~0); 49292#L1124-1 assume !(0 == ~T4_E~0); 47876#L1129-1 assume !(0 == ~T5_E~0); 47877#L1134-1 assume !(0 == ~T6_E~0); 48512#L1139-1 assume !(0 == ~T7_E~0); 49219#L1144-1 assume !(0 == ~T8_E~0); 49072#L1149-1 assume !(0 == ~T9_E~0); 47987#L1154-1 assume !(0 == ~T10_E~0); 47988#L1159-1 assume !(0 == ~T11_E~0); 49061#L1164-1 assume !(0 == ~E_M~0); 48386#L1169-1 assume !(0 == ~E_1~0); 48280#L1174-1 assume !(0 == ~E_2~0); 48143#L1179-1 assume !(0 == ~E_3~0); 48068#L1184-1 assume !(0 == ~E_4~0); 48069#L1189-1 assume !(0 == ~E_5~0); 48103#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 48186#L1199-1 assume !(0 == ~E_7~0); 49081#L1204-1 assume !(0 == ~E_8~0); 49017#L1209-1 assume !(0 == ~E_9~0); 49018#L1214-1 assume !(0 == ~E_10~0); 49379#L1219-1 assume !(0 == ~E_11~0); 49484#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48404#L544 assume 1 == ~m_pc~0; 48405#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49275#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48764#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48030#L1379 assume !(0 != activate_threads_~tmp~1#1); 48031#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48836#L563 assume !(1 == ~t1_pc~0); 48636#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47886#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47887#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48964#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 47882#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47883#L582 assume 1 == ~t2_pc~0; 48614#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48969#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48223#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48224#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 47915#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47916#L601 assume !(1 == ~t3_pc~0); 48631#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48630#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49105#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49001#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 49002#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48950#L620 assume 1 == ~t4_pc~0; 47896#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47897#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47929#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47930#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 48847#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49037#L639 assume 1 == ~t5_pc~0; 48923#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48191#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48192#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48868#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 48869#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48799#L658 assume !(1 == ~t6_pc~0); 48401#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 48402#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48215#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48216#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49005#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48238#L677 assume 1 == ~t7_pc~0; 48239#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48136#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49178#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49322#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 49323#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49401#L696 assume !(1 == ~t8_pc~0); 48465#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 48466#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49362#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49404#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 49455#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48909#L715 assume 1 == ~t9_pc~0; 48910#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48567#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48278#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48279#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 48892#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49173#L734 assume !(1 == ~t10_pc~0); 49174#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 48356#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48357#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49109#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 49110#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48439#L753 assume 1 == ~t11_pc~0; 48440#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49010#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49373#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48718#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 48719#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48771#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 48772#L1237-2 assume !(1 == ~T1_E~0); 49471#L1242-1 assume !(1 == ~T2_E~0); 48535#L1247-1 assume !(1 == ~T3_E~0); 48536#L1252-1 assume !(1 == ~T4_E~0); 48297#L1257-1 assume !(1 == ~T5_E~0); 48298#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49308#L1267-1 assume !(1 == ~T7_E~0); 49309#L1272-1 assume !(1 == ~T8_E~0); 48625#L1277-1 assume !(1 == ~T9_E~0); 48626#L1282-1 assume !(1 == ~T10_E~0); 50301#L1287-1 assume !(1 == ~T11_E~0); 50297#L1292-1 assume !(1 == ~E_M~0); 50294#L1297-1 assume !(1 == ~E_1~0); 50290#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 50287#L1307-1 assume !(1 == ~E_3~0); 50284#L1312-1 assume !(1 == ~E_4~0); 50281#L1317-1 assume !(1 == ~E_5~0); 49627#L1322-1 assume !(1 == ~E_6~0); 49599#L1327-1 assume !(1 == ~E_7~0); 49580#L1332-1 assume !(1 == ~E_8~0); 49578#L1337-1 assume !(1 == ~E_9~0); 49563#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 49551#L1347-1 assume !(1 == ~E_11~0); 49542#L1352-1 assume { :end_inline_reset_delta_events } true; 49533#L1678-2 [2024-11-13 15:57:42,210 INFO L747 eck$LassoCheckResult]: Loop: 49533#L1678-2 assume !false; 49528#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49525#L1084-1 assume !false; 49524#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49512#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49511#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49510#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 49508#L925 assume !(0 != eval_~tmp~0#1); 49507#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49506#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49505#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47899#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47900#L1114-3 assume !(0 == ~T2_E~0); 50829#L1119-3 assume !(0 == ~T3_E~0); 49503#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49504#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 50823#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49349#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49350#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48414#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48415#L1154-3 assume !(0 == ~T10_E~0); 49502#L1159-3 assume !(0 == ~T11_E~0); 50810#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 50807#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49255#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49256#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50801#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 49154#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 49155#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50795#L1199-3 assume !(0 == ~E_7~0); 49084#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49085#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50789#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 48883#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 48884#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48937#L544-39 assume 1 == ~m_pc~0; 48938#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47838#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50773#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48246#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 48247#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49443#L563-39 assume 1 == ~t1_pc~0; 49147#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47983#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50757#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49474#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49475#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49479#L582-39 assume !(1 == ~t2_pc~0); 50746#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 50741#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48648#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48649#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 48077#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48078#L601-39 assume 1 == ~t3_pc~0; 50730#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50725#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49500#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49501#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49144#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49145#L620-39 assume !(1 == ~t4_pc~0); 50714#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 50709#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48819#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48820#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49497#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49498#L639-39 assume 1 == ~t5_pc~0; 50698#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50693#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50691#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50688#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50686#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50684#L658-39 assume !(1 == ~t6_pc~0); 50679#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 49315#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49316#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50672#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50669#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50667#L677-39 assume 1 == ~t7_pc~0; 50662#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50658#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50655#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50652#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 50649#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50647#L696-39 assume 1 == ~t8_pc~0; 50642#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50639#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50635#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48859#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 48860#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48701#L715-39 assume 1 == ~t9_pc~0; 47866#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47867#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47943#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47944#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49040#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49041#L734-39 assume 1 == ~t10_pc~0; 50595#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 48724#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48725#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50582#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50578#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50575#L753-39 assume !(1 == ~t11_pc~0); 50568#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 50564#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50560#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50555#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50551#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50547#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 48791#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50539#L1242-3 assume !(1 == ~T2_E~0); 50537#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50533#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50530#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50527#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50524#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50521#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50518#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50513#L1282-3 assume !(1 == ~T10_E~0); 50511#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50509#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50507#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50505#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50503#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50500#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50498#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50496#L1322-3 assume !(1 == ~E_6~0); 50494#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50492#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50490#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50489#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 50488#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 50487#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49910#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49907#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49905#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 49901#L1697 assume !(0 == start_simulation_~tmp~3#1); 49263#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49623#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49598#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49579#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 49564#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49562#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49550#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 49541#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 49533#L1678-2 [2024-11-13 15:57:42,211 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:42,211 INFO L85 PathProgramCache]: Analyzing trace with hash -786384458, now seen corresponding path program 1 times [2024-11-13 15:57:42,211 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:42,211 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1935695129] [2024-11-13 15:57:42,211 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:42,211 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:42,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:42,305 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:42,305 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:42,305 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1935695129] [2024-11-13 15:57:42,305 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1935695129] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:42,305 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:42,305 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:42,305 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2121877536] [2024-11-13 15:57:42,306 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:42,306 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:42,306 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:42,306 INFO L85 PathProgramCache]: Analyzing trace with hash -1581503128, now seen corresponding path program 1 times [2024-11-13 15:57:42,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:42,307 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1318354379] [2024-11-13 15:57:42,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:42,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:42,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:42,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:42,378 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:42,379 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1318354379] [2024-11-13 15:57:42,379 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1318354379] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:42,379 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:42,379 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:42,379 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [218340936] [2024-11-13 15:57:42,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:42,380 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:42,380 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:42,380 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:57:42,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:57:42,381 INFO L87 Difference]: Start difference. First operand 5589 states and 8190 transitions. cyclomatic complexity: 2605 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:42,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:42,669 INFO L93 Difference]: Finished difference Result 10549 states and 15425 transitions. [2024-11-13 15:57:42,670 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10549 states and 15425 transitions. [2024-11-13 15:57:42,725 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10302 [2024-11-13 15:57:42,764 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10549 states to 10549 states and 15425 transitions. [2024-11-13 15:57:42,765 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10549 [2024-11-13 15:57:42,776 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10549 [2024-11-13 15:57:42,776 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10549 states and 15425 transitions. [2024-11-13 15:57:42,791 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:42,792 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10549 states and 15425 transitions. [2024-11-13 15:57:42,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10549 states and 15425 transitions. [2024-11-13 15:57:43,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10549 to 10545. [2024-11-13 15:57:43,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10545 states, 10545 states have (on average 1.4623992413466098) internal successors, (15421), 10544 states have internal predecessors, (15421), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:43,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10545 states to 10545 states and 15421 transitions. [2024-11-13 15:57:43,058 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10545 states and 15421 transitions. [2024-11-13 15:57:43,058 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:57:43,059 INFO L424 stractBuchiCegarLoop]: Abstraction has 10545 states and 15421 transitions. [2024-11-13 15:57:43,059 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 15:57:43,059 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10545 states and 15421 transitions. [2024-11-13 15:57:43,103 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10302 [2024-11-13 15:57:43,103 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:43,103 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:43,105 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:43,105 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:43,106 INFO L745 eck$LassoCheckResult]: Stem: 64237#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 64238#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 65027#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 65028#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64211#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 64212#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65492#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65459#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65460#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64574#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64575#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64994#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65420#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 64478#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 64479#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 64369#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 64370#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 65345#L1109 assume !(0 == ~M_E~0); 65363#L1109-2 assume !(0 == ~T1_E~0); 64378#L1114-1 assume !(0 == ~T2_E~0); 64379#L1119-1 assume !(0 == ~T3_E~0); 65423#L1124-1 assume !(0 == ~T4_E~0); 64024#L1129-1 assume !(0 == ~T5_E~0); 64025#L1134-1 assume !(0 == ~T6_E~0); 64661#L1139-1 assume !(0 == ~T7_E~0); 65354#L1144-1 assume !(0 == ~T8_E~0); 65212#L1149-1 assume !(0 == ~T9_E~0); 64136#L1154-1 assume !(0 == ~T10_E~0); 64137#L1159-1 assume !(0 == ~T11_E~0); 65201#L1164-1 assume !(0 == ~E_M~0); 64536#L1169-1 assume !(0 == ~E_1~0); 64430#L1174-1 assume !(0 == ~E_2~0); 64293#L1179-1 assume !(0 == ~E_3~0); 64217#L1184-1 assume !(0 == ~E_4~0); 64218#L1189-1 assume !(0 == ~E_5~0); 64251#L1194-1 assume !(0 == ~E_6~0); 64336#L1199-1 assume !(0 == ~E_7~0); 65221#L1204-1 assume !(0 == ~E_8~0); 65161#L1209-1 assume !(0 == ~E_9~0); 65162#L1214-1 assume !(0 == ~E_10~0); 65507#L1219-1 assume !(0 == ~E_11~0); 65614#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64553#L544 assume 1 == ~m_pc~0; 64554#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 65407#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64911#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 64179#L1379 assume !(0 != activate_threads_~tmp~1#1); 64180#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64981#L563 assume !(1 == ~t1_pc~0); 64783#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 64034#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64035#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65108#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 64030#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64031#L582 assume 1 == ~t2_pc~0; 64761#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 65114#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64374#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64375#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 64064#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64065#L601 assume !(1 == ~t3_pc~0); 64778#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 64777#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65244#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65146#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 65147#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65094#L620 assume 1 == ~t4_pc~0; 64044#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64045#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64078#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64079#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 64991#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65179#L639 assume 1 == ~t5_pc~0; 65066#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64341#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64342#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65011#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 65012#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64946#L658 assume !(1 == ~t6_pc~0); 64550#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 64551#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64366#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64367#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 65150#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64389#L677 assume 1 == ~t7_pc~0; 64390#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64286#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65318#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65452#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 65453#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65529#L696 assume !(1 == ~t8_pc~0); 64614#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 64615#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65490#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65533#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 65588#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65052#L715 assume 1 == ~t9_pc~0; 65053#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64714#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64428#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 64429#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 65034#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 65313#L734 assume !(1 == ~t10_pc~0); 65314#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 64506#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 64507#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65248#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 65249#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 64588#L753 assume 1 == ~t11_pc~0; 64589#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65155#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65500#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64866#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 64867#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64918#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 64919#L1237-2 assume !(1 == ~T1_E~0); 66042#L1242-1 assume !(1 == ~T2_E~0); 66040#L1247-1 assume !(1 == ~T3_E~0); 65449#L1252-1 assume !(1 == ~T4_E~0); 64447#L1257-1 assume !(1 == ~T5_E~0); 64448#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65980#L1267-1 assume !(1 == ~T7_E~0); 65978#L1272-1 assume !(1 == ~T8_E~0); 64772#L1277-1 assume !(1 == ~T9_E~0); 64773#L1282-1 assume !(1 == ~T10_E~0); 65861#L1287-1 assume !(1 == ~T11_E~0); 65859#L1292-1 assume !(1 == ~E_M~0); 65823#L1297-1 assume !(1 == ~E_1~0); 65821#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 65819#L1307-1 assume !(1 == ~E_3~0); 65818#L1312-1 assume !(1 == ~E_4~0); 65817#L1317-1 assume !(1 == ~E_5~0); 65781#L1322-1 assume !(1 == ~E_6~0); 65740#L1327-1 assume !(1 == ~E_7~0); 65720#L1332-1 assume !(1 == ~E_8~0); 65698#L1337-1 assume !(1 == ~E_9~0); 65683#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 65673#L1347-1 assume !(1 == ~E_11~0); 65664#L1352-1 assume { :end_inline_reset_delta_events } true; 65655#L1678-2 [2024-11-13 15:57:43,106 INFO L747 eck$LassoCheckResult]: Loop: 65655#L1678-2 assume !false; 65650#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65647#L1084-1 assume !false; 65646#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65634#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65633#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65632#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 65630#L925 assume !(0 != eval_~tmp~0#1); 65629#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65628#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65627#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 64047#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 64048#L1114-3 assume !(0 == ~T2_E~0); 65151#L1119-3 assume !(0 == ~T3_E~0); 65152#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 65176#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 65177#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 65359#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 65415#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 64563#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 64564#L1154-3 assume !(0 == ~T10_E~0); 64826#L1159-3 assume !(0 == ~T11_E~0); 64827#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 72341#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 67502#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 67500#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67498#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 67496#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 67493#L1194-3 assume !(0 == ~E_6~0); 67491#L1199-3 assume !(0 == ~E_7~0); 67489#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 67487#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 67485#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 67483#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 67480#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67478#L544-39 assume !(1 == ~m_pc~0); 63985#L544-41 is_master_triggered_~__retres1~0#1 := 0; 63986#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65055#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 64397#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 64398#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65279#L563-39 assume !(1 == ~t1_pc~0); 64131#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 64132#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65599#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65600#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 65606#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65610#L582-39 assume 1 == ~t2_pc~0; 68224#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 68221#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68219#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 67779#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 66929#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66854#L601-39 assume 1 == ~t3_pc~0; 66791#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66711#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66709#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66706#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 66704#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66702#L620-39 assume 1 == ~t4_pc~0; 66691#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 66688#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66686#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66684#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66682#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66594#L639-39 assume !(1 == ~t5_pc~0); 66539#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 66536#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66534#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66533#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 66475#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66473#L658-39 assume 1 == ~t6_pc~0; 66471#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 66467#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66465#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 66393#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 66321#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66319#L677-39 assume !(1 == ~t7_pc~0); 66317#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 66313#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66312#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66311#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 66309#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66307#L696-39 assume 1 == ~t8_pc~0; 66301#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 66299#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66205#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66203#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66200#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66198#L715-39 assume !(1 == ~t9_pc~0); 66197#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 66194#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66192#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66190#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 66187#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66185#L734-39 assume !(1 == ~t10_pc~0); 66183#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 66180#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66178#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 66176#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 66173#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 66171#L753-39 assume !(1 == ~t11_pc~0); 66109#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 66106#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66104#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66102#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 66100#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66098#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 64938#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 66096#L1242-3 assume !(1 == ~T2_E~0); 65205#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 66095#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66094#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 66092#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 66090#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 66032#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 65976#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 65938#L1282-3 assume !(1 == ~T10_E~0); 65936#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 65897#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 65895#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 65893#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 65891#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 65889#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 65887#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 65883#L1322-3 assume !(1 == ~E_6~0); 65882#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 65881#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 65880#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 65879#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 65878#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 65877#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65843#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65839#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65814#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 65811#L1697 assume !(0 == start_simulation_~tmp~3#1); 65391#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65775#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65739#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65719#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 65697#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 65682#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 65672#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 65663#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 65655#L1678-2 [2024-11-13 15:57:43,107 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:43,107 INFO L85 PathProgramCache]: Analyzing trace with hash 602909556, now seen corresponding path program 1 times [2024-11-13 15:57:43,107 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:43,107 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225211666] [2024-11-13 15:57:43,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:43,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:43,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:43,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:43,178 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:43,178 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1225211666] [2024-11-13 15:57:43,179 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1225211666] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:43,179 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:43,179 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:57:43,179 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2122799419] [2024-11-13 15:57:43,180 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:43,180 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:43,180 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:43,180 INFO L85 PathProgramCache]: Analyzing trace with hash 1943778921, now seen corresponding path program 1 times [2024-11-13 15:57:43,180 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:43,180 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [980008746] [2024-11-13 15:57:43,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:43,181 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:43,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:43,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:43,237 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:43,237 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [980008746] [2024-11-13 15:57:43,237 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [980008746] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:43,237 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:43,237 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:43,237 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1197168313] [2024-11-13 15:57:43,237 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:43,238 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:43,238 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:43,238 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:43,238 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:43,238 INFO L87 Difference]: Start difference. First operand 10545 states and 15421 transitions. cyclomatic complexity: 4884 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:43,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:43,468 INFO L93 Difference]: Finished difference Result 20729 states and 30102 transitions. [2024-11-13 15:57:43,468 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20729 states and 30102 transitions. [2024-11-13 15:57:43,649 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20471 [2024-11-13 15:57:43,732 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20729 states to 20729 states and 30102 transitions. [2024-11-13 15:57:43,732 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20729 [2024-11-13 15:57:43,754 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20729 [2024-11-13 15:57:43,754 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20729 states and 30102 transitions. [2024-11-13 15:57:43,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:43,784 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20729 states and 30102 transitions. [2024-11-13 15:57:43,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20729 states and 30102 transitions. [2024-11-13 15:57:44,167 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20729 to 20065. [2024-11-13 15:57:44,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20065 states, 20065 states have (on average 1.4535758783952155) internal successors, (29166), 20064 states have internal predecessors, (29166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:44,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20065 states to 20065 states and 29166 transitions. [2024-11-13 15:57:44,282 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20065 states and 29166 transitions. [2024-11-13 15:57:44,282 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:44,282 INFO L424 stractBuchiCegarLoop]: Abstraction has 20065 states and 29166 transitions. [2024-11-13 15:57:44,283 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 15:57:44,283 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20065 states and 29166 transitions. [2024-11-13 15:57:44,390 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19807 [2024-11-13 15:57:44,390 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:44,390 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:44,393 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:44,393 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:44,393 INFO L745 eck$LassoCheckResult]: Stem: 95518#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 95519#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 96354#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 96355#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95492#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 95493#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96895#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 96847#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96848#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95863#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95864#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 96310#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 96802#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 95764#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 95765#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 95650#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 95651#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96713#L1109 assume !(0 == ~M_E~0); 96737#L1109-2 assume !(0 == ~T1_E~0); 95659#L1114-1 assume !(0 == ~T2_E~0); 95660#L1119-1 assume !(0 == ~T3_E~0); 96805#L1124-1 assume !(0 == ~T4_E~0); 95305#L1129-1 assume !(0 == ~T5_E~0); 95306#L1134-1 assume !(0 == ~T6_E~0); 95956#L1139-1 assume !(0 == ~T7_E~0); 96724#L1144-1 assume !(0 == ~T8_E~0); 96566#L1149-1 assume !(0 == ~T9_E~0); 95416#L1154-1 assume !(0 == ~T10_E~0); 95417#L1159-1 assume !(0 == ~T11_E~0); 96556#L1164-1 assume !(0 == ~E_M~0); 95824#L1169-1 assume !(0 == ~E_1~0); 95713#L1174-1 assume !(0 == ~E_2~0); 95573#L1179-1 assume !(0 == ~E_3~0); 95498#L1184-1 assume !(0 == ~E_4~0); 95499#L1189-1 assume !(0 == ~E_5~0); 95532#L1194-1 assume !(0 == ~E_6~0); 95616#L1199-1 assume !(0 == ~E_7~0); 96575#L1204-1 assume !(0 == ~E_8~0); 96507#L1209-1 assume !(0 == ~E_9~0); 96508#L1214-1 assume !(0 == ~E_10~0); 96917#L1219-1 assume !(0 == ~E_11~0); 97087#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95841#L544 assume !(1 == ~m_pc~0); 95842#L544-2 is_master_triggered_~__retres1~0#1 := 0; 96788#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96219#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 95458#L1379 assume !(0 != activate_threads_~tmp~1#1); 95459#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96293#L563 assume !(1 == ~t1_pc~0); 96083#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 95315#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95316#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 96448#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 95311#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95312#L582 assume 1 == ~t2_pc~0; 96060#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 96454#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95655#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95656#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 95344#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95345#L601 assume !(1 == ~t3_pc~0); 96078#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 96077#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 96598#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 96490#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 96491#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96433#L620 assume 1 == ~t4_pc~0; 95325#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 95326#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95358#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 95359#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 96304#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96528#L639 assume 1 == ~t5_pc~0; 96398#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 95621#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95622#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 96330#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 96331#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 96254#L658 assume !(1 == ~t6_pc~0); 95838#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 95839#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95647#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 95648#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 96494#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 95670#L677 assume 1 == ~t7_pc~0; 95671#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 95565#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 96680#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 96835#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 96836#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96950#L696 assume !(1 == ~t8_pc~0); 95906#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 95907#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96892#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 96953#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 97034#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 96383#L715 assume 1 == ~t9_pc~0; 96384#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 96012#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 95711#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 95712#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 96361#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 96675#L734 assume !(1 == ~t10_pc~0); 96676#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 95794#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 95795#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 96603#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 96604#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 95878#L753 assume 1 == ~t11_pc~0; 95879#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 96500#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 96906#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 96171#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 96172#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96226#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 96227#L1237-2 assume !(1 == ~T1_E~0); 100196#L1242-1 assume !(1 == ~T2_E~0); 100194#L1247-1 assume !(1 == ~T3_E~0); 100192#L1252-1 assume !(1 == ~T4_E~0); 100190#L1257-1 assume !(1 == ~T5_E~0); 100188#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 96825#L1267-1 assume !(1 == ~T7_E~0); 96826#L1272-1 assume !(1 == ~T8_E~0); 96072#L1277-1 assume !(1 == ~T9_E~0); 96073#L1282-1 assume !(1 == ~T10_E~0); 96540#L1287-1 assume !(1 == ~T11_E~0); 96541#L1292-1 assume !(1 == ~E_M~0); 96493#L1297-1 assume !(1 == ~E_1~0); 95868#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 95869#L1307-1 assume !(1 == ~E_3~0); 96809#L1312-1 assume !(1 == ~E_4~0); 96119#L1317-1 assume !(1 == ~E_5~0); 96120#L1322-1 assume !(1 == ~E_6~0); 95811#L1327-1 assume !(1 == ~E_7~0); 95812#L1332-1 assume !(1 == ~E_8~0); 97953#L1337-1 assume !(1 == ~E_9~0); 97936#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 97926#L1347-1 assume !(1 == ~E_11~0); 97917#L1352-1 assume { :end_inline_reset_delta_events } true; 97908#L1678-2 [2024-11-13 15:57:44,394 INFO L747 eck$LassoCheckResult]: Loop: 97908#L1678-2 assume !false; 97903#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 97900#L1084-1 assume !false; 97899#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 97887#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 97886#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 97885#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 97884#L925 assume !(0 != eval_~tmp~0#1); 97883#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 97882#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 97879#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 97880#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 99009#L1114-3 assume !(0 == ~T2_E~0); 99004#L1119-3 assume !(0 == ~T3_E~0); 98999#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 98993#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 98988#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 98983#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 98978#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 98973#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 98968#L1154-3 assume !(0 == ~T10_E~0); 98963#L1159-3 assume !(0 == ~T11_E~0); 98958#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 98952#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 98947#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 98942#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 98937#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 98931#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 98926#L1194-3 assume !(0 == ~E_6~0); 98920#L1199-3 assume !(0 == ~E_7~0); 98915#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 98910#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 98905#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 98899#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 98895#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 98890#L544-39 assume !(1 == ~m_pc~0); 98886#L544-41 is_master_triggered_~__retres1~0#1 := 0; 98881#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 98876#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 98870#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 98865#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 98859#L563-39 assume 1 == ~t1_pc~0; 98853#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 98848#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 98841#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 98835#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 98830#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 98824#L582-39 assume 1 == ~t2_pc~0; 98819#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 98813#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 98806#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 98800#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 98795#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98789#L601-39 assume !(1 == ~t3_pc~0); 98784#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 98778#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 98771#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 98765#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 98761#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 98756#L620-39 assume 1 == ~t4_pc~0; 98709#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 98706#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 98704#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 98702#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 98700#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 98697#L639-39 assume !(1 == ~t5_pc~0); 98695#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 98692#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 98690#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 98688#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 98686#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 98685#L658-39 assume !(1 == ~t6_pc~0); 98635#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 98627#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 98619#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 98610#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 98603#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 98596#L677-39 assume 1 == ~t7_pc~0; 98587#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 98579#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 98571#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 98562#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 98555#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 98548#L696-39 assume 1 == ~t8_pc~0; 98539#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 98532#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 98526#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 98518#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 98412#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 98409#L715-39 assume !(1 == ~t9_pc~0); 98407#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 98404#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 98402#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 98400#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 98398#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 98395#L734-39 assume 1 == ~t10_pc~0; 98391#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 98389#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 98387#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 98385#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 98382#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 98327#L753-39 assume !(1 == ~t11_pc~0); 98323#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 98313#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 98303#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 98294#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 98285#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 98276#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 98266#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 98253#L1242-3 assume !(1 == ~T2_E~0); 98247#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 98242#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 98237#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 98232#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 98227#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 98222#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 98216#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 98209#L1282-3 assume !(1 == ~T10_E~0); 98206#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 98203#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 98200#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 98197#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 98193#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 98190#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 98187#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 98183#L1322-3 assume !(1 == ~E_6~0); 98181#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 98179#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 98176#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 98174#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 98172#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 98171#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 98160#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 98156#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 98152#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 98150#L1697 assume !(0 == start_simulation_~tmp~3#1); 97837#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 98146#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 98137#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 98135#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 97952#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 97935#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 97925#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 97916#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 97908#L1678-2 [2024-11-13 15:57:44,394 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:44,394 INFO L85 PathProgramCache]: Analyzing trace with hash -1258502475, now seen corresponding path program 1 times [2024-11-13 15:57:44,394 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:44,394 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [731701191] [2024-11-13 15:57:44,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:44,395 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:44,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:44,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:44,573 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:44,573 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [731701191] [2024-11-13 15:57:44,573 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [731701191] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:44,573 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:44,573 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:57:44,573 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [439991596] [2024-11-13 15:57:44,573 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:44,574 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:44,574 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:44,574 INFO L85 PathProgramCache]: Analyzing trace with hash 1288808936, now seen corresponding path program 1 times [2024-11-13 15:57:44,574 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:44,574 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1698664578] [2024-11-13 15:57:44,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:44,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:44,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:44,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:44,715 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:44,715 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1698664578] [2024-11-13 15:57:44,715 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1698664578] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:44,715 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:44,715 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:57:44,715 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1742337241] [2024-11-13 15:57:44,715 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:44,715 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:44,715 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:44,716 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:44,716 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:44,716 INFO L87 Difference]: Start difference. First operand 20065 states and 29166 transitions. cyclomatic complexity: 9117 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:45,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:45,029 INFO L93 Difference]: Finished difference Result 38325 states and 55428 transitions. [2024-11-13 15:57:45,029 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38325 states and 55428 transitions. [2024-11-13 15:57:45,182 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 38020 [2024-11-13 15:57:45,337 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38325 states to 38325 states and 55428 transitions. [2024-11-13 15:57:45,337 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38325 [2024-11-13 15:57:45,383 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38325 [2024-11-13 15:57:45,384 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38325 states and 55428 transitions. [2024-11-13 15:57:45,442 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:45,442 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38325 states and 55428 transitions. [2024-11-13 15:57:45,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38325 states and 55428 transitions. [2024-11-13 15:57:46,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38325 to 38293. [2024-11-13 15:57:46,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38293 states, 38293 states have (on average 1.446635155250307) internal successors, (55396), 38292 states have internal predecessors, (55396), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:46,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38293 states to 38293 states and 55396 transitions. [2024-11-13 15:57:46,445 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38293 states and 55396 transitions. [2024-11-13 15:57:46,446 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:46,446 INFO L424 stractBuchiCegarLoop]: Abstraction has 38293 states and 55396 transitions. [2024-11-13 15:57:46,446 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 15:57:46,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38293 states and 55396 transitions. [2024-11-13 15:57:46,553 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 37988 [2024-11-13 15:57:46,554 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:46,554 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:46,556 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:46,556 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:46,556 INFO L745 eck$LassoCheckResult]: Stem: 153917#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 153918#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 154720#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 154721#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 153891#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 153892#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 155235#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 155192#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 155193#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 154253#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 154254#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 154686#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 155143#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 154159#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 154160#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 154047#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 154048#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 155051#L1109 assume !(0 == ~M_E~0); 155077#L1109-2 assume !(0 == ~T1_E~0); 154056#L1114-1 assume !(0 == ~T2_E~0); 154057#L1119-1 assume !(0 == ~T3_E~0); 155147#L1124-1 assume !(0 == ~T4_E~0); 153704#L1129-1 assume !(0 == ~T5_E~0); 153705#L1134-1 assume !(0 == ~T6_E~0); 154342#L1139-1 assume !(0 == ~T7_E~0); 155064#L1144-1 assume !(0 == ~T8_E~0); 154910#L1149-1 assume !(0 == ~T9_E~0); 153817#L1154-1 assume !(0 == ~T10_E~0); 153818#L1159-1 assume !(0 == ~T11_E~0); 154900#L1164-1 assume !(0 == ~E_M~0); 154216#L1169-1 assume !(0 == ~E_1~0); 154109#L1174-1 assume !(0 == ~E_2~0); 153975#L1179-1 assume !(0 == ~E_3~0); 153897#L1184-1 assume !(0 == ~E_4~0); 153898#L1189-1 assume !(0 == ~E_5~0); 153930#L1194-1 assume !(0 == ~E_6~0); 154017#L1199-1 assume !(0 == ~E_7~0); 154919#L1204-1 assume !(0 == ~E_8~0); 154856#L1209-1 assume !(0 == ~E_9~0); 154857#L1214-1 assume !(0 == ~E_10~0); 155252#L1219-1 assume !(0 == ~E_11~0); 155387#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 154235#L544 assume !(1 == ~m_pc~0); 154236#L544-2 is_master_triggered_~__retres1~0#1 := 0; 155124#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 154600#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 153860#L1379 assume !(0 != activate_threads_~tmp~1#1); 153861#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 154672#L563 assume !(1 == ~t1_pc~0); 154467#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 153714#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 153715#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 154801#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 153710#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 153711#L582 assume !(1 == ~t2_pc~0); 154444#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 154806#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 154052#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 154053#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 153743#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 153744#L601 assume !(1 == ~t3_pc~0); 154462#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 154461#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 154942#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 154838#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 154839#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 154787#L620 assume 1 == ~t4_pc~0; 153726#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 153727#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 153757#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 153758#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 154681#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 154877#L639 assume 1 == ~t5_pc~0; 154758#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 154020#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 154021#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 154704#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 154705#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 154635#L658 assume !(1 == ~t6_pc~0); 154230#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 154231#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 154044#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 154045#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 154843#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 154069#L677 assume 1 == ~t7_pc~0; 154070#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 153966#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 155021#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 155180#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 155181#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 155274#L696 assume !(1 == ~t8_pc~0); 154293#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 154294#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 155233#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 155277#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 155347#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 154745#L715 assume 1 == ~t9_pc~0; 154746#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 154397#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 154107#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 154108#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 154726#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 155018#L734 assume !(1 == ~t10_pc~0); 155019#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 154186#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 154187#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 154946#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 154947#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 154267#L753 assume 1 == ~t11_pc~0; 154268#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 154848#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 155245#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 154557#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 154558#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 154609#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 154610#L1237-2 assume !(1 == ~T1_E~0); 159918#L1242-1 assume !(1 == ~T2_E~0); 159916#L1247-1 assume !(1 == ~T3_E~0); 159910#L1252-1 assume !(1 == ~T4_E~0); 159904#L1257-1 assume !(1 == ~T5_E~0); 158866#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 158864#L1267-1 assume !(1 == ~T7_E~0); 158861#L1272-1 assume !(1 == ~T8_E~0); 158859#L1277-1 assume !(1 == ~T9_E~0); 158857#L1282-1 assume !(1 == ~T10_E~0); 158855#L1287-1 assume !(1 == ~T11_E~0); 158853#L1292-1 assume !(1 == ~E_M~0); 158851#L1297-1 assume !(1 == ~E_1~0); 158849#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 158847#L1307-1 assume !(1 == ~E_3~0); 158845#L1312-1 assume !(1 == ~E_4~0); 158673#L1317-1 assume !(1 == ~E_5~0); 158671#L1322-1 assume !(1 == ~E_6~0); 158425#L1327-1 assume !(1 == ~E_7~0); 158412#L1332-1 assume !(1 == ~E_8~0); 158273#L1337-1 assume !(1 == ~E_9~0); 158227#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 158209#L1347-1 assume !(1 == ~E_11~0); 158198#L1352-1 assume { :end_inline_reset_delta_events } true; 158187#L1678-2 [2024-11-13 15:57:46,557 INFO L747 eck$LassoCheckResult]: Loop: 158187#L1678-2 assume !false; 158180#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 158176#L1084-1 assume !false; 158173#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 158148#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 158131#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 158126#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 158117#L925 assume !(0 != eval_~tmp~0#1); 158118#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 173185#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 173184#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 173183#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 173182#L1114-3 assume !(0 == ~T2_E~0); 173181#L1119-3 assume !(0 == ~T3_E~0); 173180#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 173179#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 173178#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 173177#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 173176#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 173175#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 173174#L1154-3 assume !(0 == ~T10_E~0); 173173#L1159-3 assume !(0 == ~T11_E~0); 173171#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 173169#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 173167#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 173165#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 173163#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 173161#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 173159#L1194-3 assume !(0 == ~E_6~0); 173158#L1199-3 assume !(0 == ~E_7~0); 173155#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 173153#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 173151#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 173149#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 173147#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 173145#L544-39 assume !(1 == ~m_pc~0); 173143#L544-41 is_master_triggered_~__retres1~0#1 := 0; 173141#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 173139#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 173137#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 173135#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 173133#L563-39 assume !(1 == ~t1_pc~0); 173130#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 173127#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 173125#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 173123#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 173121#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 173119#L582-39 assume !(1 == ~t2_pc~0); 173116#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 173114#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 173112#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 173110#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 173108#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 173106#L601-39 assume 1 == ~t3_pc~0; 173102#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 173100#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 173099#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 170391#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 170386#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 170381#L620-39 assume 1 == ~t4_pc~0; 170374#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 170367#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 170362#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 170355#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 170349#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 170343#L639-39 assume !(1 == ~t5_pc~0); 170336#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 170328#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 170322#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 170316#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 170310#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 170304#L658-39 assume !(1 == ~t6_pc~0); 170296#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 170289#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 170283#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 170276#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 170270#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 170264#L677-39 assume !(1 == ~t7_pc~0); 170256#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 170247#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 170241#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 170234#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 170228#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 170223#L696-39 assume 1 == ~t8_pc~0; 170215#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 170207#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 170200#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 170192#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 170185#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 170178#L715-39 assume !(1 == ~t9_pc~0); 170170#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 170161#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 170154#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 170148#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 170143#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 170138#L734-39 assume 1 == ~t10_pc~0; 170074#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 169785#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 166639#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 166638#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 166637#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 163646#L753-39 assume !(1 == ~t11_pc~0); 163642#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 163640#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 163638#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 163636#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 163634#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 163632#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 160485#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 163627#L1242-3 assume !(1 == ~T2_E~0); 163625#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 163622#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 163620#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 163618#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 162389#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 160482#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 160479#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 160075#L1282-3 assume !(1 == ~T10_E~0); 160073#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 160055#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 160049#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 160043#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 160037#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 160032#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 160025#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 160019#L1322-3 assume !(1 == ~E_6~0); 160017#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 159920#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 159919#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 159917#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 159911#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 159905#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 158887#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 158883#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 158881#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 158869#L1697 assume !(0 == start_simulation_~tmp~3#1); 158668#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 158421#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 158411#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 158272#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 158268#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 158226#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 158208#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 158197#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 158187#L1678-2 [2024-11-13 15:57:46,557 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:46,557 INFO L85 PathProgramCache]: Analyzing trace with hash 1819278198, now seen corresponding path program 1 times [2024-11-13 15:57:46,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:46,557 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2104674240] [2024-11-13 15:57:46,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:46,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:46,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:46,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:46,643 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:46,644 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2104674240] [2024-11-13 15:57:46,644 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2104674240] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:46,644 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:46,644 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:57:46,644 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1575657983] [2024-11-13 15:57:46,644 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:46,644 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:46,645 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:46,645 INFO L85 PathProgramCache]: Analyzing trace with hash 746151594, now seen corresponding path program 1 times [2024-11-13 15:57:46,645 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:46,645 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [704699943] [2024-11-13 15:57:46,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:46,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:46,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:46,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:46,737 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:46,737 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [704699943] [2024-11-13 15:57:46,738 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [704699943] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:46,738 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:46,738 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:57:46,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [446867965] [2024-11-13 15:57:46,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:46,738 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:46,738 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:46,739 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:46,739 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:46,739 INFO L87 Difference]: Start difference. First operand 38293 states and 55396 transitions. cyclomatic complexity: 17135 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:47,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:47,731 INFO L93 Difference]: Finished difference Result 73252 states and 105493 transitions. [2024-11-13 15:57:47,731 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73252 states and 105493 transitions. [2024-11-13 15:57:48,288 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 72820 [2024-11-13 15:57:48,702 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73252 states to 73252 states and 105493 transitions. [2024-11-13 15:57:48,702 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 73252 [2024-11-13 15:57:48,759 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 73252 [2024-11-13 15:57:48,759 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73252 states and 105493 transitions. [2024-11-13 15:57:48,838 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:48,838 INFO L218 hiAutomatonCegarLoop]: Abstraction has 73252 states and 105493 transitions. [2024-11-13 15:57:48,902 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73252 states and 105493 transitions. [2024-11-13 15:57:49,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73252 to 73188. [2024-11-13 15:57:49,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73188 states, 73188 states have (on average 1.440523036563371) internal successors, (105429), 73187 states have internal predecessors, (105429), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:50,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73188 states to 73188 states and 105429 transitions. [2024-11-13 15:57:50,120 INFO L240 hiAutomatonCegarLoop]: Abstraction has 73188 states and 105429 transitions. [2024-11-13 15:57:50,120 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:50,121 INFO L424 stractBuchiCegarLoop]: Abstraction has 73188 states and 105429 transitions. [2024-11-13 15:57:50,121 INFO L331 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-13 15:57:50,121 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73188 states and 105429 transitions. [2024-11-13 15:57:50,530 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 72756 [2024-11-13 15:57:50,530 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:50,530 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:50,533 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:50,533 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:50,534 INFO L745 eck$LassoCheckResult]: Stem: 265467#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 265468#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 266284#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 266285#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 265441#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 265442#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 266808#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 266770#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 266771#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 265808#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 265809#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 266242#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 266724#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 265711#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 265712#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 265598#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 265599#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 266641#L1109 assume !(0 == ~M_E~0); 266665#L1109-2 assume !(0 == ~T1_E~0); 265607#L1114-1 assume !(0 == ~T2_E~0); 265608#L1119-1 assume !(0 == ~T3_E~0); 266728#L1124-1 assume !(0 == ~T4_E~0); 265257#L1129-1 assume !(0 == ~T5_E~0); 265258#L1134-1 assume !(0 == ~T6_E~0); 265895#L1139-1 assume !(0 == ~T7_E~0); 266653#L1144-1 assume !(0 == ~T8_E~0); 266489#L1149-1 assume !(0 == ~T9_E~0); 265365#L1154-1 assume !(0 == ~T10_E~0); 265366#L1159-1 assume !(0 == ~T11_E~0); 266478#L1164-1 assume !(0 == ~E_M~0); 265770#L1169-1 assume !(0 == ~E_1~0); 265660#L1174-1 assume !(0 == ~E_2~0); 265522#L1179-1 assume !(0 == ~E_3~0); 265447#L1184-1 assume !(0 == ~E_4~0); 265448#L1189-1 assume !(0 == ~E_5~0); 265480#L1194-1 assume !(0 == ~E_6~0); 265565#L1199-1 assume !(0 == ~E_7~0); 266498#L1204-1 assume !(0 == ~E_8~0); 266432#L1209-1 assume !(0 == ~E_9~0); 266433#L1214-1 assume !(0 == ~E_10~0); 266827#L1219-1 assume !(0 == ~E_11~0); 266970#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 265788#L544 assume !(1 == ~m_pc~0); 265789#L544-2 is_master_triggered_~__retres1~0#1 := 0; 266709#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 266156#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 265408#L1379 assume !(0 != activate_threads_~tmp~1#1); 265409#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 266229#L563 assume !(1 == ~t1_pc~0); 266023#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 265267#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 265268#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 266371#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 265263#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 265264#L582 assume !(1 == ~t2_pc~0); 266001#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 266376#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 265603#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 265604#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 265293#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 265294#L601 assume !(1 == ~t3_pc~0); 266018#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 266017#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 266520#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 266413#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 266414#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 266356#L620 assume !(1 == ~t4_pc~0); 266357#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 265921#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 265307#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 265308#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 266238#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 266455#L639 assume 1 == ~t5_pc~0; 266325#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 265572#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 265573#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 266261#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 266262#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 266193#L658 assume !(1 == ~t6_pc~0); 265785#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 265786#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 265595#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 265596#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 266421#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 265618#L677 assume 1 == ~t7_pc~0; 265619#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 265515#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 266610#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 266757#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 266758#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 266859#L696 assume !(1 == ~t8_pc~0); 265848#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 265849#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 266806#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 266862#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 266929#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 266311#L715 assume 1 == ~t9_pc~0; 266312#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 265953#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 265658#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 265659#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 266291#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 266607#L734 assume !(1 == ~t10_pc~0); 266608#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 265739#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 265740#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 266525#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 266526#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 265821#L753 assume 1 == ~t11_pc~0; 265822#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 266426#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 266819#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 266109#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 266110#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 266163#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 266164#L1237-2 assume !(1 == ~T1_E~0); 266902#L1242-1 assume !(1 == ~T2_E~0); 266951#L1247-1 assume !(1 == ~T3_E~0); 272631#L1252-1 assume !(1 == ~T4_E~0); 272629#L1257-1 assume !(1 == ~T5_E~0); 272627#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 272625#L1267-1 assume !(1 == ~T7_E~0); 272623#L1272-1 assume !(1 == ~T8_E~0); 272621#L1277-1 assume !(1 == ~T9_E~0); 272619#L1282-1 assume !(1 == ~T10_E~0); 272617#L1287-1 assume !(1 == ~T11_E~0); 272614#L1292-1 assume !(1 == ~E_M~0); 272612#L1297-1 assume !(1 == ~E_1~0); 272611#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 272610#L1307-1 assume !(1 == ~E_3~0); 272609#L1312-1 assume !(1 == ~E_4~0); 272608#L1317-1 assume !(1 == ~E_5~0); 272595#L1322-1 assume !(1 == ~E_6~0); 271098#L1327-1 assume !(1 == ~E_7~0); 272592#L1332-1 assume !(1 == ~E_8~0); 272590#L1337-1 assume !(1 == ~E_9~0); 272588#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 272586#L1347-1 assume !(1 == ~E_11~0); 272585#L1352-1 assume { :end_inline_reset_delta_events } true; 272583#L1678-2 [2024-11-13 15:57:50,534 INFO L747 eck$LassoCheckResult]: Loop: 272583#L1678-2 assume !false; 272425#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 272420#L1084-1 assume !false; 272418#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 272389#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 272388#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 272387#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 272384#L925 assume !(0 != eval_~tmp~0#1); 272385#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 275585#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 275582#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 275580#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 275578#L1114-3 assume !(0 == ~T2_E~0); 275576#L1119-3 assume !(0 == ~T3_E~0); 275574#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 275572#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 275570#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 275568#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 275566#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 275564#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 275562#L1154-3 assume !(0 == ~T10_E~0); 275560#L1159-3 assume !(0 == ~T11_E~0); 275557#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 275555#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 275553#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 275551#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 275549#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 275547#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 275544#L1194-3 assume !(0 == ~E_6~0); 275542#L1199-3 assume !(0 == ~E_7~0); 275540#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 275538#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 275536#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 275534#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 275531#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 275529#L544-39 assume !(1 == ~m_pc~0); 275527#L544-41 is_master_triggered_~__retres1~0#1 := 0; 275525#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 275523#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 275521#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 275518#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 275516#L563-39 assume 1 == ~t1_pc~0; 275513#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 275511#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 275509#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 275507#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 275504#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 275502#L582-39 assume !(1 == ~t2_pc~0); 275500#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 275498#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 275496#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 275494#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 275491#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 275489#L601-39 assume 1 == ~t3_pc~0; 275486#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 275484#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 275482#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 275480#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 275477#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 275475#L620-39 assume !(1 == ~t4_pc~0); 275473#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 275471#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 275469#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 275468#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 275467#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 275466#L639-39 assume 1 == ~t5_pc~0; 275464#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 275463#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 275462#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 275461#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 275460#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 275459#L658-39 assume !(1 == ~t6_pc~0); 275457#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 275456#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 275455#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 275453#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 275451#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 275449#L677-39 assume 1 == ~t7_pc~0; 275446#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 275444#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 275442#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 275440#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 275437#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 275435#L696-39 assume 1 == ~t8_pc~0; 275432#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 275430#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 275428#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 275426#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 275424#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 275422#L715-39 assume !(1 == ~t9_pc~0); 275420#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 275417#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 275415#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 275413#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 275410#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 275408#L734-39 assume 1 == ~t10_pc~0; 275405#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 275403#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 275401#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 275399#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 275397#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 275395#L753-39 assume !(1 == ~t11_pc~0); 275392#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 275390#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 275388#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 275386#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 275383#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 275381#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 272721#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 273998#L1242-3 assume !(1 == ~T2_E~0); 273996#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 273994#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 273990#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 273988#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 273986#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 273984#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 273982#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 273975#L1282-3 assume !(1 == ~T10_E~0); 273973#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 273971#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 273969#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 273967#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 273965#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 273963#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 273961#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 272675#L1322-3 assume !(1 == ~E_6~0); 272672#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 272670#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 272668#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 272666#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 272664#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 272662#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 272641#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 272637#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 272635#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 272615#L1697 assume !(0 == start_simulation_~tmp~3#1); 272613#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 272604#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 272594#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 272593#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 272591#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 272589#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 272587#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 272584#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 272583#L1678-2 [2024-11-13 15:57:50,535 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:50,535 INFO L85 PathProgramCache]: Analyzing trace with hash -343701065, now seen corresponding path program 1 times [2024-11-13 15:57:50,535 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:50,535 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1019907945] [2024-11-13 15:57:50,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:50,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:50,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:50,623 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:50,623 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:50,623 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1019907945] [2024-11-13 15:57:50,623 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1019907945] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:50,623 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:50,623 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:57:50,623 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1272493696] [2024-11-13 15:57:50,624 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:50,624 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:50,624 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:50,624 INFO L85 PathProgramCache]: Analyzing trace with hash 308084840, now seen corresponding path program 1 times [2024-11-13 15:57:50,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:50,624 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [657014473] [2024-11-13 15:57:50,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:50,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:50,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:50,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:50,713 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:50,713 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [657014473] [2024-11-13 15:57:50,713 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [657014473] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:50,713 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:50,714 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:57:50,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1868338195] [2024-11-13 15:57:50,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:50,714 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:50,715 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:50,715 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:50,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:50,715 INFO L87 Difference]: Start difference. First operand 73188 states and 105429 transitions. cyclomatic complexity: 32305 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:51,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:51,385 INFO L93 Difference]: Finished difference Result 142687 states and 204526 transitions. [2024-11-13 15:57:51,385 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 142687 states and 204526 transitions. [2024-11-13 15:57:52,162 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 141936 [2024-11-13 15:57:52,702 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 142687 states to 142687 states and 204526 transitions. [2024-11-13 15:57:52,702 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 142687 [2024-11-13 15:57:52,777 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 142687 [2024-11-13 15:57:52,777 INFO L73 IsDeterministic]: Start isDeterministic. Operand 142687 states and 204526 transitions. [2024-11-13 15:57:52,894 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:52,894 INFO L218 hiAutomatonCegarLoop]: Abstraction has 142687 states and 204526 transitions. [2024-11-13 15:57:52,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142687 states and 204526 transitions. [2024-11-13 15:57:54,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142687 to 142559. [2024-11-13 15:57:54,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 142559 states, 142559 states have (on average 1.433778295302296) internal successors, (204398), 142558 states have internal predecessors, (204398), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:54,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142559 states to 142559 states and 204398 transitions. [2024-11-13 15:57:54,998 INFO L240 hiAutomatonCegarLoop]: Abstraction has 142559 states and 204398 transitions. [2024-11-13 15:57:54,998 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:54,999 INFO L424 stractBuchiCegarLoop]: Abstraction has 142559 states and 204398 transitions. [2024-11-13 15:57:54,999 INFO L331 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-13 15:57:54,999 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 142559 states and 204398 transitions. [2024-11-13 15:57:55,279 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 141808 [2024-11-13 15:57:55,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:55,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:55,280 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:55,281 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:55,281 INFO L745 eck$LassoCheckResult]: Stem: 481350#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 481351#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 482150#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 482151#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 481324#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 481325#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 482644#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 482609#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 482610#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 481688#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 481689#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 482114#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 482568#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 481593#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 481594#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 481481#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 481482#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 482475#L1109 assume !(0 == ~M_E~0); 482499#L1109-2 assume !(0 == ~T1_E~0); 481490#L1114-1 assume !(0 == ~T2_E~0); 481491#L1119-1 assume !(0 == ~T3_E~0); 482571#L1124-1 assume !(0 == ~T4_E~0); 481142#L1129-1 assume !(0 == ~T5_E~0); 481143#L1134-1 assume !(0 == ~T6_E~0); 481774#L1139-1 assume !(0 == ~T7_E~0); 482486#L1144-1 assume !(0 == ~T8_E~0); 482341#L1149-1 assume !(0 == ~T9_E~0); 481250#L1154-1 assume !(0 == ~T10_E~0); 481251#L1159-1 assume !(0 == ~T11_E~0); 482329#L1164-1 assume !(0 == ~E_M~0); 481651#L1169-1 assume !(0 == ~E_1~0); 481543#L1174-1 assume !(0 == ~E_2~0); 481406#L1179-1 assume !(0 == ~E_3~0); 481330#L1184-1 assume !(0 == ~E_4~0); 481331#L1189-1 assume !(0 == ~E_5~0); 481364#L1194-1 assume !(0 == ~E_6~0); 481449#L1199-1 assume !(0 == ~E_7~0); 482350#L1204-1 assume !(0 == ~E_8~0); 482285#L1209-1 assume !(0 == ~E_9~0); 482286#L1214-1 assume !(0 == ~E_10~0); 482660#L1219-1 assume !(0 == ~E_11~0); 482778#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 481668#L544 assume !(1 == ~m_pc~0); 481669#L544-2 is_master_triggered_~__retres1~0#1 := 0; 482553#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 482023#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 481292#L1379 assume !(0 != activate_threads_~tmp~1#1); 481293#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 482098#L563 assume !(1 == ~t1_pc~0); 481896#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 481152#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 481153#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 482232#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 481148#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 481149#L582 assume !(1 == ~t2_pc~0); 481875#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 482239#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 481486#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 481487#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 481178#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 481179#L601 assume !(1 == ~t3_pc~0); 481891#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 481890#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 482371#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 482270#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 482271#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 482217#L620 assume !(1 == ~t4_pc~0); 482218#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 481798#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 481192#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 481193#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 482109#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 482305#L639 assume !(1 == ~t5_pc~0); 482306#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 481454#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 481455#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 482132#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 482133#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 482063#L658 assume !(1 == ~t6_pc~0); 481665#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 481666#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 481478#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 481479#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 482274#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 481501#L677 assume 1 == ~t7_pc~0; 481502#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 481398#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 482446#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 482598#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 482599#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 482685#L696 assume !(1 == ~t8_pc~0); 481727#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 481728#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 482642#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 482688#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 482743#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 482176#L715 assume 1 == ~t9_pc~0; 482177#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 481828#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 481541#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 481542#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 482157#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 482441#L734 assume !(1 == ~t10_pc~0); 482442#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 481621#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 481622#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 482375#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 482376#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 481702#L753 assume 1 == ~t11_pc~0; 481703#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 482279#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 482652#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 481979#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 481980#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 482030#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 482031#L1237-2 assume !(1 == ~T1_E~0); 482766#L1242-1 assume !(1 == ~T2_E~0); 481795#L1247-1 assume !(1 == ~T3_E~0); 481796#L1252-1 assume !(1 == ~T4_E~0); 481560#L1257-1 assume !(1 == ~T5_E~0); 481561#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 482463#L1267-1 assume !(1 == ~T7_E~0); 482590#L1272-1 assume !(1 == ~T8_E~0); 481885#L1277-1 assume !(1 == ~T9_E~0); 481886#L1282-1 assume !(1 == ~T10_E~0); 482316#L1287-1 assume !(1 == ~T11_E~0); 482317#L1292-1 assume !(1 == ~E_M~0); 482273#L1297-1 assume !(1 == ~E_1~0); 481693#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 481694#L1307-1 assume !(1 == ~E_3~0); 482576#L1312-1 assume !(1 == ~E_4~0); 481931#L1317-1 assume !(1 == ~E_5~0); 481932#L1322-1 assume !(1 == ~E_6~0); 481638#L1327-1 assume !(1 == ~E_7~0); 481639#L1332-1 assume !(1 == ~E_8~0); 482231#L1337-1 assume !(1 == ~E_9~0); 482161#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 482162#L1347-1 assume !(1 == ~E_11~0); 482574#L1352-1 assume { :end_inline_reset_delta_events } true; 482575#L1678-2 [2024-11-13 15:57:55,281 INFO L747 eck$LassoCheckResult]: Loop: 482575#L1678-2 assume !false; 524254#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 524250#L1084-1 assume !false; 524248#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 524220#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 524217#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 524215#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 524212#L925 assume !(0 != eval_~tmp~0#1); 524213#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 552610#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 552609#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 552608#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 552607#L1114-3 assume !(0 == ~T2_E~0); 552606#L1119-3 assume !(0 == ~T3_E~0); 552605#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 552604#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 552603#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 552602#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 552601#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 552600#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 552599#L1154-3 assume !(0 == ~T10_E~0); 552598#L1159-3 assume !(0 == ~T11_E~0); 552597#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 552596#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 552595#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 552594#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 552593#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 552592#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 552591#L1194-3 assume !(0 == ~E_6~0); 552590#L1199-3 assume !(0 == ~E_7~0); 552589#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 552588#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 552587#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 552586#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 552585#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 552584#L544-39 assume !(1 == ~m_pc~0); 552583#L544-41 is_master_triggered_~__retres1~0#1 := 0; 552582#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 552581#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 552580#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 552579#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 552578#L563-39 assume 1 == ~t1_pc~0; 552576#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 552575#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 552574#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 552573#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 552572#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 552571#L582-39 assume !(1 == ~t2_pc~0); 552570#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 552569#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 552568#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 552567#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 552566#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 552565#L601-39 assume 1 == ~t3_pc~0; 552563#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 552562#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 552561#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 552560#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 552559#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 552558#L620-39 assume !(1 == ~t4_pc~0); 552557#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 552556#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 552555#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 552554#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 552553#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 552552#L639-39 assume !(1 == ~t5_pc~0); 552551#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 552550#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 552549#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 552548#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 552547#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 552546#L658-39 assume !(1 == ~t6_pc~0); 552544#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 552543#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 552542#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 552541#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 552540#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 552539#L677-39 assume 1 == ~t7_pc~0; 552537#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 552536#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 552535#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 552534#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 552533#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 552532#L696-39 assume 1 == ~t8_pc~0; 552530#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 552529#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 552528#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 552527#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 552526#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 552525#L715-39 assume 1 == ~t9_pc~0; 552523#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 552522#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 552521#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 552520#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 552519#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 552518#L734-39 assume 1 == ~t10_pc~0; 552516#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 552515#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 552514#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 552513#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 552512#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 552511#L753-39 assume !(1 == ~t11_pc~0); 552509#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 552508#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 552507#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 552506#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 552505#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 552504#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 498101#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 552503#L1242-3 assume !(1 == ~T2_E~0); 498632#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 552502#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 552501#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 552500#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 552499#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 552497#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 552495#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 552492#L1282-3 assume !(1 == ~T10_E~0); 508487#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 552489#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 552487#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 552485#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 552483#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 552480#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 552478#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 552476#L1322-3 assume !(1 == ~E_6~0); 510664#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 552472#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 552468#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 552464#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 552461#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 552458#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 483095#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 483037#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 483027#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 483025#L1697 assume !(0 == start_simulation_~tmp~3#1); 483026#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 524408#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 524398#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 524395#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 524393#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 524391#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 524389#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 524387#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 482575#L1678-2 [2024-11-13 15:57:55,281 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:55,282 INFO L85 PathProgramCache]: Analyzing trace with hash 1793793208, now seen corresponding path program 1 times [2024-11-13 15:57:55,282 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:55,282 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1195640222] [2024-11-13 15:57:55,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:55,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:55,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:55,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:55,790 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:55,790 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1195640222] [2024-11-13 15:57:55,790 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1195640222] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:55,790 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:55,791 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:57:55,791 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1664741962] [2024-11-13 15:57:55,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:55,791 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:55,791 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:55,792 INFO L85 PathProgramCache]: Analyzing trace with hash 479186280, now seen corresponding path program 1 times [2024-11-13 15:57:55,792 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:55,792 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905475107] [2024-11-13 15:57:55,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:55,792 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:55,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:55,888 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:55,888 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:55,888 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [905475107] [2024-11-13 15:57:55,888 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [905475107] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:55,888 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:55,888 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:57:55,888 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [200913125] [2024-11-13 15:57:55,888 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:55,889 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:55,890 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:55,890 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:57:55,890 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:57:55,890 INFO L87 Difference]: Start difference. First operand 142559 states and 204398 transitions. cyclomatic complexity: 61967 Second operand has 5 states, 5 states have (on average 27.8) internal successors, (139), 5 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:56,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:56,675 INFO L93 Difference]: Finished difference Result 146738 states and 208577 transitions. [2024-11-13 15:57:56,675 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 146738 states and 208577 transitions. [2024-11-13 15:57:57,653 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 145984 [2024-11-13 15:57:58,098 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 146738 states to 146738 states and 208577 transitions. [2024-11-13 15:57:58,099 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 146738 [2024-11-13 15:57:58,191 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 146738 [2024-11-13 15:57:58,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 146738 states and 208577 transitions. [2024-11-13 15:57:58,297 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:58,297 INFO L218 hiAutomatonCegarLoop]: Abstraction has 146738 states and 208577 transitions. [2024-11-13 15:57:58,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146738 states and 208577 transitions. [2024-11-13 15:57:59,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146738 to 146738. [2024-11-13 15:57:59,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 146738 states, 146738 states have (on average 1.42142457986343) internal successors, (208577), 146737 states have internal predecessors, (208577), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:58:00,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146738 states to 146738 states and 208577 transitions. [2024-11-13 15:58:00,757 INFO L240 hiAutomatonCegarLoop]: Abstraction has 146738 states and 208577 transitions. [2024-11-13 15:58:00,757 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:58:00,758 INFO L424 stractBuchiCegarLoop]: Abstraction has 146738 states and 208577 transitions. [2024-11-13 15:58:00,758 INFO L331 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-13 15:58:00,758 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 146738 states and 208577 transitions. [2024-11-13 15:58:00,997 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 145984 [2024-11-13 15:58:00,997 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:58:00,997 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:58:00,998 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:58:00,998 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:58:00,999 INFO L745 eck$LassoCheckResult]: Stem: 770660#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 770661#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 771460#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 771461#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 770634#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 770635#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 771963#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 771928#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 771929#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 770997#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 770998#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 771425#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 771883#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 770900#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 770901#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 770788#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 770789#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 771792#L1109 assume !(0 == ~M_E~0); 771817#L1109-2 assume !(0 == ~T1_E~0); 770797#L1114-1 assume !(0 == ~T2_E~0); 770798#L1119-1 assume !(0 == ~T3_E~0); 771886#L1124-1 assume !(0 == ~T4_E~0); 770450#L1129-1 assume !(0 == ~T5_E~0); 770451#L1134-1 assume !(0 == ~T6_E~0); 771086#L1139-1 assume !(0 == ~T7_E~0); 771803#L1144-1 assume !(0 == ~T8_E~0); 771658#L1149-1 assume !(0 == ~T9_E~0); 770558#L1154-1 assume !(0 == ~T10_E~0); 770559#L1159-1 assume !(0 == ~T11_E~0); 771648#L1164-1 assume !(0 == ~E_M~0); 770959#L1169-1 assume !(0 == ~E_1~0); 770850#L1174-1 assume !(0 == ~E_2~0); 770713#L1179-1 assume !(0 == ~E_3~0); 770640#L1184-1 assume !(0 == ~E_4~0); 770641#L1189-1 assume !(0 == ~E_5~0); 770673#L1194-1 assume !(0 == ~E_6~0); 770754#L1199-1 assume !(0 == ~E_7~0); 771667#L1204-1 assume !(0 == ~E_8~0); 771600#L1209-1 assume !(0 == ~E_9~0); 771601#L1214-1 assume !(0 == ~E_10~0); 771980#L1219-1 assume !(0 == ~E_11~0); 772103#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 770977#L544 assume !(1 == ~m_pc~0); 770978#L544-2 is_master_triggered_~__retres1~0#1 := 0; 771868#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 771336#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 770602#L1379 assume !(0 != activate_threads_~tmp~1#1); 770603#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 771411#L563 assume !(1 == ~t1_pc~0); 771207#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 770460#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 770461#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 771547#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 770456#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 770457#L582 assume !(1 == ~t2_pc~0); 771186#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 771552#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 770793#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 770794#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 770486#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 770487#L601 assume !(1 == ~t3_pc~0); 771202#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 771201#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 771689#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 771584#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 771585#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 771532#L620 assume !(1 == ~t4_pc~0); 771533#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 771110#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 770500#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 770501#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 771422#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 771619#L639 assume !(1 == ~t5_pc~0); 771620#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 770759#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 770760#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 771443#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 771444#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 771372#L658 assume !(1 == ~t6_pc~0); 770974#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 770975#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 772122#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 772104#L1427 assume !(0 != activate_threads_~tmp___5~0#1); 771588#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 770808#L677 assume 1 == ~t7_pc~0; 770809#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 770706#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 771765#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 771917#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 771918#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 772003#L696 assume !(1 == ~t8_pc~0); 771037#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 771038#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 771961#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 772006#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 772069#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 771489#L715 assume 1 == ~t9_pc~0; 771490#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 771139#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 770848#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 770849#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 771467#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 771760#L734 assume !(1 == ~t10_pc~0); 771761#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 770929#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 770930#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 771693#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 771694#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 771011#L753 assume 1 == ~t11_pc~0; 771012#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 771594#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 771972#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 771292#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 771293#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 771343#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 771344#L1237-2 assume !(1 == ~T1_E~0); 772046#L1242-1 assume !(1 == ~T2_E~0); 772087#L1247-1 assume !(1 == ~T3_E~0); 783765#L1252-1 assume !(1 == ~T4_E~0); 783762#L1257-1 assume !(1 == ~T5_E~0); 783760#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 783758#L1267-1 assume !(1 == ~T7_E~0); 783756#L1272-1 assume !(1 == ~T8_E~0); 783754#L1277-1 assume !(1 == ~T9_E~0); 783752#L1282-1 assume !(1 == ~T10_E~0); 779628#L1287-1 assume !(1 == ~T11_E~0); 779626#L1292-1 assume !(1 == ~E_M~0); 779623#L1297-1 assume !(1 == ~E_1~0); 779621#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 779619#L1307-1 assume !(1 == ~E_3~0); 779617#L1312-1 assume !(1 == ~E_4~0); 779615#L1317-1 assume !(1 == ~E_5~0); 779613#L1322-1 assume !(1 == ~E_6~0); 779608#L1327-1 assume !(1 == ~E_7~0); 779606#L1332-1 assume !(1 == ~E_8~0); 779604#L1337-1 assume !(1 == ~E_9~0); 779602#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 779600#L1347-1 assume !(1 == ~E_11~0); 779598#L1352-1 assume { :end_inline_reset_delta_events } true; 779595#L1678-2 [2024-11-13 15:58:00,999 INFO L747 eck$LassoCheckResult]: Loop: 779595#L1678-2 assume !false; 779448#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 779444#L1084-1 assume !false; 779442#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 779415#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 779414#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 779413#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 779411#L925 assume !(0 != eval_~tmp~0#1); 779412#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 843840#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 843839#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 843838#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 843837#L1114-3 assume !(0 == ~T2_E~0); 843836#L1119-3 assume !(0 == ~T3_E~0); 843835#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 843834#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 843833#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 843832#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 843831#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 843830#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 843829#L1154-3 assume !(0 == ~T10_E~0); 843828#L1159-3 assume !(0 == ~T11_E~0); 843827#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 843826#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 843825#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 843824#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 843823#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 843822#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 843821#L1194-3 assume !(0 == ~E_6~0); 843820#L1199-3 assume !(0 == ~E_7~0); 843819#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 843818#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 843817#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 843816#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 843815#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 843814#L544-39 assume !(1 == ~m_pc~0); 843813#L544-41 is_master_triggered_~__retres1~0#1 := 0; 843812#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 843811#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 843810#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 843809#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 843808#L563-39 assume 1 == ~t1_pc~0; 843806#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 843805#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 843804#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 843803#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 843802#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 843801#L582-39 assume !(1 == ~t2_pc~0); 843800#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 843799#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 843798#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 843797#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 843796#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 843795#L601-39 assume 1 == ~t3_pc~0; 843793#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 843792#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 843791#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 843790#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 843789#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 843788#L620-39 assume !(1 == ~t4_pc~0); 843787#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 843786#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 843785#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 843784#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 843783#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 843782#L639-39 assume !(1 == ~t5_pc~0); 843781#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 843780#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 843779#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 843778#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 843777#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 843776#L658-39 assume 1 == ~t6_pc~0; 843774#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 843772#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 843770#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 843768#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 843767#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 843766#L677-39 assume 1 == ~t7_pc~0; 843764#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 843763#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 843762#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 843761#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 843760#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 843759#L696-39 assume 1 == ~t8_pc~0; 843757#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 843756#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 843755#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 843754#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 843753#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 843752#L715-39 assume 1 == ~t9_pc~0; 843750#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 843749#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 843748#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 843747#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 843746#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 843745#L734-39 assume 1 == ~t10_pc~0; 843743#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 843742#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 843741#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 843740#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 843739#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 843738#L753-39 assume !(1 == ~t11_pc~0); 843736#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 843735#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 843734#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 843733#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 843732#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 843731#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 792873#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 843730#L1242-3 assume !(1 == ~T2_E~0); 812985#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 843729#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 843728#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 843727#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 843726#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 843720#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 843714#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 843709#L1282-3 assume !(1 == ~T10_E~0); 807089#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 843700#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 843696#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 843692#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 843690#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 843686#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 843681#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 843676#L1322-3 assume !(1 == ~E_6~0); 800371#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 843668#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 843665#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 843661#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 843660#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 843659#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 772472#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 772456#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 772374#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 772362#L1697 assume !(0 == start_simulation_~tmp~3#1); 772363#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 783042#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 783033#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 783029#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 783027#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 783025#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 783022#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 779597#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 779595#L1678-2 [2024-11-13 15:58:00,999 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:58:00,999 INFO L85 PathProgramCache]: Analyzing trace with hash -1240256838, now seen corresponding path program 1 times [2024-11-13 15:58:00,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:58:01,000 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [111032327] [2024-11-13 15:58:01,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:58:01,000 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:58:01,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:58:01,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:58:01,092 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:58:01,092 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [111032327] [2024-11-13 15:58:01,092 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [111032327] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:58:01,092 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:58:01,093 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:58:01,093 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1871238203] [2024-11-13 15:58:01,093 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:58:01,093 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:58:01,093 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:58:01,094 INFO L85 PathProgramCache]: Analyzing trace with hash -1652801753, now seen corresponding path program 1 times [2024-11-13 15:58:01,094 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:58:01,094 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [17175474] [2024-11-13 15:58:01,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:58:01,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:58:01,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:58:01,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:58:01,144 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:58:01,144 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [17175474] [2024-11-13 15:58:01,144 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [17175474] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:58:01,144 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:58:01,144 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:58:01,144 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1239621884] [2024-11-13 15:58:01,144 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:58:01,145 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:58:01,145 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:58:01,145 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:58:01,145 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:58:01,146 INFO L87 Difference]: Start difference. First operand 146738 states and 208577 transitions. cyclomatic complexity: 61967 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:58:03,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:58:03,177 INFO L93 Difference]: Finished difference Result 406752 states and 573867 transitions. [2024-11-13 15:58:03,177 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 406752 states and 573867 transitions. [2024-11-13 15:58:05,614 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 403952 [2024-11-13 15:58:06,955 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 406752 states to 406752 states and 573867 transitions. [2024-11-13 15:58:06,955 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 406752 [2024-11-13 15:58:07,087 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 406752 [2024-11-13 15:58:07,088 INFO L73 IsDeterministic]: Start isDeterministic. Operand 406752 states and 573867 transitions. [2024-11-13 15:58:07,207 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:58:07,207 INFO L218 hiAutomatonCegarLoop]: Abstraction has 406752 states and 573867 transitions. [2024-11-13 15:58:07,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 406752 states and 573867 transitions. [2024-11-13 15:58:10,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 406752 to 401376. [2024-11-13 15:58:11,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 401376 states, 401376 states have (on average 1.4118905963485608) internal successors, (566699), 401375 states have internal predecessors, (566699), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:58:12,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 401376 states to 401376 states and 566699 transitions. [2024-11-13 15:58:12,003 INFO L240 hiAutomatonCegarLoop]: Abstraction has 401376 states and 566699 transitions. [2024-11-13 15:58:12,003 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:58:12,003 INFO L424 stractBuchiCegarLoop]: Abstraction has 401376 states and 566699 transitions. [2024-11-13 15:58:12,004 INFO L331 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-13 15:58:12,004 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 401376 states and 566699 transitions. [2024-11-13 15:58:13,782 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 399344 [2024-11-13 15:58:13,782 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:58:13,782 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:58:13,783 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:58:13,783 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:58:13,783 INFO L745 eck$LassoCheckResult]: Stem: 1324162#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1324163#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1324980#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1324981#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1324136#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 1324137#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1325507#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1325465#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1325466#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1324500#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1324501#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1324943#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1325420#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1324404#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1324405#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1324294#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1324295#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1325323#L1109 assume !(0 == ~M_E~0); 1325347#L1109-2 assume !(0 == ~T1_E~0); 1324303#L1114-1 assume !(0 == ~T2_E~0); 1324304#L1119-1 assume !(0 == ~T3_E~0); 1325423#L1124-1 assume !(0 == ~T4_E~0); 1323950#L1129-1 assume !(0 == ~T5_E~0); 1323951#L1134-1 assume !(0 == ~T6_E~0); 1324592#L1139-1 assume !(0 == ~T7_E~0); 1325335#L1144-1 assume !(0 == ~T8_E~0); 1325183#L1149-1 assume !(0 == ~T9_E~0); 1324061#L1154-1 assume !(0 == ~T10_E~0); 1324062#L1159-1 assume !(0 == ~T11_E~0); 1325172#L1164-1 assume !(0 == ~E_M~0); 1324460#L1169-1 assume !(0 == ~E_1~0); 1324354#L1174-1 assume !(0 == ~E_2~0); 1324221#L1179-1 assume !(0 == ~E_3~0); 1324142#L1184-1 assume !(0 == ~E_4~0); 1324143#L1189-1 assume !(0 == ~E_5~0); 1324175#L1194-1 assume !(0 == ~E_6~0); 1324265#L1199-1 assume !(0 == ~E_7~0); 1325192#L1204-1 assume !(0 == ~E_8~0); 1325128#L1209-1 assume !(0 == ~E_9~0); 1325129#L1214-1 assume !(0 == ~E_10~0); 1325526#L1219-1 assume !(0 == ~E_11~0); 1325684#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1324480#L544 assume !(1 == ~m_pc~0); 1324481#L544-2 is_master_triggered_~__retres1~0#1 := 0; 1325401#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1324848#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1324105#L1379 assume !(0 != activate_threads_~tmp~1#1); 1324106#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1324927#L563 assume !(1 == ~t1_pc~0); 1324718#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1323960#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1323961#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1325072#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 1323956#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1323957#L582 assume !(1 == ~t2_pc~0); 1324698#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1325077#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1324299#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1324300#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 1323986#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1323987#L601 assume !(1 == ~t3_pc~0); 1324784#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1324785#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1325214#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1325110#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 1325111#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1325051#L620 assume !(1 == ~t4_pc~0); 1325052#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1324618#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1324000#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1324001#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 1324937#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1325149#L639 assume !(1 == ~t5_pc~0); 1325150#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1324268#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1324269#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1324960#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 1324961#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1324888#L658 assume !(1 == ~t6_pc~0); 1324475#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1324476#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1325719#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1325690#L1427 assume !(0 != activate_threads_~tmp___5~0#1); 1325114#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1324316#L677 assume !(1 == ~t7_pc~0); 1324210#L677-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1324211#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1325293#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1325455#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 1325456#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1325551#L696 assume !(1 == ~t8_pc~0); 1324544#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1324545#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1325505#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1325556#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 1325630#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1325007#L715 assume 1 == ~t9_pc~0; 1325008#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1324649#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1324352#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1324353#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 1324986#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1325290#L734 assume !(1 == ~t10_pc~0); 1325291#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1324430#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1324431#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1325218#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 1325219#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1324514#L753 assume 1 == ~t11_pc~0; 1324515#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1325121#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1325519#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1324806#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 1324807#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1324858#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 1324859#L1237-2 assume !(1 == ~T1_E~0); 1325604#L1242-1 assume !(1 == ~T2_E~0); 1324614#L1247-1 assume !(1 == ~T3_E~0); 1324615#L1252-1 assume !(1 == ~T4_E~0); 1324371#L1257-1 assume !(1 == ~T5_E~0); 1324372#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1325308#L1267-1 assume !(1 == ~T7_E~0); 1325446#L1272-1 assume !(1 == ~T8_E~0); 1324710#L1277-1 assume !(1 == ~T9_E~0); 1324711#L1282-1 assume !(1 == ~T10_E~0); 1325159#L1287-1 assume !(1 == ~T11_E~0); 1325160#L1292-1 assume !(1 == ~E_M~0); 1325193#L1297-1 assume !(1 == ~E_1~0); 1433266#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1433264#L1307-1 assume !(1 == ~E_3~0); 1433262#L1312-1 assume !(1 == ~E_4~0); 1433259#L1317-1 assume !(1 == ~E_5~0); 1433257#L1322-1 assume !(1 == ~E_6~0); 1325000#L1327-1 assume !(1 == ~E_7~0); 1433229#L1332-1 assume !(1 == ~E_8~0); 1433222#L1337-1 assume !(1 == ~E_9~0); 1433214#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1325558#L1347-1 assume !(1 == ~E_11~0); 1325426#L1352-1 assume { :end_inline_reset_delta_events } true; 1325427#L1678-2 [2024-11-13 15:58:13,784 INFO L747 eck$LassoCheckResult]: Loop: 1325427#L1678-2 assume !false; 1461905#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1461901#L1084-1 assume !false; 1461899#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1461873#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1461871#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1461867#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1461864#L925 assume !(0 != eval_~tmp~0#1); 1461865#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1462209#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1462206#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1462204#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1462202#L1114-3 assume !(0 == ~T2_E~0); 1462200#L1119-3 assume !(0 == ~T3_E~0); 1462198#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1462196#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1462193#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1462191#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1462189#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1462187#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1462185#L1154-3 assume !(0 == ~T10_E~0); 1462181#L1159-3 assume !(0 == ~T11_E~0); 1462179#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1462177#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1462176#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1462175#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1462174#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1462173#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1462172#L1194-3 assume !(0 == ~E_6~0); 1462171#L1199-3 assume !(0 == ~E_7~0); 1462170#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1462169#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1462168#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1462167#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1462166#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1462165#L544-39 assume !(1 == ~m_pc~0); 1462164#L544-41 is_master_triggered_~__retres1~0#1 := 0; 1462163#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1462162#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1462160#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 1462159#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1462158#L563-39 assume 1 == ~t1_pc~0; 1462156#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1462155#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1462154#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1462152#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1462151#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1462150#L582-39 assume !(1 == ~t2_pc~0); 1462149#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1462148#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1462146#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1462144#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1462142#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1462140#L601-39 assume !(1 == ~t3_pc~0); 1462138#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 1462136#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1462134#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1462131#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1462129#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1462127#L620-39 assume !(1 == ~t4_pc~0); 1462125#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 1462123#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1462121#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1462119#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1462117#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1462115#L639-39 assume !(1 == ~t5_pc~0); 1462113#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1462111#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1462109#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1462107#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1462105#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1462103#L658-39 assume 1 == ~t6_pc~0; 1462101#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1462102#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1462153#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1462092#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1462090#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1462088#L677-39 assume !(1 == ~t7_pc~0); 1462086#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1462084#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1462082#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1462080#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 1462078#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1462076#L696-39 assume !(1 == ~t8_pc~0); 1462074#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 1462071#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1462067#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1462065#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1462063#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1462061#L715-39 assume !(1 == ~t9_pc~0); 1462058#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 1462055#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1462053#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1462051#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1462049#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1462047#L734-39 assume 1 == ~t10_pc~0; 1462044#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1462042#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1462040#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1462037#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1462035#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1462033#L753-39 assume !(1 == ~t11_pc~0); 1462030#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 1462028#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1462026#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1462023#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1462021#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1462019#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1399602#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1462016#L1242-3 assume !(1 == ~T2_E~0); 1416806#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1462012#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1462010#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1462008#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1462006#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1462004#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1462002#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1461999#L1282-3 assume !(1 == ~T10_E~0); 1421716#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1461996#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1461994#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1461992#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1461990#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1461988#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1461986#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1461984#L1322-3 assume !(1 == ~E_6~0); 1433549#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1461981#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1461979#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1461977#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1461975#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1461973#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1461952#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1461948#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1461946#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1461943#L1697 assume !(0 == start_simulation_~tmp~3#1); 1461942#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1461938#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1461927#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1461926#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 1461925#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1461922#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1461918#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1461914#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 1325427#L1678-2 [2024-11-13 15:58:13,784 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:58:13,785 INFO L85 PathProgramCache]: Analyzing trace with hash 1946581819, now seen corresponding path program 1 times [2024-11-13 15:58:13,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:58:13,785 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1338499387] [2024-11-13 15:58:13,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:58:13,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:58:13,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:58:13,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:58:13,856 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:58:13,856 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1338499387] [2024-11-13 15:58:13,856 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1338499387] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:58:13,856 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:58:13,856 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:58:13,856 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1949827159] [2024-11-13 15:58:13,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:58:13,857 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:58:13,857 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:58:13,857 INFO L85 PathProgramCache]: Analyzing trace with hash -755751317, now seen corresponding path program 1 times [2024-11-13 15:58:13,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:58:13,857 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [663142034] [2024-11-13 15:58:13,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:58:13,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:58:13,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:58:13,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:58:13,903 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:58:13,903 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [663142034] [2024-11-13 15:58:13,903 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [663142034] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:58:13,903 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:58:13,903 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:58:13,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [797596653] [2024-11-13 15:58:13,904 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:58:13,904 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:58:13,904 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:58:13,904 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:58:13,904 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:58:13,905 INFO L87 Difference]: Start difference. First operand 401376 states and 566699 transitions. cyclomatic complexity: 165579 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:58:17,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:58:17,275 INFO L93 Difference]: Finished difference Result 765695 states and 1077464 transitions. [2024-11-13 15:58:17,275 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 765695 states and 1077464 transitions.