./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.12.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3ee7a55a-2220-42fa-ac96-4028399ef8f4/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3ee7a55a-2220-42fa-ac96-4028399ef8f4/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3ee7a55a-2220-42fa-ac96-4028399ef8f4/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3ee7a55a-2220-42fa-ac96-4028399ef8f4/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.12.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3ee7a55a-2220-42fa-ac96-4028399ef8f4/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3ee7a55a-2220-42fa-ac96-4028399ef8f4/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bc6dc2c99e05b6915f0a2e5b5d96221c996d96767aaa6be997dea59c4d6f5f0a --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 15:56:53,549 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 15:56:53,667 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3ee7a55a-2220-42fa-ac96-4028399ef8f4/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 15:56:53,674 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 15:56:53,675 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 15:56:53,717 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 15:56:53,718 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 15:56:53,718 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 15:56:53,718 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 15:56:53,719 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 15:56:53,719 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 15:56:53,719 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 15:56:53,719 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 15:56:53,720 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 15:56:53,720 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 15:56:53,720 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 15:56:53,720 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 15:56:53,720 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 15:56:53,721 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 15:56:53,721 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 15:56:53,721 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 15:56:53,721 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 15:56:53,721 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 15:56:53,722 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 15:56:53,722 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 15:56:53,722 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 15:56:53,722 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 15:56:53,722 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 15:56:53,723 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 15:56:53,723 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 15:56:53,723 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 15:56:53,723 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 15:56:53,723 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 15:56:53,723 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 15:56:53,724 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 15:56:53,724 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 15:56:53,727 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 15:56:53,728 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 15:56:53,728 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 15:56:53,728 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3ee7a55a-2220-42fa-ac96-4028399ef8f4/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bc6dc2c99e05b6915f0a2e5b5d96221c996d96767aaa6be997dea59c4d6f5f0a [2024-11-13 15:56:54,061 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 15:56:54,078 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 15:56:54,083 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 15:56:54,085 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 15:56:54,086 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 15:56:54,088 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3ee7a55a-2220-42fa-ac96-4028399ef8f4/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/token_ring.12.cil-2.c Unable to find full path for "g++" [2024-11-13 15:56:56,359 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 15:56:56,753 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 15:56:56,754 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3ee7a55a-2220-42fa-ac96-4028399ef8f4/sv-benchmarks/c/systemc/token_ring.12.cil-2.c [2024-11-13 15:56:56,783 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3ee7a55a-2220-42fa-ac96-4028399ef8f4/bin/uautomizer-verify-qhAvR1uOyd/data/61247b238/34575bba2729425e8d820231df3fc5c6/FLAGaa6fb44f9 [2024-11-13 15:56:56,832 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3ee7a55a-2220-42fa-ac96-4028399ef8f4/bin/uautomizer-verify-qhAvR1uOyd/data/61247b238/34575bba2729425e8d820231df3fc5c6 [2024-11-13 15:56:56,835 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 15:56:56,838 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 15:56:56,839 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 15:56:56,839 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 15:56:56,844 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 15:56:56,844 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:56:56" (1/1) ... [2024-11-13 15:56:56,846 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@59c9407 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:56:56, skipping insertion in model container [2024-11-13 15:56:56,846 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:56:56" (1/1) ... [2024-11-13 15:56:56,894 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 15:56:57,273 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:56:57,292 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 15:56:57,423 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:56:57,455 INFO L204 MainTranslator]: Completed translation [2024-11-13 15:56:57,456 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:56:57 WrapperNode [2024-11-13 15:56:57,456 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 15:56:57,457 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 15:56:57,457 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 15:56:57,457 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 15:56:57,465 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:56:57" (1/1) ... [2024-11-13 15:56:57,477 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:56:57" (1/1) ... [2024-11-13 15:56:57,607 INFO L138 Inliner]: procedures = 52, calls = 68, calls flagged for inlining = 63, calls inlined = 270, statements flattened = 4146 [2024-11-13 15:56:57,608 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 15:56:57,608 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 15:56:57,609 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 15:56:57,609 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 15:56:57,625 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:56:57" (1/1) ... [2024-11-13 15:56:57,625 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:56:57" (1/1) ... [2024-11-13 15:56:57,637 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:56:57" (1/1) ... [2024-11-13 15:56:57,690 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 15:56:57,690 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:56:57" (1/1) ... [2024-11-13 15:56:57,690 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:56:57" (1/1) ... [2024-11-13 15:56:57,740 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:56:57" (1/1) ... [2024-11-13 15:56:57,805 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:56:57" (1/1) ... [2024-11-13 15:56:57,820 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:56:57" (1/1) ... [2024-11-13 15:56:57,837 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:56:57" (1/1) ... [2024-11-13 15:56:57,869 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 15:56:57,874 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 15:56:57,878 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 15:56:57,878 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 15:56:57,879 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:56:57" (1/1) ... [2024-11-13 15:56:57,891 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:56:57,911 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3ee7a55a-2220-42fa-ac96-4028399ef8f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:56:57,928 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3ee7a55a-2220-42fa-ac96-4028399ef8f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:56:57,934 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3ee7a55a-2220-42fa-ac96-4028399ef8f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 15:56:57,972 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 15:56:57,972 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 15:56:57,972 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 15:56:57,972 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 15:56:58,157 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 15:56:58,159 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 15:57:02,394 INFO L? ?]: Removed 882 outVars from TransFormulas that were not future-live. [2024-11-13 15:57:02,394 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 15:57:02,455 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 15:57:02,455 INFO L316 CfgBuilder]: Removed 15 assume(true) statements. [2024-11-13 15:57:02,456 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:57:02 BoogieIcfgContainer [2024-11-13 15:57:02,456 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 15:57:02,457 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 15:57:02,457 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 15:57:02,469 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 15:57:02,469 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:57:02,469 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 03:56:56" (1/3) ... [2024-11-13 15:57:02,471 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@29ee7248 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:57:02, skipping insertion in model container [2024-11-13 15:57:02,471 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:57:02,471 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:56:57" (2/3) ... [2024-11-13 15:57:02,471 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@29ee7248 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:57:02, skipping insertion in model container [2024-11-13 15:57:02,474 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:57:02,474 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:57:02" (3/3) ... [2024-11-13 15:57:02,476 INFO L333 chiAutomizerObserver]: Analyzing ICFG token_ring.12.cil-2.c [2024-11-13 15:57:02,606 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 15:57:02,606 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 15:57:02,607 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 15:57:02,607 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 15:57:02,607 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 15:57:02,608 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 15:57:02,608 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 15:57:02,608 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 15:57:02,628 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1805 states, 1804 states have (on average 1.4950110864745012) internal successors, (2697), 1804 states have internal predecessors, (2697), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:02,771 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 15:57:02,772 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:02,773 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:02,801 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:02,801 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:02,801 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 15:57:02,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1805 states, 1804 states have (on average 1.4950110864745012) internal successors, (2697), 1804 states have internal predecessors, (2697), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:02,851 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 15:57:02,851 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:02,851 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:02,865 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:02,866 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:02,880 INFO L745 eck$LassoCheckResult]: Stem: 117#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1720#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 685#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1718#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 151#L841true assume !(1 == ~m_i~0);~m_st~0 := 2; 558#L841-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 106#L846-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1737#L851-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1030#L856-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 457#L861-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 491#L866-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 392#L871-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 762#L876-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 753#L881-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1325#L886-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 251#L891-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1315#L896-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 517#L901-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1202#L1194true assume !(0 == ~M_E~0); 618#L1194-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 880#L1199-1true assume !(0 == ~T2_E~0); 1073#L1204-1true assume !(0 == ~T3_E~0); 803#L1209-1true assume !(0 == ~T4_E~0); 1362#L1214-1true assume !(0 == ~T5_E~0); 1753#L1219-1true assume !(0 == ~T6_E~0); 1673#L1224-1true assume !(0 == ~T7_E~0); 292#L1229-1true assume !(0 == ~T8_E~0); 68#L1234-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 505#L1239-1true assume !(0 == ~T10_E~0); 87#L1244-1true assume !(0 == ~T11_E~0); 1455#L1249-1true assume !(0 == ~T12_E~0); 479#L1254-1true assume !(0 == ~E_M~0); 39#L1259-1true assume !(0 == ~E_1~0); 22#L1264-1true assume !(0 == ~E_2~0); 1795#L1269-1true assume !(0 == ~E_3~0); 1723#L1274-1true assume 0 == ~E_4~0;~E_4~0 := 1; 1446#L1279-1true assume !(0 == ~E_5~0); 122#L1284-1true assume !(0 == ~E_6~0); 1580#L1289-1true assume !(0 == ~E_7~0); 523#L1294-1true assume !(0 == ~E_8~0); 530#L1299-1true assume !(0 == ~E_9~0); 1643#L1304-1true assume !(0 == ~E_10~0); 1684#L1309-1true assume !(0 == ~E_11~0); 1660#L1314-1true assume 0 == ~E_12~0;~E_12~0 := 1; 102#L1319-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67#L586true assume 1 == ~m_pc~0; 1237#L587true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 781#L597true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 571#is_master_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 199#L1485true assume !(0 != activate_threads_~tmp~1#1); 1041#L1485-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1743#L605true assume !(1 == ~t1_pc~0); 1191#L605-2true is_transmit1_triggered_~__retres1~1#1 := 0; 412#L616true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 933#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1354#L1493true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 855#L1493-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 356#L624true assume 1 == ~t2_pc~0; 89#L625true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 462#L635true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 213#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1436#L1501true assume !(0 != activate_threads_~tmp___1~0#1); 1095#L1501-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 930#L643true assume !(1 == ~t3_pc~0); 777#L643-2true is_transmit3_triggered_~__retres1~3#1 := 0; 542#L654true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 911#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 255#L1509true assume !(0 != activate_threads_~tmp___2~0#1); 1286#L1509-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 132#L662true assume 1 == ~t4_pc~0; 453#L663true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 113#L673true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 562#L1517true assume !(0 != activate_threads_~tmp___3~0#1); 61#L1517-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 378#L681true assume !(1 == ~t5_pc~0); 2#L681-2true is_transmit5_triggered_~__retres1~5#1 := 0; 600#L692true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1489#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1285#L1525true assume !(0 != activate_threads_~tmp___4~0#1); 262#L1525-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 732#L700true assume 1 == ~t6_pc~0; 1794#L701true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 128#L711true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 201#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 152#L1533true assume !(0 != activate_threads_~tmp___5~0#1); 1170#L1533-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1304#L719true assume 1 == ~t7_pc~0; 1597#L720true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1615#L730true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1738#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1408#L1541true assume !(0 != activate_threads_~tmp___6~0#1); 8#L1541-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1616#L738true assume !(1 == ~t8_pc~0); 887#L738-2true is_transmit8_triggered_~__retres1~8#1 := 0; 796#L749true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1433#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 616#L1549true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1214#L1549-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 952#L757true assume 1 == ~t9_pc~0; 1655#L758true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6#L768true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 235#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1068#L1557true assume !(0 != activate_threads_~tmp___8~0#1); 594#L1557-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1598#L776true assume !(1 == ~t10_pc~0); 1104#L776-2true is_transmit10_triggered_~__retres1~10#1 := 0; 202#L787true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1208#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 123#L1565true assume !(0 != activate_threads_~tmp___9~0#1); 770#L1565-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 103#L795true assume 1 == ~t11_pc~0; 273#L796true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1065#L806true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1347#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1336#L1573true assume !(0 != activate_threads_~tmp___10~0#1); 772#L1573-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 756#L814true assume !(1 == ~t12_pc~0); 910#L814-2true is_transmit12_triggered_~__retres1~12#1 := 0; 1004#L825true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1324#L1581true assume !(0 != activate_threads_~tmp___11~0#1); 228#L1581-2true havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1110#L1332true assume !(1 == ~M_E~0); 1498#L1332-2true assume !(1 == ~T1_E~0); 1532#L1337-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 697#L1342-1true assume !(1 == ~T3_E~0); 1440#L1347-1true assume !(1 == ~T4_E~0); 1152#L1352-1true assume !(1 == ~T5_E~0); 957#L1357-1true assume !(1 == ~T6_E~0); 391#L1362-1true assume !(1 == ~T7_E~0); 1224#L1367-1true assume !(1 == ~T8_E~0); 167#L1372-1true assume !(1 == ~T9_E~0); 496#L1377-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 342#L1382-1true assume !(1 == ~T11_E~0); 852#L1387-1true assume !(1 == ~T12_E~0); 1387#L1392-1true assume !(1 == ~E_M~0); 357#L1397-1true assume !(1 == ~E_1~0); 1504#L1402-1true assume !(1 == ~E_2~0); 175#L1407-1true assume !(1 == ~E_3~0); 1635#L1412-1true assume !(1 == ~E_4~0); 1064#L1417-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1806#L1422-1true assume !(1 == ~E_6~0); 1503#L1427-1true assume !(1 == ~E_7~0); 274#L1432-1true assume !(1 == ~E_8~0); 1393#L1437-1true assume !(1 == ~E_9~0); 995#L1442-1true assume !(1 == ~E_10~0); 1309#L1447-1true assume !(1 == ~E_11~0); 841#L1452-1true assume !(1 == ~E_12~0); 75#L1457-1true assume { :end_inline_reset_delta_events } true; 1441#L1803-2true [2024-11-13 15:57:02,884 INFO L747 eck$LassoCheckResult]: Loop: 1441#L1803-2true assume !false; 241#L1804true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 280#L1169-1true assume !true; 515#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 306#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 619#L1194-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1653#L1194-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 156#L1199-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 886#L1204-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 290#L1209-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 12#L1214-3true assume !(0 == ~T5_E~0); 681#L1219-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 411#L1224-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1801#L1229-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 429#L1234-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 91#L1239-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 323#L1244-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 716#L1249-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 1557#L1254-3true assume !(0 == ~E_M~0); 1355#L1259-3true assume 0 == ~E_1~0;~E_1~0 := 1; 827#L1264-3true assume 0 == ~E_2~0;~E_2~0 := 1; 94#L1269-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1621#L1274-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1439#L1279-3true assume 0 == ~E_5~0;~E_5~0 := 1; 410#L1284-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1494#L1289-3true assume 0 == ~E_7~0;~E_7~0 := 1; 397#L1294-3true assume !(0 == ~E_8~0); 1675#L1299-3true assume 0 == ~E_9~0;~E_9~0 := 1; 660#L1304-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1018#L1309-3true assume 0 == ~E_11~0;~E_11~0 := 1; 343#L1314-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1754#L1319-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 346#L586-42true assume 1 == ~m_pc~0; 1045#L587-14true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 127#L597-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 380#is_master_triggered_returnLabel#15true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1431#L1485-42true assume !(0 != activate_threads_~tmp~1#1); 425#L1485-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 895#L605-42true assume !(1 == ~t1_pc~0); 1759#L605-44true is_transmit1_triggered_~__retres1~1#1 := 0; 635#L616-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1651#is_transmit1_triggered_returnLabel#15true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 426#L1493-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 476#L1493-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 431#L624-42true assume !(1 == ~t2_pc~0); 528#L624-44true is_transmit2_triggered_~__retres1~2#1 := 0; 1450#L635-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 593#is_transmit2_triggered_returnLabel#15true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1702#L1501-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 322#L1501-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1297#L643-42true assume !(1 == ~t3_pc~0); 978#L643-44true is_transmit3_triggered_~__retres1~3#1 := 0; 516#L654-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 901#is_transmit3_triggered_returnLabel#15true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 407#L1509-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1005#L1509-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1321#L662-42true assume !(1 == ~t4_pc~0); 1374#L662-44true is_transmit4_triggered_~__retres1~4#1 := 0; 136#L673-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 976#is_transmit4_triggered_returnLabel#15true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1474#L1517-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1419#L1517-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1338#L681-42true assume !(1 == ~t5_pc~0); 73#L681-44true is_transmit5_triggered_~__retres1~5#1 := 0; 754#L692-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 655#is_transmit5_triggered_returnLabel#15true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1636#L1525-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1072#L1525-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 334#L700-42true assume !(1 == ~t6_pc~0); 221#L700-44true is_transmit6_triggered_~__retres1~6#1 := 0; 959#L711-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 181#is_transmit6_triggered_returnLabel#15true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1086#L1533-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1706#L1533-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1460#L719-42true assume !(1 == ~t7_pc~0); 162#L719-44true is_transmit7_triggered_~__retres1~7#1 := 0; 372#L730-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 670#is_transmit7_triggered_returnLabel#15true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 541#L1541-42true assume !(0 != activate_threads_~tmp___6~0#1); 381#L1541-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1445#L738-42true assume !(1 == ~t8_pc~0); 1211#L738-44true is_transmit8_triggered_~__retres1~8#1 := 0; 351#L749-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 785#is_transmit8_triggered_returnLabel#15true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 93#L1549-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 375#L1549-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1255#L757-42true assume 1 == ~t9_pc~0; 604#L758-14true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 182#L768-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1664#is_transmit9_triggered_returnLabel#15true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 643#L1557-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 245#L1557-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1044#L776-42true assume !(1 == ~t10_pc~0); 968#L776-44true is_transmit10_triggered_~__retres1~10#1 := 0; 1031#L787-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 773#is_transmit10_triggered_returnLabel#15true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1611#L1565-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1799#L1565-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 795#L795-42true assume 1 == ~t11_pc~0; 1463#L796-14true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 160#L806-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1412#is_transmit11_triggered_returnLabel#15true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 210#L1573-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 387#L1573-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1125#L814-42true assume 1 == ~t12_pc~0; 1047#L815-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 118#L825-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 637#is_transmit12_triggered_returnLabel#15true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26#L1581-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1755#L1581-44true havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100#L1332-3true assume 1 == ~M_E~0;~M_E~0 := 2; 713#L1332-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 88#L1337-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 563#L1342-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1039#L1347-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 688#L1352-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1204#L1357-3true assume !(1 == ~T6_E~0); 1793#L1362-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1658#L1367-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1625#L1372-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 19#L1377-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 433#L1382-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 332#L1387-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1001#L1392-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1713#L1397-3true assume !(1 == ~E_1~0); 1493#L1402-3true assume 1 == ~E_2~0;~E_2~0 := 2; 645#L1407-3true assume 1 == ~E_3~0;~E_3~0 := 2; 140#L1412-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1242#L1417-3true assume 1 == ~E_5~0;~E_5~0 := 2; 576#L1422-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1197#L1427-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1395#L1432-3true assume 1 == ~E_8~0;~E_8~0 := 2; 875#L1437-3true assume !(1 == ~E_9~0); 662#L1442-3true assume 1 == ~E_10~0;~E_10~0 := 2; 889#L1447-3true assume 1 == ~E_11~0;~E_11~0 := 2; 43#L1452-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1767#L1457-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 366#L914-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1404#L981-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 174#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 135#L1822true assume !(0 == start_simulation_~tmp~3#1); 745#L1822-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 771#L914-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 270#L981-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 20#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 704#L1777true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 798#L1784true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1241#stop_simulation_returnLabel#1true start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1249#L1835true assume !(0 != start_simulation_~tmp___0~1#1); 1441#L1803-2true [2024-11-13 15:57:02,892 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:02,892 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 1 times [2024-11-13 15:57:02,903 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:02,903 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1720383799] [2024-11-13 15:57:02,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:02,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:03,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:03,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:03,418 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:03,419 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1720383799] [2024-11-13 15:57:03,420 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1720383799] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:03,420 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:03,420 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:03,422 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2145322740] [2024-11-13 15:57:03,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:03,428 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:03,429 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:03,429 INFO L85 PathProgramCache]: Analyzing trace with hash 578114867, now seen corresponding path program 1 times [2024-11-13 15:57:03,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:03,429 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1470655198] [2024-11-13 15:57:03,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:03,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:03,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:03,596 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:03,597 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:03,597 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1470655198] [2024-11-13 15:57:03,598 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1470655198] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:03,598 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:03,598 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:57:03,599 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2022417260] [2024-11-13 15:57:03,599 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:03,602 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:03,603 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:03,642 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-13 15:57:03,643 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-13 15:57:03,651 INFO L87 Difference]: Start difference. First operand has 1805 states, 1804 states have (on average 1.4950110864745012) internal successors, (2697), 1804 states have internal predecessors, (2697), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:03,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:03,774 INFO L93 Difference]: Finished difference Result 1803 states and 2664 transitions. [2024-11-13 15:57:03,776 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1803 states and 2664 transitions. [2024-11-13 15:57:03,803 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:03,834 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1803 states to 1798 states and 2659 transitions. [2024-11-13 15:57:03,836 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2024-11-13 15:57:03,841 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2024-11-13 15:57:03,842 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2659 transitions. [2024-11-13 15:57:03,857 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:03,857 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2659 transitions. [2024-11-13 15:57:03,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2659 transitions. [2024-11-13 15:57:03,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2024-11-13 15:57:03,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.4788654060066742) internal successors, (2659), 1797 states have internal predecessors, (2659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:03,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2659 transitions. [2024-11-13 15:57:03,977 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2659 transitions. [2024-11-13 15:57:03,978 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-13 15:57:03,982 INFO L424 stractBuchiCegarLoop]: Abstraction has 1798 states and 2659 transitions. [2024-11-13 15:57:03,982 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 15:57:03,982 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2659 transitions. [2024-11-13 15:57:03,999 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:03,999 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:03,999 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:04,004 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:04,004 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:04,005 INFO L745 eck$LassoCheckResult]: Stem: 3859#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 3860#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 4794#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4795#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3929#L841 assume !(1 == ~m_i~0);~m_st~0 := 2; 3930#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3834#L846-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3835#L851-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5122#L856-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4475#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4476#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4367#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4368#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4876#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4877#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4126#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4127#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4561#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4562#L1194 assume !(0 == ~M_E~0); 4714#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4715#L1199-1 assume !(0 == ~T2_E~0); 5001#L1204-1 assume !(0 == ~T3_E~0); 4926#L1209-1 assume !(0 == ~T4_E~0); 4927#L1214-1 assume !(0 == ~T5_E~0); 5325#L1219-1 assume !(0 == ~T6_E~0); 5411#L1224-1 assume !(0 == ~T7_E~0); 4200#L1229-1 assume !(0 == ~T8_E~0); 3754#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3755#L1239-1 assume !(0 == ~T10_E~0); 3797#L1244-1 assume !(0 == ~T11_E~0); 3798#L1249-1 assume !(0 == ~T12_E~0); 4505#L1254-1 assume !(0 == ~E_M~0); 3696#L1259-1 assume !(0 == ~E_1~0); 3661#L1264-1 assume !(0 == ~E_2~0); 3662#L1269-1 assume !(0 == ~E_3~0); 5413#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 5357#L1279-1 assume !(0 == ~E_5~0); 3870#L1284-1 assume !(0 == ~E_6~0); 3871#L1289-1 assume !(0 == ~E_7~0); 4568#L1294-1 assume !(0 == ~E_8~0); 4569#L1299-1 assume !(0 == ~E_9~0); 4580#L1304-1 assume !(0 == ~E_10~0); 5404#L1309-1 assume !(0 == ~E_11~0); 5409#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 3827#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3751#L586 assume 1 == ~m_pc~0; 3752#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3819#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4640#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4026#L1485 assume !(0 != activate_threads_~tmp~1#1); 4027#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5128#L605 assume !(1 == ~t1_pc~0); 4654#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4396#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4397#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5040#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4975#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4304#L624 assume 1 == ~t2_pc~0; 3801#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3802#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4053#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4054#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 5160#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5038#L643 assume !(1 == ~t3_pc~0); 4896#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4598#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4599#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4133#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 4134#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3891#L662 assume 1 == ~t4_pc~0; 3892#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3850#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3713#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3714#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 3740#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3741#L681 assume !(1 == ~t5_pc~0); 3617#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3618#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4680#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5286#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 4145#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4146#L700 assume 1 == ~t6_pc~0; 4856#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3883#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3884#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3931#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 3932#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5214#L719 assume 1 == ~t7_pc~0; 5295#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4102#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5401#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5343#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 3631#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3632#L738 assume !(1 == ~t8_pc~0); 5008#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4917#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4918#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4710#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4711#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5060#L757 assume 1 == ~t9_pc~0; 5061#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3626#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3627#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4100#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 4672#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4673#L776 assume !(1 == ~t10_pc~0); 3648#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3647#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4030#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3872#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 3873#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3828#L795 assume 1 == ~t11_pc~0; 3829#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4165#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5142#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5313#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 4890#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4880#L814 assume !(1 == ~t12_pc~0); 4740#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4741#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3674#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3675#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 4084#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4085#L1332 assume !(1 == ~M_E~0); 5173#L1332-2 assume !(1 == ~T1_E~0); 5375#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4811#L1342-1 assume !(1 == ~T3_E~0); 4812#L1347-1 assume !(1 == ~T4_E~0); 5201#L1352-1 assume !(1 == ~T5_E~0); 5066#L1357-1 assume !(1 == ~T6_E~0); 4365#L1362-1 assume !(1 == ~T7_E~0); 4366#L1367-1 assume !(1 == ~T8_E~0); 3965#L1372-1 assume !(1 == ~T9_E~0); 3966#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4276#L1382-1 assume !(1 == ~T11_E~0); 4277#L1387-1 assume !(1 == ~T12_E~0); 4973#L1392-1 assume !(1 == ~E_M~0); 4305#L1397-1 assume !(1 == ~E_1~0); 4306#L1402-1 assume !(1 == ~E_2~0); 3980#L1407-1 assume !(1 == ~E_3~0); 3981#L1412-1 assume !(1 == ~E_4~0); 5140#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 5141#L1422-1 assume !(1 == ~E_6~0); 5377#L1427-1 assume !(1 == ~E_7~0); 4166#L1432-1 assume !(1 == ~E_8~0); 4167#L1437-1 assume !(1 == ~E_9~0); 5093#L1442-1 assume !(1 == ~E_10~0); 5094#L1447-1 assume !(1 == ~E_11~0); 4965#L1452-1 assume !(1 == ~E_12~0); 3771#L1457-1 assume { :end_inline_reset_delta_events } true; 3772#L1803-2 [2024-11-13 15:57:04,007 INFO L747 eck$LassoCheckResult]: Loop: 3772#L1803-2 assume !false; 4108#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4057#L1169-1 assume !false; 4177#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4347#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3836#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3837#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5181#L996 assume !(0 != eval_~tmp~0#1); 4558#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4222#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4223#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4716#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3939#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3940#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4196#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3640#L1214-3 assume !(0 == ~T5_E~0); 3641#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4394#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4395#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4429#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3807#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3808#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4245#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4835#L1254-3 assume !(0 == ~E_M~0); 5319#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4948#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3813#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3814#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5354#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4392#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4393#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4374#L1294-3 assume !(0 == ~E_8~0); 4375#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4767#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4768#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4278#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4279#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4284#L586-42 assume !(1 == ~m_pc~0); 4285#L586-44 is_master_triggered_~__retres1~0#1 := 0; 3881#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3882#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4348#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 4422#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4423#L605-42 assume 1 == ~t1_pc~0; 5013#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4733#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4734#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4424#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4425#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4433#L624-42 assume !(1 == ~t2_pc~0); 4434#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 4578#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4670#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4671#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4243#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4244#L643-42 assume 1 == ~t3_pc~0; 4602#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4559#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4560#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4389#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4390#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5103#L662-42 assume !(1 == ~t4_pc~0); 5306#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 3902#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3903#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5081#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5347#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5314#L681-42 assume 1 == ~t5_pc~0; 4612#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3768#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4760#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4761#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5149#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4262#L700-42 assume 1 == ~t6_pc~0; 4263#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4072#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3992#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3993#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5156#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5364#L719-42 assume !(1 == ~t7_pc~0); 3953#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 3954#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4334#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4597#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 4349#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4350#L738-42 assume 1 == ~t8_pc~0; 4548#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4293#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4294#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3811#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3812#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4343#L757-42 assume 1 == ~t9_pc~0; 4686#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3994#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3995#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4747#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4113#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4114#L776-42 assume !(1 == ~t10_pc~0); 5073#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 5074#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4891#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4892#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5399#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4914#L795-42 assume !(1 == ~t11_pc~0); 4915#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 3948#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3949#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4047#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4048#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4359#L814-42 assume !(1 == ~t12_pc~0); 4228#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 3861#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3862#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3669#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 3670#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3823#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3824#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3799#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3800#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4629#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4799#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4800#L1357-3 assume !(1 == ~T6_E~0); 5235#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5407#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5403#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3655#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3656#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4259#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4260#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5099#L1397-3 assume !(1 == ~E_1~0); 5374#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4749#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3907#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3908#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4649#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4650#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5232#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4994#L1437-3 assume !(1 == ~E_9~0); 4769#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4770#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3703#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 3704#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4322#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4163#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3979#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 3899#L1822 assume !(0 == start_simulation_~tmp~3#1); 3900#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4865#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4160#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3657#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 3658#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4821#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4920#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 5260#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 3772#L1803-2 [2024-11-13 15:57:04,007 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:04,008 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 2 times [2024-11-13 15:57:04,008 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:04,008 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1482852921] [2024-11-13 15:57:04,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:04,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:04,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:04,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:04,227 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:04,228 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1482852921] [2024-11-13 15:57:04,229 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1482852921] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:04,229 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:04,229 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:04,229 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1467718571] [2024-11-13 15:57:04,229 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:04,230 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:04,230 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:04,231 INFO L85 PathProgramCache]: Analyzing trace with hash 761407766, now seen corresponding path program 1 times [2024-11-13 15:57:04,231 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:04,231 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [209519404] [2024-11-13 15:57:04,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:04,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:04,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:04,425 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:04,425 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:04,425 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [209519404] [2024-11-13 15:57:04,425 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [209519404] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:04,426 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:04,426 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:04,426 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1380677015] [2024-11-13 15:57:04,426 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:04,427 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:04,427 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:04,427 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:04,428 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:04,428 INFO L87 Difference]: Start difference. First operand 1798 states and 2659 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:04,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:04,499 INFO L93 Difference]: Finished difference Result 1798 states and 2658 transitions. [2024-11-13 15:57:04,499 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2658 transitions. [2024-11-13 15:57:04,514 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:04,530 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2658 transitions. [2024-11-13 15:57:04,531 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2024-11-13 15:57:04,534 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2024-11-13 15:57:04,534 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2658 transitions. [2024-11-13 15:57:04,542 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:04,543 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2658 transitions. [2024-11-13 15:57:04,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2658 transitions. [2024-11-13 15:57:04,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2024-11-13 15:57:04,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.478309232480534) internal successors, (2658), 1797 states have internal predecessors, (2658), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:04,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2658 transitions. [2024-11-13 15:57:04,621 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2658 transitions. [2024-11-13 15:57:04,623 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:04,623 INFO L424 stractBuchiCegarLoop]: Abstraction has 1798 states and 2658 transitions. [2024-11-13 15:57:04,624 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 15:57:04,624 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2658 transitions. [2024-11-13 15:57:04,635 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:04,636 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:04,636 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:04,639 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:04,639 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:04,640 INFO L745 eck$LassoCheckResult]: Stem: 7462#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 7463#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 8397#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8398#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7532#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 7533#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7437#L846-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7438#L851-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8725#L856-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8078#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8079#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7970#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7971#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8479#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8480#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7729#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 7730#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8164#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8165#L1194 assume !(0 == ~M_E~0); 8317#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8318#L1199-1 assume !(0 == ~T2_E~0); 8604#L1204-1 assume !(0 == ~T3_E~0); 8529#L1209-1 assume !(0 == ~T4_E~0); 8530#L1214-1 assume !(0 == ~T5_E~0); 8928#L1219-1 assume !(0 == ~T6_E~0); 9014#L1224-1 assume !(0 == ~T7_E~0); 7803#L1229-1 assume !(0 == ~T8_E~0); 7357#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7358#L1239-1 assume !(0 == ~T10_E~0); 7400#L1244-1 assume !(0 == ~T11_E~0); 7401#L1249-1 assume !(0 == ~T12_E~0); 8108#L1254-1 assume !(0 == ~E_M~0); 7299#L1259-1 assume !(0 == ~E_1~0); 7264#L1264-1 assume !(0 == ~E_2~0); 7265#L1269-1 assume !(0 == ~E_3~0); 9016#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8960#L1279-1 assume !(0 == ~E_5~0); 7473#L1284-1 assume !(0 == ~E_6~0); 7474#L1289-1 assume !(0 == ~E_7~0); 8171#L1294-1 assume !(0 == ~E_8~0); 8172#L1299-1 assume !(0 == ~E_9~0); 8183#L1304-1 assume !(0 == ~E_10~0); 9007#L1309-1 assume !(0 == ~E_11~0); 9012#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 7430#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7354#L586 assume 1 == ~m_pc~0; 7355#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7422#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8243#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7629#L1485 assume !(0 != activate_threads_~tmp~1#1); 7630#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8731#L605 assume !(1 == ~t1_pc~0); 8257#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7999#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8000#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8643#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8578#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7907#L624 assume 1 == ~t2_pc~0; 7404#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7405#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7656#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7657#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 8763#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8641#L643 assume !(1 == ~t3_pc~0); 8499#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8201#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8202#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7736#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 7737#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7494#L662 assume 1 == ~t4_pc~0; 7495#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7453#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7316#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7317#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 7343#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7344#L681 assume !(1 == ~t5_pc~0); 7220#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7221#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8283#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8889#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 7748#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7749#L700 assume 1 == ~t6_pc~0; 8459#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7486#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7487#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7534#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 7535#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8817#L719 assume 1 == ~t7_pc~0; 8898#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7705#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9004#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8946#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 7234#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7235#L738 assume !(1 == ~t8_pc~0); 8611#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8520#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8521#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8313#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8314#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8663#L757 assume 1 == ~t9_pc~0; 8664#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7229#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7230#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7703#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 8275#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8276#L776 assume !(1 == ~t10_pc~0); 7251#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7250#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7633#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7475#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 7476#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7431#L795 assume 1 == ~t11_pc~0; 7432#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7768#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8745#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8916#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 8493#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8483#L814 assume !(1 == ~t12_pc~0); 8343#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8344#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7277#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7278#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 7687#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7688#L1332 assume !(1 == ~M_E~0); 8776#L1332-2 assume !(1 == ~T1_E~0); 8978#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8414#L1342-1 assume !(1 == ~T3_E~0); 8415#L1347-1 assume !(1 == ~T4_E~0); 8804#L1352-1 assume !(1 == ~T5_E~0); 8669#L1357-1 assume !(1 == ~T6_E~0); 7968#L1362-1 assume !(1 == ~T7_E~0); 7969#L1367-1 assume !(1 == ~T8_E~0); 7568#L1372-1 assume !(1 == ~T9_E~0); 7569#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7879#L1382-1 assume !(1 == ~T11_E~0); 7880#L1387-1 assume !(1 == ~T12_E~0); 8576#L1392-1 assume !(1 == ~E_M~0); 7908#L1397-1 assume !(1 == ~E_1~0); 7909#L1402-1 assume !(1 == ~E_2~0); 7583#L1407-1 assume !(1 == ~E_3~0); 7584#L1412-1 assume !(1 == ~E_4~0); 8743#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 8744#L1422-1 assume !(1 == ~E_6~0); 8980#L1427-1 assume !(1 == ~E_7~0); 7769#L1432-1 assume !(1 == ~E_8~0); 7770#L1437-1 assume !(1 == ~E_9~0); 8696#L1442-1 assume !(1 == ~E_10~0); 8697#L1447-1 assume !(1 == ~E_11~0); 8568#L1452-1 assume !(1 == ~E_12~0); 7374#L1457-1 assume { :end_inline_reset_delta_events } true; 7375#L1803-2 [2024-11-13 15:57:04,641 INFO L747 eck$LassoCheckResult]: Loop: 7375#L1803-2 assume !false; 7711#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7660#L1169-1 assume !false; 7780#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7950#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7439#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7440#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8784#L996 assume !(0 != eval_~tmp~0#1); 8161#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7825#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7826#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8319#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7542#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7543#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7799#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7243#L1214-3 assume !(0 == ~T5_E~0); 7244#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7997#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7998#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8032#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7410#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7411#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 7848#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8438#L1254-3 assume !(0 == ~E_M~0); 8922#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8551#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7416#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7417#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8957#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7995#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7996#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7977#L1294-3 assume !(0 == ~E_8~0); 7978#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8370#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8371#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7881#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 7882#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7887#L586-42 assume !(1 == ~m_pc~0); 7888#L586-44 is_master_triggered_~__retres1~0#1 := 0; 7484#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7485#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7951#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 8025#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8026#L605-42 assume 1 == ~t1_pc~0; 8616#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8336#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8337#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8027#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8028#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8036#L624-42 assume !(1 == ~t2_pc~0); 8037#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 8181#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8273#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8274#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7846#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7847#L643-42 assume 1 == ~t3_pc~0; 8205#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8162#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8163#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7992#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7993#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8706#L662-42 assume !(1 == ~t4_pc~0); 8909#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 7505#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7506#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8684#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8950#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8917#L681-42 assume 1 == ~t5_pc~0; 8215#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7371#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8363#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8364#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8752#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7865#L700-42 assume 1 == ~t6_pc~0; 7866#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7675#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7595#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7596#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8759#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8967#L719-42 assume !(1 == ~t7_pc~0); 7556#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 7557#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7937#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8200#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 7952#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7953#L738-42 assume 1 == ~t8_pc~0; 8151#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7896#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7897#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7414#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7415#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7946#L757-42 assume 1 == ~t9_pc~0; 8289#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7597#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7598#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8350#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7716#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7717#L776-42 assume !(1 == ~t10_pc~0); 8676#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 8677#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8494#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8495#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9002#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8517#L795-42 assume !(1 == ~t11_pc~0); 8518#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 7551#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7552#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7650#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7651#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7962#L814-42 assume !(1 == ~t12_pc~0); 7831#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 7464#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7465#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7272#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 7273#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7426#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7427#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7402#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7403#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8232#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8402#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8403#L1357-3 assume !(1 == ~T6_E~0); 8838#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9010#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9006#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7258#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7259#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7862#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 7863#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8702#L1397-3 assume !(1 == ~E_1~0); 8977#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8352#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7510#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7511#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8252#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8253#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8835#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8597#L1437-3 assume !(1 == ~E_9~0); 8372#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 8373#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7306#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 7307#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7925#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7766#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7582#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 7502#L1822 assume !(0 == start_simulation_~tmp~3#1); 7503#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8468#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7763#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7260#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 7261#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8424#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8523#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 8863#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 7375#L1803-2 [2024-11-13 15:57:04,642 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:04,642 INFO L85 PathProgramCache]: Analyzing trace with hash -494851220, now seen corresponding path program 1 times [2024-11-13 15:57:04,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:04,642 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2031396980] [2024-11-13 15:57:04,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:04,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:04,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:04,733 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:04,733 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:04,733 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2031396980] [2024-11-13 15:57:04,733 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2031396980] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:04,733 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:04,734 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:04,734 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2132410029] [2024-11-13 15:57:04,734 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:04,734 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:04,735 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:04,735 INFO L85 PathProgramCache]: Analyzing trace with hash 761407766, now seen corresponding path program 2 times [2024-11-13 15:57:04,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:04,736 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [921121766] [2024-11-13 15:57:04,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:04,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:04,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:04,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:04,855 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:04,856 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [921121766] [2024-11-13 15:57:04,856 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [921121766] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:04,856 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:04,856 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:04,856 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1983418449] [2024-11-13 15:57:04,856 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:04,856 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:04,857 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:04,857 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:04,858 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:04,858 INFO L87 Difference]: Start difference. First operand 1798 states and 2658 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:04,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:04,916 INFO L93 Difference]: Finished difference Result 1798 states and 2657 transitions. [2024-11-13 15:57:04,916 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2657 transitions. [2024-11-13 15:57:04,931 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:04,942 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2657 transitions. [2024-11-13 15:57:04,943 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2024-11-13 15:57:04,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2024-11-13 15:57:04,946 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2657 transitions. [2024-11-13 15:57:04,950 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:04,950 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2657 transitions. [2024-11-13 15:57:04,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2657 transitions. [2024-11-13 15:57:04,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2024-11-13 15:57:04,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.4777530589543937) internal successors, (2657), 1797 states have internal predecessors, (2657), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:04,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2657 transitions. [2024-11-13 15:57:04,992 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2657 transitions. [2024-11-13 15:57:04,993 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:04,994 INFO L424 stractBuchiCegarLoop]: Abstraction has 1798 states and 2657 transitions. [2024-11-13 15:57:04,994 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 15:57:04,994 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2657 transitions. [2024-11-13 15:57:05,006 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:05,006 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:05,007 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:05,011 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:05,011 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:05,011 INFO L745 eck$LassoCheckResult]: Stem: 11065#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 11066#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 12000#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12001#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11135#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 11136#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11040#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11041#L851-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12328#L856-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11681#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11682#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11573#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11574#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12082#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12083#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11332#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 11333#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11767#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11768#L1194 assume !(0 == ~M_E~0); 11920#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11921#L1199-1 assume !(0 == ~T2_E~0); 12207#L1204-1 assume !(0 == ~T3_E~0); 12132#L1209-1 assume !(0 == ~T4_E~0); 12133#L1214-1 assume !(0 == ~T5_E~0); 12531#L1219-1 assume !(0 == ~T6_E~0); 12617#L1224-1 assume !(0 == ~T7_E~0); 11406#L1229-1 assume !(0 == ~T8_E~0); 10960#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10961#L1239-1 assume !(0 == ~T10_E~0); 11003#L1244-1 assume !(0 == ~T11_E~0); 11004#L1249-1 assume !(0 == ~T12_E~0); 11711#L1254-1 assume !(0 == ~E_M~0); 10902#L1259-1 assume !(0 == ~E_1~0); 10867#L1264-1 assume !(0 == ~E_2~0); 10868#L1269-1 assume !(0 == ~E_3~0); 12619#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12563#L1279-1 assume !(0 == ~E_5~0); 11076#L1284-1 assume !(0 == ~E_6~0); 11077#L1289-1 assume !(0 == ~E_7~0); 11774#L1294-1 assume !(0 == ~E_8~0); 11775#L1299-1 assume !(0 == ~E_9~0); 11786#L1304-1 assume !(0 == ~E_10~0); 12610#L1309-1 assume !(0 == ~E_11~0); 12615#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 11033#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10957#L586 assume 1 == ~m_pc~0; 10958#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11025#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11846#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11232#L1485 assume !(0 != activate_threads_~tmp~1#1); 11233#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12334#L605 assume !(1 == ~t1_pc~0); 11860#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11602#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11603#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12246#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12181#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11510#L624 assume 1 == ~t2_pc~0; 11007#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11008#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11259#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11260#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 12366#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12244#L643 assume !(1 == ~t3_pc~0); 12102#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11804#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11805#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11339#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 11340#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11097#L662 assume 1 == ~t4_pc~0; 11098#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11056#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10919#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10920#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 10946#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10947#L681 assume !(1 == ~t5_pc~0); 10823#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10824#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11886#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12492#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 11351#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11352#L700 assume 1 == ~t6_pc~0; 12062#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11089#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11090#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11137#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 11138#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12420#L719 assume 1 == ~t7_pc~0; 12501#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11308#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12607#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12549#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 10837#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10838#L738 assume !(1 == ~t8_pc~0); 12214#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12123#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12124#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11916#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11917#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12266#L757 assume 1 == ~t9_pc~0; 12267#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10832#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10833#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11306#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 11878#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11879#L776 assume !(1 == ~t10_pc~0); 10854#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10853#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11236#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11078#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 11079#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 11034#L795 assume 1 == ~t11_pc~0; 11035#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11371#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12348#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12519#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 12096#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12086#L814 assume !(1 == ~t12_pc~0); 11946#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 11947#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10880#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 10881#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 11290#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11291#L1332 assume !(1 == ~M_E~0); 12379#L1332-2 assume !(1 == ~T1_E~0); 12581#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12017#L1342-1 assume !(1 == ~T3_E~0); 12018#L1347-1 assume !(1 == ~T4_E~0); 12407#L1352-1 assume !(1 == ~T5_E~0); 12272#L1357-1 assume !(1 == ~T6_E~0); 11571#L1362-1 assume !(1 == ~T7_E~0); 11572#L1367-1 assume !(1 == ~T8_E~0); 11171#L1372-1 assume !(1 == ~T9_E~0); 11172#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11482#L1382-1 assume !(1 == ~T11_E~0); 11483#L1387-1 assume !(1 == ~T12_E~0); 12179#L1392-1 assume !(1 == ~E_M~0); 11511#L1397-1 assume !(1 == ~E_1~0); 11512#L1402-1 assume !(1 == ~E_2~0); 11186#L1407-1 assume !(1 == ~E_3~0); 11187#L1412-1 assume !(1 == ~E_4~0); 12346#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 12347#L1422-1 assume !(1 == ~E_6~0); 12583#L1427-1 assume !(1 == ~E_7~0); 11372#L1432-1 assume !(1 == ~E_8~0); 11373#L1437-1 assume !(1 == ~E_9~0); 12299#L1442-1 assume !(1 == ~E_10~0); 12300#L1447-1 assume !(1 == ~E_11~0); 12171#L1452-1 assume !(1 == ~E_12~0); 10977#L1457-1 assume { :end_inline_reset_delta_events } true; 10978#L1803-2 [2024-11-13 15:57:05,012 INFO L747 eck$LassoCheckResult]: Loop: 10978#L1803-2 assume !false; 11314#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11263#L1169-1 assume !false; 11383#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11553#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11042#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11043#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12387#L996 assume !(0 != eval_~tmp~0#1); 11764#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11428#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11429#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11922#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11145#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11146#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11402#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10846#L1214-3 assume !(0 == ~T5_E~0); 10847#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11600#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11601#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11635#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11013#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11014#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 11451#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12041#L1254-3 assume !(0 == ~E_M~0); 12525#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12154#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11019#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11020#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12560#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11598#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11599#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11580#L1294-3 assume !(0 == ~E_8~0); 11581#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11973#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11974#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11484#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11485#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11490#L586-42 assume !(1 == ~m_pc~0); 11491#L586-44 is_master_triggered_~__retres1~0#1 := 0; 11087#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11088#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11554#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 11628#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11629#L605-42 assume 1 == ~t1_pc~0; 12219#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11939#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11940#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11630#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11631#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11639#L624-42 assume !(1 == ~t2_pc~0); 11640#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 11784#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11876#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11877#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11449#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11450#L643-42 assume 1 == ~t3_pc~0; 11808#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11765#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11766#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11595#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11596#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12309#L662-42 assume !(1 == ~t4_pc~0); 12512#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 11108#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11109#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12287#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12553#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12520#L681-42 assume 1 == ~t5_pc~0; 11818#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10974#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11966#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11967#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12355#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11468#L700-42 assume 1 == ~t6_pc~0; 11469#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11278#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11198#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11199#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12362#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12570#L719-42 assume !(1 == ~t7_pc~0); 11159#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 11160#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11540#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11803#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 11555#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11556#L738-42 assume 1 == ~t8_pc~0; 11754#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11499#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11500#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11017#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11018#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11549#L757-42 assume 1 == ~t9_pc~0; 11892#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11200#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11201#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11953#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11319#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11320#L776-42 assume !(1 == ~t10_pc~0); 12279#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 12280#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12097#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12098#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12605#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12120#L795-42 assume !(1 == ~t11_pc~0); 12121#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 11154#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11155#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11253#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11254#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11565#L814-42 assume 1 == ~t12_pc~0; 12337#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11067#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11068#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 10875#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 10876#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11029#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11030#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11005#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11006#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11835#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12005#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12006#L1357-3 assume !(1 == ~T6_E~0); 12441#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12613#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12609#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10861#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 10862#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11465#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11466#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12305#L1397-3 assume !(1 == ~E_1~0); 12580#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11955#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11113#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11114#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11855#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11856#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12438#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12200#L1437-3 assume !(1 == ~E_9~0); 11975#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 11976#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 10909#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 10910#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11528#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11369#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11185#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 11105#L1822 assume !(0 == start_simulation_~tmp~3#1); 11106#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 12071#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11366#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10863#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 10864#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12027#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12126#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 12466#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 10978#L1803-2 [2024-11-13 15:57:05,012 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:05,012 INFO L85 PathProgramCache]: Analyzing trace with hash -833138770, now seen corresponding path program 1 times [2024-11-13 15:57:05,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:05,012 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049688664] [2024-11-13 15:57:05,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:05,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:05,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:05,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:05,142 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:05,142 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2049688664] [2024-11-13 15:57:05,142 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2049688664] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:05,142 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:05,142 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:05,142 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1243042096] [2024-11-13 15:57:05,143 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:05,143 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:05,143 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:05,143 INFO L85 PathProgramCache]: Analyzing trace with hash 1634885461, now seen corresponding path program 1 times [2024-11-13 15:57:05,144 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:05,144 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1010266658] [2024-11-13 15:57:05,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:05,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:05,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:05,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:05,374 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:05,374 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1010266658] [2024-11-13 15:57:05,374 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1010266658] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:05,375 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:05,375 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:05,375 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [476183422] [2024-11-13 15:57:05,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:05,375 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:05,377 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:05,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:05,378 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:05,378 INFO L87 Difference]: Start difference. First operand 1798 states and 2657 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:05,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:05,436 INFO L93 Difference]: Finished difference Result 1798 states and 2656 transitions. [2024-11-13 15:57:05,436 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2656 transitions. [2024-11-13 15:57:05,450 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:05,462 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2656 transitions. [2024-11-13 15:57:05,462 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2024-11-13 15:57:05,464 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2024-11-13 15:57:05,464 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2656 transitions. [2024-11-13 15:57:05,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:05,468 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2656 transitions. [2024-11-13 15:57:05,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2656 transitions. [2024-11-13 15:57:05,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2024-11-13 15:57:05,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.4771968854282536) internal successors, (2656), 1797 states have internal predecessors, (2656), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:05,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2656 transitions. [2024-11-13 15:57:05,513 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2656 transitions. [2024-11-13 15:57:05,513 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:05,514 INFO L424 stractBuchiCegarLoop]: Abstraction has 1798 states and 2656 transitions. [2024-11-13 15:57:05,514 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 15:57:05,514 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2656 transitions. [2024-11-13 15:57:05,526 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:05,527 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:05,530 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:05,533 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:05,536 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:05,537 INFO L745 eck$LassoCheckResult]: Stem: 14668#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 14669#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 15603#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15604#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14738#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 14739#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14643#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14644#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15931#L856-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 15284#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15285#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15176#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15177#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15685#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15686#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14935#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 14936#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 15370#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15371#L1194 assume !(0 == ~M_E~0); 15523#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15524#L1199-1 assume !(0 == ~T2_E~0); 15810#L1204-1 assume !(0 == ~T3_E~0); 15735#L1209-1 assume !(0 == ~T4_E~0); 15736#L1214-1 assume !(0 == ~T5_E~0); 16134#L1219-1 assume !(0 == ~T6_E~0); 16220#L1224-1 assume !(0 == ~T7_E~0); 15009#L1229-1 assume !(0 == ~T8_E~0); 14563#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14564#L1239-1 assume !(0 == ~T10_E~0); 14606#L1244-1 assume !(0 == ~T11_E~0); 14607#L1249-1 assume !(0 == ~T12_E~0); 15314#L1254-1 assume !(0 == ~E_M~0); 14505#L1259-1 assume !(0 == ~E_1~0); 14470#L1264-1 assume !(0 == ~E_2~0); 14471#L1269-1 assume !(0 == ~E_3~0); 16222#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 16166#L1279-1 assume !(0 == ~E_5~0); 14679#L1284-1 assume !(0 == ~E_6~0); 14680#L1289-1 assume !(0 == ~E_7~0); 15377#L1294-1 assume !(0 == ~E_8~0); 15378#L1299-1 assume !(0 == ~E_9~0); 15389#L1304-1 assume !(0 == ~E_10~0); 16213#L1309-1 assume !(0 == ~E_11~0); 16218#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 14636#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14560#L586 assume 1 == ~m_pc~0; 14561#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14628#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15449#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14835#L1485 assume !(0 != activate_threads_~tmp~1#1); 14836#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15937#L605 assume !(1 == ~t1_pc~0); 15463#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15205#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15206#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15849#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15784#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15113#L624 assume 1 == ~t2_pc~0; 14610#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14611#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14862#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14863#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 15969#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15847#L643 assume !(1 == ~t3_pc~0); 15705#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15407#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15408#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14942#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 14943#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14700#L662 assume 1 == ~t4_pc~0; 14701#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14659#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14522#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14523#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 14549#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14550#L681 assume !(1 == ~t5_pc~0); 14426#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 14427#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15489#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16095#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 14954#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14955#L700 assume 1 == ~t6_pc~0; 15665#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14692#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14693#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14740#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 14741#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16023#L719 assume 1 == ~t7_pc~0; 16104#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14911#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16210#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16152#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 14440#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14441#L738 assume !(1 == ~t8_pc~0); 15817#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 15726#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15727#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15519#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15520#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15869#L757 assume 1 == ~t9_pc~0; 15870#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14435#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14436#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14909#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 15481#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15482#L776 assume !(1 == ~t10_pc~0); 14457#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14456#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14839#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14681#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 14682#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14637#L795 assume 1 == ~t11_pc~0; 14638#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14974#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15951#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16122#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 15699#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15689#L814 assume !(1 == ~t12_pc~0); 15549#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 15550#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14483#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14484#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 14893#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14894#L1332 assume !(1 == ~M_E~0); 15982#L1332-2 assume !(1 == ~T1_E~0); 16184#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15620#L1342-1 assume !(1 == ~T3_E~0); 15621#L1347-1 assume !(1 == ~T4_E~0); 16010#L1352-1 assume !(1 == ~T5_E~0); 15875#L1357-1 assume !(1 == ~T6_E~0); 15174#L1362-1 assume !(1 == ~T7_E~0); 15175#L1367-1 assume !(1 == ~T8_E~0); 14774#L1372-1 assume !(1 == ~T9_E~0); 14775#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15085#L1382-1 assume !(1 == ~T11_E~0); 15086#L1387-1 assume !(1 == ~T12_E~0); 15782#L1392-1 assume !(1 == ~E_M~0); 15114#L1397-1 assume !(1 == ~E_1~0); 15115#L1402-1 assume !(1 == ~E_2~0); 14789#L1407-1 assume !(1 == ~E_3~0); 14790#L1412-1 assume !(1 == ~E_4~0); 15949#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 15950#L1422-1 assume !(1 == ~E_6~0); 16186#L1427-1 assume !(1 == ~E_7~0); 14975#L1432-1 assume !(1 == ~E_8~0); 14976#L1437-1 assume !(1 == ~E_9~0); 15902#L1442-1 assume !(1 == ~E_10~0); 15903#L1447-1 assume !(1 == ~E_11~0); 15774#L1452-1 assume !(1 == ~E_12~0); 14580#L1457-1 assume { :end_inline_reset_delta_events } true; 14581#L1803-2 [2024-11-13 15:57:05,537 INFO L747 eck$LassoCheckResult]: Loop: 14581#L1803-2 assume !false; 14917#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14866#L1169-1 assume !false; 14986#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15156#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14645#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14646#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15990#L996 assume !(0 != eval_~tmp~0#1); 15367#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15031#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15032#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15525#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14748#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14749#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15005#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14449#L1214-3 assume !(0 == ~T5_E~0); 14450#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15203#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15204#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15238#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14616#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14617#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 15054#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 15644#L1254-3 assume !(0 == ~E_M~0); 16128#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15757#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14622#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14623#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16163#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15201#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15202#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15183#L1294-3 assume !(0 == ~E_8~0); 15184#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15576#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15577#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 15087#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 15088#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15093#L586-42 assume !(1 == ~m_pc~0); 15094#L586-44 is_master_triggered_~__retres1~0#1 := 0; 14690#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14691#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15157#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 15231#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15232#L605-42 assume 1 == ~t1_pc~0; 15822#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15542#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15543#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15233#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15234#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15242#L624-42 assume !(1 == ~t2_pc~0); 15243#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 15387#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15479#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15480#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15052#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15053#L643-42 assume 1 == ~t3_pc~0; 15411#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15368#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15369#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15198#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15199#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15912#L662-42 assume !(1 == ~t4_pc~0); 16115#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 14711#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14712#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15890#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16156#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16123#L681-42 assume !(1 == ~t5_pc~0); 14576#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 14577#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15569#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15570#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15958#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15071#L700-42 assume 1 == ~t6_pc~0; 15072#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14881#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14801#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14802#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15965#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16173#L719-42 assume 1 == ~t7_pc~0; 15682#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14763#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15143#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15406#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 15158#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15159#L738-42 assume 1 == ~t8_pc~0; 15357#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15102#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15103#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14620#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14621#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15152#L757-42 assume 1 == ~t9_pc~0; 15495#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14803#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14804#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15556#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14922#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14923#L776-42 assume !(1 == ~t10_pc~0); 15882#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 15883#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15700#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 15701#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16208#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15723#L795-42 assume !(1 == ~t11_pc~0); 15724#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 14757#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14758#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14856#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14857#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15168#L814-42 assume 1 == ~t12_pc~0; 15940#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 14670#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14671#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14478#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 14479#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14632#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14633#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14608#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14609#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15438#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15608#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15609#L1357-3 assume !(1 == ~T6_E~0); 16044#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16216#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16212#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14464#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14465#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15068#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15069#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15908#L1397-3 assume !(1 == ~E_1~0); 16183#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15558#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14716#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14717#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15458#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15459#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16041#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15803#L1437-3 assume !(1 == ~E_9~0); 15578#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15579#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 14512#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 14513#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15131#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14972#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14788#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 14708#L1822 assume !(0 == start_simulation_~tmp~3#1); 14709#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15674#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14969#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14466#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 14467#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15630#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15729#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 16069#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 14581#L1803-2 [2024-11-13 15:57:05,538 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:05,539 INFO L85 PathProgramCache]: Analyzing trace with hash -1259693268, now seen corresponding path program 1 times [2024-11-13 15:57:05,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:05,539 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1758048122] [2024-11-13 15:57:05,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:05,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:05,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:05,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:05,645 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:05,645 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1758048122] [2024-11-13 15:57:05,645 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1758048122] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:05,646 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:05,646 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:05,646 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1494811966] [2024-11-13 15:57:05,646 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:05,646 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:05,647 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:05,647 INFO L85 PathProgramCache]: Analyzing trace with hash 8545749, now seen corresponding path program 1 times [2024-11-13 15:57:05,648 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:05,648 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [584131337] [2024-11-13 15:57:05,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:05,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:05,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:05,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:05,785 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:05,785 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [584131337] [2024-11-13 15:57:05,785 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [584131337] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:05,785 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:05,785 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:05,785 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [608554558] [2024-11-13 15:57:05,785 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:05,786 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:05,786 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:05,786 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:05,786 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:05,787 INFO L87 Difference]: Start difference. First operand 1798 states and 2656 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:05,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:05,847 INFO L93 Difference]: Finished difference Result 1798 states and 2655 transitions. [2024-11-13 15:57:05,847 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2655 transitions. [2024-11-13 15:57:05,863 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:05,895 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2655 transitions. [2024-11-13 15:57:05,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2024-11-13 15:57:05,898 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2024-11-13 15:57:05,898 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2655 transitions. [2024-11-13 15:57:05,901 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:05,902 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2655 transitions. [2024-11-13 15:57:05,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2655 transitions. [2024-11-13 15:57:05,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2024-11-13 15:57:05,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.4766407119021134) internal successors, (2655), 1797 states have internal predecessors, (2655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:05,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2655 transitions. [2024-11-13 15:57:05,942 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2655 transitions. [2024-11-13 15:57:05,942 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:05,943 INFO L424 stractBuchiCegarLoop]: Abstraction has 1798 states and 2655 transitions. [2024-11-13 15:57:05,943 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 15:57:05,943 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2655 transitions. [2024-11-13 15:57:05,953 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:05,953 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:05,953 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:05,956 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:05,957 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:05,957 INFO L745 eck$LassoCheckResult]: Stem: 18273#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 18274#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 19207#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19208#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18341#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 18342#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18246#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18247#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19534#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18887#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 18888#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 18779#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18780#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19288#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19289#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18538#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 18539#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 18975#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18976#L1194 assume !(0 == ~M_E~0); 19126#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19127#L1199-1 assume !(0 == ~T2_E~0); 19413#L1204-1 assume !(0 == ~T3_E~0); 19338#L1209-1 assume !(0 == ~T4_E~0); 19339#L1214-1 assume !(0 == ~T5_E~0); 19737#L1219-1 assume !(0 == ~T6_E~0); 19823#L1224-1 assume !(0 == ~T7_E~0); 18614#L1229-1 assume !(0 == ~T8_E~0); 18174#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18175#L1239-1 assume !(0 == ~T10_E~0); 18211#L1244-1 assume !(0 == ~T11_E~0); 18212#L1249-1 assume !(0 == ~T12_E~0); 18917#L1254-1 assume !(0 == ~E_M~0); 18108#L1259-1 assume !(0 == ~E_1~0); 18073#L1264-1 assume !(0 == ~E_2~0); 18074#L1269-1 assume !(0 == ~E_3~0); 19825#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19769#L1279-1 assume !(0 == ~E_5~0); 18282#L1284-1 assume !(0 == ~E_6~0); 18283#L1289-1 assume !(0 == ~E_7~0); 18982#L1294-1 assume !(0 == ~E_8~0); 18983#L1299-1 assume !(0 == ~E_9~0); 18994#L1304-1 assume !(0 == ~E_10~0); 19816#L1309-1 assume !(0 == ~E_11~0); 19821#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 18240#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18163#L586 assume 1 == ~m_pc~0; 18164#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18231#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19052#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18438#L1485 assume !(0 != activate_threads_~tmp~1#1); 18439#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19540#L605 assume !(1 == ~t1_pc~0); 19066#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18808#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18809#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19452#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19388#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18716#L624 assume 1 == ~t2_pc~0; 18216#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18217#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18465#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18466#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 19572#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19450#L643 assume !(1 == ~t3_pc~0); 19310#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19016#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19017#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18545#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 18546#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18303#L662 assume 1 == ~t4_pc~0; 18304#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18262#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18128#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18129#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 18154#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18155#L681 assume !(1 == ~t5_pc~0); 18029#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 18030#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19092#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19698#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 18557#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18558#L700 assume 1 == ~t6_pc~0; 19268#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18295#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18296#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18343#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 18344#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19626#L719 assume 1 == ~t7_pc~0; 19710#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18515#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19813#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19755#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 18043#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18044#L738 assume !(1 == ~t8_pc~0); 19420#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19329#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19330#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19122#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19123#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19472#L757 assume 1 == ~t9_pc~0; 19473#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18038#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18039#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18512#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 19084#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19085#L776 assume !(1 == ~t10_pc~0); 18060#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 18059#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18445#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18284#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 18285#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18241#L795 assume 1 == ~t11_pc~0; 18242#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18581#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19554#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19726#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 19302#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19292#L814 assume !(1 == ~t12_pc~0); 19152#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 19153#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18089#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18090#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 18496#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18497#L1332 assume !(1 == ~M_E~0); 19585#L1332-2 assume !(1 == ~T1_E~0); 19788#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19225#L1342-1 assume !(1 == ~T3_E~0); 19226#L1347-1 assume !(1 == ~T4_E~0); 19614#L1352-1 assume !(1 == ~T5_E~0); 19478#L1357-1 assume !(1 == ~T6_E~0); 18777#L1362-1 assume !(1 == ~T7_E~0); 18778#L1367-1 assume !(1 == ~T8_E~0); 18379#L1372-1 assume !(1 == ~T9_E~0); 18380#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18688#L1382-1 assume !(1 == ~T11_E~0); 18689#L1387-1 assume !(1 == ~T12_E~0); 19385#L1392-1 assume !(1 == ~E_M~0); 18717#L1397-1 assume !(1 == ~E_1~0); 18718#L1402-1 assume !(1 == ~E_2~0); 18394#L1407-1 assume !(1 == ~E_3~0); 18395#L1412-1 assume !(1 == ~E_4~0); 19552#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 19553#L1422-1 assume !(1 == ~E_6~0); 19789#L1427-1 assume !(1 == ~E_7~0); 18577#L1432-1 assume !(1 == ~E_8~0); 18578#L1437-1 assume !(1 == ~E_9~0); 19505#L1442-1 assume !(1 == ~E_10~0); 19506#L1447-1 assume !(1 == ~E_11~0); 19377#L1452-1 assume !(1 == ~E_12~0); 18183#L1457-1 assume { :end_inline_reset_delta_events } true; 18184#L1803-2 [2024-11-13 15:57:05,958 INFO L747 eck$LassoCheckResult]: Loop: 18184#L1803-2 assume !false; 18520#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18469#L1169-1 assume !false; 18589#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18759#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18248#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18249#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19593#L996 assume !(0 != eval_~tmp~0#1); 18970#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18634#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18635#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19128#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18351#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18352#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18608#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18052#L1214-3 assume !(0 == ~T5_E~0); 18053#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18806#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18807#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18841#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18219#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18220#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18657#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 19247#L1254-3 assume !(0 == ~E_M~0); 19731#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19360#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18225#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18226#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19766#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18804#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18805#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18786#L1294-3 assume !(0 == ~E_8~0); 18787#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19179#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19180#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18690#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 18691#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18696#L586-42 assume !(1 == ~m_pc~0); 18697#L586-44 is_master_triggered_~__retres1~0#1 := 0; 18293#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18294#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18760#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 18834#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18835#L605-42 assume 1 == ~t1_pc~0; 19425#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19145#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19146#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18836#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18837#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18845#L624-42 assume !(1 == ~t2_pc~0); 18846#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 18990#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19082#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19083#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18655#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18656#L643-42 assume 1 == ~t3_pc~0; 19012#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18971#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18972#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18801#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18802#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19515#L662-42 assume !(1 == ~t4_pc~0); 19718#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 18314#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18315#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19493#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19759#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19725#L681-42 assume 1 == ~t5_pc~0; 19024#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18180#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19172#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19173#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19561#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18674#L700-42 assume 1 == ~t6_pc~0; 18675#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18484#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18404#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18405#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19568#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19776#L719-42 assume 1 == ~t7_pc~0; 19285#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18366#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18746#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19009#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 18761#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18762#L738-42 assume 1 == ~t8_pc~0; 18960#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18705#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18706#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18223#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18224#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18755#L757-42 assume 1 == ~t9_pc~0; 19098#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18406#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18407#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19159#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18525#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18526#L776-42 assume !(1 == ~t10_pc~0); 19485#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 19486#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19303#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19304#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19811#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19326#L795-42 assume 1 == ~t11_pc~0; 19328#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18360#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18361#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18459#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18460#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18771#L814-42 assume !(1 == ~t12_pc~0); 18640#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 18271#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18272#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18081#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 18082#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18235#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18236#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18209#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18210#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19041#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19211#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19212#L1357-3 assume !(1 == ~T6_E~0); 19647#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19819#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19815#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18067#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18068#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18671#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18672#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19511#L1397-3 assume !(1 == ~E_1~0); 19786#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19161#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18319#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18320#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19061#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19062#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19644#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19406#L1437-3 assume !(1 == ~E_9~0); 19181#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19182#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 18115#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 18116#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18734#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18575#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18391#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 18311#L1822 assume !(0 == start_simulation_~tmp~3#1); 18312#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19277#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18572#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18069#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 18070#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19233#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19332#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 19672#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 18184#L1803-2 [2024-11-13 15:57:05,958 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:05,960 INFO L85 PathProgramCache]: Analyzing trace with hash -719263762, now seen corresponding path program 1 times [2024-11-13 15:57:05,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:05,960 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [617164727] [2024-11-13 15:57:05,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:05,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:05,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:06,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:06,049 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:06,051 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [617164727] [2024-11-13 15:57:06,052 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [617164727] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:06,052 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:06,052 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:06,052 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [669773744] [2024-11-13 15:57:06,052 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:06,053 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:06,053 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:06,053 INFO L85 PathProgramCache]: Analyzing trace with hash -1573817836, now seen corresponding path program 1 times [2024-11-13 15:57:06,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:06,053 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1212002389] [2024-11-13 15:57:06,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:06,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:06,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:06,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:06,171 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:06,171 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1212002389] [2024-11-13 15:57:06,171 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1212002389] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:06,171 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:06,171 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:06,172 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1158777772] [2024-11-13 15:57:06,172 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:06,172 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:06,172 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:06,173 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:06,173 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:06,174 INFO L87 Difference]: Start difference. First operand 1798 states and 2655 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:06,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:06,231 INFO L93 Difference]: Finished difference Result 1798 states and 2654 transitions. [2024-11-13 15:57:06,231 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2654 transitions. [2024-11-13 15:57:06,247 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:06,259 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2654 transitions. [2024-11-13 15:57:06,260 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2024-11-13 15:57:06,262 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2024-11-13 15:57:06,262 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2654 transitions. [2024-11-13 15:57:06,266 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:06,266 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2654 transitions. [2024-11-13 15:57:06,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2654 transitions. [2024-11-13 15:57:06,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2024-11-13 15:57:06,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.4760845383759733) internal successors, (2654), 1797 states have internal predecessors, (2654), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:06,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2654 transitions. [2024-11-13 15:57:06,311 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2654 transitions. [2024-11-13 15:57:06,312 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:06,315 INFO L424 stractBuchiCegarLoop]: Abstraction has 1798 states and 2654 transitions. [2024-11-13 15:57:06,318 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 15:57:06,318 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2654 transitions. [2024-11-13 15:57:06,328 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:06,328 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:06,328 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:06,351 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:06,351 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:06,351 INFO L745 eck$LassoCheckResult]: Stem: 21876#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 21877#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 22809#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22810#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21944#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 21945#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21849#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21850#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23137#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22490#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22491#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22382#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 22383#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22891#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22892#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22141#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22142#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22578#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22579#L1194 assume !(0 == ~M_E~0); 22729#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22730#L1199-1 assume !(0 == ~T2_E~0); 23016#L1204-1 assume !(0 == ~T3_E~0); 22941#L1209-1 assume !(0 == ~T4_E~0); 22942#L1214-1 assume !(0 == ~T5_E~0); 23340#L1219-1 assume !(0 == ~T6_E~0); 23426#L1224-1 assume !(0 == ~T7_E~0); 22217#L1229-1 assume !(0 == ~T8_E~0); 21777#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21778#L1239-1 assume !(0 == ~T10_E~0); 21814#L1244-1 assume !(0 == ~T11_E~0); 21815#L1249-1 assume !(0 == ~T12_E~0); 22520#L1254-1 assume !(0 == ~E_M~0); 21711#L1259-1 assume !(0 == ~E_1~0); 21676#L1264-1 assume !(0 == ~E_2~0); 21677#L1269-1 assume !(0 == ~E_3~0); 23428#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 23372#L1279-1 assume !(0 == ~E_5~0); 21885#L1284-1 assume !(0 == ~E_6~0); 21886#L1289-1 assume !(0 == ~E_7~0); 22583#L1294-1 assume !(0 == ~E_8~0); 22584#L1299-1 assume !(0 == ~E_9~0); 22597#L1304-1 assume !(0 == ~E_10~0); 23419#L1309-1 assume !(0 == ~E_11~0); 23424#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 21843#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21766#L586 assume 1 == ~m_pc~0; 21767#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21834#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22655#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22041#L1485 assume !(0 != activate_threads_~tmp~1#1); 22042#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23143#L605 assume !(1 == ~t1_pc~0); 22669#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22411#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22412#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23055#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22991#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22319#L624 assume 1 == ~t2_pc~0; 21819#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21820#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22068#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22069#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 23175#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23053#L643 assume !(1 == ~t3_pc~0); 22911#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22619#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22620#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22148#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 22149#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21906#L662 assume 1 == ~t4_pc~0; 21907#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21865#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21731#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21732#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 21757#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21758#L681 assume !(1 == ~t5_pc~0); 21632#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21633#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22695#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23301#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 22160#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22161#L700 assume 1 == ~t6_pc~0; 22871#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21898#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21899#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21946#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 21947#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23229#L719 assume 1 == ~t7_pc~0; 23310#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22117#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23416#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23358#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 21646#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21647#L738 assume !(1 == ~t8_pc~0); 23023#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22932#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22933#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22725#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22726#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23075#L757 assume 1 == ~t9_pc~0; 23076#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21641#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21642#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22115#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 22687#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22688#L776 assume !(1 == ~t10_pc~0); 21663#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21662#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22045#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21887#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 21888#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21844#L795 assume 1 == ~t11_pc~0; 21845#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22180#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23157#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23329#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 22905#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22895#L814 assume !(1 == ~t12_pc~0); 22755#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22756#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21689#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21690#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 22099#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22100#L1332 assume !(1 == ~M_E~0); 23188#L1332-2 assume !(1 == ~T1_E~0); 23391#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22826#L1342-1 assume !(1 == ~T3_E~0); 22827#L1347-1 assume !(1 == ~T4_E~0); 23217#L1352-1 assume !(1 == ~T5_E~0); 23081#L1357-1 assume !(1 == ~T6_E~0); 22380#L1362-1 assume !(1 == ~T7_E~0); 22381#L1367-1 assume !(1 == ~T8_E~0); 21982#L1372-1 assume !(1 == ~T9_E~0); 21983#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22291#L1382-1 assume !(1 == ~T11_E~0); 22292#L1387-1 assume !(1 == ~T12_E~0); 22988#L1392-1 assume !(1 == ~E_M~0); 22320#L1397-1 assume !(1 == ~E_1~0); 22321#L1402-1 assume !(1 == ~E_2~0); 21997#L1407-1 assume !(1 == ~E_3~0); 21998#L1412-1 assume !(1 == ~E_4~0); 23155#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 23156#L1422-1 assume !(1 == ~E_6~0); 23392#L1427-1 assume !(1 == ~E_7~0); 22181#L1432-1 assume !(1 == ~E_8~0); 22182#L1437-1 assume !(1 == ~E_9~0); 23108#L1442-1 assume !(1 == ~E_10~0); 23109#L1447-1 assume !(1 == ~E_11~0); 22980#L1452-1 assume !(1 == ~E_12~0); 21786#L1457-1 assume { :end_inline_reset_delta_events } true; 21787#L1803-2 [2024-11-13 15:57:06,352 INFO L747 eck$LassoCheckResult]: Loop: 21787#L1803-2 assume !false; 22123#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22072#L1169-1 assume !false; 22192#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22362#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21851#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21852#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 23196#L996 assume !(0 != eval_~tmp~0#1); 22575#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22240#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22241#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22731#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21954#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21955#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22211#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21659#L1214-3 assume !(0 == ~T5_E~0); 21660#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22409#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22410#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22447#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21822#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21823#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22260#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 22850#L1254-3 assume !(0 == ~E_M~0); 23334#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22963#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21828#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21829#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23369#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22407#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22408#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22389#L1294-3 assume !(0 == ~E_8~0); 22390#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22782#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22783#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22293#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 22294#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22301#L586-42 assume !(1 == ~m_pc~0); 22302#L586-44 is_master_triggered_~__retres1~0#1 := 0; 21893#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21894#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22363#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 22437#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22438#L605-42 assume 1 == ~t1_pc~0; 23027#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22748#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22749#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22439#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22440#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22444#L624-42 assume !(1 == ~t2_pc~0); 22445#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 22590#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22685#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22686#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22258#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22259#L643-42 assume 1 == ~t3_pc~0; 22615#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22573#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22574#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22404#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22405#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23118#L662-42 assume !(1 == ~t4_pc~0); 23320#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 21917#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21918#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23096#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23362#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23328#L681-42 assume 1 == ~t5_pc~0; 22627#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21783#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22775#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22776#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23164#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22277#L700-42 assume 1 == ~t6_pc~0; 22278#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22087#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22007#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22008#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23171#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23379#L719-42 assume !(1 == ~t7_pc~0); 21968#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 21969#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22349#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22612#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 22364#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22365#L738-42 assume 1 == ~t8_pc~0; 22563#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22308#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22309#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21826#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21827#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22358#L757-42 assume 1 == ~t9_pc~0; 22698#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22009#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22010#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22762#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22127#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22128#L776-42 assume !(1 == ~t10_pc~0); 23088#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 23089#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22906#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22907#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23414#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22929#L795-42 assume !(1 == ~t11_pc~0); 22930#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 21963#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21964#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22060#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 22061#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22374#L814-42 assume !(1 == ~t12_pc~0); 22243#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 21874#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21875#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21684#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 21685#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21838#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21839#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21812#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21813#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22644#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22814#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22815#L1357-3 assume !(1 == ~T6_E~0); 23250#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23422#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23418#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21670#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21671#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22274#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22275#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23114#L1397-3 assume !(1 == ~E_1~0); 23389#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22764#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21922#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21923#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22664#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22665#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 23247#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23008#L1437-3 assume !(1 == ~E_9~0); 22784#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22785#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21718#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21719#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22337#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22178#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21994#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 21914#L1822 assume !(0 == start_simulation_~tmp~3#1); 21915#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22880#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22172#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21672#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 21673#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22836#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22935#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 23274#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 21787#L1803-2 [2024-11-13 15:57:06,352 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:06,352 INFO L85 PathProgramCache]: Analyzing trace with hash -563283220, now seen corresponding path program 1 times [2024-11-13 15:57:06,352 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:06,352 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1734470232] [2024-11-13 15:57:06,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:06,353 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:06,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:06,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:06,449 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:06,449 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1734470232] [2024-11-13 15:57:06,449 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1734470232] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:06,449 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:06,449 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:06,449 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1825340775] [2024-11-13 15:57:06,449 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:06,450 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:06,451 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:06,451 INFO L85 PathProgramCache]: Analyzing trace with hash 761407766, now seen corresponding path program 3 times [2024-11-13 15:57:06,451 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:06,451 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390478674] [2024-11-13 15:57:06,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:06,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:06,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:06,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:06,603 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:06,603 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390478674] [2024-11-13 15:57:06,603 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1390478674] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:06,603 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:06,604 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:06,604 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1020571485] [2024-11-13 15:57:06,604 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:06,604 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:06,604 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:06,605 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:06,605 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:06,605 INFO L87 Difference]: Start difference. First operand 1798 states and 2654 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:06,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:06,682 INFO L93 Difference]: Finished difference Result 1798 states and 2653 transitions. [2024-11-13 15:57:06,682 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2653 transitions. [2024-11-13 15:57:06,700 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:06,714 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2653 transitions. [2024-11-13 15:57:06,715 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2024-11-13 15:57:06,717 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2024-11-13 15:57:06,717 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2653 transitions. [2024-11-13 15:57:06,722 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:06,722 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2653 transitions. [2024-11-13 15:57:06,727 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2653 transitions. [2024-11-13 15:57:06,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2024-11-13 15:57:06,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.4755283648498332) internal successors, (2653), 1797 states have internal predecessors, (2653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:06,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2653 transitions. [2024-11-13 15:57:06,779 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2653 transitions. [2024-11-13 15:57:06,779 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:06,782 INFO L424 stractBuchiCegarLoop]: Abstraction has 1798 states and 2653 transitions. [2024-11-13 15:57:06,782 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 15:57:06,782 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2653 transitions. [2024-11-13 15:57:06,795 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:06,795 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:06,795 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:06,799 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:06,799 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:06,800 INFO L745 eck$LassoCheckResult]: Stem: 25479#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 25480#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 26412#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26413#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25547#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 25548#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25452#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25453#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26740#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26093#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26094#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25985#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25986#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 26494#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26495#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25744#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25745#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26181#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26182#L1194 assume !(0 == ~M_E~0); 26332#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26333#L1199-1 assume !(0 == ~T2_E~0); 26619#L1204-1 assume !(0 == ~T3_E~0); 26544#L1209-1 assume !(0 == ~T4_E~0); 26545#L1214-1 assume !(0 == ~T5_E~0); 26943#L1219-1 assume !(0 == ~T6_E~0); 27029#L1224-1 assume !(0 == ~T7_E~0); 25818#L1229-1 assume !(0 == ~T8_E~0); 25378#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25379#L1239-1 assume !(0 == ~T10_E~0); 25417#L1244-1 assume !(0 == ~T11_E~0); 25418#L1249-1 assume !(0 == ~T12_E~0); 26123#L1254-1 assume !(0 == ~E_M~0); 25314#L1259-1 assume !(0 == ~E_1~0); 25279#L1264-1 assume !(0 == ~E_2~0); 25280#L1269-1 assume !(0 == ~E_3~0); 27031#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 26975#L1279-1 assume !(0 == ~E_5~0); 25488#L1284-1 assume !(0 == ~E_6~0); 25489#L1289-1 assume !(0 == ~E_7~0); 26186#L1294-1 assume !(0 == ~E_8~0); 26187#L1299-1 assume !(0 == ~E_9~0); 26200#L1304-1 assume !(0 == ~E_10~0); 27022#L1309-1 assume !(0 == ~E_11~0); 27027#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 25446#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25369#L586 assume 1 == ~m_pc~0; 25370#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25437#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26258#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25644#L1485 assume !(0 != activate_threads_~tmp~1#1); 25645#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26746#L605 assume !(1 == ~t1_pc~0); 26272#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26014#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26015#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26658#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26594#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25922#L624 assume 1 == ~t2_pc~0; 25422#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25423#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25671#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25672#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 26778#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26656#L643 assume !(1 == ~t3_pc~0); 26514#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26218#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26219#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25751#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 25752#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25509#L662 assume 1 == ~t4_pc~0; 25510#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25468#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25331#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25332#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 25360#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25361#L681 assume !(1 == ~t5_pc~0); 25235#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25236#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26298#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26904#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 25763#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25764#L700 assume 1 == ~t6_pc~0; 26474#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25501#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25502#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25549#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 25550#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26832#L719 assume 1 == ~t7_pc~0; 26913#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25720#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27019#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26961#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 25249#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25250#L738 assume !(1 == ~t8_pc~0); 26626#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 26535#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26536#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26328#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26329#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26678#L757 assume 1 == ~t9_pc~0; 26679#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25244#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25245#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25718#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 26290#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26291#L776 assume !(1 == ~t10_pc~0); 25266#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25265#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25648#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25490#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 25491#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25447#L795 assume 1 == ~t11_pc~0; 25448#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25783#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26760#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26931#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 26508#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26498#L814 assume !(1 == ~t12_pc~0); 26358#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 26359#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25292#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25293#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 25702#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25703#L1332 assume !(1 == ~M_E~0); 26791#L1332-2 assume !(1 == ~T1_E~0); 26994#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26429#L1342-1 assume !(1 == ~T3_E~0); 26430#L1347-1 assume !(1 == ~T4_E~0); 26819#L1352-1 assume !(1 == ~T5_E~0); 26684#L1357-1 assume !(1 == ~T6_E~0); 25983#L1362-1 assume !(1 == ~T7_E~0); 25984#L1367-1 assume !(1 == ~T8_E~0); 25583#L1372-1 assume !(1 == ~T9_E~0); 25584#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25894#L1382-1 assume !(1 == ~T11_E~0); 25895#L1387-1 assume !(1 == ~T12_E~0); 26591#L1392-1 assume !(1 == ~E_M~0); 25923#L1397-1 assume !(1 == ~E_1~0); 25924#L1402-1 assume !(1 == ~E_2~0); 25600#L1407-1 assume !(1 == ~E_3~0); 25601#L1412-1 assume !(1 == ~E_4~0); 26758#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26759#L1422-1 assume !(1 == ~E_6~0); 26995#L1427-1 assume !(1 == ~E_7~0); 25784#L1432-1 assume !(1 == ~E_8~0); 25785#L1437-1 assume !(1 == ~E_9~0); 26711#L1442-1 assume !(1 == ~E_10~0); 26712#L1447-1 assume !(1 == ~E_11~0); 26583#L1452-1 assume !(1 == ~E_12~0); 25389#L1457-1 assume { :end_inline_reset_delta_events } true; 25390#L1803-2 [2024-11-13 15:57:06,801 INFO L747 eck$LassoCheckResult]: Loop: 25390#L1803-2 assume !false; 25726#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25675#L1169-1 assume !false; 25795#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25965#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25454#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25455#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 26799#L996 assume !(0 != eval_~tmp~0#1); 26176#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25843#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25844#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26334#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25557#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25558#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25814#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25262#L1214-3 assume !(0 == ~T5_E~0); 25263#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26012#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26013#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26047#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25425#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25426#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25863#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 26453#L1254-3 assume !(0 == ~E_M~0); 26937#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26566#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25431#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25432#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26972#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26010#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26011#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25992#L1294-3 assume !(0 == ~E_8~0); 25993#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26385#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26386#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25896#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 25897#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25902#L586-42 assume 1 == ~m_pc~0; 25904#L587-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25499#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25500#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25968#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 26040#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26041#L605-42 assume 1 == ~t1_pc~0; 26632#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26351#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26352#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26045#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26046#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26051#L624-42 assume !(1 == ~t2_pc~0); 26052#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 26197#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26288#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26289#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25861#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25862#L643-42 assume 1 == ~t3_pc~0; 26222#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26177#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26178#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26007#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26008#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26721#L662-42 assume !(1 == ~t4_pc~0); 26924#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 25520#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25521#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26699#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26965#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26932#L681-42 assume 1 == ~t5_pc~0; 26233#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25386#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26378#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26379#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26767#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25879#L700-42 assume !(1 == ~t6_pc~0); 25686#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 25687#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25610#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25611#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26774#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26980#L719-42 assume !(1 == ~t7_pc~0); 25568#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 25569#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25952#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26215#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 25966#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25967#L738-42 assume 1 == ~t8_pc~0; 26166#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25909#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25910#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25429#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25430#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25961#L757-42 assume 1 == ~t9_pc~0; 26301#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25612#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25613#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26365#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25730#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25731#L776-42 assume !(1 == ~t10_pc~0); 26691#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 26692#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26509#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26510#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 27017#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26532#L795-42 assume !(1 == ~t11_pc~0); 26533#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 25564#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25565#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25663#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25664#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25977#L814-42 assume !(1 == ~t12_pc~0); 25846#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 25477#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25478#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25287#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25288#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25441#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25442#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25415#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25416#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26247#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26417#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26418#L1357-3 assume !(1 == ~T6_E~0); 26852#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27025#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 27021#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25273#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25274#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25877#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25878#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26717#L1397-3 assume !(1 == ~E_1~0); 26992#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26367#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25525#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25526#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26267#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26268#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26850#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 26611#L1437-3 assume !(1 == ~E_9~0); 26387#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26388#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 25321#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 25322#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25938#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25781#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25597#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 25517#L1822 assume !(0 == start_simulation_~tmp~3#1); 25518#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26483#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25775#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25275#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 25276#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26439#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26538#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 26877#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 25390#L1803-2 [2024-11-13 15:57:06,802 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:06,802 INFO L85 PathProgramCache]: Analyzing trace with hash -973893586, now seen corresponding path program 1 times [2024-11-13 15:57:06,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:06,802 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [633770479] [2024-11-13 15:57:06,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:06,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:06,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:06,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:06,907 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:06,907 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [633770479] [2024-11-13 15:57:06,907 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [633770479] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:06,907 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:06,907 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:06,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [358056648] [2024-11-13 15:57:06,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:06,908 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:06,908 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:06,908 INFO L85 PathProgramCache]: Analyzing trace with hash -1491077738, now seen corresponding path program 1 times [2024-11-13 15:57:06,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:06,910 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [34290165] [2024-11-13 15:57:06,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:06,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:06,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:07,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:07,022 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:07,023 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [34290165] [2024-11-13 15:57:07,023 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [34290165] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:07,023 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:07,023 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:07,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1252303509] [2024-11-13 15:57:07,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:07,024 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:07,024 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:07,024 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:07,024 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:07,025 INFO L87 Difference]: Start difference. First operand 1798 states and 2653 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:07,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:07,081 INFO L93 Difference]: Finished difference Result 1798 states and 2652 transitions. [2024-11-13 15:57:07,082 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2652 transitions. [2024-11-13 15:57:07,095 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:07,108 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2652 transitions. [2024-11-13 15:57:07,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2024-11-13 15:57:07,110 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2024-11-13 15:57:07,111 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2652 transitions. [2024-11-13 15:57:07,114 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:07,115 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2652 transitions. [2024-11-13 15:57:07,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2652 transitions. [2024-11-13 15:57:07,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2024-11-13 15:57:07,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.474972191323693) internal successors, (2652), 1797 states have internal predecessors, (2652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:07,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2652 transitions. [2024-11-13 15:57:07,160 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2652 transitions. [2024-11-13 15:57:07,160 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:07,161 INFO L424 stractBuchiCegarLoop]: Abstraction has 1798 states and 2652 transitions. [2024-11-13 15:57:07,161 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 15:57:07,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2652 transitions. [2024-11-13 15:57:07,171 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:07,172 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:07,172 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:07,175 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:07,175 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:07,175 INFO L745 eck$LassoCheckResult]: Stem: 29080#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 29081#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 30015#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30016#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29150#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 29151#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29055#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29056#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30343#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29696#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29697#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29588#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29589#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 30097#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30098#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29347#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29348#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29782#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29783#L1194 assume !(0 == ~M_E~0); 29935#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29936#L1199-1 assume !(0 == ~T2_E~0); 30222#L1204-1 assume !(0 == ~T3_E~0); 30147#L1209-1 assume !(0 == ~T4_E~0); 30148#L1214-1 assume !(0 == ~T5_E~0); 30546#L1219-1 assume !(0 == ~T6_E~0); 30632#L1224-1 assume !(0 == ~T7_E~0); 29421#L1229-1 assume !(0 == ~T8_E~0); 28975#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28976#L1239-1 assume !(0 == ~T10_E~0); 29018#L1244-1 assume !(0 == ~T11_E~0); 29019#L1249-1 assume !(0 == ~T12_E~0); 29726#L1254-1 assume !(0 == ~E_M~0); 28917#L1259-1 assume !(0 == ~E_1~0); 28882#L1264-1 assume !(0 == ~E_2~0); 28883#L1269-1 assume !(0 == ~E_3~0); 30634#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 30578#L1279-1 assume !(0 == ~E_5~0); 29091#L1284-1 assume !(0 == ~E_6~0); 29092#L1289-1 assume !(0 == ~E_7~0); 29789#L1294-1 assume !(0 == ~E_8~0); 29790#L1299-1 assume !(0 == ~E_9~0); 29801#L1304-1 assume !(0 == ~E_10~0); 30625#L1309-1 assume !(0 == ~E_11~0); 30630#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 29049#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28972#L586 assume 1 == ~m_pc~0; 28973#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29040#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29861#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29247#L1485 assume !(0 != activate_threads_~tmp~1#1); 29248#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30349#L605 assume !(1 == ~t1_pc~0); 29875#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29617#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29618#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30261#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30196#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29525#L624 assume 1 == ~t2_pc~0; 29022#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29023#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29274#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29275#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 30381#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30259#L643 assume !(1 == ~t3_pc~0); 30117#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29821#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29822#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29354#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 29355#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29112#L662 assume 1 == ~t4_pc~0; 29113#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29071#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28934#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28935#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 28963#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28964#L681 assume !(1 == ~t5_pc~0); 28838#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28839#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29901#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30507#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 29366#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29367#L700 assume 1 == ~t6_pc~0; 30077#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29104#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29105#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29152#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 29153#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30435#L719 assume 1 == ~t7_pc~0; 30516#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29323#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30622#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30564#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 28852#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28853#L738 assume !(1 == ~t8_pc~0); 30229#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 30138#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30139#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29931#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29932#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30281#L757 assume 1 == ~t9_pc~0; 30282#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28847#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28848#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29321#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 29893#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29894#L776 assume !(1 == ~t10_pc~0); 28869#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28868#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29251#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29093#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 29094#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29050#L795 assume 1 == ~t11_pc~0; 29051#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29386#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30363#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30534#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 30111#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30101#L814 assume !(1 == ~t12_pc~0); 29961#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29962#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28895#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28896#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 29305#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29306#L1332 assume !(1 == ~M_E~0); 30394#L1332-2 assume !(1 == ~T1_E~0); 30596#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30032#L1342-1 assume !(1 == ~T3_E~0); 30033#L1347-1 assume !(1 == ~T4_E~0); 30422#L1352-1 assume !(1 == ~T5_E~0); 30287#L1357-1 assume !(1 == ~T6_E~0); 29586#L1362-1 assume !(1 == ~T7_E~0); 29587#L1367-1 assume !(1 == ~T8_E~0); 29186#L1372-1 assume !(1 == ~T9_E~0); 29187#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29497#L1382-1 assume !(1 == ~T11_E~0); 29498#L1387-1 assume !(1 == ~T12_E~0); 30194#L1392-1 assume !(1 == ~E_M~0); 29526#L1397-1 assume !(1 == ~E_1~0); 29527#L1402-1 assume !(1 == ~E_2~0); 29201#L1407-1 assume !(1 == ~E_3~0); 29202#L1412-1 assume !(1 == ~E_4~0); 30361#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30362#L1422-1 assume !(1 == ~E_6~0); 30598#L1427-1 assume !(1 == ~E_7~0); 29387#L1432-1 assume !(1 == ~E_8~0); 29388#L1437-1 assume !(1 == ~E_9~0); 30314#L1442-1 assume !(1 == ~E_10~0); 30315#L1447-1 assume !(1 == ~E_11~0); 30186#L1452-1 assume !(1 == ~E_12~0); 28992#L1457-1 assume { :end_inline_reset_delta_events } true; 28993#L1803-2 [2024-11-13 15:57:07,176 INFO L747 eck$LassoCheckResult]: Loop: 28993#L1803-2 assume !false; 29329#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29278#L1169-1 assume !false; 29398#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29568#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29057#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29058#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30402#L996 assume !(0 != eval_~tmp~0#1); 29779#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29443#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29444#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29937#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29160#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29161#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29417#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28863#L1214-3 assume !(0 == ~T5_E~0); 28864#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29615#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29616#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29650#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29028#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29029#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29466#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 30056#L1254-3 assume !(0 == ~E_M~0); 30540#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30169#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29034#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29035#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30575#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29613#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29614#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29595#L1294-3 assume !(0 == ~E_8~0); 29596#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29988#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29989#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 29499#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 29500#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29505#L586-42 assume !(1 == ~m_pc~0); 29506#L586-44 is_master_triggered_~__retres1~0#1 := 0; 29102#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29103#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29569#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 29643#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29644#L605-42 assume 1 == ~t1_pc~0; 30234#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29954#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29955#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29647#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29648#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29654#L624-42 assume !(1 == ~t2_pc~0); 29655#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 29799#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29891#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29892#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29464#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29465#L643-42 assume 1 == ~t3_pc~0; 29825#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29780#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29781#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29610#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29611#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30324#L662-42 assume 1 == ~t4_pc~0; 30528#L663-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29123#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29124#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30302#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30568#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30535#L681-42 assume 1 == ~t5_pc~0; 29836#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28989#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29981#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29982#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30370#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29483#L700-42 assume 1 == ~t6_pc~0; 29484#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29293#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29213#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29214#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30377#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30585#L719-42 assume !(1 == ~t7_pc~0); 29174#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 29175#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29555#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29818#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 29570#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29571#L738-42 assume 1 == ~t8_pc~0; 29770#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29514#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29515#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29032#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29033#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29564#L757-42 assume 1 == ~t9_pc~0; 29910#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29215#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29216#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29968#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29334#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29335#L776-42 assume !(1 == ~t10_pc~0); 30294#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 30295#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30113#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30114#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30620#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30135#L795-42 assume !(1 == ~t11_pc~0); 30136#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 29169#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29170#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29268#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29269#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29580#L814-42 assume 1 == ~t12_pc~0; 30352#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 29082#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 29083#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28890#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28891#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29044#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29045#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29020#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29021#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29850#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30020#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30021#L1357-3 assume !(1 == ~T6_E~0); 30456#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30628#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30624#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28876#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28877#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29480#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 29481#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30320#L1397-3 assume !(1 == ~E_1~0); 30595#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29970#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29128#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29129#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29870#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29871#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30451#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30214#L1437-3 assume !(1 == ~E_9~0); 29990#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29991#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28924#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28925#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29539#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29384#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29198#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 29120#L1822 assume !(0 == start_simulation_~tmp~3#1); 29121#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 30086#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29376#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28878#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 28879#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30042#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30141#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 30479#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 28993#L1803-2 [2024-11-13 15:57:07,176 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:07,177 INFO L85 PathProgramCache]: Analyzing trace with hash 813976236, now seen corresponding path program 1 times [2024-11-13 15:57:07,177 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:07,177 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1102274922] [2024-11-13 15:57:07,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:07,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:07,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:07,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:07,273 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:07,274 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1102274922] [2024-11-13 15:57:07,274 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1102274922] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:07,274 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:07,274 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:07,274 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [191958881] [2024-11-13 15:57:07,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:07,275 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:07,275 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:07,275 INFO L85 PathProgramCache]: Analyzing trace with hash 517700500, now seen corresponding path program 1 times [2024-11-13 15:57:07,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:07,276 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [568595828] [2024-11-13 15:57:07,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:07,276 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:07,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:07,393 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:07,393 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:07,393 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [568595828] [2024-11-13 15:57:07,393 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [568595828] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:07,394 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:07,394 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:07,394 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [866239795] [2024-11-13 15:57:07,394 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:07,394 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:07,395 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:07,395 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:07,395 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:07,395 INFO L87 Difference]: Start difference. First operand 1798 states and 2652 transitions. cyclomatic complexity: 855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:07,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:07,453 INFO L93 Difference]: Finished difference Result 1798 states and 2651 transitions. [2024-11-13 15:57:07,453 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2651 transitions. [2024-11-13 15:57:07,466 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:07,477 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2651 transitions. [2024-11-13 15:57:07,478 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2024-11-13 15:57:07,480 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2024-11-13 15:57:07,480 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2651 transitions. [2024-11-13 15:57:07,484 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:07,484 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2651 transitions. [2024-11-13 15:57:07,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2651 transitions. [2024-11-13 15:57:07,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2024-11-13 15:57:07,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.474416017797553) internal successors, (2651), 1797 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:07,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2651 transitions. [2024-11-13 15:57:07,526 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2651 transitions. [2024-11-13 15:57:07,527 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:07,528 INFO L424 stractBuchiCegarLoop]: Abstraction has 1798 states and 2651 transitions. [2024-11-13 15:57:07,528 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 15:57:07,528 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2651 transitions. [2024-11-13 15:57:07,538 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:07,538 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:07,538 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:07,541 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:07,541 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:07,542 INFO L745 eck$LassoCheckResult]: Stem: 32683#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 32684#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 33618#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33619#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32753#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 32754#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32658#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32659#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33946#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33299#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33300#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33191#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33192#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33700#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33701#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 32950#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32951#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33385#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33386#L1194 assume !(0 == ~M_E~0); 33538#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33539#L1199-1 assume !(0 == ~T2_E~0); 33825#L1204-1 assume !(0 == ~T3_E~0); 33750#L1209-1 assume !(0 == ~T4_E~0); 33751#L1214-1 assume !(0 == ~T5_E~0); 34149#L1219-1 assume !(0 == ~T6_E~0); 34235#L1224-1 assume !(0 == ~T7_E~0); 33024#L1229-1 assume !(0 == ~T8_E~0); 32578#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32579#L1239-1 assume !(0 == ~T10_E~0); 32621#L1244-1 assume !(0 == ~T11_E~0); 32622#L1249-1 assume !(0 == ~T12_E~0); 33329#L1254-1 assume !(0 == ~E_M~0); 32520#L1259-1 assume !(0 == ~E_1~0); 32485#L1264-1 assume !(0 == ~E_2~0); 32486#L1269-1 assume !(0 == ~E_3~0); 34237#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 34181#L1279-1 assume !(0 == ~E_5~0); 32694#L1284-1 assume !(0 == ~E_6~0); 32695#L1289-1 assume !(0 == ~E_7~0); 33392#L1294-1 assume !(0 == ~E_8~0); 33393#L1299-1 assume !(0 == ~E_9~0); 33404#L1304-1 assume !(0 == ~E_10~0); 34228#L1309-1 assume !(0 == ~E_11~0); 34233#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 32651#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32575#L586 assume 1 == ~m_pc~0; 32576#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32643#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33464#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32850#L1485 assume !(0 != activate_threads_~tmp~1#1); 32851#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33952#L605 assume !(1 == ~t1_pc~0); 33478#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33220#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33221#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33864#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33799#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33128#L624 assume 1 == ~t2_pc~0; 32625#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32626#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32877#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32878#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 33984#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33862#L643 assume !(1 == ~t3_pc~0); 33720#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33422#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33423#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32957#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 32958#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32715#L662 assume 1 == ~t4_pc~0; 32716#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32674#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32537#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32538#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 32564#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32565#L681 assume !(1 == ~t5_pc~0); 32441#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32442#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33504#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34110#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 32969#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32970#L700 assume 1 == ~t6_pc~0; 33680#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32707#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32708#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32755#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 32756#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34038#L719 assume 1 == ~t7_pc~0; 34119#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32926#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34225#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34167#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 32455#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32456#L738 assume !(1 == ~t8_pc~0); 33832#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 33741#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33742#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33534#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33535#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33884#L757 assume 1 == ~t9_pc~0; 33885#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32450#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32451#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32924#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 33496#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33497#L776 assume !(1 == ~t10_pc~0); 32472#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32471#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32854#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32696#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 32697#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32652#L795 assume 1 == ~t11_pc~0; 32653#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32989#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33966#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34137#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 33714#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33704#L814 assume !(1 == ~t12_pc~0); 33564#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33565#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32498#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32499#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 32908#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32909#L1332 assume !(1 == ~M_E~0); 33997#L1332-2 assume !(1 == ~T1_E~0); 34199#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33635#L1342-1 assume !(1 == ~T3_E~0); 33636#L1347-1 assume !(1 == ~T4_E~0); 34025#L1352-1 assume !(1 == ~T5_E~0); 33890#L1357-1 assume !(1 == ~T6_E~0); 33189#L1362-1 assume !(1 == ~T7_E~0); 33190#L1367-1 assume !(1 == ~T8_E~0); 32789#L1372-1 assume !(1 == ~T9_E~0); 32790#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33100#L1382-1 assume !(1 == ~T11_E~0); 33101#L1387-1 assume !(1 == ~T12_E~0); 33797#L1392-1 assume !(1 == ~E_M~0); 33129#L1397-1 assume !(1 == ~E_1~0); 33130#L1402-1 assume !(1 == ~E_2~0); 32804#L1407-1 assume !(1 == ~E_3~0); 32805#L1412-1 assume !(1 == ~E_4~0); 33964#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 33965#L1422-1 assume !(1 == ~E_6~0); 34201#L1427-1 assume !(1 == ~E_7~0); 32990#L1432-1 assume !(1 == ~E_8~0); 32991#L1437-1 assume !(1 == ~E_9~0); 33917#L1442-1 assume !(1 == ~E_10~0); 33918#L1447-1 assume !(1 == ~E_11~0); 33789#L1452-1 assume !(1 == ~E_12~0); 32595#L1457-1 assume { :end_inline_reset_delta_events } true; 32596#L1803-2 [2024-11-13 15:57:07,542 INFO L747 eck$LassoCheckResult]: Loop: 32596#L1803-2 assume !false; 32932#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32881#L1169-1 assume !false; 33001#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33171#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32660#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32661#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34005#L996 assume !(0 != eval_~tmp~0#1); 33382#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33046#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33047#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33540#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32763#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32764#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33020#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32464#L1214-3 assume !(0 == ~T5_E~0); 32465#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33218#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33219#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33253#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32631#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32632#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33069#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 33659#L1254-3 assume !(0 == ~E_M~0); 34143#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33772#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32637#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32638#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 34178#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33216#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33217#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33198#L1294-3 assume !(0 == ~E_8~0); 33199#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33591#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 33592#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 33102#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 33103#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33108#L586-42 assume !(1 == ~m_pc~0); 33109#L586-44 is_master_triggered_~__retres1~0#1 := 0; 32705#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32706#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33172#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 33246#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33247#L605-42 assume 1 == ~t1_pc~0; 33837#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33557#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33558#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33248#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33249#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33257#L624-42 assume !(1 == ~t2_pc~0); 33258#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 33402#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33494#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33495#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33067#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33068#L643-42 assume 1 == ~t3_pc~0; 33426#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33383#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33384#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33213#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33214#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33927#L662-42 assume !(1 == ~t4_pc~0); 34130#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 32726#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32727#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33905#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34171#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34138#L681-42 assume 1 == ~t5_pc~0; 33436#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32592#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33584#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33585#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33973#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33086#L700-42 assume 1 == ~t6_pc~0; 33087#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32896#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32816#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32817#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33980#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34188#L719-42 assume 1 == ~t7_pc~0; 33697#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32778#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33158#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33421#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 33173#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33174#L738-42 assume 1 == ~t8_pc~0; 33372#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33117#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33118#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32635#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32636#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33167#L757-42 assume 1 == ~t9_pc~0; 33510#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32818#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32819#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33571#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32937#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32938#L776-42 assume !(1 == ~t10_pc~0); 33897#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 33898#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33715#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33716#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34223#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33738#L795-42 assume !(1 == ~t11_pc~0); 33739#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 32772#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32773#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32871#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32872#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33183#L814-42 assume 1 == ~t12_pc~0; 33955#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 32685#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32686#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32493#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32494#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32647#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32648#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32623#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32624#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33453#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33623#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33624#L1357-3 assume !(1 == ~T6_E~0); 34059#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34231#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34227#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32479#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32480#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33083#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33084#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33923#L1397-3 assume !(1 == ~E_1~0); 34198#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33573#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32731#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32732#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33473#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33474#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 34056#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33818#L1437-3 assume !(1 == ~E_9~0); 33593#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33594#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32527#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 32528#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33146#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32987#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32803#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 32723#L1822 assume !(0 == start_simulation_~tmp~3#1); 32724#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33689#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32984#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32481#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 32482#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33645#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33744#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 34084#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 32596#L1803-2 [2024-11-13 15:57:07,543 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:07,543 INFO L85 PathProgramCache]: Analyzing trace with hash -1345107858, now seen corresponding path program 1 times [2024-11-13 15:57:07,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:07,544 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [855937968] [2024-11-13 15:57:07,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:07,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:07,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:07,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:07,619 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:07,619 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [855937968] [2024-11-13 15:57:07,619 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [855937968] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:07,619 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:07,619 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:07,619 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [681415494] [2024-11-13 15:57:07,619 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:07,620 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:07,620 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:07,621 INFO L85 PathProgramCache]: Analyzing trace with hash 1493785940, now seen corresponding path program 1 times [2024-11-13 15:57:07,621 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:07,621 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1566902838] [2024-11-13 15:57:07,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:07,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:07,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:07,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:07,720 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:07,720 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1566902838] [2024-11-13 15:57:07,720 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1566902838] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:07,721 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:07,721 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:07,721 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [532547916] [2024-11-13 15:57:07,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:07,722 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:07,722 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:07,722 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:07,723 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:07,723 INFO L87 Difference]: Start difference. First operand 1798 states and 2651 transitions. cyclomatic complexity: 854 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:07,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:07,779 INFO L93 Difference]: Finished difference Result 1798 states and 2650 transitions. [2024-11-13 15:57:07,779 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2650 transitions. [2024-11-13 15:57:07,791 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:07,806 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2650 transitions. [2024-11-13 15:57:07,806 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2024-11-13 15:57:07,808 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2024-11-13 15:57:07,808 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2650 transitions. [2024-11-13 15:57:07,812 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:07,812 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2650 transitions. [2024-11-13 15:57:07,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2650 transitions. [2024-11-13 15:57:07,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2024-11-13 15:57:07,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.4738598442714126) internal successors, (2650), 1797 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:07,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2650 transitions. [2024-11-13 15:57:07,857 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2650 transitions. [2024-11-13 15:57:07,857 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:07,858 INFO L424 stractBuchiCegarLoop]: Abstraction has 1798 states and 2650 transitions. [2024-11-13 15:57:07,858 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 15:57:07,858 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2650 transitions. [2024-11-13 15:57:07,868 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:07,869 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:07,869 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:07,871 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:07,872 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:07,872 INFO L745 eck$LassoCheckResult]: Stem: 36286#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 36287#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 37221#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37222#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36356#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 36357#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36261#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36262#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37549#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36902#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36903#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36794#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36795#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37303#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 37304#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36553#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 36554#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 36988#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36989#L1194 assume !(0 == ~M_E~0); 37141#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37142#L1199-1 assume !(0 == ~T2_E~0); 37428#L1204-1 assume !(0 == ~T3_E~0); 37353#L1209-1 assume !(0 == ~T4_E~0); 37354#L1214-1 assume !(0 == ~T5_E~0); 37752#L1219-1 assume !(0 == ~T6_E~0); 37838#L1224-1 assume !(0 == ~T7_E~0); 36627#L1229-1 assume !(0 == ~T8_E~0); 36181#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36182#L1239-1 assume !(0 == ~T10_E~0); 36224#L1244-1 assume !(0 == ~T11_E~0); 36225#L1249-1 assume !(0 == ~T12_E~0); 36932#L1254-1 assume !(0 == ~E_M~0); 36123#L1259-1 assume !(0 == ~E_1~0); 36088#L1264-1 assume !(0 == ~E_2~0); 36089#L1269-1 assume !(0 == ~E_3~0); 37840#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 37784#L1279-1 assume !(0 == ~E_5~0); 36297#L1284-1 assume !(0 == ~E_6~0); 36298#L1289-1 assume !(0 == ~E_7~0); 36995#L1294-1 assume !(0 == ~E_8~0); 36996#L1299-1 assume !(0 == ~E_9~0); 37007#L1304-1 assume !(0 == ~E_10~0); 37831#L1309-1 assume !(0 == ~E_11~0); 37836#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 36254#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36178#L586 assume 1 == ~m_pc~0; 36179#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36246#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37067#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36453#L1485 assume !(0 != activate_threads_~tmp~1#1); 36454#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37555#L605 assume !(1 == ~t1_pc~0); 37081#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36823#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36824#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37467#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37402#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36731#L624 assume 1 == ~t2_pc~0; 36228#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36229#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36480#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36481#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 37587#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37465#L643 assume !(1 == ~t3_pc~0); 37323#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37025#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37026#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36560#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 36561#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36318#L662 assume 1 == ~t4_pc~0; 36319#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36277#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36140#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36141#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 36167#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36168#L681 assume !(1 == ~t5_pc~0); 36044#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36045#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37107#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37713#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 36572#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36573#L700 assume 1 == ~t6_pc~0; 37283#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36310#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36311#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36358#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 36359#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37641#L719 assume 1 == ~t7_pc~0; 37722#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36529#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37828#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37770#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 36058#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36059#L738 assume !(1 == ~t8_pc~0); 37435#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 37344#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37345#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37137#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37138#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37487#L757 assume 1 == ~t9_pc~0; 37488#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36053#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36054#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36527#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 37099#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37100#L776 assume !(1 == ~t10_pc~0); 36075#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36074#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36457#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36299#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 36300#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36255#L795 assume 1 == ~t11_pc~0; 36256#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36592#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37569#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37740#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 37317#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37307#L814 assume !(1 == ~t12_pc~0); 37167#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 37168#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36101#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36102#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 36511#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36512#L1332 assume !(1 == ~M_E~0); 37600#L1332-2 assume !(1 == ~T1_E~0); 37802#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37238#L1342-1 assume !(1 == ~T3_E~0); 37239#L1347-1 assume !(1 == ~T4_E~0); 37628#L1352-1 assume !(1 == ~T5_E~0); 37493#L1357-1 assume !(1 == ~T6_E~0); 36792#L1362-1 assume !(1 == ~T7_E~0); 36793#L1367-1 assume !(1 == ~T8_E~0); 36392#L1372-1 assume !(1 == ~T9_E~0); 36393#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36703#L1382-1 assume !(1 == ~T11_E~0); 36704#L1387-1 assume !(1 == ~T12_E~0); 37400#L1392-1 assume !(1 == ~E_M~0); 36732#L1397-1 assume !(1 == ~E_1~0); 36733#L1402-1 assume !(1 == ~E_2~0); 36407#L1407-1 assume !(1 == ~E_3~0); 36408#L1412-1 assume !(1 == ~E_4~0); 37567#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 37568#L1422-1 assume !(1 == ~E_6~0); 37804#L1427-1 assume !(1 == ~E_7~0); 36593#L1432-1 assume !(1 == ~E_8~0); 36594#L1437-1 assume !(1 == ~E_9~0); 37520#L1442-1 assume !(1 == ~E_10~0); 37521#L1447-1 assume !(1 == ~E_11~0); 37392#L1452-1 assume !(1 == ~E_12~0); 36198#L1457-1 assume { :end_inline_reset_delta_events } true; 36199#L1803-2 [2024-11-13 15:57:07,873 INFO L747 eck$LassoCheckResult]: Loop: 36199#L1803-2 assume !false; 36535#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36484#L1169-1 assume !false; 36604#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36774#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36263#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36264#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 37608#L996 assume !(0 != eval_~tmp~0#1); 36985#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36649#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36650#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37143#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36366#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36367#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36623#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36067#L1214-3 assume !(0 == ~T5_E~0); 36068#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36821#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36822#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36856#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36234#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36235#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36672#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 37262#L1254-3 assume !(0 == ~E_M~0); 37746#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37375#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36240#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36241#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37781#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36819#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36820#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36801#L1294-3 assume !(0 == ~E_8~0); 36802#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 37194#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37195#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36705#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 36706#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36711#L586-42 assume !(1 == ~m_pc~0); 36712#L586-44 is_master_triggered_~__retres1~0#1 := 0; 36308#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36309#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36775#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 36849#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36850#L605-42 assume 1 == ~t1_pc~0; 37440#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37160#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37161#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36851#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36852#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36860#L624-42 assume !(1 == ~t2_pc~0); 36861#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 37005#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37097#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37098#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36670#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36671#L643-42 assume 1 == ~t3_pc~0; 37029#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36986#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36987#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36816#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36817#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37530#L662-42 assume !(1 == ~t4_pc~0); 37733#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 36329#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36330#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37508#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37774#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37741#L681-42 assume !(1 == ~t5_pc~0); 36194#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 36195#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37187#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37188#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37576#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36689#L700-42 assume 1 == ~t6_pc~0; 36690#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36499#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36419#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36420#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37583#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37791#L719-42 assume 1 == ~t7_pc~0; 37300#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36381#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36761#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37024#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 36776#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36777#L738-42 assume !(1 == ~t8_pc~0); 36976#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 36720#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36721#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36238#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36239#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36770#L757-42 assume 1 == ~t9_pc~0; 37113#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36421#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36422#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37174#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36540#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36541#L776-42 assume !(1 == ~t10_pc~0); 37500#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 37501#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37318#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37319#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37826#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37341#L795-42 assume !(1 == ~t11_pc~0); 37342#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 36375#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36376#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36474#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36475#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36786#L814-42 assume 1 == ~t12_pc~0; 37558#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36288#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36289#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36096#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36097#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36250#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36251#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36226#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36227#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37056#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37226#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37227#L1357-3 assume !(1 == ~T6_E~0); 37662#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37834#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37830#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36082#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36083#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36686#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36687#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37526#L1397-3 assume !(1 == ~E_1~0); 37801#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37176#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36334#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36335#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37076#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37077#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37659#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37421#L1437-3 assume !(1 == ~E_9~0); 37196#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37197#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 36130#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 36131#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36749#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36590#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36406#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 36326#L1822 assume !(0 == start_simulation_~tmp~3#1); 36327#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37292#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36587#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36084#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 36085#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37248#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37347#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 37687#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 36199#L1803-2 [2024-11-13 15:57:07,873 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:07,873 INFO L85 PathProgramCache]: Analyzing trace with hash -1762996560, now seen corresponding path program 1 times [2024-11-13 15:57:07,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:07,874 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [222995467] [2024-11-13 15:57:07,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:07,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:07,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:07,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:07,948 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:07,948 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [222995467] [2024-11-13 15:57:07,948 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [222995467] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:07,948 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:07,948 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:07,948 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1787898573] [2024-11-13 15:57:07,949 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:07,949 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:07,949 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:07,950 INFO L85 PathProgramCache]: Analyzing trace with hash 1146174614, now seen corresponding path program 1 times [2024-11-13 15:57:07,950 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:07,950 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2036536824] [2024-11-13 15:57:07,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:07,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:07,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:08,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:08,089 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:08,089 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2036536824] [2024-11-13 15:57:08,089 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2036536824] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:08,089 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:08,089 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:08,089 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1225303904] [2024-11-13 15:57:08,089 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:08,090 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:08,090 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:08,091 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:08,091 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:08,092 INFO L87 Difference]: Start difference. First operand 1798 states and 2650 transitions. cyclomatic complexity: 853 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:08,149 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:08,149 INFO L93 Difference]: Finished difference Result 1798 states and 2649 transitions. [2024-11-13 15:57:08,149 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2649 transitions. [2024-11-13 15:57:08,162 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:08,179 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2649 transitions. [2024-11-13 15:57:08,179 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2024-11-13 15:57:08,181 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2024-11-13 15:57:08,182 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2649 transitions. [2024-11-13 15:57:08,185 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:08,186 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2649 transitions. [2024-11-13 15:57:08,190 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2649 transitions. [2024-11-13 15:57:08,217 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2024-11-13 15:57:08,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.4733036707452725) internal successors, (2649), 1797 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:08,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2649 transitions. [2024-11-13 15:57:08,239 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2649 transitions. [2024-11-13 15:57:08,239 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:08,239 INFO L424 stractBuchiCegarLoop]: Abstraction has 1798 states and 2649 transitions. [2024-11-13 15:57:08,240 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 15:57:08,240 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2649 transitions. [2024-11-13 15:57:08,249 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:08,250 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:08,250 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:08,252 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:08,253 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:08,253 INFO L745 eck$LassoCheckResult]: Stem: 39889#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 39890#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 40824#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40825#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39959#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 39960#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39864#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39865#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41152#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40505#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40506#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40397#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40398#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40906#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40907#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40156#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40157#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40591#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40592#L1194 assume !(0 == ~M_E~0); 40744#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40745#L1199-1 assume !(0 == ~T2_E~0); 41031#L1204-1 assume !(0 == ~T3_E~0); 40956#L1209-1 assume !(0 == ~T4_E~0); 40957#L1214-1 assume !(0 == ~T5_E~0); 41355#L1219-1 assume !(0 == ~T6_E~0); 41441#L1224-1 assume !(0 == ~T7_E~0); 40230#L1229-1 assume !(0 == ~T8_E~0); 39784#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39785#L1239-1 assume !(0 == ~T10_E~0); 39827#L1244-1 assume !(0 == ~T11_E~0); 39828#L1249-1 assume !(0 == ~T12_E~0); 40535#L1254-1 assume !(0 == ~E_M~0); 39726#L1259-1 assume !(0 == ~E_1~0); 39691#L1264-1 assume !(0 == ~E_2~0); 39692#L1269-1 assume !(0 == ~E_3~0); 41443#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 41387#L1279-1 assume !(0 == ~E_5~0); 39900#L1284-1 assume !(0 == ~E_6~0); 39901#L1289-1 assume !(0 == ~E_7~0); 40598#L1294-1 assume !(0 == ~E_8~0); 40599#L1299-1 assume !(0 == ~E_9~0); 40610#L1304-1 assume !(0 == ~E_10~0); 41434#L1309-1 assume !(0 == ~E_11~0); 41439#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 39857#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39781#L586 assume 1 == ~m_pc~0; 39782#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39849#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40670#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40056#L1485 assume !(0 != activate_threads_~tmp~1#1); 40057#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41158#L605 assume !(1 == ~t1_pc~0); 40684#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40426#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40427#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41070#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41005#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40334#L624 assume 1 == ~t2_pc~0; 39831#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39832#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40083#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40084#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 41190#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41068#L643 assume !(1 == ~t3_pc~0); 40926#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40628#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40629#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40163#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 40164#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39921#L662 assume 1 == ~t4_pc~0; 39922#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39880#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39743#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39744#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 39770#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39771#L681 assume !(1 == ~t5_pc~0); 39647#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39648#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40710#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41316#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 40175#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40176#L700 assume 1 == ~t6_pc~0; 40886#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39913#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39914#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39961#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 39962#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41244#L719 assume 1 == ~t7_pc~0; 41325#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40132#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41431#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41373#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 39661#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39662#L738 assume !(1 == ~t8_pc~0); 41038#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 40947#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40948#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40740#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40741#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41090#L757 assume 1 == ~t9_pc~0; 41091#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39656#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39657#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40130#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 40702#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40703#L776 assume !(1 == ~t10_pc~0); 39678#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39677#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40060#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39902#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 39903#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39858#L795 assume 1 == ~t11_pc~0; 39859#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 40195#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41172#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41343#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 40920#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40910#L814 assume !(1 == ~t12_pc~0); 40770#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40771#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39704#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39705#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 40114#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40115#L1332 assume !(1 == ~M_E~0); 41203#L1332-2 assume !(1 == ~T1_E~0); 41405#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40841#L1342-1 assume !(1 == ~T3_E~0); 40842#L1347-1 assume !(1 == ~T4_E~0); 41231#L1352-1 assume !(1 == ~T5_E~0); 41096#L1357-1 assume !(1 == ~T6_E~0); 40395#L1362-1 assume !(1 == ~T7_E~0); 40396#L1367-1 assume !(1 == ~T8_E~0); 39995#L1372-1 assume !(1 == ~T9_E~0); 39996#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40306#L1382-1 assume !(1 == ~T11_E~0); 40307#L1387-1 assume !(1 == ~T12_E~0); 41003#L1392-1 assume !(1 == ~E_M~0); 40335#L1397-1 assume !(1 == ~E_1~0); 40336#L1402-1 assume !(1 == ~E_2~0); 40010#L1407-1 assume !(1 == ~E_3~0); 40011#L1412-1 assume !(1 == ~E_4~0); 41170#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 41171#L1422-1 assume !(1 == ~E_6~0); 41407#L1427-1 assume !(1 == ~E_7~0); 40196#L1432-1 assume !(1 == ~E_8~0); 40197#L1437-1 assume !(1 == ~E_9~0); 41123#L1442-1 assume !(1 == ~E_10~0); 41124#L1447-1 assume !(1 == ~E_11~0); 40995#L1452-1 assume !(1 == ~E_12~0); 39801#L1457-1 assume { :end_inline_reset_delta_events } true; 39802#L1803-2 [2024-11-13 15:57:08,254 INFO L747 eck$LassoCheckResult]: Loop: 39802#L1803-2 assume !false; 40138#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40087#L1169-1 assume !false; 40207#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40377#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39866#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39867#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 41211#L996 assume !(0 != eval_~tmp~0#1); 40588#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40252#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40253#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40746#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39969#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 39970#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40226#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39670#L1214-3 assume !(0 == ~T5_E~0); 39671#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40424#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40425#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40459#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39837#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 39838#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40275#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 40865#L1254-3 assume !(0 == ~E_M~0); 41349#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40978#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 39843#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39844#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 41384#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40422#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40423#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40404#L1294-3 assume !(0 == ~E_8~0); 40405#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40797#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40798#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40308#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 40309#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40314#L586-42 assume !(1 == ~m_pc~0); 40315#L586-44 is_master_triggered_~__retres1~0#1 := 0; 39911#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39912#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40378#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 40452#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40453#L605-42 assume 1 == ~t1_pc~0; 41043#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40763#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40764#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40454#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40455#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40463#L624-42 assume !(1 == ~t2_pc~0); 40464#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 40608#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40700#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40701#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40273#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40274#L643-42 assume 1 == ~t3_pc~0; 40632#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40589#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40590#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40419#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40420#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41133#L662-42 assume !(1 == ~t4_pc~0); 41336#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 39932#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39933#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41111#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41377#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41344#L681-42 assume 1 == ~t5_pc~0; 40642#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39798#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40790#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40791#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41179#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40292#L700-42 assume 1 == ~t6_pc~0; 40293#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40102#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40022#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40023#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41186#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41394#L719-42 assume 1 == ~t7_pc~0; 40903#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39984#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40364#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40627#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 40379#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40380#L738-42 assume 1 == ~t8_pc~0; 40578#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40323#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40324#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39841#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39842#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40373#L757-42 assume 1 == ~t9_pc~0; 40716#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40024#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40025#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40777#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 40143#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40144#L776-42 assume 1 == ~t10_pc~0; 41120#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41104#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40921#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40922#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41429#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40944#L795-42 assume !(1 == ~t11_pc~0); 40945#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 39978#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39979#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40077#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40078#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40389#L814-42 assume !(1 == ~t12_pc~0); 40258#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 39891#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39892#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39699#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 39700#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39853#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39854#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39829#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39830#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40659#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40829#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40830#L1357-3 assume !(1 == ~T6_E~0); 41265#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41437#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41433#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 39685#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 39686#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40289#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 40290#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41129#L1397-3 assume !(1 == ~E_1~0); 41404#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40779#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39937#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39938#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40679#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40680#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41262#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41024#L1437-3 assume !(1 == ~E_9~0); 40799#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40800#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 39733#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 39734#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40352#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40193#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40009#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 39929#L1822 assume !(0 == start_simulation_~tmp~3#1); 39930#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40895#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40190#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39687#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 39688#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40851#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40950#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 41290#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 39802#L1803-2 [2024-11-13 15:57:08,254 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:08,255 INFO L85 PathProgramCache]: Analyzing trace with hash 1133017134, now seen corresponding path program 1 times [2024-11-13 15:57:08,255 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:08,255 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981246485] [2024-11-13 15:57:08,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:08,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:08,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:08,332 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:08,332 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:08,332 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1981246485] [2024-11-13 15:57:08,332 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1981246485] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:08,332 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:08,332 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:08,332 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [586186998] [2024-11-13 15:57:08,332 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:08,333 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:08,333 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:08,333 INFO L85 PathProgramCache]: Analyzing trace with hash 380040916, now seen corresponding path program 1 times [2024-11-13 15:57:08,333 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:08,333 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [940715751] [2024-11-13 15:57:08,334 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:08,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:08,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:08,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:08,427 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:08,427 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [940715751] [2024-11-13 15:57:08,427 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [940715751] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:08,428 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:08,428 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:08,428 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1253246159] [2024-11-13 15:57:08,428 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:08,428 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:08,428 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:08,429 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:08,429 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:08,429 INFO L87 Difference]: Start difference. First operand 1798 states and 2649 transitions. cyclomatic complexity: 852 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:08,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:08,485 INFO L93 Difference]: Finished difference Result 1798 states and 2648 transitions. [2024-11-13 15:57:08,485 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2648 transitions. [2024-11-13 15:57:08,497 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:08,512 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2648 transitions. [2024-11-13 15:57:08,513 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2024-11-13 15:57:08,515 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2024-11-13 15:57:08,515 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2648 transitions. [2024-11-13 15:57:08,518 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:08,519 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2648 transitions. [2024-11-13 15:57:08,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2648 transitions. [2024-11-13 15:57:08,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2024-11-13 15:57:08,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.4727474972191323) internal successors, (2648), 1797 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:08,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2648 transitions. [2024-11-13 15:57:08,569 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2648 transitions. [2024-11-13 15:57:08,570 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:08,570 INFO L424 stractBuchiCegarLoop]: Abstraction has 1798 states and 2648 transitions. [2024-11-13 15:57:08,570 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 15:57:08,571 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2648 transitions. [2024-11-13 15:57:08,583 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:08,583 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:08,583 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:08,586 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:08,590 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:08,591 INFO L745 eck$LassoCheckResult]: Stem: 43492#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 43493#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 44427#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44428#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43562#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 43563#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43467#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43468#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 44755#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 44108#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44109#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44000#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 44001#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44509#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44510#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43759#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43760#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 44194#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44195#L1194 assume !(0 == ~M_E~0); 44347#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44348#L1199-1 assume !(0 == ~T2_E~0); 44634#L1204-1 assume !(0 == ~T3_E~0); 44559#L1209-1 assume !(0 == ~T4_E~0); 44560#L1214-1 assume !(0 == ~T5_E~0); 44958#L1219-1 assume !(0 == ~T6_E~0); 45044#L1224-1 assume !(0 == ~T7_E~0); 43833#L1229-1 assume !(0 == ~T8_E~0); 43387#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43388#L1239-1 assume !(0 == ~T10_E~0); 43430#L1244-1 assume !(0 == ~T11_E~0); 43431#L1249-1 assume !(0 == ~T12_E~0); 44138#L1254-1 assume !(0 == ~E_M~0); 43329#L1259-1 assume !(0 == ~E_1~0); 43294#L1264-1 assume !(0 == ~E_2~0); 43295#L1269-1 assume !(0 == ~E_3~0); 45046#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 44990#L1279-1 assume !(0 == ~E_5~0); 43503#L1284-1 assume !(0 == ~E_6~0); 43504#L1289-1 assume !(0 == ~E_7~0); 44201#L1294-1 assume !(0 == ~E_8~0); 44202#L1299-1 assume !(0 == ~E_9~0); 44213#L1304-1 assume !(0 == ~E_10~0); 45037#L1309-1 assume !(0 == ~E_11~0); 45042#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 43460#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43384#L586 assume 1 == ~m_pc~0; 43385#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 43452#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44273#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43659#L1485 assume !(0 != activate_threads_~tmp~1#1); 43660#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44761#L605 assume !(1 == ~t1_pc~0); 44287#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 44029#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44030#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44673#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44608#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43937#L624 assume 1 == ~t2_pc~0; 43434#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43435#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43686#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43687#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 44793#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44671#L643 assume !(1 == ~t3_pc~0); 44529#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44231#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44232#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43766#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 43767#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43524#L662 assume 1 == ~t4_pc~0; 43525#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43483#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43346#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43347#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 43373#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43374#L681 assume !(1 == ~t5_pc~0); 43250#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 43251#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44313#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44919#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 43778#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43779#L700 assume 1 == ~t6_pc~0; 44489#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43516#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43517#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43564#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 43565#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44847#L719 assume 1 == ~t7_pc~0; 44928#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43735#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45034#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44976#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 43264#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43265#L738 assume !(1 == ~t8_pc~0); 44641#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 44550#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44551#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44343#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44344#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44693#L757 assume 1 == ~t9_pc~0; 44694#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43259#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43260#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43733#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 44305#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44306#L776 assume !(1 == ~t10_pc~0); 43281#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 43280#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43663#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43505#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 43506#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43461#L795 assume 1 == ~t11_pc~0; 43462#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43798#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44775#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44946#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 44523#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44513#L814 assume !(1 == ~t12_pc~0); 44373#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 44374#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43307#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43308#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 43717#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43718#L1332 assume !(1 == ~M_E~0); 44806#L1332-2 assume !(1 == ~T1_E~0); 45008#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44444#L1342-1 assume !(1 == ~T3_E~0); 44445#L1347-1 assume !(1 == ~T4_E~0); 44834#L1352-1 assume !(1 == ~T5_E~0); 44699#L1357-1 assume !(1 == ~T6_E~0); 43998#L1362-1 assume !(1 == ~T7_E~0); 43999#L1367-1 assume !(1 == ~T8_E~0); 43598#L1372-1 assume !(1 == ~T9_E~0); 43599#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43909#L1382-1 assume !(1 == ~T11_E~0); 43910#L1387-1 assume !(1 == ~T12_E~0); 44606#L1392-1 assume !(1 == ~E_M~0); 43938#L1397-1 assume !(1 == ~E_1~0); 43939#L1402-1 assume !(1 == ~E_2~0); 43613#L1407-1 assume !(1 == ~E_3~0); 43614#L1412-1 assume !(1 == ~E_4~0); 44773#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 44774#L1422-1 assume !(1 == ~E_6~0); 45010#L1427-1 assume !(1 == ~E_7~0); 43799#L1432-1 assume !(1 == ~E_8~0); 43800#L1437-1 assume !(1 == ~E_9~0); 44726#L1442-1 assume !(1 == ~E_10~0); 44727#L1447-1 assume !(1 == ~E_11~0); 44598#L1452-1 assume !(1 == ~E_12~0); 43404#L1457-1 assume { :end_inline_reset_delta_events } true; 43405#L1803-2 [2024-11-13 15:57:08,591 INFO L747 eck$LassoCheckResult]: Loop: 43405#L1803-2 assume !false; 43741#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43690#L1169-1 assume !false; 43810#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43980#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43469#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43470#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 44814#L996 assume !(0 != eval_~tmp~0#1); 44191#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43855#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43856#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44349#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 43572#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 43573#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43829#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43273#L1214-3 assume !(0 == ~T5_E~0); 43274#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44027#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44028#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44062#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43440#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 43441#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43878#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 44468#L1254-3 assume !(0 == ~E_M~0); 44952#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44581#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43446#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43447#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44987#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44025#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44026#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 44007#L1294-3 assume !(0 == ~E_8~0); 44008#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 44400#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44401#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43911#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 43912#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43917#L586-42 assume !(1 == ~m_pc~0); 43918#L586-44 is_master_triggered_~__retres1~0#1 := 0; 43514#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43515#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43981#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 44055#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44056#L605-42 assume 1 == ~t1_pc~0; 44646#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44366#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44367#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44057#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44058#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44066#L624-42 assume !(1 == ~t2_pc~0); 44067#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 44211#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44303#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44304#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43876#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43877#L643-42 assume 1 == ~t3_pc~0; 44235#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44192#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44193#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44022#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44023#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44736#L662-42 assume !(1 == ~t4_pc~0); 44939#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 43535#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43536#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44714#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44980#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44947#L681-42 assume 1 == ~t5_pc~0; 44245#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43401#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44393#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44394#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 44782#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43895#L700-42 assume 1 == ~t6_pc~0; 43896#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43705#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43625#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43626#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 44789#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44997#L719-42 assume !(1 == ~t7_pc~0); 43586#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 43587#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43967#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44230#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 43982#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43983#L738-42 assume 1 == ~t8_pc~0; 44181#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43926#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43927#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43444#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43445#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43976#L757-42 assume !(1 == ~t9_pc~0); 44320#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 43627#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43628#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44380#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43746#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43747#L776-42 assume !(1 == ~t10_pc~0); 44706#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 44707#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44524#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44525#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45032#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44547#L795-42 assume !(1 == ~t11_pc~0); 44548#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 43581#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43582#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43680#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43681#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43992#L814-42 assume !(1 == ~t12_pc~0); 43861#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 43494#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43495#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43302#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43303#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43456#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43457#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43432#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43433#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44262#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44432#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44433#L1357-3 assume !(1 == ~T6_E~0); 44868#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 45040#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 45036#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 43288#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43289#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43892#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43893#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44732#L1397-3 assume !(1 == ~E_1~0); 45007#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44382#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 43540#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43541#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44282#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 44283#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44865#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 44627#L1437-3 assume !(1 == ~E_9~0); 44402#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44403#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 43336#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 43337#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43955#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43796#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43612#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 43532#L1822 assume !(0 == start_simulation_~tmp~3#1); 43533#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44498#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43793#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43290#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 43291#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44454#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44553#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 44893#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 43405#L1803-2 [2024-11-13 15:57:08,592 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:08,592 INFO L85 PathProgramCache]: Analyzing trace with hash -1544509712, now seen corresponding path program 1 times [2024-11-13 15:57:08,592 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:08,592 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [70116495] [2024-11-13 15:57:08,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:08,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:08,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:08,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:08,704 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:08,704 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [70116495] [2024-11-13 15:57:08,704 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [70116495] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:08,704 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:08,704 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:57:08,705 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [904644289] [2024-11-13 15:57:08,705 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:08,705 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:08,705 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:08,707 INFO L85 PathProgramCache]: Analyzing trace with hash 1338336407, now seen corresponding path program 1 times [2024-11-13 15:57:08,707 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:08,707 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1758801478] [2024-11-13 15:57:08,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:08,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:08,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:08,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:08,830 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:08,830 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1758801478] [2024-11-13 15:57:08,830 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1758801478] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:08,830 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:08,830 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:08,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56064504] [2024-11-13 15:57:08,830 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:08,831 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:08,831 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:08,832 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:08,832 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:08,832 INFO L87 Difference]: Start difference. First operand 1798 states and 2648 transitions. cyclomatic complexity: 851 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:08,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:08,904 INFO L93 Difference]: Finished difference Result 1798 states and 2643 transitions. [2024-11-13 15:57:08,904 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1798 states and 2643 transitions. [2024-11-13 15:57:08,917 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:08,927 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1798 states to 1798 states and 2643 transitions. [2024-11-13 15:57:08,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1798 [2024-11-13 15:57:08,929 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1798 [2024-11-13 15:57:08,930 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1798 states and 2643 transitions. [2024-11-13 15:57:08,933 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:08,933 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2643 transitions. [2024-11-13 15:57:08,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1798 states and 2643 transitions. [2024-11-13 15:57:08,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1798 to 1798. [2024-11-13 15:57:08,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1798 states, 1798 states have (on average 1.4699666295884315) internal successors, (2643), 1797 states have internal predecessors, (2643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:08,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1798 states to 1798 states and 2643 transitions. [2024-11-13 15:57:08,983 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1798 states and 2643 transitions. [2024-11-13 15:57:08,984 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:08,985 INFO L424 stractBuchiCegarLoop]: Abstraction has 1798 states and 2643 transitions. [2024-11-13 15:57:08,985 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 15:57:08,985 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1798 states and 2643 transitions. [2024-11-13 15:57:08,995 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1635 [2024-11-13 15:57:08,996 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:08,996 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:08,999 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:09,002 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:09,003 INFO L745 eck$LassoCheckResult]: Stem: 47097#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 47098#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 48030#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48031#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47165#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 47166#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47070#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47071#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48358#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47711#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47712#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47603#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 47604#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48112#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 48113#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47362#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47363#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47797#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47798#L1194 assume !(0 == ~M_E~0); 47950#L1194-2 assume !(0 == ~T1_E~0); 47951#L1199-1 assume !(0 == ~T2_E~0); 48237#L1204-1 assume !(0 == ~T3_E~0); 48162#L1209-1 assume !(0 == ~T4_E~0); 48163#L1214-1 assume !(0 == ~T5_E~0); 48561#L1219-1 assume !(0 == ~T6_E~0); 48647#L1224-1 assume !(0 == ~T7_E~0); 47436#L1229-1 assume !(0 == ~T8_E~0); 46990#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46991#L1239-1 assume !(0 == ~T10_E~0); 47033#L1244-1 assume !(0 == ~T11_E~0); 47034#L1249-1 assume !(0 == ~T12_E~0); 47741#L1254-1 assume !(0 == ~E_M~0); 46932#L1259-1 assume !(0 == ~E_1~0); 46897#L1264-1 assume !(0 == ~E_2~0); 46898#L1269-1 assume !(0 == ~E_3~0); 48649#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 48593#L1279-1 assume !(0 == ~E_5~0); 47106#L1284-1 assume !(0 == ~E_6~0); 47107#L1289-1 assume !(0 == ~E_7~0); 47804#L1294-1 assume !(0 == ~E_8~0); 47805#L1299-1 assume !(0 == ~E_9~0); 47816#L1304-1 assume !(0 == ~E_10~0); 48640#L1309-1 assume !(0 == ~E_11~0); 48645#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 47063#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46987#L586 assume 1 == ~m_pc~0; 46988#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47055#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47876#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47262#L1485 assume !(0 != activate_threads_~tmp~1#1); 47263#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48364#L605 assume !(1 == ~t1_pc~0); 47890#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47632#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47633#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48276#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48211#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47540#L624 assume 1 == ~t2_pc~0; 47037#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47038#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47289#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47290#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 48396#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48274#L643 assume !(1 == ~t3_pc~0); 48132#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 47834#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47835#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47369#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 47370#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47127#L662 assume 1 == ~t4_pc~0; 47128#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47086#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46949#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46950#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 46976#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46977#L681 assume !(1 == ~t5_pc~0); 46853#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 46854#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47916#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48522#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 47381#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47382#L700 assume 1 == ~t6_pc~0; 48092#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47119#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47120#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47167#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 47168#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48450#L719 assume 1 == ~t7_pc~0; 48531#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47338#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48637#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48579#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 46867#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46868#L738 assume !(1 == ~t8_pc~0); 48244#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 48153#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48154#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47946#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47947#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48296#L757 assume 1 == ~t9_pc~0; 48297#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46862#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46863#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47336#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 47908#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47909#L776 assume !(1 == ~t10_pc~0); 46884#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46883#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47266#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47108#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 47109#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47064#L795 assume 1 == ~t11_pc~0; 47065#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 47401#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48378#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48549#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 48126#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48116#L814 assume !(1 == ~t12_pc~0); 47976#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 47977#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46910#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46911#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 47320#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47321#L1332 assume !(1 == ~M_E~0); 48409#L1332-2 assume !(1 == ~T1_E~0); 48611#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48047#L1342-1 assume !(1 == ~T3_E~0); 48048#L1347-1 assume !(1 == ~T4_E~0); 48437#L1352-1 assume !(1 == ~T5_E~0); 48302#L1357-1 assume !(1 == ~T6_E~0); 47601#L1362-1 assume !(1 == ~T7_E~0); 47602#L1367-1 assume !(1 == ~T8_E~0); 47201#L1372-1 assume !(1 == ~T9_E~0); 47202#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47512#L1382-1 assume !(1 == ~T11_E~0); 47513#L1387-1 assume !(1 == ~T12_E~0); 48209#L1392-1 assume !(1 == ~E_M~0); 47541#L1397-1 assume !(1 == ~E_1~0); 47542#L1402-1 assume !(1 == ~E_2~0); 47216#L1407-1 assume !(1 == ~E_3~0); 47217#L1412-1 assume !(1 == ~E_4~0); 48376#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 48377#L1422-1 assume !(1 == ~E_6~0); 48613#L1427-1 assume !(1 == ~E_7~0); 47402#L1432-1 assume !(1 == ~E_8~0); 47403#L1437-1 assume !(1 == ~E_9~0); 48329#L1442-1 assume !(1 == ~E_10~0); 48330#L1447-1 assume !(1 == ~E_11~0); 48201#L1452-1 assume !(1 == ~E_12~0); 47007#L1457-1 assume { :end_inline_reset_delta_events } true; 47008#L1803-2 [2024-11-13 15:57:09,003 INFO L747 eck$LassoCheckResult]: Loop: 47008#L1803-2 assume !false; 47344#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47293#L1169-1 assume !false; 47413#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47583#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47072#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47073#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 48417#L996 assume !(0 != eval_~tmp~0#1); 47794#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47458#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47459#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47952#L1194-5 assume !(0 == ~T1_E~0); 47175#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47176#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47432#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46876#L1214-3 assume !(0 == ~T5_E~0); 46877#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47630#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47631#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47665#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47043#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 47044#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47481#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 48071#L1254-3 assume !(0 == ~E_M~0); 48555#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 48184#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47049#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47050#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48590#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47628#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47629#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47610#L1294-3 assume !(0 == ~E_8~0); 47611#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 48003#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 48004#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47514#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 47515#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47520#L586-42 assume !(1 == ~m_pc~0); 47521#L586-44 is_master_triggered_~__retres1~0#1 := 0; 47117#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47118#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47584#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 47658#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47659#L605-42 assume 1 == ~t1_pc~0; 48249#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47969#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47970#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47660#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47661#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47669#L624-42 assume !(1 == ~t2_pc~0); 47670#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 47814#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47906#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47907#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47479#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47480#L643-42 assume 1 == ~t3_pc~0; 47838#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47795#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47796#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47625#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47626#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48339#L662-42 assume !(1 == ~t4_pc~0); 48542#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 47138#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47139#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48317#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48583#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48550#L681-42 assume 1 == ~t5_pc~0; 47848#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47004#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47996#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47997#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48385#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47498#L700-42 assume 1 == ~t6_pc~0; 47499#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47308#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47228#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47229#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48392#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48600#L719-42 assume !(1 == ~t7_pc~0); 47189#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 47190#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47570#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47833#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 47585#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47586#L738-42 assume 1 == ~t8_pc~0; 47784#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47529#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47530#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47047#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47048#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47579#L757-42 assume 1 == ~t9_pc~0; 47922#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47230#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47231#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47983#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47349#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47350#L776-42 assume !(1 == ~t10_pc~0); 48309#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 48310#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48127#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48128#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48635#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48150#L795-42 assume !(1 == ~t11_pc~0); 48151#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 47184#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47185#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47283#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 47284#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47595#L814-42 assume !(1 == ~t12_pc~0); 47464#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 47095#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47096#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46905#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 46906#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47059#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47060#L1332-5 assume !(1 == ~T1_E~0); 47035#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47036#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47865#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48035#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48036#L1357-3 assume !(1 == ~T6_E~0); 48471#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48643#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 48639#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46891#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46892#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47495#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47496#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 48335#L1397-3 assume !(1 == ~E_1~0); 48610#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 47985#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 47143#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47144#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47885#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47886#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 48468#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 48230#L1437-3 assume !(1 == ~E_9~0); 48005#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 48006#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 46939#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 46940#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47558#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47399#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47215#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 47135#L1822 assume !(0 == start_simulation_~tmp~3#1); 47136#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 48101#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47396#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 46893#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 46894#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48057#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48156#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 48496#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 47008#L1803-2 [2024-11-13 15:57:09,003 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:09,004 INFO L85 PathProgramCache]: Analyzing trace with hash -2089382286, now seen corresponding path program 1 times [2024-11-13 15:57:09,004 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:09,004 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1318516729] [2024-11-13 15:57:09,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:09,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:09,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:09,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:09,135 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:09,135 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1318516729] [2024-11-13 15:57:09,135 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1318516729] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:09,135 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:09,136 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:09,136 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1445583962] [2024-11-13 15:57:09,137 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:09,137 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:09,138 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:09,139 INFO L85 PathProgramCache]: Analyzing trace with hash 158602966, now seen corresponding path program 1 times [2024-11-13 15:57:09,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:09,140 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [290237964] [2024-11-13 15:57:09,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:09,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:09,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:09,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:09,237 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:09,237 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [290237964] [2024-11-13 15:57:09,237 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [290237964] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:09,237 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:09,237 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:09,238 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [733101277] [2024-11-13 15:57:09,238 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:09,238 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:09,238 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:09,239 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:57:09,239 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:57:09,242 INFO L87 Difference]: Start difference. First operand 1798 states and 2643 transitions. cyclomatic complexity: 846 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:09,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:09,498 INFO L93 Difference]: Finished difference Result 3340 states and 4894 transitions. [2024-11-13 15:57:09,499 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3340 states and 4894 transitions. [2024-11-13 15:57:09,519 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3151 [2024-11-13 15:57:09,537 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3340 states to 3340 states and 4894 transitions. [2024-11-13 15:57:09,537 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3340 [2024-11-13 15:57:09,541 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3340 [2024-11-13 15:57:09,541 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3340 states and 4894 transitions. [2024-11-13 15:57:09,547 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:09,547 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3340 states and 4894 transitions. [2024-11-13 15:57:09,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3340 states and 4894 transitions. [2024-11-13 15:57:09,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3340 to 3340. [2024-11-13 15:57:09,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3340 states, 3340 states have (on average 1.4652694610778443) internal successors, (4894), 3339 states have internal predecessors, (4894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:09,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3340 states to 3340 states and 4894 transitions. [2024-11-13 15:57:09,686 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3340 states and 4894 transitions. [2024-11-13 15:57:09,687 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:57:09,689 INFO L424 stractBuchiCegarLoop]: Abstraction has 3340 states and 4894 transitions. [2024-11-13 15:57:09,689 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 15:57:09,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3340 states and 4894 transitions. [2024-11-13 15:57:09,707 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3151 [2024-11-13 15:57:09,708 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:09,708 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:09,711 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:09,712 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:09,712 INFO L745 eck$LassoCheckResult]: Stem: 52246#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 52247#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 53196#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53197#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 52314#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 52315#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52219#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52220#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53539#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52867#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 52868#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 52758#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 52759#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53284#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 53285#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 52515#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 52516#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 52959#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52960#L1194 assume !(0 == ~M_E~0); 53112#L1194-2 assume !(0 == ~T1_E~0); 53113#L1199-1 assume !(0 == ~T2_E~0); 53412#L1204-1 assume !(0 == ~T3_E~0); 53335#L1209-1 assume !(0 == ~T4_E~0); 53336#L1214-1 assume !(0 == ~T5_E~0); 53767#L1219-1 assume !(0 == ~T6_E~0); 53863#L1224-1 assume !(0 == ~T7_E~0); 52593#L1229-1 assume !(0 == ~T8_E~0); 52146#L1234-1 assume !(0 == ~T9_E~0); 52147#L1239-1 assume !(0 == ~T10_E~0); 52183#L1244-1 assume !(0 == ~T11_E~0); 52184#L1249-1 assume !(0 == ~T12_E~0); 52899#L1254-1 assume !(0 == ~E_M~0); 52080#L1259-1 assume !(0 == ~E_1~0); 52045#L1264-1 assume !(0 == ~E_2~0); 52046#L1269-1 assume !(0 == ~E_3~0); 53867#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 53801#L1279-1 assume !(0 == ~E_5~0); 52255#L1284-1 assume !(0 == ~E_6~0); 52256#L1289-1 assume !(0 == ~E_7~0); 52966#L1294-1 assume !(0 == ~E_8~0); 52967#L1299-1 assume !(0 == ~E_9~0); 52978#L1304-1 assume !(0 == ~E_10~0); 53855#L1309-1 assume !(0 == ~E_11~0); 53861#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 52213#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52135#L586 assume 1 == ~m_pc~0; 52136#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 52203#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53037#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 52411#L1485 assume !(0 != activate_threads_~tmp~1#1); 52412#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53548#L605 assume !(1 == ~t1_pc~0); 53051#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 52787#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52788#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53453#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53386#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52695#L624 assume 1 == ~t2_pc~0; 52188#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52189#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52440#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52441#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 53583#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53451#L643 assume !(1 == ~t3_pc~0); 53305#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53001#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53002#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52522#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 52523#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52276#L662 assume 1 == ~t4_pc~0; 52277#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 52235#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52100#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52101#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 52126#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52127#L681 assume !(1 == ~t5_pc~0); 52001#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52002#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53078#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53719#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 52536#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52537#L700 assume 1 == ~t6_pc~0; 53261#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52268#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52269#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52316#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 52317#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53643#L719 assume 1 == ~t7_pc~0; 53732#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52489#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53850#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53787#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 52015#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52016#L738 assume !(1 == ~t8_pc~0); 53419#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 53326#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53327#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53108#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53109#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53476#L757 assume 1 == ~t9_pc~0; 53477#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52010#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52011#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52487#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 53070#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53071#L776 assume !(1 == ~t10_pc~0); 52032#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 52031#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52418#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52257#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 52258#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 52214#L795 assume 1 == ~t11_pc~0; 52215#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 52558#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53563#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53752#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 53299#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53288#L814 assume !(1 == ~t12_pc~0); 53139#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 53140#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52061#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52062#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 52471#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52472#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 53596#L1332-2 assume !(1 == ~T1_E~0); 53820#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53214#L1342-1 assume !(1 == ~T3_E~0); 53215#L1347-1 assume !(1 == ~T4_E~0); 53631#L1352-1 assume !(1 == ~T5_E~0); 53483#L1357-1 assume !(1 == ~T6_E~0); 52756#L1362-1 assume !(1 == ~T7_E~0); 52757#L1367-1 assume !(1 == ~T8_E~0); 52352#L1372-1 assume !(1 == ~T9_E~0); 52353#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52667#L1382-1 assume !(1 == ~T11_E~0); 52668#L1387-1 assume !(1 == ~T12_E~0); 53382#L1392-1 assume !(1 == ~E_M~0); 53905#L1397-1 assume !(1 == ~E_1~0); 53903#L1402-1 assume !(1 == ~E_2~0); 53902#L1407-1 assume !(1 == ~E_3~0); 53901#L1412-1 assume !(1 == ~E_4~0); 53900#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 53899#L1422-1 assume !(1 == ~E_6~0); 53898#L1427-1 assume !(1 == ~E_7~0); 53897#L1432-1 assume !(1 == ~E_8~0); 53896#L1437-1 assume !(1 == ~E_9~0); 53895#L1442-1 assume !(1 == ~E_10~0); 53894#L1447-1 assume !(1 == ~E_11~0); 53893#L1452-1 assume !(1 == ~E_12~0); 53892#L1457-1 assume { :end_inline_reset_delta_events } true; 53890#L1803-2 [2024-11-13 15:57:09,713 INFO L747 eck$LassoCheckResult]: Loop: 53890#L1803-2 assume !false; 53889#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53887#L1169-1 assume !false; 53886#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53882#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52221#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52222#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 53605#L996 assume !(0 != eval_~tmp~0#1); 53607#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52616#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52617#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53872#L1194-5 assume !(0 == ~T1_E~0); 54919#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54918#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54917#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54916#L1214-3 assume !(0 == ~T5_E~0); 54915#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 54914#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 54913#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 54912#L1234-3 assume !(0 == ~T9_E~0); 54911#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 54910#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 54909#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 54908#L1254-3 assume !(0 == ~E_M~0); 54907#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54906#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54905#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54904#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 54903#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54902#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54901#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54900#L1294-3 assume !(0 == ~E_8~0); 54899#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 54898#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 54897#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 54896#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 54895#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54894#L586-42 assume 1 == ~m_pc~0; 54892#L587-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 54891#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54890#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 54889#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 54888#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54887#L605-42 assume 1 == ~t1_pc~0; 54885#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 54884#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54883#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54882#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54881#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54880#L624-42 assume !(1 == ~t2_pc~0); 54878#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 54877#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54876#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54875#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54874#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54873#L643-42 assume 1 == ~t3_pc~0; 54871#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54870#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54869#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54868#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54867#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54866#L662-42 assume !(1 == ~t4_pc~0); 54864#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 54863#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54862#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54861#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54860#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54859#L681-42 assume 1 == ~t5_pc~0; 54857#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54856#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54855#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54854#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54853#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54852#L700-42 assume !(1 == ~t6_pc~0); 54850#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 54849#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54848#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54847#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54846#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54845#L719-42 assume 1 == ~t7_pc~0; 54843#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 54842#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54841#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54840#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 54839#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54838#L738-42 assume 1 == ~t8_pc~0; 54836#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54835#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54834#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54833#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 54832#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54831#L757-42 assume 1 == ~t9_pc~0; 54829#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54828#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54827#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54826#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 54825#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54824#L776-42 assume 1 == ~t10_pc~0; 54822#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 54821#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54820#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54819#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 54818#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54817#L795-42 assume 1 == ~t11_pc~0; 54816#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54814#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54813#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54812#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 54811#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54810#L814-42 assume 1 == ~t12_pc~0; 54808#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 54807#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 54806#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54805#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 54804#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54803#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 52208#L1332-5 assume !(1 == ~T1_E~0); 54802#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54801#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54800#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54799#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54798#L1357-3 assume !(1 == ~T6_E~0); 54797#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54796#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54795#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 53853#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54794#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54793#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 54792#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 54791#L1397-3 assume !(1 == ~E_1~0); 54790#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54789#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54788#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54787#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54786#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 54785#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 54784#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 54783#L1437-3 assume !(1 == ~E_9~0); 54782#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 54781#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 54780#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 53870#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53871#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 54119#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54116#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 54114#L1822 assume !(0 == start_simulation_~tmp~3#1); 53480#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 54103#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52551#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52041#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 52042#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 53906#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53904#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 53891#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 53890#L1803-2 [2024-11-13 15:57:09,713 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:09,714 INFO L85 PathProgramCache]: Analyzing trace with hash 1144190578, now seen corresponding path program 1 times [2024-11-13 15:57:09,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:09,714 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1855941539] [2024-11-13 15:57:09,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:09,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:09,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:09,890 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:09,891 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:09,891 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1855941539] [2024-11-13 15:57:09,891 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1855941539] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:09,892 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:09,892 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:09,892 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [634838799] [2024-11-13 15:57:09,892 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:09,893 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:09,894 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:09,894 INFO L85 PathProgramCache]: Analyzing trace with hash 1898023124, now seen corresponding path program 1 times [2024-11-13 15:57:09,894 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:09,895 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [302863908] [2024-11-13 15:57:09,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:09,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:09,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:10,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:10,016 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:10,017 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [302863908] [2024-11-13 15:57:10,017 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [302863908] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:10,017 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:10,017 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:10,017 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1176191519] [2024-11-13 15:57:10,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:10,018 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:10,018 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:10,018 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:57:10,019 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:57:10,019 INFO L87 Difference]: Start difference. First operand 3340 states and 4894 transitions. cyclomatic complexity: 1556 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:10,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:10,380 INFO L93 Difference]: Finished difference Result 6214 states and 9085 transitions. [2024-11-13 15:57:10,380 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6214 states and 9085 transitions. [2024-11-13 15:57:10,421 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5997 [2024-11-13 15:57:10,450 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6214 states to 6214 states and 9085 transitions. [2024-11-13 15:57:10,450 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6214 [2024-11-13 15:57:10,458 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6214 [2024-11-13 15:57:10,458 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6214 states and 9085 transitions. [2024-11-13 15:57:10,470 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:10,471 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6214 states and 9085 transitions. [2024-11-13 15:57:10,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6214 states and 9085 transitions. [2024-11-13 15:57:10,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6214 to 6212. [2024-11-13 15:57:10,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6212 states, 6212 states have (on average 1.4621699935608499) internal successors, (9083), 6211 states have internal predecessors, (9083), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:10,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6212 states to 6212 states and 9083 transitions. [2024-11-13 15:57:10,638 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6212 states and 9083 transitions. [2024-11-13 15:57:10,639 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:57:10,640 INFO L424 stractBuchiCegarLoop]: Abstraction has 6212 states and 9083 transitions. [2024-11-13 15:57:10,640 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 15:57:10,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6212 states and 9083 transitions. [2024-11-13 15:57:10,673 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5997 [2024-11-13 15:57:10,673 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:10,674 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:10,676 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:10,677 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:10,677 INFO L745 eck$LassoCheckResult]: Stem: 61808#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 61809#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 62783#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62784#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 61878#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 61879#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61783#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61784#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63154#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62446#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62447#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 62333#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 62334#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 62869#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 62870#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 62080#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 62081#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 62539#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 62540#L1194 assume !(0 == ~M_E~0); 62696#L1194-2 assume !(0 == ~T1_E~0); 62697#L1199-1 assume !(0 == ~T2_E~0); 63005#L1204-1 assume !(0 == ~T3_E~0); 62926#L1209-1 assume !(0 == ~T4_E~0); 62927#L1214-1 assume !(0 == ~T5_E~0); 63430#L1219-1 assume !(0 == ~T6_E~0); 63589#L1224-1 assume !(0 == ~T7_E~0); 62158#L1229-1 assume !(0 == ~T8_E~0); 61702#L1234-1 assume !(0 == ~T9_E~0); 61703#L1239-1 assume !(0 == ~T10_E~0); 61745#L1244-1 assume !(0 == ~T11_E~0); 61746#L1249-1 assume !(0 == ~T12_E~0); 62478#L1254-1 assume !(0 == ~E_M~0); 61644#L1259-1 assume !(0 == ~E_1~0); 61609#L1264-1 assume !(0 == ~E_2~0); 61610#L1269-1 assume !(0 == ~E_3~0); 63600#L1274-1 assume !(0 == ~E_4~0); 63483#L1279-1 assume !(0 == ~E_5~0); 61819#L1284-1 assume !(0 == ~E_6~0); 61820#L1289-1 assume !(0 == ~E_7~0); 62546#L1294-1 assume !(0 == ~E_8~0); 62547#L1299-1 assume !(0 == ~E_9~0); 62558#L1304-1 assume !(0 == ~E_10~0); 63576#L1309-1 assume !(0 == ~E_11~0); 63582#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 61776#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61699#L586 assume 1 == ~m_pc~0; 61700#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 61767#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62621#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 61977#L1485 assume !(0 != activate_threads_~tmp~1#1); 61978#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63162#L605 assume !(1 == ~t1_pc~0); 62635#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 62362#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62363#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63049#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62977#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62266#L624 assume 1 == ~t2_pc~0; 61749#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 61750#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62004#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62005#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 63203#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63047#L643 assume !(1 == ~t3_pc~0); 62891#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62577#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62578#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62087#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 62088#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61840#L662 assume 1 == ~t4_pc~0; 61841#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 61799#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61661#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61662#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 61688#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61689#L681 assume !(1 == ~t5_pc~0); 61565#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 61566#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62661#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 63365#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 62099#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62100#L700 assume 1 == ~t6_pc~0; 62849#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 61832#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61833#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 61880#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 61881#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63273#L719 assume 1 == ~t7_pc~0; 63385#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62053#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63565#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 63464#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 61579#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61580#L738 assume !(1 == ~t8_pc~0); 63012#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 62917#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62918#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62692#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 62693#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63076#L757 assume 1 == ~t9_pc~0; 63077#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 61574#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 61575#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62051#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 62653#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62654#L776 assume !(1 == ~t10_pc~0); 61596#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 61595#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 61981#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 61821#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 61822#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 61777#L795 assume 1 == ~t11_pc~0; 61778#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 62122#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 63184#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 63413#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 62885#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62873#L814 assume !(1 == ~t12_pc~0); 62725#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 62726#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61622#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 61623#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 62035#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62036#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 63221#L1332-2 assume !(1 == ~T1_E~0); 65011#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65010#L1342-1 assume !(1 == ~T3_E~0); 65009#L1347-1 assume !(1 == ~T4_E~0); 63255#L1352-1 assume !(1 == ~T5_E~0); 63256#L1357-1 assume !(1 == ~T6_E~0); 64778#L1362-1 assume !(1 == ~T7_E~0); 63318#L1367-1 assume !(1 == ~T8_E~0); 63319#L1372-1 assume !(1 == ~T9_E~0); 64397#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 64395#L1382-1 assume !(1 == ~T11_E~0); 64300#L1387-1 assume !(1 == ~T12_E~0); 64297#L1392-1 assume !(1 == ~E_M~0); 64296#L1397-1 assume !(1 == ~E_1~0); 64294#L1402-1 assume !(1 == ~E_2~0); 61930#L1407-1 assume !(1 == ~E_3~0); 61931#L1412-1 assume !(1 == ~E_4~0); 64197#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 64154#L1422-1 assume !(1 == ~E_6~0); 64115#L1427-1 assume !(1 == ~E_7~0); 64113#L1432-1 assume !(1 == ~E_8~0); 64087#L1437-1 assume !(1 == ~E_9~0); 64055#L1442-1 assume !(1 == ~E_10~0); 63672#L1447-1 assume !(1 == ~E_11~0); 63669#L1452-1 assume !(1 == ~E_12~0); 63660#L1457-1 assume { :end_inline_reset_delta_events } true; 63652#L1803-2 [2024-11-13 15:57:10,679 INFO L747 eck$LassoCheckResult]: Loop: 63652#L1803-2 assume !false; 63646#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63642#L1169-1 assume !false; 63641#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63637#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63627#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63626#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 63624#L996 assume !(0 != eval_~tmp~0#1); 63623#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 63622#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 63620#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 63621#L1194-5 assume !(0 == ~T1_E~0); 67776#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 67775#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 67774#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 67773#L1214-3 assume !(0 == ~T5_E~0); 67772#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 67771#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 67770#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 67769#L1234-3 assume !(0 == ~T9_E~0); 67768#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 67767#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 67766#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 67765#L1254-3 assume !(0 == ~E_M~0); 67764#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 67763#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 67762#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67761#L1274-3 assume !(0 == ~E_4~0); 67760#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 67759#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 67758#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 67757#L1294-3 assume !(0 == ~E_8~0); 67756#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 67755#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 67754#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 67753#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 67752#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67751#L586-42 assume 1 == ~m_pc~0; 67749#L587-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 67748#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67747#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 67746#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 67745#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67744#L605-42 assume !(1 == ~t1_pc~0); 67743#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 67741#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67740#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 67739#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 67738#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67737#L624-42 assume !(1 == ~t2_pc~0); 67735#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 67734#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67733#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 67732#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 67731#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67730#L643-42 assume !(1 == ~t3_pc~0); 67729#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 67727#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67726#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 67725#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 67724#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67723#L662-42 assume !(1 == ~t4_pc~0); 67721#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 67720#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67719#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 67718#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 67717#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67716#L681-42 assume !(1 == ~t5_pc~0); 67715#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 67713#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67712#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 67711#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 67710#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 67709#L700-42 assume !(1 == ~t6_pc~0); 67707#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 67706#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 67705#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 67704#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 67703#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 67702#L719-42 assume !(1 == ~t7_pc~0); 67701#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 67699#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 67698#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 67697#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 67696#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 67695#L738-42 assume 1 == ~t8_pc~0; 67693#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 67692#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66324#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 61759#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 61760#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62306#L757-42 assume 1 == ~t9_pc~0; 62667#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62668#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65709#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65707#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 65316#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 65314#L776-42 assume 1 == ~t10_pc~0; 65310#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 65223#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 65221#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 65219#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 65216#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65120#L795-42 assume !(1 == ~t11_pc~0); 65116#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 65005#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65003#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 64892#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 64776#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 64774#L814-42 assume 1 == ~t12_pc~0; 64771#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 64612#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 64610#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 64608#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 64606#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64386#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 61772#L1332-5 assume !(1 == ~T1_E~0); 64287#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 64285#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64284#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64196#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 64153#L1357-3 assume !(1 == ~T6_E~0); 64150#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64146#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 64112#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 64109#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 64085#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 64082#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 64080#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 64078#L1397-3 assume !(1 == ~E_1~0); 64076#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 62734#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 62735#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 64045#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 64044#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 64042#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 64039#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 64037#L1437-3 assume !(1 == ~E_9~0); 64035#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 63941#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 63939#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 63937#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63914#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63902#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63901#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 63900#L1822 assume !(0 == start_simulation_~tmp~3#1); 63080#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63880#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63871#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63856#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 63854#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 63838#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63668#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 63659#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 63652#L1803-2 [2024-11-13 15:57:10,679 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:10,680 INFO L85 PathProgramCache]: Analyzing trace with hash -1221844492, now seen corresponding path program 1 times [2024-11-13 15:57:10,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:10,680 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [523331814] [2024-11-13 15:57:10,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:10,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:10,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:10,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:10,864 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:10,864 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [523331814] [2024-11-13 15:57:10,865 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [523331814] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:10,865 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:10,865 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:10,865 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [707394825] [2024-11-13 15:57:10,865 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:10,866 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:10,866 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:10,866 INFO L85 PathProgramCache]: Analyzing trace with hash 928015707, now seen corresponding path program 1 times [2024-11-13 15:57:10,866 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:10,866 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [956043333] [2024-11-13 15:57:10,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:10,867 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:10,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:10,964 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:10,964 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:10,964 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [956043333] [2024-11-13 15:57:10,964 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [956043333] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:10,964 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:10,964 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:10,965 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1596344623] [2024-11-13 15:57:10,965 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:10,965 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:10,965 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:10,966 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:57:10,966 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:57:10,966 INFO L87 Difference]: Start difference. First operand 6212 states and 9083 transitions. cyclomatic complexity: 2875 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:11,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:11,302 INFO L93 Difference]: Finished difference Result 11734 states and 17118 transitions. [2024-11-13 15:57:11,303 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11734 states and 17118 transitions. [2024-11-13 15:57:11,380 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11503 [2024-11-13 15:57:11,442 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11734 states to 11734 states and 17118 transitions. [2024-11-13 15:57:11,442 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11734 [2024-11-13 15:57:11,457 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11734 [2024-11-13 15:57:11,457 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11734 states and 17118 transitions. [2024-11-13 15:57:11,477 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:11,478 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11734 states and 17118 transitions. [2024-11-13 15:57:11,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11734 states and 17118 transitions. [2024-11-13 15:57:11,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11734 to 11730. [2024-11-13 15:57:11,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11730 states, 11730 states have (on average 1.458994032395567) internal successors, (17114), 11729 states have internal predecessors, (17114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:11,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11730 states to 11730 states and 17114 transitions. [2024-11-13 15:57:11,758 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11730 states and 17114 transitions. [2024-11-13 15:57:11,758 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:57:11,759 INFO L424 stractBuchiCegarLoop]: Abstraction has 11730 states and 17114 transitions. [2024-11-13 15:57:11,759 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 15:57:11,760 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11730 states and 17114 transitions. [2024-11-13 15:57:11,847 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11503 [2024-11-13 15:57:11,848 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:11,848 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:11,851 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:11,851 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:11,851 INFO L745 eck$LassoCheckResult]: Stem: 79764#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 79765#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 80704#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 80705#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 79834#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 79835#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 79739#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 79740#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81038#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 80384#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 80385#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 80274#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 80275#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 80787#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 80788#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 80032#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 80033#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 80470#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 80471#L1194 assume !(0 == ~M_E~0); 80623#L1194-2 assume !(0 == ~T1_E~0); 80624#L1199-1 assume !(0 == ~T2_E~0); 80913#L1204-1 assume !(0 == ~T3_E~0); 80837#L1209-1 assume !(0 == ~T4_E~0); 80838#L1214-1 assume !(0 == ~T5_E~0); 81253#L1219-1 assume !(0 == ~T6_E~0); 81353#L1224-1 assume !(0 == ~T7_E~0); 80106#L1229-1 assume !(0 == ~T8_E~0); 79658#L1234-1 assume !(0 == ~T9_E~0); 79659#L1239-1 assume !(0 == ~T10_E~0); 79701#L1244-1 assume !(0 == ~T11_E~0); 79702#L1249-1 assume !(0 == ~T12_E~0); 80414#L1254-1 assume !(0 == ~E_M~0); 79600#L1259-1 assume !(0 == ~E_1~0); 79565#L1264-1 assume !(0 == ~E_2~0); 79566#L1269-1 assume !(0 == ~E_3~0); 81360#L1274-1 assume !(0 == ~E_4~0); 81289#L1279-1 assume !(0 == ~E_5~0); 79775#L1284-1 assume !(0 == ~E_6~0); 79776#L1289-1 assume !(0 == ~E_7~0); 80477#L1294-1 assume !(0 == ~E_8~0); 80478#L1299-1 assume !(0 == ~E_9~0); 80489#L1304-1 assume !(0 == ~E_10~0); 81346#L1309-1 assume !(0 == ~E_11~0); 81351#L1314-1 assume !(0 == ~E_12~0); 79732#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79655#L586 assume 1 == ~m_pc~0; 79656#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 79723#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 80549#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 79932#L1485 assume !(0 != activate_threads_~tmp~1#1); 79933#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81045#L605 assume !(1 == ~t1_pc~0); 80563#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 80304#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 80305#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 80953#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 80887#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80211#L624 assume 1 == ~t2_pc~0; 79705#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 79706#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79959#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 79960#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 81077#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80951#L643 assume !(1 == ~t3_pc~0); 80807#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 80507#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80508#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 80039#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 80040#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 79796#L662 assume 1 == ~t4_pc~0; 79797#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 79755#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 79617#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 79618#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 79644#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 79645#L681 assume !(1 == ~t5_pc~0); 79521#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 79522#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 80589#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 81209#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 80051#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 80052#L700 assume 1 == ~t6_pc~0; 80767#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 79788#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 79789#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 79836#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 79837#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 81135#L719 assume 1 == ~t7_pc~0; 81218#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 80008#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 81339#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 81274#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 79535#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 79536#L738 assume !(1 == ~t8_pc~0); 80920#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 80828#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 80829#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 80619#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 80620#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 80974#L757 assume 1 == ~t9_pc~0; 80975#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 79530#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 79531#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 80006#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 80581#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 80582#L776 assume !(1 == ~t10_pc~0); 79552#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 79551#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 79936#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 79777#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 79778#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 79733#L795 assume 1 == ~t11_pc~0; 79734#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 80071#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 81059#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 81238#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 80801#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 80791#L814 assume !(1 == ~t12_pc~0); 80650#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 80651#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 79578#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 79579#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 79990#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79991#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 81090#L1332-2 assume !(1 == ~T1_E~0); 90903#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 90901#L1342-1 assume !(1 == ~T3_E~0); 90898#L1347-1 assume !(1 == ~T4_E~0); 90896#L1352-1 assume !(1 == ~T5_E~0); 90894#L1357-1 assume !(1 == ~T6_E~0); 90892#L1362-1 assume !(1 == ~T7_E~0); 81169#L1367-1 assume !(1 == ~T8_E~0); 79870#L1372-1 assume !(1 == ~T9_E~0); 79871#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 80183#L1382-1 assume !(1 == ~T11_E~0); 80184#L1387-1 assume !(1 == ~T12_E~0); 80885#L1392-1 assume !(1 == ~E_M~0); 80212#L1397-1 assume !(1 == ~E_1~0); 80213#L1402-1 assume !(1 == ~E_2~0); 79885#L1407-1 assume !(1 == ~E_3~0); 79886#L1412-1 assume !(1 == ~E_4~0); 84703#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 84699#L1422-1 assume !(1 == ~E_6~0); 84696#L1427-1 assume !(1 == ~E_7~0); 84693#L1432-1 assume !(1 == ~E_8~0); 84690#L1437-1 assume !(1 == ~E_9~0); 84686#L1442-1 assume !(1 == ~E_10~0); 84683#L1447-1 assume !(1 == ~E_11~0); 81417#L1452-1 assume !(1 == ~E_12~0); 81406#L1457-1 assume { :end_inline_reset_delta_events } true; 81398#L1803-2 [2024-11-13 15:57:11,852 INFO L747 eck$LassoCheckResult]: Loop: 81398#L1803-2 assume !false; 81392#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 81388#L1169-1 assume !false; 81387#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 81383#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 81373#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 81372#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 81370#L996 assume !(0 != eval_~tmp~0#1); 81369#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 81368#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 81366#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 81367#L1194-5 assume !(0 == ~T1_E~0); 88476#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 88474#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 88472#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 88470#L1214-3 assume !(0 == ~T5_E~0); 88467#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 88465#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 88463#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 88461#L1234-3 assume !(0 == ~T9_E~0); 88459#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 88457#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 88456#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 88453#L1254-3 assume !(0 == ~E_M~0); 88451#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 88449#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 88447#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 88445#L1274-3 assume !(0 == ~E_4~0); 88443#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 88440#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 88438#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 88436#L1294-3 assume !(0 == ~E_8~0); 88323#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 88303#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 88293#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 88285#L1314-3 assume !(0 == ~E_12~0); 88279#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88258#L586-42 assume !(1 == ~m_pc~0); 88255#L586-44 is_master_triggered_~__retres1~0#1 := 0; 88252#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88250#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 88248#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 88246#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88244#L605-42 assume !(1 == ~t1_pc~0); 88240#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 88237#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88235#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 88233#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 88231#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88228#L624-42 assume !(1 == ~t2_pc~0); 88225#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 88223#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88221#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 88219#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 88217#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88216#L643-42 assume !(1 == ~t3_pc~0); 88215#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 88178#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88172#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 88167#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 88162#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88160#L662-42 assume !(1 == ~t4_pc~0); 87243#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 87229#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87167#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 87156#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87145#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87136#L681-42 assume !(1 == ~t5_pc~0); 87129#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 87124#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87122#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 87121#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 87120#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 87119#L700-42 assume 1 == ~t6_pc~0; 87117#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 87114#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 87112#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 87110#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 87108#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87106#L719-42 assume !(1 == ~t7_pc~0); 87104#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 87101#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 87099#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 87097#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 87094#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 87092#L738-42 assume !(1 == ~t8_pc~0); 87089#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 87072#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 87068#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 87063#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 87058#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 87054#L757-42 assume 1 == ~t9_pc~0; 87049#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 87045#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 87041#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 87036#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 87032#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 87028#L776-42 assume !(1 == ~t10_pc~0); 87024#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 87019#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 87015#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 87010#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 87006#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 87002#L795-42 assume !(1 == ~t11_pc~0); 86997#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 86993#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 86989#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 86984#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 86980#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 86976#L814-42 assume 1 == ~t12_pc~0; 86971#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 86967#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 86963#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 86958#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 86953#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86949#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 79728#L1332-5 assume !(1 == ~T1_E~0); 86942#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86938#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86933#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86928#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 86923#L1357-3 assume !(1 == ~T6_E~0); 86919#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 86915#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 86911#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 81343#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 86902#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 86897#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 86893#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 86889#L1397-3 assume !(1 == ~E_1~0); 86885#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 86881#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 86879#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 82303#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 86873#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 86871#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 86868#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 86863#L1437-3 assume !(1 == ~E_9~0); 86857#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 86851#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 85913#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 85909#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 84744#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 84731#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 84729#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 84727#L1822 assume !(0 == start_simulation_~tmp~3#1); 80978#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 81700#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 81692#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 81690#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 81688#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 81668#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 81414#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 81405#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 81398#L1803-2 [2024-11-13 15:57:11,853 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:11,853 INFO L85 PathProgramCache]: Analyzing trace with hash 931262326, now seen corresponding path program 1 times [2024-11-13 15:57:11,853 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:11,854 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989254138] [2024-11-13 15:57:11,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:11,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:11,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:11,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:11,978 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:11,978 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [989254138] [2024-11-13 15:57:11,978 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [989254138] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:11,979 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:11,979 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:57:11,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [323153576] [2024-11-13 15:57:11,979 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:11,979 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:11,980 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:11,980 INFO L85 PathProgramCache]: Analyzing trace with hash -1018742177, now seen corresponding path program 1 times [2024-11-13 15:57:11,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:11,980 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [838737310] [2024-11-13 15:57:11,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:11,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:12,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:12,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:12,081 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:12,081 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [838737310] [2024-11-13 15:57:12,081 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [838737310] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:12,081 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:12,081 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:12,082 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1097061767] [2024-11-13 15:57:12,082 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:12,083 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:12,083 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:12,083 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:12,083 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:12,084 INFO L87 Difference]: Start difference. First operand 11730 states and 17114 transitions. cyclomatic complexity: 5392 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:12,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:12,414 INFO L93 Difference]: Finished difference Result 23111 states and 33516 transitions. [2024-11-13 15:57:12,414 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23111 states and 33516 transitions. [2024-11-13 15:57:12,542 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22869 [2024-11-13 15:57:12,659 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23111 states to 23111 states and 33516 transitions. [2024-11-13 15:57:12,659 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23111 [2024-11-13 15:57:12,699 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23111 [2024-11-13 15:57:12,700 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23111 states and 33516 transitions. [2024-11-13 15:57:12,740 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:12,740 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23111 states and 33516 transitions. [2024-11-13 15:57:12,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23111 states and 33516 transitions. [2024-11-13 15:57:13,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23111 to 22391. [2024-11-13 15:57:13,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22391 states, 22391 states have (on average 1.4514760394801483) internal successors, (32500), 22390 states have internal predecessors, (32500), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:13,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22391 states to 22391 states and 32500 transitions. [2024-11-13 15:57:13,343 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22391 states and 32500 transitions. [2024-11-13 15:57:13,343 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:13,344 INFO L424 stractBuchiCegarLoop]: Abstraction has 22391 states and 32500 transitions. [2024-11-13 15:57:13,344 INFO L331 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-13 15:57:13,344 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22391 states and 32500 transitions. [2024-11-13 15:57:13,556 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22149 [2024-11-13 15:57:13,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:13,556 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:13,560 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:13,560 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:13,560 INFO L745 eck$LassoCheckResult]: Stem: 114615#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 114616#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 115599#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 115600#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 114684#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 114685#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 114588#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 114589#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 116002#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 115247#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 115248#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 115133#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 115134#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 115693#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 115694#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 114884#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 114885#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 115341#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 115342#L1194 assume !(0 == ~M_E~0); 115502#L1194-2 assume !(0 == ~T1_E~0); 115503#L1199-1 assume !(0 == ~T2_E~0); 115838#L1204-1 assume !(0 == ~T3_E~0); 115751#L1209-1 assume !(0 == ~T4_E~0); 115752#L1214-1 assume !(0 == ~T5_E~0); 116318#L1219-1 assume !(0 == ~T6_E~0); 116520#L1224-1 assume !(0 == ~T7_E~0); 114962#L1229-1 assume !(0 == ~T8_E~0); 114514#L1234-1 assume !(0 == ~T9_E~0); 114515#L1239-1 assume !(0 == ~T10_E~0); 114551#L1244-1 assume !(0 == ~T11_E~0); 114552#L1249-1 assume !(0 == ~T12_E~0); 115278#L1254-1 assume !(0 == ~E_M~0); 114449#L1259-1 assume !(0 == ~E_1~0); 114413#L1264-1 assume !(0 == ~E_2~0); 114414#L1269-1 assume !(0 == ~E_3~0); 116532#L1274-1 assume !(0 == ~E_4~0); 116381#L1279-1 assume !(0 == ~E_5~0); 114624#L1284-1 assume !(0 == ~E_6~0); 114625#L1289-1 assume !(0 == ~E_7~0); 115350#L1294-1 assume !(0 == ~E_8~0); 115351#L1299-1 assume !(0 == ~E_9~0); 115362#L1304-1 assume !(0 == ~E_10~0); 116498#L1309-1 assume !(0 == ~E_11~0); 116510#L1314-1 assume !(0 == ~E_12~0); 114582#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 114504#L586 assume !(1 == ~m_pc~0); 114505#L586-2 is_master_triggered_~__retres1~0#1 := 0; 114571#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115423#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 114783#L1485 assume !(0 != activate_threads_~tmp~1#1); 114784#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 116010#L605 assume !(1 == ~t1_pc~0); 115439#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 115165#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 115166#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 115890#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 115810#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 115069#L624 assume 1 == ~t2_pc~0; 114556#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 114557#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 114810#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 114811#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 116059#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 115886#L643 assume !(1 == ~t3_pc~0); 115721#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 115386#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 115387#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 114891#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 114892#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 114645#L662 assume 1 == ~t4_pc~0; 114646#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 114604#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 114469#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 114470#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 114495#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 114496#L681 assume !(1 == ~t5_pc~0); 114369#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 114370#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 115467#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 116253#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 114905#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 114906#L700 assume 1 == ~t6_pc~0; 115670#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 114636#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 114637#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 114686#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 114687#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 116137#L719 assume 1 == ~t7_pc~0; 116277#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 114860#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 116490#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 116356#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 114383#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 114384#L738 assume !(1 == ~t8_pc~0); 115845#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 115742#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 115743#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 115498#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 115499#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 115917#L757 assume 1 == ~t9_pc~0; 115918#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 114378#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 114379#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 114857#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 115459#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 115460#L776 assume !(1 == ~t10_pc~0); 114400#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 114399#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 114790#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 114626#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 114627#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 114583#L795 assume 1 == ~t11_pc~0; 114584#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 114927#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 116034#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 116305#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 115710#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 115697#L814 assume !(1 == ~t12_pc~0); 115530#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 115531#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 114429#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 114430#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 114841#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 114842#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 116076#L1332-2 assume !(1 == ~T1_E~0); 116446#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 116447#L1342-1 assume !(1 == ~T3_E~0); 116375#L1347-1 assume !(1 == ~T4_E~0); 116376#L1352-1 assume !(1 == ~T5_E~0); 115924#L1357-1 assume !(1 == ~T6_E~0); 115925#L1362-1 assume !(1 == ~T7_E~0); 116197#L1367-1 assume !(1 == ~T8_E~0); 116198#L1372-1 assume !(1 == ~T9_E~0); 117769#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 117767#L1382-1 assume !(1 == ~T11_E~0); 117766#L1387-1 assume !(1 == ~T12_E~0); 117765#L1392-1 assume !(1 == ~E_M~0); 117763#L1397-1 assume !(1 == ~E_1~0); 117761#L1402-1 assume !(1 == ~E_2~0); 117759#L1407-1 assume !(1 == ~E_3~0); 117757#L1412-1 assume !(1 == ~E_4~0); 117755#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 117554#L1422-1 assume !(1 == ~E_6~0); 117552#L1427-1 assume !(1 == ~E_7~0); 117550#L1432-1 assume !(1 == ~E_8~0); 117548#L1437-1 assume !(1 == ~E_9~0); 117547#L1442-1 assume !(1 == ~E_10~0); 117546#L1447-1 assume !(1 == ~E_11~0); 117529#L1452-1 assume !(1 == ~E_12~0); 117518#L1457-1 assume { :end_inline_reset_delta_events } true; 117510#L1803-2 [2024-11-13 15:57:13,561 INFO L747 eck$LassoCheckResult]: Loop: 117510#L1803-2 assume !false; 117504#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 117500#L1169-1 assume !false; 117499#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 117495#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 117485#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 117484#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 117482#L996 assume !(0 != eval_~tmp~0#1); 117481#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 117480#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 117477#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 117476#L1194-5 assume !(0 == ~T1_E~0); 117475#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 117474#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 117473#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 117472#L1214-3 assume !(0 == ~T5_E~0); 117471#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 117470#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 117469#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 117468#L1234-3 assume !(0 == ~T9_E~0); 117467#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 117466#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 117465#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 117464#L1254-3 assume !(0 == ~E_M~0); 117463#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 117462#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 117461#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 117460#L1274-3 assume !(0 == ~E_4~0); 117459#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 117458#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 117457#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 117456#L1294-3 assume !(0 == ~E_8~0); 117455#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 117454#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 115992#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 115044#L1314-3 assume !(0 == ~E_12~0); 115045#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 115052#L586-42 assume !(1 == ~m_pc~0); 115053#L586-44 is_master_triggered_~__retres1~0#1 := 0; 124287#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124283#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 124279#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 124275#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 124271#L605-42 assume !(1 == ~t1_pc~0); 124267#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 124259#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 124255#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 124251#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 124247#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 124243#L624-42 assume 1 == ~t2_pc~0; 124239#L625-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 124231#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 124227#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 124223#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 124219#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 124215#L643-42 assume !(1 == ~t3_pc~0); 124211#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 124203#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 124199#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 124195#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 124191#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 124187#L662-42 assume 1 == ~t4_pc~0; 124183#L663-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 124175#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 124171#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 124167#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 124163#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 124159#L681-42 assume !(1 == ~t5_pc~0); 124155#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 124147#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 124143#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 124139#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 124135#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 124131#L700-42 assume 1 == ~t6_pc~0; 124127#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 124119#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 124115#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 124111#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 124107#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 124103#L719-42 assume !(1 == ~t7_pc~0); 124099#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 124091#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 124087#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 124083#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 124079#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 124075#L738-42 assume !(1 == ~t8_pc~0); 124071#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 124063#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 124059#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 124055#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 124051#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 124047#L757-42 assume !(1 == ~t9_pc~0); 124043#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 124035#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 124031#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 124027#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 124022#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 124017#L776-42 assume 1 == ~t10_pc~0; 124011#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 124003#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 123998#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 123993#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 123988#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 123982#L795-42 assume 1 == ~t11_pc~0; 123977#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 123968#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 123963#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 123958#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 123953#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 123947#L814-42 assume 1 == ~t12_pc~0; 123941#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 123933#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 123928#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 123923#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 123918#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 123912#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 118708#L1332-5 assume !(1 == ~T1_E~0); 123903#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 123898#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 123893#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 123888#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 123882#L1357-3 assume !(1 == ~T6_E~0); 123877#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 123872#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 123866#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 123859#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 123856#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 123852#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 123849#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 123845#L1397-3 assume !(1 == ~E_1~0); 123841#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 123837#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 123832#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 123826#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 123823#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 123820#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 123809#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 123805#L1437-3 assume !(1 == ~E_9~0); 123801#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 123798#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 123793#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 118578#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 123756#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 123740#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 123734#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 123730#L1822 assume !(0 == start_simulation_~tmp~3#1); 115921#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 117575#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 117566#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 117564#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 117545#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 117543#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 117526#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 117517#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 117510#L1803-2 [2024-11-13 15:57:13,562 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:13,562 INFO L85 PathProgramCache]: Analyzing trace with hash 1218722231, now seen corresponding path program 1 times [2024-11-13 15:57:13,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:13,562 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1517642319] [2024-11-13 15:57:13,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:13,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:13,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:13,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:13,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:13,723 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1517642319] [2024-11-13 15:57:13,723 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1517642319] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:13,723 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:13,723 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:57:13,723 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [370725730] [2024-11-13 15:57:13,723 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:13,724 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:13,724 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:13,724 INFO L85 PathProgramCache]: Analyzing trace with hash 14115484, now seen corresponding path program 1 times [2024-11-13 15:57:13,725 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:13,725 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [706385353] [2024-11-13 15:57:13,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:13,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:13,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:13,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:13,829 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:13,829 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [706385353] [2024-11-13 15:57:13,829 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [706385353] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:13,829 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:13,830 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:13,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [713520979] [2024-11-13 15:57:13,830 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:13,830 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:13,831 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:13,831 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:57:13,831 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:57:13,831 INFO L87 Difference]: Start difference. First operand 22391 states and 32500 transitions. cyclomatic complexity: 10125 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:14,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:14,478 INFO L93 Difference]: Finished difference Result 23000 states and 33109 transitions. [2024-11-13 15:57:14,478 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23000 states and 33109 transitions. [2024-11-13 15:57:14,622 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22755 [2024-11-13 15:57:14,752 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23000 states to 23000 states and 33109 transitions. [2024-11-13 15:57:14,752 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23000 [2024-11-13 15:57:14,777 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23000 [2024-11-13 15:57:14,778 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23000 states and 33109 transitions. [2024-11-13 15:57:14,814 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:14,814 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23000 states and 33109 transitions. [2024-11-13 15:57:14,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23000 states and 33109 transitions. [2024-11-13 15:57:15,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23000 to 23000. [2024-11-13 15:57:15,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23000 states, 23000 states have (on average 1.4395217391304347) internal successors, (33109), 22999 states have internal predecessors, (33109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:15,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23000 states to 23000 states and 33109 transitions. [2024-11-13 15:57:15,506 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23000 states and 33109 transitions. [2024-11-13 15:57:15,506 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:57:15,507 INFO L424 stractBuchiCegarLoop]: Abstraction has 23000 states and 33109 transitions. [2024-11-13 15:57:15,507 INFO L331 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-13 15:57:15,507 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23000 states and 33109 transitions. [2024-11-13 15:57:15,588 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22755 [2024-11-13 15:57:15,588 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:15,588 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:15,591 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:15,592 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:15,592 INFO L745 eck$LassoCheckResult]: Stem: 160013#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 160014#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 161007#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 161008#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 160084#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 160085#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 159988#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 159989#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 161412#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 160656#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 160657#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 160541#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 160542#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 161100#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 161101#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 160285#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 160286#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 160749#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 160750#L1194 assume !(0 == ~M_E~0); 160916#L1194-2 assume !(0 == ~T1_E~0); 160917#L1199-1 assume !(0 == ~T2_E~0); 161256#L1204-1 assume !(0 == ~T3_E~0); 161160#L1209-1 assume !(0 == ~T4_E~0); 161161#L1214-1 assume !(0 == ~T5_E~0); 161722#L1219-1 assume !(0 == ~T6_E~0); 161905#L1224-1 assume !(0 == ~T7_E~0); 160363#L1229-1 assume !(0 == ~T8_E~0); 159907#L1234-1 assume !(0 == ~T9_E~0); 159908#L1239-1 assume !(0 == ~T10_E~0); 159949#L1244-1 assume !(0 == ~T11_E~0); 159950#L1249-1 assume !(0 == ~T12_E~0); 160687#L1254-1 assume !(0 == ~E_M~0); 159849#L1259-1 assume !(0 == ~E_1~0); 159813#L1264-1 assume !(0 == ~E_2~0); 159814#L1269-1 assume !(0 == ~E_3~0); 161918#L1274-1 assume !(0 == ~E_4~0); 161777#L1279-1 assume !(0 == ~E_5~0); 160024#L1284-1 assume !(0 == ~E_6~0); 160025#L1289-1 assume !(0 == ~E_7~0); 160758#L1294-1 assume !(0 == ~E_8~0); 160759#L1299-1 assume !(0 == ~E_9~0); 160770#L1304-1 assume !(0 == ~E_10~0); 161885#L1309-1 assume !(0 == ~E_11~0); 161899#L1314-1 assume !(0 == ~E_12~0); 159980#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 159905#L586 assume !(1 == ~m_pc~0); 159906#L586-2 is_master_triggered_~__retres1~0#1 := 0; 159971#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 160837#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 160183#L1485 assume !(0 != activate_threads_~tmp~1#1); 160184#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 161419#L605 assume !(1 == ~t1_pc~0); 160853#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 160573#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 160574#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 161303#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 161223#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 160477#L624 assume 1 == ~t2_pc~0; 159953#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 159954#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 160210#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 160211#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 161476#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 161301#L643 assume !(1 == ~t3_pc~0); 161129#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 160790#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 160791#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 160292#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 160293#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 160045#L662 assume 1 == ~t4_pc~0; 160046#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 160004#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 159867#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 159868#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 159894#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 159895#L681 assume !(1 == ~t5_pc~0); 159769#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 159770#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 160880#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 161655#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 160306#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 160307#L700 assume 1 == ~t6_pc~0; 161077#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 160036#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 160037#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 160086#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 160087#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 161548#L719 assume 1 == ~t7_pc~0; 161673#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 160260#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 161873#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 161757#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 159783#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 159784#L738 assume !(1 == ~t8_pc~0); 161263#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 161151#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 161152#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 160912#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 160913#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 161327#L757 assume 1 == ~t9_pc~0; 161328#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 159778#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 159779#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 160258#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 160872#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 160873#L776 assume !(1 == ~t10_pc~0); 159800#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 159799#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 160187#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 160026#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 160027#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 159981#L795 assume 1 == ~t11_pc~0; 159982#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 160326#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 161447#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 161705#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 161120#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 161104#L814 assume !(1 == ~t12_pc~0); 160945#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 160946#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 159826#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 159827#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 160242#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 160243#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 161492#L1332-2 assume !(1 == ~T1_E~0); 161807#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 161026#L1342-1 assume !(1 == ~T3_E~0); 161027#L1347-1 assume !(1 == ~T4_E~0); 161526#L1352-1 assume !(1 == ~T5_E~0); 161335#L1357-1 assume !(1 == ~T6_E~0); 160539#L1362-1 assume !(1 == ~T7_E~0); 160540#L1367-1 assume !(1 == ~T8_E~0); 160120#L1372-1 assume !(1 == ~T9_E~0); 160121#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 160715#L1382-1 assume !(1 == ~T11_E~0); 163461#L1387-1 assume !(1 == ~T12_E~0); 161740#L1392-1 assume !(1 == ~E_M~0); 160478#L1397-1 assume !(1 == ~E_1~0); 160479#L1402-1 assume !(1 == ~E_2~0); 160135#L1407-1 assume !(1 == ~E_3~0); 160136#L1412-1 assume !(1 == ~E_4~0); 163419#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 163415#L1422-1 assume !(1 == ~E_6~0); 163413#L1427-1 assume !(1 == ~E_7~0); 163397#L1432-1 assume !(1 == ~E_8~0); 163393#L1437-1 assume !(1 == ~E_9~0); 163389#L1442-1 assume !(1 == ~E_10~0); 163383#L1447-1 assume !(1 == ~E_11~0); 163379#L1452-1 assume !(1 == ~E_12~0); 163374#L1457-1 assume { :end_inline_reset_delta_events } true; 163372#L1803-2 [2024-11-13 15:57:15,593 INFO L747 eck$LassoCheckResult]: Loop: 163372#L1803-2 assume !false; 163366#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 163362#L1169-1 assume !false; 163361#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 163357#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 163347#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 163346#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 163344#L996 assume !(0 != eval_~tmp~0#1); 163343#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 163342#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 163339#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 163340#L1194-5 assume !(0 == ~T1_E~0); 163926#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 163923#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 163920#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 163917#L1214-3 assume !(0 == ~T5_E~0); 163914#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 163911#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 163908#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 163905#L1234-3 assume !(0 == ~T9_E~0); 163902#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 163899#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 163896#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 163893#L1254-3 assume !(0 == ~E_M~0); 163890#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 163887#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 163884#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 163881#L1274-3 assume !(0 == ~E_4~0); 163878#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 163875#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 163872#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 163869#L1294-3 assume !(0 == ~E_8~0); 163866#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 163863#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 163860#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 163857#L1314-3 assume !(0 == ~E_12~0); 163854#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 163851#L586-42 assume !(1 == ~m_pc~0); 163848#L586-44 is_master_triggered_~__retres1~0#1 := 0; 163845#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163840#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 163835#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 163830#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 163825#L605-42 assume !(1 == ~t1_pc~0); 163822#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 163818#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 163812#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 163808#L1493-42 assume !(0 != activate_threads_~tmp___0~0#1); 163804#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 163801#L624-42 assume 1 == ~t2_pc~0; 163798#L625-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 163794#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 163789#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 163786#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 163783#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 163780#L643-42 assume 1 == ~t3_pc~0; 163776#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 163773#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 163768#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 163765#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 163762#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 163759#L662-42 assume !(1 == ~t4_pc~0); 163755#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 163752#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 163747#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 163744#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 163741#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 163738#L681-42 assume 1 == ~t5_pc~0; 163734#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 163731#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 163726#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 163723#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 163720#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 163717#L700-42 assume 1 == ~t6_pc~0; 163714#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 163710#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 163705#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 163702#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 163699#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 163696#L719-42 assume 1 == ~t7_pc~0; 163692#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 163689#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 163684#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 163681#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 163678#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 163675#L738-42 assume 1 == ~t8_pc~0; 163671#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 163668#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 163663#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 163660#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 163657#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 163654#L757-42 assume 1 == ~t9_pc~0; 163650#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 163647#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 163642#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 163639#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 163636#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 163633#L776-42 assume !(1 == ~t10_pc~0); 163630#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 163626#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 163621#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 163618#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 163615#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 163612#L795-42 assume !(1 == ~t11_pc~0); 163608#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 163605#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 163600#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 163597#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 163594#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 163591#L814-42 assume 1 == ~t12_pc~0; 163587#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 163584#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 163581#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 163578#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 163575#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 163572#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 159976#L1332-5 assume !(1 == ~T1_E~0); 163567#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 163564#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 163561#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 163557#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 163555#L1357-3 assume !(1 == ~T6_E~0); 163553#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 163551#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 163548#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 163545#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 163523#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 163519#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 163508#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 163503#L1397-3 assume !(1 == ~E_1~0); 163498#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 163488#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 163487#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 163477#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 163476#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 163475#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 163474#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 163473#L1437-3 assume !(1 == ~E_9~0); 163462#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 163460#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 163451#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 163446#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 163440#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 163426#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 163422#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 163417#L1822 assume !(0 == start_simulation_~tmp~3#1); 161331#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 163406#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 163395#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 163391#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 163387#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 163381#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 163376#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 163373#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 163372#L1803-2 [2024-11-13 15:57:15,593 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:15,594 INFO L85 PathProgramCache]: Analyzing trace with hash -1724859847, now seen corresponding path program 1 times [2024-11-13 15:57:15,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:15,594 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1324712044] [2024-11-13 15:57:15,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:15,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:15,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:15,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:15,699 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:15,699 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1324712044] [2024-11-13 15:57:15,700 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1324712044] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:15,700 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:15,700 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:57:15,700 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [517212033] [2024-11-13 15:57:15,700 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:15,701 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:15,702 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:15,702 INFO L85 PathProgramCache]: Analyzing trace with hash -1130984100, now seen corresponding path program 1 times [2024-11-13 15:57:15,702 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:15,702 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952470003] [2024-11-13 15:57:15,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:15,703 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:15,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:15,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:15,786 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:15,787 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952470003] [2024-11-13 15:57:15,787 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1952470003] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:15,787 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:15,787 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:15,787 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [40310342] [2024-11-13 15:57:15,787 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:15,787 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:15,787 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:15,788 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:15,788 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:15,788 INFO L87 Difference]: Start difference. First operand 23000 states and 33109 transitions. cyclomatic complexity: 10125 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:16,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:16,363 INFO L93 Difference]: Finished difference Result 44040 states and 63119 transitions. [2024-11-13 15:57:16,363 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44040 states and 63119 transitions. [2024-11-13 15:57:16,551 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43748 [2024-11-13 15:57:16,742 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44040 states to 44040 states and 63119 transitions. [2024-11-13 15:57:16,742 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44040 [2024-11-13 15:57:16,786 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44040 [2024-11-13 15:57:16,786 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44040 states and 63119 transitions. [2024-11-13 15:57:16,850 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:16,850 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44040 states and 63119 transitions. [2024-11-13 15:57:17,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44040 states and 63119 transitions. [2024-11-13 15:57:18,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44040 to 44008. [2024-11-13 15:57:18,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44008 states, 44008 states have (on average 1.4335348118523905) internal successors, (63087), 44007 states have internal predecessors, (63087), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:18,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44008 states to 44008 states and 63087 transitions. [2024-11-13 15:57:18,319 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44008 states and 63087 transitions. [2024-11-13 15:57:18,320 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:18,321 INFO L424 stractBuchiCegarLoop]: Abstraction has 44008 states and 63087 transitions. [2024-11-13 15:57:18,321 INFO L331 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-13 15:57:18,321 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44008 states and 63087 transitions. [2024-11-13 15:57:18,530 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43716 [2024-11-13 15:57:18,530 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:18,530 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:18,535 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:18,535 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:18,536 INFO L745 eck$LassoCheckResult]: Stem: 227056#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 227057#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 228020#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 228021#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 227128#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 227129#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 227030#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 227031#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 228396#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 227687#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 227688#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 227574#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 227575#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 228108#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 228109#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 227328#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 227329#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 227777#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 227778#L1194 assume !(0 == ~M_E~0); 227932#L1194-2 assume !(0 == ~T1_E~0); 227933#L1199-1 assume !(0 == ~T2_E~0); 228247#L1204-1 assume !(0 == ~T3_E~0); 228162#L1209-1 assume !(0 == ~T4_E~0); 228163#L1214-1 assume !(0 == ~T5_E~0); 228641#L1219-1 assume !(0 == ~T6_E~0); 228759#L1224-1 assume !(0 == ~T7_E~0); 227405#L1229-1 assume !(0 == ~T8_E~0); 226961#L1234-1 assume !(0 == ~T9_E~0); 226962#L1239-1 assume !(0 == ~T10_E~0); 226997#L1244-1 assume !(0 == ~T11_E~0); 226998#L1249-1 assume !(0 == ~T12_E~0); 227719#L1254-1 assume !(0 == ~E_M~0); 226895#L1259-1 assume !(0 == ~E_1~0); 226860#L1264-1 assume !(0 == ~E_2~0); 226861#L1269-1 assume !(0 == ~E_3~0); 228771#L1274-1 assume !(0 == ~E_4~0); 228678#L1279-1 assume !(0 == ~E_5~0); 227065#L1284-1 assume !(0 == ~E_6~0); 227066#L1289-1 assume !(0 == ~E_7~0); 227784#L1294-1 assume !(0 == ~E_8~0); 227785#L1299-1 assume !(0 == ~E_9~0); 227796#L1304-1 assume !(0 == ~E_10~0); 228746#L1309-1 assume !(0 == ~E_11~0); 228755#L1314-1 assume !(0 == ~E_12~0); 227024#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 226951#L586 assume !(1 == ~m_pc~0); 226952#L586-2 is_master_triggered_~__retres1~0#1 := 0; 227014#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 227855#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 227228#L1485 assume !(0 != activate_threads_~tmp~1#1); 227229#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 228402#L605 assume !(1 == ~t1_pc~0); 227870#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 227604#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 227605#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 228295#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 228222#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 227510#L624 assume !(1 == ~t2_pc~0); 227511#L624-2 is_transmit2_triggered_~__retres1~2#1 := 0; 227693#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 227254#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 227255#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 228443#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 228293#L643 assume !(1 == ~t3_pc~0); 228133#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 227819#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 227820#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 227335#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 227336#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 227087#L662 assume 1 == ~t4_pc~0; 227088#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 227045#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 226916#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 226917#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 226942#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 226943#L681 assume !(1 == ~t5_pc~0); 226816#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 226817#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 227897#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 228587#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 227347#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 227348#L700 assume 1 == ~t6_pc~0; 228084#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 227078#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 227079#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 227130#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 227131#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 228506#L719 assume 1 == ~t7_pc~0; 228603#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 227304#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 228739#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 228662#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 226830#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 226831#L738 assume !(1 == ~t8_pc~0); 228257#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 228154#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 228155#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 227928#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 227929#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 228318#L757 assume 1 == ~t9_pc~0; 228319#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 226825#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 226826#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 227301#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 227889#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 227890#L776 assume !(1 == ~t10_pc~0); 226847#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 226846#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 227232#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 227067#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 227068#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 227025#L795 assume 1 == ~t11_pc~0; 227026#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 227369#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 228423#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 228629#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 228124#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 228112#L814 assume !(1 == ~t12_pc~0); 227958#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 227959#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 226875#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 226876#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 227285#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 227286#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 228456#L1332-2 assume !(1 == ~T1_E~0); 228701#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 228041#L1342-1 assume !(1 == ~T3_E~0); 228042#L1347-1 assume !(1 == ~T4_E~0); 228492#L1352-1 assume !(1 == ~T5_E~0); 228325#L1357-1 assume !(1 == ~T6_E~0); 227572#L1362-1 assume !(1 == ~T7_E~0); 227573#L1367-1 assume !(1 == ~T8_E~0); 227166#L1372-1 assume !(1 == ~T9_E~0); 227167#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 227483#L1382-1 assume !(1 == ~T11_E~0); 227484#L1387-1 assume !(1 == ~T12_E~0); 228219#L1392-1 assume !(1 == ~E_M~0); 227512#L1397-1 assume !(1 == ~E_1~0); 227513#L1402-1 assume !(1 == ~E_2~0); 227182#L1407-1 assume !(1 == ~E_3~0); 227183#L1412-1 assume !(1 == ~E_4~0); 228745#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 252739#L1422-1 assume !(1 == ~E_6~0); 252737#L1427-1 assume !(1 == ~E_7~0); 252735#L1432-1 assume !(1 == ~E_8~0); 252572#L1437-1 assume !(1 == ~E_9~0); 252489#L1442-1 assume !(1 == ~E_10~0); 252486#L1447-1 assume !(1 == ~E_11~0); 252485#L1452-1 assume !(1 == ~E_12~0); 250899#L1457-1 assume { :end_inline_reset_delta_events } true; 252442#L1803-2 [2024-11-13 15:57:18,537 INFO L747 eck$LassoCheckResult]: Loop: 252442#L1803-2 assume !false; 252430#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 252421#L1169-1 assume !false; 252345#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 252339#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 252327#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 252325#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 252322#L996 assume !(0 != eval_~tmp~0#1); 252323#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 254379#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 254377#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 254375#L1194-5 assume !(0 == ~T1_E~0); 254374#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 254372#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 254370#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 254365#L1214-3 assume !(0 == ~T5_E~0); 254363#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 254361#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 254360#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 254359#L1234-3 assume !(0 == ~T9_E~0); 254358#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 254357#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 254356#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 254355#L1254-3 assume !(0 == ~E_M~0); 254354#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 254353#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 254352#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 254351#L1274-3 assume !(0 == ~E_4~0); 254350#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 254349#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 254347#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 254345#L1294-3 assume !(0 == ~E_8~0); 254343#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 254341#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 254339#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 254337#L1314-3 assume !(0 == ~E_12~0); 254335#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 254333#L586-42 assume !(1 == ~m_pc~0); 254331#L586-44 is_master_triggered_~__retres1~0#1 := 0; 254329#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 254327#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 254325#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 254323#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 254321#L605-42 assume !(1 == ~t1_pc~0); 254319#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 255616#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 255614#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 254311#L1493-42 assume !(0 != activate_threads_~tmp___0~0#1); 254308#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 254306#L624-42 assume !(1 == ~t2_pc~0); 254304#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 254302#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 254300#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 254298#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 254296#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 254294#L643-42 assume 1 == ~t3_pc~0; 254291#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 254289#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 254287#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 254285#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 254283#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 254281#L662-42 assume 1 == ~t4_pc~0; 254279#L663-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 254276#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 254273#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 254271#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 254269#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 254268#L681-42 assume !(1 == ~t5_pc~0); 254267#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 254263#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 254261#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 254259#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 254257#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 254255#L700-42 assume 1 == ~t6_pc~0; 254253#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 254250#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 254248#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 254246#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 254243#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 254241#L719-42 assume !(1 == ~t7_pc~0); 254238#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 254235#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 254233#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 254230#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 254228#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 254226#L738-42 assume !(1 == ~t8_pc~0); 254224#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 254221#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 254219#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 254218#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 254217#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 253588#L757-42 assume !(1 == ~t9_pc~0); 253585#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 253582#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 253580#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 253578#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 253576#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 253574#L776-42 assume !(1 == ~t10_pc~0); 253570#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 253567#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 253565#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 253563#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 253561#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 253558#L795-42 assume !(1 == ~t11_pc~0); 253555#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 253553#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 253551#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 253549#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 253547#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 253546#L814-42 assume !(1 == ~t12_pc~0); 253542#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 253539#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 253537#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 253535#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 253532#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 253530#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 251161#L1332-5 assume !(1 == ~T1_E~0); 253527#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 253525#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 253523#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 253520#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 253518#L1357-3 assume !(1 == ~T6_E~0); 253516#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 253514#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 253512#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 251145#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 253510#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 253507#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 253505#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 253503#L1397-3 assume !(1 == ~E_1~0); 253501#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 253101#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 252870#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 252865#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 252863#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 252861#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 252859#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 252856#L1437-3 assume !(1 == ~E_9~0); 252854#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 252853#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 252852#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 252848#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 252717#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 252704#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 252702#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 252700#L1822 assume !(0 == start_simulation_~tmp~3#1); 230957#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 252548#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 252539#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 252537#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 252535#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 252532#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 252530#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 252483#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 252442#L1803-2 [2024-11-13 15:57:18,539 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:18,540 INFO L85 PathProgramCache]: Analyzing trace with hash -607674886, now seen corresponding path program 1 times [2024-11-13 15:57:18,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:18,540 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [641807546] [2024-11-13 15:57:18,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:18,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:18,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:18,684 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:18,684 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:18,684 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [641807546] [2024-11-13 15:57:18,685 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [641807546] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:18,685 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:18,685 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:57:18,685 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2109274287] [2024-11-13 15:57:18,685 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:18,686 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:18,687 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:18,687 INFO L85 PathProgramCache]: Analyzing trace with hash 1831197281, now seen corresponding path program 1 times [2024-11-13 15:57:18,687 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:18,687 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1275263783] [2024-11-13 15:57:18,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:18,688 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:18,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:18,964 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:18,964 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:18,964 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1275263783] [2024-11-13 15:57:18,965 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1275263783] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:18,965 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:18,965 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:18,965 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [395632403] [2024-11-13 15:57:18,965 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:18,966 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:18,966 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:18,966 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:18,966 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:18,967 INFO L87 Difference]: Start difference. First operand 44008 states and 63087 transitions. cyclomatic complexity: 19111 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:19,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:19,647 INFO L93 Difference]: Finished difference Result 84359 states and 120448 transitions. [2024-11-13 15:57:19,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84359 states and 120448 transitions. [2024-11-13 15:57:20,136 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 83940 [2024-11-13 15:57:20,645 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84359 states to 84359 states and 120448 transitions. [2024-11-13 15:57:20,645 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 84359 [2024-11-13 15:57:20,682 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 84359 [2024-11-13 15:57:20,682 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84359 states and 120448 transitions. [2024-11-13 15:57:20,736 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:20,736 INFO L218 hiAutomatonCegarLoop]: Abstraction has 84359 states and 120448 transitions. [2024-11-13 15:57:20,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84359 states and 120448 transitions. [2024-11-13 15:57:21,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84359 to 84295. [2024-11-13 15:57:21,941 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84295 states, 84295 states have (on average 1.4281274096921526) internal successors, (120384), 84294 states have internal predecessors, (120384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:22,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84295 states to 84295 states and 120384 transitions. [2024-11-13 15:57:22,215 INFO L240 hiAutomatonCegarLoop]: Abstraction has 84295 states and 120384 transitions. [2024-11-13 15:57:22,216 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:22,216 INFO L424 stractBuchiCegarLoop]: Abstraction has 84295 states and 120384 transitions. [2024-11-13 15:57:22,216 INFO L331 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-13 15:57:22,216 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84295 states and 120384 transitions. [2024-11-13 15:57:22,862 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 83876 [2024-11-13 15:57:22,862 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:22,862 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:22,865 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:22,865 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:22,866 INFO L745 eck$LassoCheckResult]: Stem: 355432#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 355433#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 356408#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 356409#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 355502#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 355503#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 355407#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 355408#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 356786#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 356065#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 356066#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 355949#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 355950#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 356497#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 356498#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 355703#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 355704#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 356156#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 356157#L1194 assume !(0 == ~M_E~0); 356319#L1194-2 assume !(0 == ~T1_E~0); 356320#L1199-1 assume !(0 == ~T2_E~0); 356640#L1204-1 assume !(0 == ~T3_E~0); 356553#L1209-1 assume !(0 == ~T4_E~0); 356554#L1214-1 assume !(0 == ~T5_E~0); 357060#L1219-1 assume !(0 == ~T6_E~0); 357228#L1224-1 assume !(0 == ~T7_E~0); 355779#L1229-1 assume !(0 == ~T8_E~0); 355328#L1234-1 assume !(0 == ~T9_E~0); 355329#L1239-1 assume !(0 == ~T10_E~0); 355371#L1244-1 assume !(0 == ~T11_E~0); 355372#L1249-1 assume !(0 == ~T12_E~0); 356096#L1254-1 assume !(0 == ~E_M~0); 355270#L1259-1 assume !(0 == ~E_1~0); 355234#L1264-1 assume !(0 == ~E_2~0); 355235#L1269-1 assume !(0 == ~E_3~0); 357240#L1274-1 assume !(0 == ~E_4~0); 357104#L1279-1 assume !(0 == ~E_5~0); 355443#L1284-1 assume !(0 == ~E_6~0); 355444#L1289-1 assume !(0 == ~E_7~0); 356165#L1294-1 assume !(0 == ~E_8~0); 356166#L1299-1 assume !(0 == ~E_9~0); 356177#L1304-1 assume !(0 == ~E_10~0); 357215#L1309-1 assume !(0 == ~E_11~0); 357224#L1314-1 assume !(0 == ~E_12~0); 355399#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 355326#L586 assume !(1 == ~m_pc~0); 355327#L586-2 is_master_triggered_~__retres1~0#1 := 0; 355390#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 356240#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 355601#L1485 assume !(0 != activate_threads_~tmp~1#1); 355602#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 356793#L605 assume !(1 == ~t1_pc~0); 356256#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 355980#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 355981#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 356685#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 356612#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 355886#L624 assume !(1 == ~t2_pc~0); 355887#L624-2 is_transmit2_triggered_~__retres1~2#1 := 0; 356071#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 355628#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 355629#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 356848#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 356683#L643 assume !(1 == ~t3_pc~0); 356523#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 356195#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 356196#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 355710#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 355711#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 355464#L662 assume !(1 == ~t4_pc~0); 355465#L662-2 is_transmit4_triggered_~__retres1~4#1 := 0; 355423#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 355288#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 355289#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 355315#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 355316#L681 assume !(1 == ~t5_pc~0); 355190#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 355191#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 356283#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 357009#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 355723#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 355724#L700 assume 1 == ~t6_pc~0; 356472#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 355455#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 355456#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 355504#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 355505#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 356914#L719 assume 1 == ~t7_pc~0; 357022#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 355677#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 357200#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 357089#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 355204#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 355205#L738 assume !(1 == ~t8_pc~0); 356647#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 356544#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 356545#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 356315#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 356316#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 356705#L757 assume 1 == ~t9_pc~0; 356706#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 355199#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 355200#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 355675#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 356275#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 356276#L776 assume !(1 == ~t10_pc~0); 355221#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 355220#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 355605#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 355445#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 355446#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 355400#L795 assume 1 == ~t11_pc~0; 355401#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 355744#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 356823#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 357045#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 356514#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 356501#L814 assume !(1 == ~t12_pc~0); 356348#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 356349#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 355247#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 355248#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 355659#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 355660#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 356863#L1332-2 assume !(1 == ~T1_E~0); 357141#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 356425#L1342-1 assume !(1 == ~T3_E~0); 356426#L1347-1 assume !(1 == ~T4_E~0); 356896#L1352-1 assume !(1 == ~T5_E~0); 356712#L1357-1 assume !(1 == ~T6_E~0); 355947#L1362-1 assume !(1 == ~T7_E~0); 355948#L1367-1 assume !(1 == ~T8_E~0); 355539#L1372-1 assume !(1 == ~T9_E~0); 355540#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 375446#L1382-1 assume !(1 == ~T11_E~0); 375444#L1387-1 assume !(1 == ~T12_E~0); 375442#L1392-1 assume !(1 == ~E_M~0); 375440#L1397-1 assume !(1 == ~E_1~0); 375438#L1402-1 assume !(1 == ~E_2~0); 375436#L1407-1 assume !(1 == ~E_3~0); 375433#L1412-1 assume !(1 == ~E_4~0); 375431#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 375429#L1422-1 assume !(1 == ~E_6~0); 375427#L1427-1 assume !(1 == ~E_7~0); 375425#L1432-1 assume !(1 == ~E_8~0); 375423#L1437-1 assume !(1 == ~E_9~0); 373427#L1442-1 assume !(1 == ~E_10~0); 373425#L1447-1 assume !(1 == ~E_11~0); 373421#L1452-1 assume !(1 == ~E_12~0); 373415#L1457-1 assume { :end_inline_reset_delta_events } true; 373410#L1803-2 [2024-11-13 15:57:22,867 INFO L747 eck$LassoCheckResult]: Loop: 373410#L1803-2 assume !false; 373409#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 373405#L1169-1 assume !false; 373404#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 373399#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 373388#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 373386#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 373383#L996 assume !(0 != eval_~tmp~0#1); 373384#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 393614#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 393613#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 393612#L1194-5 assume !(0 == ~T1_E~0); 393611#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 393609#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 393608#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 393607#L1214-3 assume !(0 == ~T5_E~0); 393606#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 393604#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 393603#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 393602#L1234-3 assume !(0 == ~T9_E~0); 393601#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 393599#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 393598#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 393596#L1254-3 assume !(0 == ~E_M~0); 393594#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 393593#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 393592#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 393590#L1274-3 assume !(0 == ~E_4~0); 393587#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 393585#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 393583#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 393581#L1294-3 assume !(0 == ~E_8~0); 393578#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 393576#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 393574#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 393572#L1314-3 assume !(0 == ~E_12~0); 393570#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 393566#L586-42 assume !(1 == ~m_pc~0); 393564#L586-44 is_master_triggered_~__retres1~0#1 := 0; 393562#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 393560#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 393557#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 393555#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 393553#L605-42 assume 1 == ~t1_pc~0; 393551#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 393552#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 393610#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 393542#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 393540#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 393538#L624-42 assume !(1 == ~t2_pc~0); 393535#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 393533#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 393531#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 393529#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 393527#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 393525#L643-42 assume !(1 == ~t3_pc~0); 393522#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 393519#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 393517#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 393515#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 393513#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 393511#L662-42 assume !(1 == ~t4_pc~0); 393510#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 393509#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 393508#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 393507#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 393505#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 393503#L681-42 assume 1 == ~t5_pc~0; 393500#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 393498#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 393496#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 393494#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 393492#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 393490#L700-42 assume 1 == ~t6_pc~0; 393488#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 393485#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 393482#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 393480#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 393478#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 393476#L719-42 assume !(1 == ~t7_pc~0); 393474#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 393471#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 393468#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 393466#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 393464#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 393462#L738-42 assume !(1 == ~t8_pc~0); 393460#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 393457#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 393454#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 393452#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 393450#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 393448#L757-42 assume !(1 == ~t9_pc~0); 393446#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 393443#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 380998#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 380996#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 380994#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 380992#L776-42 assume !(1 == ~t10_pc~0); 380988#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 380985#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 380983#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 380981#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 380979#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 380977#L795-42 assume 1 == ~t11_pc~0; 380975#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 380972#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 380970#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 380968#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 380966#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 380964#L814-42 assume 1 == ~t12_pc~0; 380961#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 380958#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 380956#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 380954#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 380952#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 380950#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 357668#L1332-5 assume !(1 == ~T1_E~0); 380945#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 380943#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 380941#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 380938#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 380936#L1357-3 assume !(1 == ~T6_E~0); 380934#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 380932#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 380930#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 380926#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 380924#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 380922#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 380920#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 380917#L1397-3 assume !(1 == ~E_1~0); 380915#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 380913#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 380911#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 380907#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 380905#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 380903#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 380901#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 380899#L1437-3 assume !(1 == ~E_9~0); 380897#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 380895#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 380893#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 380888#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 374628#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 374614#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 374612#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 374610#L1822 assume !(0 == start_simulation_~tmp~3#1); 374607#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 374590#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 374581#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 374579#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 374577#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 374575#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 374573#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 373414#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 373410#L1803-2 [2024-11-13 15:57:22,867 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:22,867 INFO L85 PathProgramCache]: Analyzing trace with hash 852319035, now seen corresponding path program 1 times [2024-11-13 15:57:22,868 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:22,868 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1861454430] [2024-11-13 15:57:22,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:22,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:22,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:22,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:22,970 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:22,970 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1861454430] [2024-11-13 15:57:22,970 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1861454430] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:22,971 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:22,971 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:57:22,971 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [41114699] [2024-11-13 15:57:22,971 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:22,971 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:22,972 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:22,972 INFO L85 PathProgramCache]: Analyzing trace with hash -1875778851, now seen corresponding path program 1 times [2024-11-13 15:57:22,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:22,972 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1408234269] [2024-11-13 15:57:22,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:22,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:23,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:23,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:23,229 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:23,229 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1408234269] [2024-11-13 15:57:23,229 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1408234269] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:23,230 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:23,230 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:23,230 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [514221303] [2024-11-13 15:57:23,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:23,230 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:23,231 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:23,231 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:57:23,231 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:57:23,232 INFO L87 Difference]: Start difference. First operand 84295 states and 120384 transitions. cyclomatic complexity: 36153 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:24,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:24,188 INFO L93 Difference]: Finished difference Result 161570 states and 229881 transitions. [2024-11-13 15:57:24,189 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 161570 states and 229881 transitions. [2024-11-13 15:57:24,960 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 160832 [2024-11-13 15:57:25,713 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 161570 states to 161570 states and 229881 transitions. [2024-11-13 15:57:25,714 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 161570 [2024-11-13 15:57:25,802 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 161570 [2024-11-13 15:57:25,802 INFO L73 IsDeterministic]: Start isDeterministic. Operand 161570 states and 229881 transitions. [2024-11-13 15:57:25,916 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:25,917 INFO L218 hiAutomatonCegarLoop]: Abstraction has 161570 states and 229881 transitions. [2024-11-13 15:57:26,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161570 states and 229881 transitions. [2024-11-13 15:57:27,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161570 to 161442. [2024-11-13 15:57:27,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 161442 states, 161442 states have (on average 1.4231302882769044) internal successors, (229753), 161441 states have internal predecessors, (229753), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:28,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161442 states to 161442 states and 229753 transitions. [2024-11-13 15:57:28,759 INFO L240 hiAutomatonCegarLoop]: Abstraction has 161442 states and 229753 transitions. [2024-11-13 15:57:28,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:57:28,760 INFO L424 stractBuchiCegarLoop]: Abstraction has 161442 states and 229753 transitions. [2024-11-13 15:57:28,760 INFO L331 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-13 15:57:28,760 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 161442 states and 229753 transitions. [2024-11-13 15:57:29,151 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 160704 [2024-11-13 15:57:29,151 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:29,151 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:29,155 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:29,155 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:29,156 INFO L745 eck$LassoCheckResult]: Stem: 601302#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 601303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 602268#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 602269#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 601370#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 601371#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 601275#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 601276#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 602631#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 601930#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 601931#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 601820#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 601821#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 602351#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 602352#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 601572#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 601573#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 602022#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 602023#L1194 assume !(0 == ~M_E~0); 602181#L1194-2 assume !(0 == ~T1_E~0); 602182#L1199-1 assume !(0 == ~T2_E~0); 602489#L1204-1 assume !(0 == ~T3_E~0); 602404#L1209-1 assume !(0 == ~T4_E~0); 602405#L1214-1 assume !(0 == ~T5_E~0); 602881#L1219-1 assume !(0 == ~T6_E~0); 603020#L1224-1 assume !(0 == ~T7_E~0); 601651#L1229-1 assume !(0 == ~T8_E~0); 601206#L1234-1 assume !(0 == ~T9_E~0); 601207#L1239-1 assume !(0 == ~T10_E~0); 601243#L1244-1 assume !(0 == ~T11_E~0); 601244#L1249-1 assume !(0 == ~T12_E~0); 601963#L1254-1 assume !(0 == ~E_M~0); 601141#L1259-1 assume !(0 == ~E_1~0); 601106#L1264-1 assume !(0 == ~E_2~0); 601107#L1269-1 assume !(0 == ~E_3~0); 603038#L1274-1 assume !(0 == ~E_4~0); 602928#L1279-1 assume !(0 == ~E_5~0); 601311#L1284-1 assume !(0 == ~E_6~0); 601312#L1289-1 assume !(0 == ~E_7~0); 602031#L1294-1 assume !(0 == ~E_8~0); 602032#L1299-1 assume !(0 == ~E_9~0); 602044#L1304-1 assume !(0 == ~E_10~0); 603007#L1309-1 assume !(0 == ~E_11~0); 603016#L1314-1 assume !(0 == ~E_12~0); 601269#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 601196#L586 assume !(1 == ~m_pc~0); 601197#L586-2 is_master_triggered_~__retres1~0#1 := 0; 601260#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 602105#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 601470#L1485 assume !(0 != activate_threads_~tmp~1#1); 601471#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 602641#L605 assume !(1 == ~t1_pc~0); 602120#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 601851#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 601852#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 602530#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 602463#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 601756#L624 assume !(1 == ~t2_pc~0); 601757#L624-2 is_transmit2_triggered_~__retres1~2#1 := 0; 601936#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 601497#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 601498#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 602682#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 602528#L643 assume !(1 == ~t3_pc~0); 602376#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 602067#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 602068#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 601579#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 601580#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 601333#L662 assume !(1 == ~t4_pc~0); 601334#L662-2 is_transmit4_triggered_~__retres1~4#1 := 0; 601291#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 601162#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 601163#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 601188#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 601189#L681 assume !(1 == ~t5_pc~0); 601062#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 601063#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 602147#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 602830#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 601591#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 601592#L700 assume !(1 == ~t6_pc~0); 601413#L700-2 is_transmit6_triggered_~__retres1~6#1 := 0; 601324#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 601325#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 601372#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 601373#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 602742#L719 assume 1 == ~t7_pc~0; 602842#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 601547#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 602997#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 602909#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 601076#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 601077#L738 assume !(1 == ~t8_pc~0); 602496#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 602395#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 602396#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 602177#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 602178#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 602552#L757 assume 1 == ~t9_pc~0; 602553#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 601071#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 601072#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 601544#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 602139#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 602140#L776 assume !(1 == ~t10_pc~0); 601093#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 601092#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 601474#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 601313#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 601314#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 601270#L795 assume 1 == ~t11_pc~0; 601271#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 601613#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 602661#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 602867#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 602367#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 602355#L814 assume !(1 == ~t12_pc~0); 602210#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 602211#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 601122#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 601123#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 601528#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 601529#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 602695#L1332-2 assume !(1 == ~T1_E~0); 605337#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 605334#L1342-1 assume !(1 == ~T3_E~0); 605333#L1347-1 assume !(1 == ~T4_E~0); 605331#L1352-1 assume !(1 == ~T5_E~0); 605329#L1357-1 assume !(1 == ~T6_E~0); 605327#L1362-1 assume !(1 == ~T7_E~0); 605325#L1367-1 assume !(1 == ~T8_E~0); 605323#L1372-1 assume !(1 == ~T9_E~0); 605321#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 605317#L1382-1 assume !(1 == ~T11_E~0); 605315#L1387-1 assume !(1 == ~T12_E~0); 605313#L1392-1 assume !(1 == ~E_M~0); 605311#L1397-1 assume !(1 == ~E_1~0); 605308#L1402-1 assume !(1 == ~E_2~0); 605306#L1407-1 assume !(1 == ~E_3~0); 605304#L1412-1 assume !(1 == ~E_4~0); 605302#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 605300#L1422-1 assume !(1 == ~E_6~0); 605298#L1427-1 assume !(1 == ~E_7~0); 605296#L1432-1 assume !(1 == ~E_8~0); 605294#L1437-1 assume !(1 == ~E_9~0); 605292#L1442-1 assume !(1 == ~E_10~0); 604944#L1447-1 assume !(1 == ~E_11~0); 604943#L1452-1 assume !(1 == ~E_12~0); 604939#L1457-1 assume { :end_inline_reset_delta_events } true; 604936#L1803-2 [2024-11-13 15:57:29,157 INFO L747 eck$LassoCheckResult]: Loop: 604936#L1803-2 assume !false; 604934#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 604929#L1169-1 assume !false; 604927#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 604908#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 604897#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 604895#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 604892#L996 assume !(0 != eval_~tmp~0#1); 604893#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 611694#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 611692#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 611690#L1194-5 assume !(0 == ~T1_E~0); 611687#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 611685#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 611683#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 611681#L1214-3 assume !(0 == ~T5_E~0); 611679#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 611677#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 611674#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 611672#L1234-3 assume !(0 == ~T9_E~0); 611670#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 611668#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 611666#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 611664#L1254-3 assume !(0 == ~E_M~0); 611661#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 611659#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 611657#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 611655#L1274-3 assume !(0 == ~E_4~0); 611653#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 611651#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 611648#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 611646#L1294-3 assume !(0 == ~E_8~0); 611644#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 611642#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 611640#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 611639#L1314-3 assume !(0 == ~E_12~0); 611638#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 611634#L586-42 assume !(1 == ~m_pc~0); 611632#L586-44 is_master_triggered_~__retres1~0#1 := 0; 611630#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 611629#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 611626#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 611625#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 611624#L605-42 assume 1 == ~t1_pc~0; 611623#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 611621#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 611619#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 611616#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 611615#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 611614#L624-42 assume !(1 == ~t2_pc~0); 611613#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 611612#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 611611#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 611610#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 611609#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 611608#L643-42 assume !(1 == ~t3_pc~0); 611607#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 611605#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 611604#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 611603#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 611602#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 611601#L662-42 assume !(1 == ~t4_pc~0); 611600#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 611599#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 611598#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 611597#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 611596#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 611595#L681-42 assume 1 == ~t5_pc~0; 611593#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 611592#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 611591#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 611589#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 611588#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 611587#L700-42 assume !(1 == ~t6_pc~0); 611586#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 611585#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 608921#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 608907#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 608905#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 608903#L719-42 assume 1 == ~t7_pc~0; 608899#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 608895#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 608894#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 608893#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 608891#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 608890#L738-42 assume !(1 == ~t8_pc~0); 607689#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 607686#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 607683#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 607681#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 607679#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 607676#L757-42 assume 1 == ~t9_pc~0; 607657#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 607655#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 607653#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 607651#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 607649#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 607647#L776-42 assume !(1 == ~t10_pc~0); 607645#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 607642#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 607639#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 607637#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 607635#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 607633#L795-42 assume 1 == ~t11_pc~0; 607631#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 607628#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 607626#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 607624#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 607622#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 607620#L814-42 assume 1 == ~t12_pc~0; 607617#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 607615#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 607612#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 607610#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 607608#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 607606#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 607050#L1332-5 assume !(1 == ~T1_E~0); 607601#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 607598#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 607596#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 606923#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 606921#L1357-3 assume !(1 == ~T6_E~0); 606919#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 606917#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 606914#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 606910#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 606908#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 606906#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 606904#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 606902#L1397-3 assume !(1 == ~E_1~0); 606899#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 606897#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 606895#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 606891#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 606889#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 606887#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 606884#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 606882#L1437-3 assume !(1 == ~E_9~0); 606880#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 606878#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 606876#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 606872#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 606493#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 606480#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 606478#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 605469#L1822 assume !(0 == start_simulation_~tmp~3#1); 605465#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 604977#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 604968#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 604966#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 604964#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 604961#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 604959#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 604938#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 604936#L1803-2 [2024-11-13 15:57:29,158 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:29,158 INFO L85 PathProgramCache]: Analyzing trace with hash 1989947900, now seen corresponding path program 1 times [2024-11-13 15:57:29,158 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:29,158 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [768193370] [2024-11-13 15:57:29,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:29,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:29,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:29,315 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:29,315 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:29,316 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [768193370] [2024-11-13 15:57:29,316 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [768193370] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:29,316 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:29,317 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:29,317 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1893515769] [2024-11-13 15:57:29,317 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:29,318 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:29,319 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:29,320 INFO L85 PathProgramCache]: Analyzing trace with hash -1133813092, now seen corresponding path program 1 times [2024-11-13 15:57:29,320 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:29,320 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399329613] [2024-11-13 15:57:29,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:29,320 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:29,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:29,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:29,432 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:29,432 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1399329613] [2024-11-13 15:57:29,432 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1399329613] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:29,432 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:29,432 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:29,433 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1527712969] [2024-11-13 15:57:29,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:29,433 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:29,433 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:29,434 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:57:29,434 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:57:29,434 INFO L87 Difference]: Start difference. First operand 161442 states and 229753 transitions. cyclomatic complexity: 68439 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:32,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:32,952 INFO L93 Difference]: Finished difference Result 454896 states and 642499 transitions. [2024-11-13 15:57:32,952 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454896 states and 642499 transitions. [2024-11-13 15:57:35,015 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 452112 [2024-11-13 15:57:36,492 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454896 states to 454896 states and 642499 transitions. [2024-11-13 15:57:36,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454896 [2024-11-13 15:57:36,736 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454896 [2024-11-13 15:57:36,736 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454896 states and 642499 transitions. [2024-11-13 15:57:37,040 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:37,040 INFO L218 hiAutomatonCegarLoop]: Abstraction has 454896 states and 642499 transitions. [2024-11-13 15:57:37,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454896 states and 642499 transitions. [2024-11-13 15:57:41,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454896 to 448624. [2024-11-13 15:57:42,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 448624 states, 448624 states have (on average 1.413323852491173) internal successors, (634051), 448623 states have internal predecessors, (634051), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:44,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 448624 states to 448624 states and 634051 transitions. [2024-11-13 15:57:44,682 INFO L240 hiAutomatonCegarLoop]: Abstraction has 448624 states and 634051 transitions. [2024-11-13 15:57:44,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:57:44,686 INFO L424 stractBuchiCegarLoop]: Abstraction has 448624 states and 634051 transitions. [2024-11-13 15:57:44,687 INFO L331 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-13 15:57:44,687 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 448624 states and 634051 transitions. [2024-11-13 15:57:46,821 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 446608 [2024-11-13 15:57:46,821 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:57:46,821 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:57:46,823 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:46,823 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:57:46,823 INFO L745 eck$LassoCheckResult]: Stem: 1217652#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1217653#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1218604#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1218605#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1217719#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 1217720#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1217626#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1217627#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1218985#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1218277#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1218278#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1218165#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1218166#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1218695#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1218696#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1217920#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1217921#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1218369#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1218370#L1194 assume !(0 == ~M_E~0); 1218521#L1194-2 assume !(0 == ~T1_E~0); 1218522#L1199-1 assume !(0 == ~T2_E~0); 1218841#L1204-1 assume !(0 == ~T3_E~0); 1218750#L1209-1 assume !(0 == ~T4_E~0); 1218751#L1214-1 assume !(0 == ~T5_E~0); 1219244#L1219-1 assume !(0 == ~T6_E~0); 1219385#L1224-1 assume !(0 == ~T7_E~0); 1217996#L1229-1 assume !(0 == ~T8_E~0); 1217556#L1234-1 assume !(0 == ~T9_E~0); 1217557#L1239-1 assume !(0 == ~T10_E~0); 1217593#L1244-1 assume !(0 == ~T11_E~0); 1217594#L1249-1 assume !(0 == ~T12_E~0); 1218308#L1254-1 assume !(0 == ~E_M~0); 1217490#L1259-1 assume !(0 == ~E_1~0); 1217454#L1264-1 assume !(0 == ~E_2~0); 1217455#L1269-1 assume !(0 == ~E_3~0); 1219396#L1274-1 assume !(0 == ~E_4~0); 1219290#L1279-1 assume !(0 == ~E_5~0); 1217661#L1284-1 assume !(0 == ~E_6~0); 1217662#L1289-1 assume !(0 == ~E_7~0); 1218374#L1294-1 assume !(0 == ~E_8~0); 1218375#L1299-1 assume !(0 == ~E_9~0); 1218388#L1304-1 assume !(0 == ~E_10~0); 1219375#L1309-1 assume !(0 == ~E_11~0); 1219383#L1314-1 assume !(0 == ~E_12~0); 1217620#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1217546#L586 assume !(1 == ~m_pc~0); 1217547#L586-2 is_master_triggered_~__retres1~0#1 := 0; 1217610#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1218446#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1217817#L1485 assume !(0 != activate_threads_~tmp~1#1); 1217818#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1218992#L605 assume !(1 == ~t1_pc~0); 1218461#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1218195#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1218196#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1218886#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 1218807#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1218102#L624 assume !(1 == ~t2_pc~0); 1218103#L624-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1218283#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1217845#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1217846#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 1219035#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1218885#L643 assume !(1 == ~t3_pc~0); 1218720#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1218410#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1218411#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1217927#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 1217928#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1217683#L662 assume !(1 == ~t4_pc~0); 1217684#L662-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1217642#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1217511#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1217512#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 1217537#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1217538#L681 assume !(1 == ~t5_pc~0); 1217410#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1217411#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1218487#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1219193#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 1217939#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1217940#L700 assume !(1 == ~t6_pc~0); 1217762#L700-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1217674#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1217675#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1217721#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 1217722#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1219098#L719 assume !(1 == ~t7_pc~0); 1217893#L719-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1217894#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1219368#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1219270#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 1217424#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1217425#L738 assume !(1 == ~t8_pc~0); 1218848#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1218741#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1218742#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1218517#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1218518#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1218910#L757 assume 1 == ~t9_pc~0; 1218911#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1217419#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1217420#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1217892#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 1218479#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1218480#L776 assume !(1 == ~t10_pc~0); 1217441#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1217440#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1217821#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1217663#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 1217664#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1217621#L795 assume 1 == ~t11_pc~0; 1217622#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1217959#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1219011#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1219227#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 1218714#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1218699#L814 assume !(1 == ~t12_pc~0); 1218547#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1218548#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1217470#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1217471#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 1217876#L1581-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1217877#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 1219050#L1332-2 assume !(1 == ~T1_E~0); 1219322#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1218623#L1342-1 assume !(1 == ~T3_E~0); 1218624#L1347-1 assume !(1 == ~T4_E~0); 1219086#L1352-1 assume !(1 == ~T5_E~0); 1218917#L1357-1 assume !(1 == ~T6_E~0); 1218163#L1362-1 assume !(1 == ~T7_E~0); 1218164#L1367-1 assume !(1 == ~T8_E~0); 1217758#L1372-1 assume !(1 == ~T9_E~0); 1217759#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1218073#L1382-1 assume !(1 == ~T11_E~0); 1218074#L1387-1 assume !(1 == ~T12_E~0); 1218804#L1392-1 assume !(1 == ~E_M~0); 1218104#L1397-1 assume !(1 == ~E_1~0); 1218105#L1402-1 assume !(1 == ~E_2~0); 1217773#L1407-1 assume !(1 == ~E_3~0); 1217774#L1412-1 assume !(1 == ~E_4~0); 1219009#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1219010#L1422-1 assume !(1 == ~E_6~0); 1219323#L1427-1 assume !(1 == ~E_7~0); 1217960#L1432-1 assume !(1 == ~E_8~0); 1217961#L1437-1 assume !(1 == ~E_9~0); 1218951#L1442-1 assume !(1 == ~E_10~0); 1218952#L1447-1 assume !(1 == ~E_11~0); 1218794#L1452-1 assume !(1 == ~E_12~0); 1217565#L1457-1 assume { :end_inline_reset_delta_events } true; 1217566#L1803-2 [2024-11-13 15:57:46,824 INFO L747 eck$LassoCheckResult]: Loop: 1217566#L1803-2 assume !false; 1357504#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1357499#L1169-1 assume !false; 1357497#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1357484#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1357473#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1357471#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1357469#L996 assume !(0 != eval_~tmp~0#1); 1357470#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1357827#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1357825#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1357823#L1194-5 assume !(0 == ~T1_E~0); 1357821#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1357819#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1357817#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1357815#L1214-3 assume !(0 == ~T5_E~0); 1357813#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1357811#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1357808#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1357806#L1234-3 assume !(0 == ~T9_E~0); 1357804#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1357802#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1357800#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1357798#L1254-3 assume !(0 == ~E_M~0); 1357795#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1357793#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1357791#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1357789#L1274-3 assume !(0 == ~E_4~0); 1357787#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1357785#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1357782#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1357780#L1294-3 assume !(0 == ~E_8~0); 1357778#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1357776#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1357774#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1357772#L1314-3 assume !(0 == ~E_12~0); 1357769#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1357767#L586-42 assume !(1 == ~m_pc~0); 1357765#L586-44 is_master_triggered_~__retres1~0#1 := 0; 1357763#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1357761#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1357759#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 1357756#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1357754#L605-42 assume !(1 == ~t1_pc~0); 1357750#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1357748#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1357746#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1357744#L1493-42 assume !(0 != activate_threads_~tmp___0~0#1); 1357741#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1357739#L624-42 assume !(1 == ~t2_pc~0); 1357737#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1357735#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1357733#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1357731#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1357729#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1357727#L643-42 assume !(1 == ~t3_pc~0); 1357725#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1357723#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1357721#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1357719#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1357717#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1357715#L662-42 assume !(1 == ~t4_pc~0); 1357713#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1357711#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1357709#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1357707#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1357705#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1357703#L681-42 assume 1 == ~t5_pc~0; 1357700#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1357698#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1357696#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1357694#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1357692#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1357691#L700-42 assume !(1 == ~t6_pc~0); 1357690#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1357689#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1357688#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1357687#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1357686#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1357685#L719-42 assume !(1 == ~t7_pc~0); 1357684#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1357683#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1357682#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1357681#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 1357680#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1357679#L738-42 assume 1 == ~t8_pc~0; 1357677#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1357676#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1357674#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1357673#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1357672#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1357671#L757-42 assume 1 == ~t9_pc~0; 1357669#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1357668#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1357667#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1357665#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1357663#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1357661#L776-42 assume 1 == ~t10_pc~0; 1357658#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1357656#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1357654#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1357650#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1357648#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1357646#L795-42 assume 1 == ~t11_pc~0; 1357644#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1357640#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1357638#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1357636#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1357634#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1357632#L814-42 assume 1 == ~t12_pc~0; 1357629#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1357627#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1357625#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1357623#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1357621#L1581-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1357619#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1330787#L1332-5 assume !(1 == ~T1_E~0); 1357616#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1357614#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1357612#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1357610#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1357608#L1357-3 assume !(1 == ~T6_E~0); 1357606#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1357604#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1357602#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1353540#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1357598#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1357596#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1357594#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1357592#L1397-3 assume !(1 == ~E_1~0); 1357590#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1357588#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1357586#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1346330#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1357583#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1357581#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1357579#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1357577#L1437-3 assume !(1 == ~E_9~0); 1357575#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1357573#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1357571#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1349025#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1357563#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1357550#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1357548#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1357546#L1822 assume !(0 == start_simulation_~tmp~3#1); 1357543#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1357527#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1357518#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1357516#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 1357514#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1357512#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1357509#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1357507#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 1217566#L1803-2 [2024-11-13 15:57:46,824 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:46,824 INFO L85 PathProgramCache]: Analyzing trace with hash -1728090755, now seen corresponding path program 1 times [2024-11-13 15:57:46,824 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:46,825 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [20417359] [2024-11-13 15:57:46,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:46,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:46,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:46,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:46,943 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:46,943 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [20417359] [2024-11-13 15:57:46,943 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [20417359] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:46,944 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:46,944 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:57:46,944 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1517930578] [2024-11-13 15:57:46,944 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:46,944 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:57:46,945 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:57:46,945 INFO L85 PathProgramCache]: Analyzing trace with hash 507576478, now seen corresponding path program 1 times [2024-11-13 15:57:46,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:57:46,945 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1307096589] [2024-11-13 15:57:46,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:57:46,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:57:46,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:57:47,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:57:47,013 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:57:47,013 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1307096589] [2024-11-13 15:57:47,013 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1307096589] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:57:47,013 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:57:47,013 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:57:47,013 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1879816542] [2024-11-13 15:57:47,013 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:57:47,014 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:57:47,014 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:57:47,014 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:57:47,014 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:57:47,015 INFO L87 Difference]: Start difference. First operand 448624 states and 634051 transitions. cyclomatic complexity: 185683 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:57:50,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:57:50,094 INFO L93 Difference]: Finished difference Result 460483 states and 645910 transitions. [2024-11-13 15:57:50,094 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 460483 states and 645910 transitions. [2024-11-13 15:57:52,902 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 458464 [2024-11-13 15:57:54,776 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 460483 states to 460483 states and 645910 transitions. [2024-11-13 15:57:54,777 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 460483 [2024-11-13 15:57:54,977 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 460483 [2024-11-13 15:57:54,977 INFO L73 IsDeterministic]: Start isDeterministic. Operand 460483 states and 645910 transitions. [2024-11-13 15:57:55,253 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:57:55,253 INFO L218 hiAutomatonCegarLoop]: Abstraction has 460483 states and 645910 transitions. [2024-11-13 15:57:55,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 460483 states and 645910 transitions.