./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.13.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_848854c3-9e5e-4d8e-b9df-1dc494732398/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_848854c3-9e5e-4d8e-b9df-1dc494732398/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_848854c3-9e5e-4d8e-b9df-1dc494732398/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_848854c3-9e5e-4d8e-b9df-1dc494732398/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.13.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_848854c3-9e5e-4d8e-b9df-1dc494732398/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_848854c3-9e5e-4d8e-b9df-1dc494732398/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0dcd4461cca64e9ab41b6ad7ff4c6eaa4177bddcca1c612fa1571b77ac664a95 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 12:54:33,549 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 12:54:33,645 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_848854c3-9e5e-4d8e-b9df-1dc494732398/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 12:54:33,654 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 12:54:33,654 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 12:54:33,692 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 12:54:33,694 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 12:54:33,694 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 12:54:33,695 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 12:54:33,695 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 12:54:33,697 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 12:54:33,697 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 12:54:33,697 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 12:54:33,698 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 12:54:33,698 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 12:54:33,699 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 12:54:33,699 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 12:54:33,699 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 12:54:33,699 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 12:54:33,699 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 12:54:33,699 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 12:54:33,699 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 12:54:33,700 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 12:54:33,700 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 12:54:33,700 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 12:54:33,700 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 12:54:33,700 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 12:54:33,700 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 12:54:33,700 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 12:54:33,700 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 12:54:33,701 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 12:54:33,701 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 12:54:33,701 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 12:54:33,701 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 12:54:33,701 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 12:54:33,701 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 12:54:33,701 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 12:54:33,701 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 12:54:33,702 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 12:54:33,702 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_848854c3-9e5e-4d8e-b9df-1dc494732398/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0dcd4461cca64e9ab41b6ad7ff4c6eaa4177bddcca1c612fa1571b77ac664a95 [2024-11-13 12:54:34,049 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 12:54:34,064 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 12:54:34,067 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 12:54:34,068 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 12:54:34,069 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 12:54:34,070 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_848854c3-9e5e-4d8e-b9df-1dc494732398/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/token_ring.13.cil-2.c Unable to find full path for "g++" [2024-11-13 12:54:36,009 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 12:54:36,317 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 12:54:36,318 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_848854c3-9e5e-4d8e-b9df-1dc494732398/sv-benchmarks/c/systemc/token_ring.13.cil-2.c [2024-11-13 12:54:36,335 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_848854c3-9e5e-4d8e-b9df-1dc494732398/bin/uautomizer-verify-qhAvR1uOyd/data/e27c46081/6e7f7793227848acbcc42bac1c256082/FLAG44410b773 [2024-11-13 12:54:36,351 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_848854c3-9e5e-4d8e-b9df-1dc494732398/bin/uautomizer-verify-qhAvR1uOyd/data/e27c46081/6e7f7793227848acbcc42bac1c256082 [2024-11-13 12:54:36,358 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 12:54:36,359 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 12:54:36,363 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 12:54:36,363 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 12:54:36,368 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 12:54:36,369 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 12:54:36" (1/1) ... [2024-11-13 12:54:36,371 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@e56aace and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:54:36, skipping insertion in model container [2024-11-13 12:54:36,374 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 12:54:36" (1/1) ... [2024-11-13 12:54:36,431 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 12:54:36,813 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 12:54:36,831 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 12:54:36,945 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 12:54:36,971 INFO L204 MainTranslator]: Completed translation [2024-11-13 12:54:36,971 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:54:36 WrapperNode [2024-11-13 12:54:36,972 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 12:54:36,973 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 12:54:36,973 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 12:54:36,973 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 12:54:36,979 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:54:36" (1/1) ... [2024-11-13 12:54:36,995 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:54:36" (1/1) ... [2024-11-13 12:54:37,144 INFO L138 Inliner]: procedures = 54, calls = 71, calls flagged for inlining = 66, calls inlined = 303, statements flattened = 4666 [2024-11-13 12:54:37,144 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 12:54:37,145 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 12:54:37,145 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 12:54:37,145 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 12:54:37,155 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:54:36" (1/1) ... [2024-11-13 12:54:37,156 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:54:36" (1/1) ... [2024-11-13 12:54:37,167 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:54:36" (1/1) ... [2024-11-13 12:54:37,205 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 12:54:37,205 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:54:36" (1/1) ... [2024-11-13 12:54:37,206 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:54:36" (1/1) ... [2024-11-13 12:54:37,272 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:54:36" (1/1) ... [2024-11-13 12:54:37,312 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:54:36" (1/1) ... [2024-11-13 12:54:37,319 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:54:36" (1/1) ... [2024-11-13 12:54:37,328 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:54:36" (1/1) ... [2024-11-13 12:54:37,351 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 12:54:37,352 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 12:54:37,352 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 12:54:37,352 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 12:54:37,353 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:54:36" (1/1) ... [2024-11-13 12:54:37,367 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:54:37,379 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_848854c3-9e5e-4d8e-b9df-1dc494732398/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:54:37,393 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_848854c3-9e5e-4d8e-b9df-1dc494732398/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:54:37,441 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_848854c3-9e5e-4d8e-b9df-1dc494732398/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 12:54:37,469 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 12:54:37,469 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 12:54:37,470 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 12:54:37,470 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 12:54:37,638 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 12:54:37,640 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 12:54:41,880 INFO L? ?]: Removed 1004 outVars from TransFormulas that were not future-live. [2024-11-13 12:54:41,881 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 12:54:41,930 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 12:54:41,930 INFO L316 CfgBuilder]: Removed 16 assume(true) statements. [2024-11-13 12:54:41,931 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 12:54:41 BoogieIcfgContainer [2024-11-13 12:54:41,931 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 12:54:41,932 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 12:54:41,932 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 12:54:41,937 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 12:54:41,938 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 12:54:41,938 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 12:54:36" (1/3) ... [2024-11-13 12:54:41,939 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4bdc341 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 12:54:41, skipping insertion in model container [2024-11-13 12:54:41,939 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 12:54:41,939 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:54:36" (2/3) ... [2024-11-13 12:54:41,940 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4bdc341 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 12:54:41, skipping insertion in model container [2024-11-13 12:54:41,940 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 12:54:41,940 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 12:54:41" (3/3) ... [2024-11-13 12:54:41,944 INFO L333 chiAutomizerObserver]: Analyzing ICFG token_ring.13.cil-2.c [2024-11-13 12:54:42,030 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 12:54:42,030 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 12:54:42,031 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 12:54:42,031 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 12:54:42,031 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 12:54:42,031 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 12:54:42,031 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 12:54:42,031 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 12:54:42,045 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2039 states, 2038 states have (on average 1.4921491658488715) internal successors, (3041), 2038 states have internal predecessors, (3041), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:42,158 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2024-11-13 12:54:42,159 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:42,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:42,173 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:42,175 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:42,175 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 12:54:42,181 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2039 states, 2038 states have (on average 1.4921491658488715) internal successors, (3041), 2038 states have internal predecessors, (3041), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:42,223 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2024-11-13 12:54:42,225 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:42,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:42,234 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:42,236 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:42,250 INFO L745 eck$LassoCheckResult]: Stem: 154#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1954#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 758#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1947#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1875#L902true assume !(1 == ~m_i~0);~m_st~0 := 2; 471#L902-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1625#L907-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 514#L912-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1555#L917-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 840#L922-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 994#L927-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 494#L932-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 379#L937-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1485#L942-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 668#L947-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1544#L952-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 586#L957-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 915#L962-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 364#L967-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1972#L1279true assume 0 == ~M_E~0;~M_E~0 := 1; 1556#L1279-2true assume !(0 == ~T1_E~0); 164#L1284-1true assume !(0 == ~T2_E~0); 1785#L1289-1true assume !(0 == ~T3_E~0); 583#L1294-1true assume !(0 == ~T4_E~0); 591#L1299-1true assume !(0 == ~T5_E~0); 1865#L1304-1true assume !(0 == ~T6_E~0); 1912#L1309-1true assume !(0 == ~T7_E~0); 1881#L1314-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 126#L1319-1true assume !(0 == ~T9_E~0); 1114#L1324-1true assume !(0 == ~T10_E~0); 214#L1329-1true assume !(0 == ~T11_E~0); 1377#L1334-1true assume !(0 == ~T12_E~0); 1814#L1339-1true assume !(0 == ~T13_E~0); 1534#L1344-1true assume !(0 == ~E_M~0); 1970#L1349-1true assume !(0 == ~E_1~0); 724#L1354-1true assume 0 == ~E_2~0;~E_2~0 := 1; 1119#L1359-1true assume !(0 == ~E_3~0); 1791#L1364-1true assume !(0 == ~E_4~0); 282#L1369-1true assume !(0 == ~E_5~0); 1093#L1374-1true assume !(0 == ~E_6~0); 729#L1379-1true assume !(0 == ~E_7~0); 791#L1384-1true assume !(0 == ~E_8~0); 2016#L1389-1true assume !(0 == ~E_9~0); 1412#L1394-1true assume 0 == ~E_10~0;~E_10~0 := 1; 1880#L1399-1true assume !(0 == ~E_11~0); 1643#L1404-1true assume !(0 == ~E_12~0); 334#L1409-1true assume !(0 == ~E_13~0); 1618#L1414-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1963#L628true assume !(1 == ~m_pc~0); 1420#L628-2true is_master_triggered_~__retres1~0#1 := 0; 944#L639true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 634#is_master_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1660#L1591true assume !(0 != activate_threads_~tmp~1#1); 1897#L1591-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 617#L647true assume 1 == ~t1_pc~0; 242#L648true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 654#L658true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1065#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1640#L1599true assume !(0 != activate_threads_~tmp___0~0#1); 1511#L1599-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1924#L666true assume 1 == ~t2_pc~0; 163#L667true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 249#L677true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 237#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1538#L1607true assume !(0 != activate_threads_~tmp___1~0#1); 883#L1607-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1866#L685true assume !(1 == ~t3_pc~0); 1034#L685-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1686#L696true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1045#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 765#L1615true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1070#L1615-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 409#L704true assume 1 == ~t4_pc~0; 1246#L705true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 776#L715true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1786#L1623true assume !(0 != activate_threads_~tmp___3~0#1); 653#L1623-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 762#L723true assume !(1 == ~t5_pc~0); 955#L723-2true is_transmit5_triggered_~__retres1~5#1 := 0; 1113#L734true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1654#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 866#L1631true assume !(0 != activate_threads_~tmp___4~0#1); 887#L1631-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 273#L742true assume 1 == ~t6_pc~0; 967#L743true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 358#L753true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 232#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 111#L1639true assume !(0 != activate_threads_~tmp___5~0#1); 1369#L1639-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 315#L761true assume !(1 == ~t7_pc~0); 323#L761-2true is_transmit7_triggered_~__retres1~7#1 := 0; 247#L772true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1967#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 767#L1647true assume !(0 != activate_threads_~tmp___6~0#1); 1565#L1647-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 122#L780true assume 1 == ~t8_pc~0; 592#L781true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 268#L791true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1606#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 736#L1655true assume !(0 != activate_threads_~tmp___7~0#1); 830#L1655-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1403#L799true assume 1 == ~t9_pc~0; 922#L800true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 123#L810true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 265#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1008#L1663true assume !(0 != activate_threads_~tmp___8~0#1); 1931#L1663-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 853#L818true assume !(1 == ~t10_pc~0); 25#L818-2true is_transmit10_triggered_~__retres1~10#1 := 0; 916#L829true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1385#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 856#L1671true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1099#L1671-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 892#L837true assume 1 == ~t11_pc~0; 1808#L838true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1584#L848true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1516#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 825#L1679true assume !(0 != activate_threads_~tmp___10~0#1); 1869#L1679-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 623#L856true assume !(1 == ~t12_pc~0); 1452#L856-2true is_transmit12_triggered_~__retres1~12#1 := 0; 1253#L867true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1224#L1687true assume !(0 != activate_threads_~tmp___11~0#1); 1800#L1687-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1562#L875true assume 1 == ~t13_pc~0; 589#L876true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 359#L886true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1439#is_transmit13_triggered_returnLabel#1true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 326#L1695true assume !(0 != activate_threads_~tmp___12~0#1); 914#L1695-2true havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1908#L1427true assume !(1 == ~M_E~0); 901#L1427-2true assume !(1 == ~T1_E~0); 308#L1432-1true assume !(1 == ~T2_E~0); 1566#L1437-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1129#L1442-1true assume !(1 == ~T4_E~0); 1494#L1447-1true assume !(1 == ~T5_E~0); 962#L1452-1true assume !(1 == ~T6_E~0); 87#L1457-1true assume !(1 == ~T7_E~0); 1158#L1462-1true assume !(1 == ~T8_E~0); 1852#L1467-1true assume !(1 == ~T9_E~0); 1185#L1472-1true assume !(1 == ~T10_E~0); 1381#L1477-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 912#L1482-1true assume !(1 == ~T12_E~0); 1304#L1487-1true assume !(1 == ~T13_E~0); 254#L1492-1true assume !(1 == ~E_M~0); 666#L1497-1true assume !(1 == ~E_1~0); 459#L1502-1true assume !(1 == ~E_2~0); 1303#L1507-1true assume !(1 == ~E_3~0); 190#L1512-1true assume !(1 == ~E_4~0); 1280#L1517-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1398#L1522-1true assume !(1 == ~E_6~0); 615#L1527-1true assume !(1 == ~E_7~0); 1765#L1532-1true assume !(1 == ~E_8~0); 2028#L1537-1true assume !(1 == ~E_9~0); 781#L1542-1true assume !(1 == ~E_10~0); 638#L1547-1true assume !(1 == ~E_11~0); 1796#L1552-1true assume !(1 == ~E_12~0); 44#L1557-1true assume 1 == ~E_13~0;~E_13~0 := 2; 352#L1562-1true assume { :end_inline_reset_delta_events } true; 759#L1928-2true [2024-11-13 12:54:42,257 INFO L747 eck$LassoCheckResult]: Loop: 759#L1928-2true assume !false; 663#L1929true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 533#L1254-1true assume false; 577#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 338#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1610#L1279-3true assume 0 == ~M_E~0;~M_E~0 := 1; 472#L1279-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 461#L1284-3true assume !(0 == ~T2_E~0); 1665#L1289-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 451#L1294-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1903#L1299-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 721#L1304-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1146#L1309-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 383#L1314-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1984#L1319-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1212#L1324-3true assume !(0 == ~T10_E~0); 189#L1329-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1834#L1334-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 644#L1339-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 938#L1344-3true assume 0 == ~E_M~0;~E_M~0 := 1; 889#L1349-3true assume 0 == ~E_1~0;~E_1~0 := 1; 373#L1354-3true assume 0 == ~E_2~0;~E_2~0 := 1; 898#L1359-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1863#L1364-3true assume !(0 == ~E_4~0); 1750#L1369-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1443#L1374-3true assume 0 == ~E_6~0;~E_6~0 := 1; 256#L1379-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1310#L1384-3true assume 0 == ~E_8~0;~E_8~0 := 1; 372#L1389-3true assume 0 == ~E_9~0;~E_9~0 := 1; 555#L1394-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1957#L1399-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1474#L1404-3true assume !(0 == ~E_12~0); 1397#L1409-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1554#L1414-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 801#L628-45true assume 1 == ~m_pc~0; 553#L629-15true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1744#L639-15true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 971#is_master_triggered_returnLabel#16true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 393#L1591-45true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1667#L1591-47true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 921#L647-45true assume !(1 == ~t1_pc~0); 1404#L647-47true is_transmit1_triggered_~__retres1~1#1 := 0; 735#L658-15true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1867#is_transmit1_triggered_returnLabel#16true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 218#L1599-45true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1552#L1599-47true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 331#L666-45true assume !(1 == ~t2_pc~0); 630#L666-47true is_transmit2_triggered_~__retres1~2#1 := 0; 1693#L677-15true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 968#is_transmit2_triggered_returnLabel#16true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1023#L1607-45true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1019#L1607-47true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96#L685-45true assume 1 == ~t3_pc~0; 730#L686-15true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1537#L696-15true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1990#is_transmit3_triggered_returnLabel#16true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1275#L1615-45true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1558#L1615-47true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1639#L704-45true assume 1 == ~t4_pc~0; 1316#L705-15true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 492#L715-15true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1317#is_transmit4_triggered_returnLabel#16true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2031#L1623-45true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1993#L1623-47true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 827#L723-45true assume 1 == ~t5_pc~0; 1827#L724-15true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1706#L734-15true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1983#is_transmit5_triggered_returnLabel#16true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 381#L1631-45true assume !(0 != activate_threads_~tmp___4~0#1); 1937#L1631-47true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1235#L742-45true assume 1 == ~t6_pc~0; 1845#L743-15true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 897#L753-15true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 685#is_transmit6_triggered_returnLabel#16true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 926#L1639-45true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1279#L1639-47true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 999#L761-45true assume !(1 == ~t7_pc~0); 1167#L761-47true is_transmit7_triggered_~__retres1~7#1 := 0; 535#L772-15true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 755#is_transmit7_triggered_returnLabel#16true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 192#L1647-45true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1962#L1647-47true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1401#L780-45true assume 1 == ~t8_pc~0; 396#L781-15true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 197#L791-15true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1736#is_transmit8_triggered_returnLabel#16true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1764#L1655-45true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 180#L1655-47true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 642#L799-45true assume !(1 == ~t9_pc~0); 298#L799-47true is_transmit9_triggered_~__retres1~9#1 := 0; 2022#L810-15true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1091#is_transmit9_triggered_returnLabel#16true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 963#L1663-45true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1828#L1663-47true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 152#L818-45true assume 1 == ~t10_pc~0; 1064#L819-15true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 943#L829-15true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1203#is_transmit10_triggered_returnLabel#16true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 491#L1671-45true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1056#L1671-47true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1530#L837-45true assume 1 == ~t11_pc~0; 1771#L838-15true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 536#L848-15true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 188#is_transmit11_triggered_returnLabel#16true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1856#L1679-45true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 224#L1679-47true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2040#L856-45true assume 1 == ~t12_pc~0; 1549#L857-15true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1274#L867-15true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1136#is_transmit12_triggered_returnLabel#16true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1810#L1687-45true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 734#L1687-47true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1282#L875-45true assume 1 == ~t13_pc~0; 709#L876-15true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 757#L886-15true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1079#is_transmit13_triggered_returnLabel#16true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1493#L1695-45true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1775#L1695-47true havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1374#L1427-3true assume !(1 == ~M_E~0); 580#L1427-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1567#L1432-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1006#L1437-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 723#L1442-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1024#L1447-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 51#L1452-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1992#L1457-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1259#L1462-3true assume !(1 == ~T8_E~0); 1681#L1467-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1073#L1472-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1714#L1477-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 173#L1482-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 246#L1487-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1820#L1492-3true assume 1 == ~E_M~0;~E_M~0 := 2; 337#L1497-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1027#L1502-3true assume !(1 == ~E_2~0); 1210#L1507-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1929#L1512-3true assume 1 == ~E_4~0;~E_4~0 := 2; 361#L1517-3true assume 1 == ~E_5~0;~E_5~0 := 2; 194#L1522-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1682#L1527-3true assume 1 == ~E_7~0;~E_7~0 := 2; 176#L1532-3true assume 1 == ~E_8~0;~E_8~0 := 2; 899#L1537-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1581#L1542-3true assume !(1 == ~E_10~0); 1011#L1547-3true assume 1 == ~E_11~0;~E_11~0 := 2; 710#L1552-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1406#L1557-3true assume 1 == ~E_13~0;~E_13~0 := 2; 285#L1562-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1981#L980-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1421#L1052-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 208#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 817#L1947true assume !(0 == start_simulation_~tmp~3#1); 987#L1947-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1134#L980-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1629#L1052-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 1461#L1902true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1173#L1909true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1411#stop_simulation_returnLabel#1true start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1720#L1960true assume !(0 != start_simulation_~tmp___0~1#1); 759#L1928-2true [2024-11-13 12:54:42,263 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:42,264 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 1 times [2024-11-13 12:54:42,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:42,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1721254895] [2024-11-13 12:54:42,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:42,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:42,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:42,725 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:42,725 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:42,725 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1721254895] [2024-11-13 12:54:42,726 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1721254895] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:42,726 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:42,727 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:42,728 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [617310224] [2024-11-13 12:54:42,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:42,733 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:42,735 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:42,735 INFO L85 PathProgramCache]: Analyzing trace with hash 2085382109, now seen corresponding path program 1 times [2024-11-13 12:54:42,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:42,735 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [686504289] [2024-11-13 12:54:42,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:42,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:42,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:42,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:42,853 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:42,854 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [686504289] [2024-11-13 12:54:42,854 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [686504289] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:42,854 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:42,854 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 12:54:42,854 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760619732] [2024-11-13 12:54:42,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:42,855 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:42,856 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:42,888 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-13 12:54:42,888 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-13 12:54:42,896 INFO L87 Difference]: Start difference. First operand has 2039 states, 2038 states have (on average 1.4921491658488715) internal successors, (3041), 2038 states have internal predecessors, (3041), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:42,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:43,000 INFO L93 Difference]: Finished difference Result 2037 states and 3006 transitions. [2024-11-13 12:54:43,007 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3006 transitions. [2024-11-13 12:54:43,034 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:43,062 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2032 states and 3001 transitions. [2024-11-13 12:54:43,064 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-13 12:54:43,067 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-13 12:54:43,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 3001 transitions. [2024-11-13 12:54:43,081 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:43,083 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 3001 transitions. [2024-11-13 12:54:43,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 3001 transitions. [2024-11-13 12:54:43,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-13 12:54:43,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4768700787401574) internal successors, (3001), 2031 states have internal predecessors, (3001), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:43,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 3001 transitions. [2024-11-13 12:54:43,217 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 3001 transitions. [2024-11-13 12:54:43,217 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-13 12:54:43,223 INFO L424 stractBuchiCegarLoop]: Abstraction has 2032 states and 3001 transitions. [2024-11-13 12:54:43,223 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 12:54:43,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 3001 transitions. [2024-11-13 12:54:43,237 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:43,238 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:43,238 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:43,245 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:43,246 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:43,247 INFO L745 eck$LassoCheckResult]: Stem: 4416#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4417#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5403#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5404#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6103#L902 assume !(1 == ~m_i~0);~m_st~0 := 2; 4997#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4998#L907-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 5068#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5069#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5506#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5507#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5032#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4837#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4838#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5296#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5297#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5176#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5177#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4811#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4812#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 6027#L1279-2 assume !(0 == ~T1_E~0); 4437#L1284-1 assume !(0 == ~T2_E~0); 4438#L1289-1 assume !(0 == ~T3_E~0); 5173#L1294-1 assume !(0 == ~T4_E~0); 5174#L1299-1 assume !(0 == ~T5_E~0); 5185#L1304-1 assume !(0 == ~T6_E~0); 6102#L1309-1 assume !(0 == ~T7_E~0); 6104#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4361#L1319-1 assume !(0 == ~T9_E~0); 4362#L1324-1 assume !(0 == ~T10_E~0); 4535#L1329-1 assume !(0 == ~T11_E~0); 4536#L1334-1 assume !(0 == ~T12_E~0); 5945#L1339-1 assume !(0 == ~T13_E~0); 6017#L1344-1 assume !(0 == ~E_M~0); 6018#L1349-1 assume !(0 == ~E_1~0); 5362#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5363#L1359-1 assume !(0 == ~E_3~0); 5770#L1364-1 assume !(0 == ~E_4~0); 4661#L1369-1 assume !(0 == ~E_5~0); 4662#L1374-1 assume !(0 == ~E_6~0); 5369#L1379-1 assume !(0 == ~E_7~0); 5370#L1384-1 assume !(0 == ~E_8~0); 5447#L1389-1 assume !(0 == ~E_9~0); 5964#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 5965#L1399-1 assume !(0 == ~E_11~0); 6058#L1404-1 assume !(0 == ~E_12~0); 4759#L1409-1 assume !(0 == ~E_13~0); 4760#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6053#L628 assume !(1 == ~m_pc~0); 4660#L628-2 is_master_triggered_~__retres1~0#1 := 0; 4659#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5244#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5245#L1591 assume !(0 != activate_threads_~tmp~1#1); 6066#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5225#L647 assume 1 == ~t1_pc~0; 4585#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4586#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5276#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5733#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 6005#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6006#L666 assume 1 == ~t2_pc~0; 4434#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4435#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4576#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4577#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 5558#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5559#L685 assume !(1 == ~t3_pc~0); 5653#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5652#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5722#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5411#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5412#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4885#L704 assume 1 == ~t4_pc~0; 4886#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5423#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4225#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4226#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 5274#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5275#L723 assume !(1 == ~t5_pc~0); 5407#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5625#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5763#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5537#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 5538#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4643#L742 assume 1 == ~t6_pc~0; 4644#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4800#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4567#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4330#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 4331#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4721#L761 assume !(1 == ~t7_pc~0); 4722#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4597#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4598#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5414#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 5415#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4353#L780 assume 1 == ~t8_pc~0; 4354#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4633#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4634#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5376#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 5377#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5493#L799 assume 1 == ~t9_pc~0; 5595#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4356#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4357#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4628#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 5696#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5519#L818 assume !(1 == ~t10_pc~0); 4140#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4141#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5588#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5522#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5523#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5565#L837 assume 1 == ~t11_pc~0; 5566#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 5401#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6009#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5486#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 5487#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5233#L856 assume !(1 == ~t12_pc~0); 5234#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 5868#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4158#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4159#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 5846#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 6030#L875 assume 1 == ~t13_pc~0; 5183#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4801#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4802#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4739#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 4740#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5587#L1427 assume !(1 == ~M_E~0); 5572#L1427-2 assume !(1 == ~T1_E~0); 4708#L1432-1 assume !(1 == ~T2_E~0); 4709#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5775#L1442-1 assume !(1 == ~T4_E~0); 5776#L1447-1 assume !(1 == ~T5_E~0); 5634#L1452-1 assume !(1 == ~T6_E~0); 4277#L1457-1 assume !(1 == ~T7_E~0); 4278#L1462-1 assume !(1 == ~T8_E~0); 5793#L1467-1 assume !(1 == ~T9_E~0); 5814#L1472-1 assume !(1 == ~T10_E~0); 5815#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5583#L1482-1 assume !(1 == ~T12_E~0); 5584#L1487-1 assume !(1 == ~T13_E~0); 4608#L1492-1 assume !(1 == ~E_M~0); 4609#L1497-1 assume !(1 == ~E_1~0); 4979#L1502-1 assume !(1 == ~E_2~0); 4980#L1507-1 assume !(1 == ~E_3~0); 4485#L1512-1 assume !(1 == ~E_4~0); 4486#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 5887#L1522-1 assume !(1 == ~E_6~0); 5222#L1527-1 assume !(1 == ~E_7~0); 5223#L1532-1 assume !(1 == ~E_8~0); 6088#L1537-1 assume !(1 == ~E_9~0); 5430#L1542-1 assume !(1 == ~E_10~0); 5251#L1547-1 assume !(1 == ~E_11~0); 5252#L1552-1 assume !(1 == ~E_12~0); 4181#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 4182#L1562-1 assume { :end_inline_reset_delta_events } true; 4791#L1928-2 [2024-11-13 12:54:43,248 INFO L747 eck$LassoCheckResult]: Loop: 4791#L1928-2 assume !false; 5289#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4866#L1254-1 assume !false; 5098#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4510#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4511#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4710#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5873#L1067 assume !(0 != eval_~tmp~0#1); 5163#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4768#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4769#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4999#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4983#L1284-3 assume !(0 == ~T2_E~0); 4984#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4964#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4965#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5357#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5358#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4845#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4846#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5836#L1324-3 assume !(0 == ~T10_E~0); 4483#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4484#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 5257#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 5258#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5562#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4829#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4830#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5570#L1364-3 assume !(0 == ~E_4~0); 6087#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5979#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4612#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4613#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4827#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4828#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 5134#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5989#L1404-3 assume !(0 == ~E_12~0); 5954#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5955#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5459#L628-45 assume 1 == ~m_pc~0; 5129#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5131#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5642#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4863#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4864#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5594#L647-45 assume !(1 == ~t1_pc~0); 4433#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 4432#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5375#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4541#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4542#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4752#L666-45 assume !(1 == ~t2_pc~0); 4753#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 5243#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5640#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5641#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5706#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4293#L685-45 assume 1 == ~t3_pc~0; 4294#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5371#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6019#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5885#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5886#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6028#L704-45 assume !(1 == ~t4_pc~0); 4160#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 4161#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5029#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5910#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6116#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5488#L723-45 assume !(1 == ~t5_pc~0); 5489#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 5966#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6078#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4841#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 4842#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5856#L742-45 assume 1 == ~t6_pc~0; 5857#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5106#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5316#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5317#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5599#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5685#L761-45 assume !(1 == ~t7_pc~0); 5686#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 5100#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5101#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4489#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4490#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5958#L780-45 assume 1 == ~t8_pc~0; 4867#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4500#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4501#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6085#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4469#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4470#L799-45 assume !(1 == ~t9_pc~0); 4688#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 4689#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5751#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5635#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5636#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4411#L818-45 assume 1 == ~t10_pc~0; 4412#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4529#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5612#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5027#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5028#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5731#L837-45 assume !(1 == ~t11_pc~0); 4957#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 4958#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4481#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4482#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4550#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4551#L856-45 assume !(1 == ~t12_pc~0); 4552#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 4553#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5782#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5783#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5373#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5374#L875-45 assume 1 == ~t13_pc~0; 5341#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5342#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5402#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5743#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 5999#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5943#L1427-3 assume !(1 == ~M_E~0); 5168#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5169#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5693#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5360#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5361#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4198#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4199#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5871#L1462-3 assume !(1 == ~T8_E~0); 5872#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5739#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5740#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4453#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4454#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4596#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4766#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4767#L1502-3 assume !(1 == ~E_2~0); 5713#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5834#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4805#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4493#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4494#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4460#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4461#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5571#L1542-3 assume !(1 == ~E_10~0); 5699#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 5344#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5345#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4664#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4665#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4086#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4523#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4524#L1947 assume !(0 == start_simulation_~tmp~3#1); 5477#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5667#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4725#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4148#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 4149#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5802#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5803#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 5963#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 4791#L1928-2 [2024-11-13 12:54:43,251 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:43,251 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 2 times [2024-11-13 12:54:43,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:43,251 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [129689795] [2024-11-13 12:54:43,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:43,252 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:43,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:43,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:43,414 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:43,414 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [129689795] [2024-11-13 12:54:43,414 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [129689795] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:43,414 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:43,414 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:43,415 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1379330123] [2024-11-13 12:54:43,415 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:43,415 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:43,415 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:43,416 INFO L85 PathProgramCache]: Analyzing trace with hash 741001488, now seen corresponding path program 1 times [2024-11-13 12:54:43,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:43,416 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1350136237] [2024-11-13 12:54:43,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:43,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:43,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:43,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:43,573 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:43,573 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1350136237] [2024-11-13 12:54:43,574 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1350136237] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:43,574 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:43,574 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:43,574 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1099873153] [2024-11-13 12:54:43,574 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:43,575 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:43,575 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:43,575 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:54:43,575 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:54:43,576 INFO L87 Difference]: Start difference. First operand 2032 states and 3001 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:43,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:43,656 INFO L93 Difference]: Finished difference Result 2032 states and 3000 transitions. [2024-11-13 12:54:43,657 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 3000 transitions. [2024-11-13 12:54:43,672 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:43,684 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 3000 transitions. [2024-11-13 12:54:43,685 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-13 12:54:43,687 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-13 12:54:43,687 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 3000 transitions. [2024-11-13 12:54:43,691 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:43,691 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 3000 transitions. [2024-11-13 12:54:43,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 3000 transitions. [2024-11-13 12:54:43,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-13 12:54:43,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4763779527559056) internal successors, (3000), 2031 states have internal predecessors, (3000), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:43,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 3000 transitions. [2024-11-13 12:54:43,756 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 3000 transitions. [2024-11-13 12:54:43,757 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:54:43,758 INFO L424 stractBuchiCegarLoop]: Abstraction has 2032 states and 3000 transitions. [2024-11-13 12:54:43,758 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 12:54:43,758 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 3000 transitions. [2024-11-13 12:54:43,771 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:43,772 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:43,772 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:43,776 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:43,778 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:43,779 INFO L745 eck$LassoCheckResult]: Stem: 8487#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 8488#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 9474#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9475#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10174#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 9068#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9069#L907-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 9139#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9140#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9577#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9578#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9103#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8908#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8909#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9367#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9368#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9247#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9248#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 8882#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8883#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 10098#L1279-2 assume !(0 == ~T1_E~0); 8508#L1284-1 assume !(0 == ~T2_E~0); 8509#L1289-1 assume !(0 == ~T3_E~0); 9244#L1294-1 assume !(0 == ~T4_E~0); 9245#L1299-1 assume !(0 == ~T5_E~0); 9256#L1304-1 assume !(0 == ~T6_E~0); 10173#L1309-1 assume !(0 == ~T7_E~0); 10175#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8432#L1319-1 assume !(0 == ~T9_E~0); 8433#L1324-1 assume !(0 == ~T10_E~0); 8606#L1329-1 assume !(0 == ~T11_E~0); 8607#L1334-1 assume !(0 == ~T12_E~0); 10016#L1339-1 assume !(0 == ~T13_E~0); 10088#L1344-1 assume !(0 == ~E_M~0); 10089#L1349-1 assume !(0 == ~E_1~0); 9433#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 9434#L1359-1 assume !(0 == ~E_3~0); 9841#L1364-1 assume !(0 == ~E_4~0); 8732#L1369-1 assume !(0 == ~E_5~0); 8733#L1374-1 assume !(0 == ~E_6~0); 9440#L1379-1 assume !(0 == ~E_7~0); 9441#L1384-1 assume !(0 == ~E_8~0); 9518#L1389-1 assume !(0 == ~E_9~0); 10035#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 10036#L1399-1 assume !(0 == ~E_11~0); 10129#L1404-1 assume !(0 == ~E_12~0); 8830#L1409-1 assume !(0 == ~E_13~0); 8831#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10124#L628 assume !(1 == ~m_pc~0); 8731#L628-2 is_master_triggered_~__retres1~0#1 := 0; 8730#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9315#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9316#L1591 assume !(0 != activate_threads_~tmp~1#1); 10137#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9296#L647 assume 1 == ~t1_pc~0; 8656#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8657#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9347#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9804#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 10076#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10077#L666 assume 1 == ~t2_pc~0; 8505#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8506#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8647#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8648#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 9629#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9630#L685 assume !(1 == ~t3_pc~0); 9724#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9723#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9793#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9482#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9483#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8956#L704 assume 1 == ~t4_pc~0; 8957#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9494#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8296#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8297#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 9345#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9346#L723 assume !(1 == ~t5_pc~0); 9478#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9696#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9834#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9608#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 9609#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8714#L742 assume 1 == ~t6_pc~0; 8715#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8871#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8638#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8401#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 8402#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8792#L761 assume !(1 == ~t7_pc~0); 8793#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8668#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8669#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9485#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 9486#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8424#L780 assume 1 == ~t8_pc~0; 8425#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8704#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8705#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9447#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 9448#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9564#L799 assume 1 == ~t9_pc~0; 9666#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8427#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8428#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8699#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 9767#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9590#L818 assume !(1 == ~t10_pc~0); 8211#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8212#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9659#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9593#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9594#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9636#L837 assume 1 == ~t11_pc~0; 9637#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9472#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10080#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9557#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 9558#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9304#L856 assume !(1 == ~t12_pc~0); 9305#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 9939#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8229#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8230#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 9917#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 10101#L875 assume 1 == ~t13_pc~0; 9254#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8872#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8873#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8810#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 8811#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9658#L1427 assume !(1 == ~M_E~0); 9643#L1427-2 assume !(1 == ~T1_E~0); 8779#L1432-1 assume !(1 == ~T2_E~0); 8780#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9846#L1442-1 assume !(1 == ~T4_E~0); 9847#L1447-1 assume !(1 == ~T5_E~0); 9705#L1452-1 assume !(1 == ~T6_E~0); 8348#L1457-1 assume !(1 == ~T7_E~0); 8349#L1462-1 assume !(1 == ~T8_E~0); 9864#L1467-1 assume !(1 == ~T9_E~0); 9885#L1472-1 assume !(1 == ~T10_E~0); 9886#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9654#L1482-1 assume !(1 == ~T12_E~0); 9655#L1487-1 assume !(1 == ~T13_E~0); 8679#L1492-1 assume !(1 == ~E_M~0); 8680#L1497-1 assume !(1 == ~E_1~0); 9050#L1502-1 assume !(1 == ~E_2~0); 9051#L1507-1 assume !(1 == ~E_3~0); 8556#L1512-1 assume !(1 == ~E_4~0); 8557#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 9958#L1522-1 assume !(1 == ~E_6~0); 9293#L1527-1 assume !(1 == ~E_7~0); 9294#L1532-1 assume !(1 == ~E_8~0); 10159#L1537-1 assume !(1 == ~E_9~0); 9501#L1542-1 assume !(1 == ~E_10~0); 9322#L1547-1 assume !(1 == ~E_11~0); 9323#L1552-1 assume !(1 == ~E_12~0); 8252#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 8253#L1562-1 assume { :end_inline_reset_delta_events } true; 8862#L1928-2 [2024-11-13 12:54:43,779 INFO L747 eck$LassoCheckResult]: Loop: 8862#L1928-2 assume !false; 9360#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8937#L1254-1 assume !false; 9169#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8581#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8582#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8781#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9944#L1067 assume !(0 != eval_~tmp~0#1); 9234#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8839#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8840#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9070#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9054#L1284-3 assume !(0 == ~T2_E~0); 9055#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9035#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9036#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9428#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9429#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8916#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8917#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9907#L1324-3 assume !(0 == ~T10_E~0); 8554#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8555#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 9328#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 9329#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9633#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8900#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8901#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9641#L1364-3 assume !(0 == ~E_4~0); 10158#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10050#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8683#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8684#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8898#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8899#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9205#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10060#L1404-3 assume !(0 == ~E_12~0); 10025#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 10026#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9530#L628-45 assume 1 == ~m_pc~0; 9200#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9202#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9713#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8934#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8935#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9665#L647-45 assume 1 == ~t1_pc~0; 8502#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8503#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9446#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8612#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8613#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8823#L666-45 assume !(1 == ~t2_pc~0); 8824#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 9314#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9711#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9712#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9777#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8364#L685-45 assume 1 == ~t3_pc~0; 8365#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9442#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10090#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9956#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9957#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10099#L704-45 assume !(1 == ~t4_pc~0); 8231#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 8232#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9100#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9981#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10187#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9559#L723-45 assume !(1 == ~t5_pc~0); 9560#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 10037#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10149#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8912#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 8913#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9927#L742-45 assume 1 == ~t6_pc~0; 9928#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9177#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9387#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9388#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9670#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9756#L761-45 assume !(1 == ~t7_pc~0); 9757#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 9171#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9172#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8560#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8561#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10029#L780-45 assume 1 == ~t8_pc~0; 8938#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8571#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8572#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10156#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8540#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8541#L799-45 assume !(1 == ~t9_pc~0); 8759#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 8760#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9822#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9706#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9707#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8482#L818-45 assume 1 == ~t10_pc~0; 8483#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8600#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9683#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9098#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9099#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9802#L837-45 assume !(1 == ~t11_pc~0); 9028#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 9029#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8552#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8553#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8621#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8622#L856-45 assume 1 == ~t12_pc~0; 10097#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8624#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 9853#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9854#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9444#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9445#L875-45 assume 1 == ~t13_pc~0; 9412#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9413#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9473#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9814#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 10070#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10014#L1427-3 assume !(1 == ~M_E~0); 9239#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9240#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9764#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9431#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9432#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8269#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8270#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9942#L1462-3 assume !(1 == ~T8_E~0); 9943#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9810#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9811#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8524#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8525#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 8667#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8837#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8838#L1502-3 assume !(1 == ~E_2~0); 9784#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9905#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8876#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8564#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8565#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8531#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8532#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9642#L1542-3 assume !(1 == ~E_10~0); 9770#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9415#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 9416#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 8735#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8736#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8157#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8594#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 8595#L1947 assume !(0 == start_simulation_~tmp~3#1); 9548#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9738#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8796#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8219#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 8220#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9873#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9874#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 10034#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 8862#L1928-2 [2024-11-13 12:54:43,780 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:43,780 INFO L85 PathProgramCache]: Analyzing trace with hash 1533490443, now seen corresponding path program 1 times [2024-11-13 12:54:43,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:43,780 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1819872089] [2024-11-13 12:54:43,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:43,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:43,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:43,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:43,925 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:43,925 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1819872089] [2024-11-13 12:54:43,926 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1819872089] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:43,926 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:43,926 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:43,926 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1057350625] [2024-11-13 12:54:43,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:43,926 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:43,927 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:43,927 INFO L85 PathProgramCache]: Analyzing trace with hash -1855091762, now seen corresponding path program 1 times [2024-11-13 12:54:43,927 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:43,927 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2081835551] [2024-11-13 12:54:43,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:43,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:44,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:44,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:44,156 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:44,156 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2081835551] [2024-11-13 12:54:44,156 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2081835551] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:44,156 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:44,156 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:44,157 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2037245472] [2024-11-13 12:54:44,157 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:44,157 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:44,157 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:44,157 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:54:44,157 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:54:44,158 INFO L87 Difference]: Start difference. First operand 2032 states and 3000 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:44,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:44,222 INFO L93 Difference]: Finished difference Result 2032 states and 2999 transitions. [2024-11-13 12:54:44,222 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2999 transitions. [2024-11-13 12:54:44,237 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:44,250 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2999 transitions. [2024-11-13 12:54:44,250 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-13 12:54:44,253 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-13 12:54:44,254 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2999 transitions. [2024-11-13 12:54:44,258 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:44,258 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2999 transitions. [2024-11-13 12:54:44,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2999 transitions. [2024-11-13 12:54:44,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-13 12:54:44,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4758858267716535) internal successors, (2999), 2031 states have internal predecessors, (2999), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:44,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2999 transitions. [2024-11-13 12:54:44,302 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2999 transitions. [2024-11-13 12:54:44,303 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:54:44,305 INFO L424 stractBuchiCegarLoop]: Abstraction has 2032 states and 2999 transitions. [2024-11-13 12:54:44,305 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 12:54:44,305 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2999 transitions. [2024-11-13 12:54:44,317 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:44,317 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:44,317 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:44,320 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:44,320 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:44,321 INFO L745 eck$LassoCheckResult]: Stem: 12558#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 12559#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 13545#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13546#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14245#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 13139#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13140#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13210#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 13211#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13648#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13649#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13174#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12979#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12980#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13438#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13439#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13318#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13319#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12953#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12954#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 14169#L1279-2 assume !(0 == ~T1_E~0); 12579#L1284-1 assume !(0 == ~T2_E~0); 12580#L1289-1 assume !(0 == ~T3_E~0); 13315#L1294-1 assume !(0 == ~T4_E~0); 13316#L1299-1 assume !(0 == ~T5_E~0); 13327#L1304-1 assume !(0 == ~T6_E~0); 14244#L1309-1 assume !(0 == ~T7_E~0); 14246#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12503#L1319-1 assume !(0 == ~T9_E~0); 12504#L1324-1 assume !(0 == ~T10_E~0); 12677#L1329-1 assume !(0 == ~T11_E~0); 12678#L1334-1 assume !(0 == ~T12_E~0); 14087#L1339-1 assume !(0 == ~T13_E~0); 14159#L1344-1 assume !(0 == ~E_M~0); 14160#L1349-1 assume !(0 == ~E_1~0); 13504#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 13505#L1359-1 assume !(0 == ~E_3~0); 13912#L1364-1 assume !(0 == ~E_4~0); 12803#L1369-1 assume !(0 == ~E_5~0); 12804#L1374-1 assume !(0 == ~E_6~0); 13511#L1379-1 assume !(0 == ~E_7~0); 13512#L1384-1 assume !(0 == ~E_8~0); 13589#L1389-1 assume !(0 == ~E_9~0); 14106#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 14107#L1399-1 assume !(0 == ~E_11~0); 14200#L1404-1 assume !(0 == ~E_12~0); 12901#L1409-1 assume !(0 == ~E_13~0); 12902#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14195#L628 assume !(1 == ~m_pc~0); 12802#L628-2 is_master_triggered_~__retres1~0#1 := 0; 12801#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13386#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13387#L1591 assume !(0 != activate_threads_~tmp~1#1); 14208#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13367#L647 assume 1 == ~t1_pc~0; 12727#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12728#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13418#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13875#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 14147#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14148#L666 assume 1 == ~t2_pc~0; 12576#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12577#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12718#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12719#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 13700#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13701#L685 assume !(1 == ~t3_pc~0); 13795#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13794#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13864#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13553#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13554#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13027#L704 assume 1 == ~t4_pc~0; 13028#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13565#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12367#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12368#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 13416#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13417#L723 assume !(1 == ~t5_pc~0); 13549#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13767#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13905#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13679#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 13680#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12785#L742 assume 1 == ~t6_pc~0; 12786#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12942#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12709#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12472#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 12473#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12863#L761 assume !(1 == ~t7_pc~0); 12864#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 12739#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12740#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13556#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 13557#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12495#L780 assume 1 == ~t8_pc~0; 12496#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12775#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12776#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13518#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 13519#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13635#L799 assume 1 == ~t9_pc~0; 13737#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12498#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12499#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12770#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 13838#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13661#L818 assume !(1 == ~t10_pc~0); 12282#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12283#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13730#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13664#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13665#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13707#L837 assume 1 == ~t11_pc~0; 13708#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13543#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14151#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13628#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 13629#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13375#L856 assume !(1 == ~t12_pc~0); 13376#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 14010#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12300#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12301#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 13988#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 14172#L875 assume 1 == ~t13_pc~0; 13325#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12943#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12944#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12881#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 12882#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13729#L1427 assume !(1 == ~M_E~0); 13714#L1427-2 assume !(1 == ~T1_E~0); 12850#L1432-1 assume !(1 == ~T2_E~0); 12851#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13917#L1442-1 assume !(1 == ~T4_E~0); 13918#L1447-1 assume !(1 == ~T5_E~0); 13776#L1452-1 assume !(1 == ~T6_E~0); 12419#L1457-1 assume !(1 == ~T7_E~0); 12420#L1462-1 assume !(1 == ~T8_E~0); 13935#L1467-1 assume !(1 == ~T9_E~0); 13956#L1472-1 assume !(1 == ~T10_E~0); 13957#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13725#L1482-1 assume !(1 == ~T12_E~0); 13726#L1487-1 assume !(1 == ~T13_E~0); 12750#L1492-1 assume !(1 == ~E_M~0); 12751#L1497-1 assume !(1 == ~E_1~0); 13121#L1502-1 assume !(1 == ~E_2~0); 13122#L1507-1 assume !(1 == ~E_3~0); 12627#L1512-1 assume !(1 == ~E_4~0); 12628#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14029#L1522-1 assume !(1 == ~E_6~0); 13364#L1527-1 assume !(1 == ~E_7~0); 13365#L1532-1 assume !(1 == ~E_8~0); 14230#L1537-1 assume !(1 == ~E_9~0); 13572#L1542-1 assume !(1 == ~E_10~0); 13393#L1547-1 assume !(1 == ~E_11~0); 13394#L1552-1 assume !(1 == ~E_12~0); 12323#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 12324#L1562-1 assume { :end_inline_reset_delta_events } true; 12933#L1928-2 [2024-11-13 12:54:44,321 INFO L747 eck$LassoCheckResult]: Loop: 12933#L1928-2 assume !false; 13431#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13008#L1254-1 assume !false; 13240#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12652#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12653#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12852#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14015#L1067 assume !(0 != eval_~tmp~0#1); 13305#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12910#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12911#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13141#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13125#L1284-3 assume !(0 == ~T2_E~0); 13126#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13106#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13107#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13499#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13500#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12987#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12988#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13978#L1324-3 assume !(0 == ~T10_E~0); 12625#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12626#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 13399#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 13400#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13704#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12971#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12972#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13712#L1364-3 assume !(0 == ~E_4~0); 14229#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14121#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12754#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12755#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12969#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12970#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 13276#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14131#L1404-3 assume !(0 == ~E_12~0); 14096#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 14097#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13601#L628-45 assume 1 == ~m_pc~0; 13271#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13273#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13784#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13005#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13006#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13736#L647-45 assume 1 == ~t1_pc~0; 12573#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12574#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13517#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12683#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12684#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12894#L666-45 assume 1 == ~t2_pc~0; 12896#L667-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13385#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13782#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13783#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13848#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12435#L685-45 assume 1 == ~t3_pc~0; 12436#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13513#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14161#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14027#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14028#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14170#L704-45 assume 1 == ~t4_pc~0; 14051#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12303#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13171#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14052#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14258#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13630#L723-45 assume 1 == ~t5_pc~0; 13632#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14108#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14220#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12983#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 12984#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13998#L742-45 assume 1 == ~t6_pc~0; 13999#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13248#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13458#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13459#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13741#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13827#L761-45 assume !(1 == ~t7_pc~0); 13828#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 13242#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13243#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12631#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12632#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14100#L780-45 assume 1 == ~t8_pc~0; 13009#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12642#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12643#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14227#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12611#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12612#L799-45 assume 1 == ~t9_pc~0; 13397#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12831#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13893#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13777#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13778#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12553#L818-45 assume 1 == ~t10_pc~0; 12554#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12671#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13754#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13169#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13170#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13873#L837-45 assume !(1 == ~t11_pc~0); 13099#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 13100#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12623#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12624#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12692#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12693#L856-45 assume !(1 == ~t12_pc~0); 12694#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 12695#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 13924#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13925#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13515#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13516#L875-45 assume 1 == ~t13_pc~0; 13483#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13484#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13544#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13885#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 14141#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14085#L1427-3 assume !(1 == ~M_E~0); 13310#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13311#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13835#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13502#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13503#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12340#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12341#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14013#L1462-3 assume !(1 == ~T8_E~0); 14014#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13881#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13882#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12595#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12596#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 12738#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12908#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12909#L1502-3 assume !(1 == ~E_2~0); 13855#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13976#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12947#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12635#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12636#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12602#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12603#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13713#L1542-3 assume !(1 == ~E_10~0); 13841#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13486#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 13487#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12806#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12807#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12228#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12665#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 12666#L1947 assume !(0 == start_simulation_~tmp~3#1); 13619#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13809#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12867#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12290#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 12291#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13944#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13945#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 14105#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 12933#L1928-2 [2024-11-13 12:54:44,322 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:44,322 INFO L85 PathProgramCache]: Analyzing trace with hash -992005239, now seen corresponding path program 1 times [2024-11-13 12:54:44,323 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:44,323 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1834367043] [2024-11-13 12:54:44,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:44,323 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:44,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:44,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:44,435 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:44,435 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1834367043] [2024-11-13 12:54:44,435 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1834367043] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:44,435 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:44,436 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:44,437 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1864901078] [2024-11-13 12:54:44,437 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:44,437 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:44,438 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:44,439 INFO L85 PathProgramCache]: Analyzing trace with hash -33106293, now seen corresponding path program 1 times [2024-11-13 12:54:44,439 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:44,439 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [573963908] [2024-11-13 12:54:44,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:44,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:44,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:44,580 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:44,581 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:44,581 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [573963908] [2024-11-13 12:54:44,582 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [573963908] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:44,582 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:44,582 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:44,582 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [786528793] [2024-11-13 12:54:44,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:44,583 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:44,584 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:44,584 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:54:44,584 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:54:44,584 INFO L87 Difference]: Start difference. First operand 2032 states and 2999 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:44,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:44,642 INFO L93 Difference]: Finished difference Result 2032 states and 2998 transitions. [2024-11-13 12:54:44,643 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2998 transitions. [2024-11-13 12:54:44,658 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:44,670 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2998 transitions. [2024-11-13 12:54:44,670 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-13 12:54:44,672 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-13 12:54:44,673 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2998 transitions. [2024-11-13 12:54:44,676 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:44,676 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2998 transitions. [2024-11-13 12:54:44,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2998 transitions. [2024-11-13 12:54:44,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-13 12:54:44,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4753937007874016) internal successors, (2998), 2031 states have internal predecessors, (2998), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:44,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2998 transitions. [2024-11-13 12:54:44,721 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2998 transitions. [2024-11-13 12:54:44,722 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:54:44,722 INFO L424 stractBuchiCegarLoop]: Abstraction has 2032 states and 2998 transitions. [2024-11-13 12:54:44,722 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 12:54:44,723 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2998 transitions. [2024-11-13 12:54:44,735 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:44,735 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:44,738 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:44,742 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:44,743 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:44,743 INFO L745 eck$LassoCheckResult]: Stem: 16629#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 16630#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 17616#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17617#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18316#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 17210#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17211#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17281#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17282#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 17719#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17720#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17245#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17050#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17051#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17509#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17510#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17389#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 17390#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 17024#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17025#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 18240#L1279-2 assume !(0 == ~T1_E~0); 16650#L1284-1 assume !(0 == ~T2_E~0); 16651#L1289-1 assume !(0 == ~T3_E~0); 17386#L1294-1 assume !(0 == ~T4_E~0); 17387#L1299-1 assume !(0 == ~T5_E~0); 17398#L1304-1 assume !(0 == ~T6_E~0); 18315#L1309-1 assume !(0 == ~T7_E~0); 18317#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16574#L1319-1 assume !(0 == ~T9_E~0); 16575#L1324-1 assume !(0 == ~T10_E~0); 16748#L1329-1 assume !(0 == ~T11_E~0); 16749#L1334-1 assume !(0 == ~T12_E~0); 18158#L1339-1 assume !(0 == ~T13_E~0); 18230#L1344-1 assume !(0 == ~E_M~0); 18231#L1349-1 assume !(0 == ~E_1~0); 17575#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 17576#L1359-1 assume !(0 == ~E_3~0); 17983#L1364-1 assume !(0 == ~E_4~0); 16874#L1369-1 assume !(0 == ~E_5~0); 16875#L1374-1 assume !(0 == ~E_6~0); 17582#L1379-1 assume !(0 == ~E_7~0); 17583#L1384-1 assume !(0 == ~E_8~0); 17660#L1389-1 assume !(0 == ~E_9~0); 18177#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 18178#L1399-1 assume !(0 == ~E_11~0); 18271#L1404-1 assume !(0 == ~E_12~0); 16972#L1409-1 assume !(0 == ~E_13~0); 16973#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18266#L628 assume !(1 == ~m_pc~0); 16873#L628-2 is_master_triggered_~__retres1~0#1 := 0; 16872#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17457#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17458#L1591 assume !(0 != activate_threads_~tmp~1#1); 18279#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17438#L647 assume 1 == ~t1_pc~0; 16798#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16799#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17489#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17946#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 18218#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18219#L666 assume 1 == ~t2_pc~0; 16647#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16648#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16789#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16790#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 17771#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17772#L685 assume !(1 == ~t3_pc~0); 17866#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17865#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17935#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17624#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17625#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17098#L704 assume 1 == ~t4_pc~0; 17099#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17636#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16438#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16439#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 17487#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17488#L723 assume !(1 == ~t5_pc~0); 17620#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17838#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17976#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17750#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 17751#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16856#L742 assume 1 == ~t6_pc~0; 16857#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17013#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16780#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16543#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 16544#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16934#L761 assume !(1 == ~t7_pc~0); 16935#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 16810#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16811#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17627#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 17628#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16566#L780 assume 1 == ~t8_pc~0; 16567#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16846#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16847#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17589#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 17590#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17706#L799 assume 1 == ~t9_pc~0; 17808#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16569#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16570#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16841#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 17909#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17732#L818 assume !(1 == ~t10_pc~0); 16353#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16354#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17801#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17735#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17736#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17778#L837 assume 1 == ~t11_pc~0; 17779#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17614#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18222#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17699#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 17700#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17446#L856 assume !(1 == ~t12_pc~0); 17447#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 18081#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16371#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16372#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 18059#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 18243#L875 assume 1 == ~t13_pc~0; 17396#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17014#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17015#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 16952#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 16953#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17800#L1427 assume !(1 == ~M_E~0); 17785#L1427-2 assume !(1 == ~T1_E~0); 16921#L1432-1 assume !(1 == ~T2_E~0); 16922#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17988#L1442-1 assume !(1 == ~T4_E~0); 17989#L1447-1 assume !(1 == ~T5_E~0); 17847#L1452-1 assume !(1 == ~T6_E~0); 16490#L1457-1 assume !(1 == ~T7_E~0); 16491#L1462-1 assume !(1 == ~T8_E~0); 18006#L1467-1 assume !(1 == ~T9_E~0); 18027#L1472-1 assume !(1 == ~T10_E~0); 18028#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17796#L1482-1 assume !(1 == ~T12_E~0); 17797#L1487-1 assume !(1 == ~T13_E~0); 16821#L1492-1 assume !(1 == ~E_M~0); 16822#L1497-1 assume !(1 == ~E_1~0); 17192#L1502-1 assume !(1 == ~E_2~0); 17193#L1507-1 assume !(1 == ~E_3~0); 16698#L1512-1 assume !(1 == ~E_4~0); 16699#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18100#L1522-1 assume !(1 == ~E_6~0); 17435#L1527-1 assume !(1 == ~E_7~0); 17436#L1532-1 assume !(1 == ~E_8~0); 18301#L1537-1 assume !(1 == ~E_9~0); 17643#L1542-1 assume !(1 == ~E_10~0); 17464#L1547-1 assume !(1 == ~E_11~0); 17465#L1552-1 assume !(1 == ~E_12~0); 16394#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 16395#L1562-1 assume { :end_inline_reset_delta_events } true; 17004#L1928-2 [2024-11-13 12:54:44,743 INFO L747 eck$LassoCheckResult]: Loop: 17004#L1928-2 assume !false; 17502#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17079#L1254-1 assume !false; 17311#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16723#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16724#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16923#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 18086#L1067 assume !(0 != eval_~tmp~0#1); 17376#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16981#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16982#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17212#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17196#L1284-3 assume !(0 == ~T2_E~0); 17197#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17177#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17178#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17570#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17571#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17058#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17059#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18049#L1324-3 assume !(0 == ~T10_E~0); 16696#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 16697#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 17470#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 17471#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17775#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17042#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17043#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17783#L1364-3 assume !(0 == ~E_4~0); 18300#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18192#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16825#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16826#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17040#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17041#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17347#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18202#L1404-3 assume !(0 == ~E_12~0); 18167#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 18168#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17672#L628-45 assume 1 == ~m_pc~0; 17342#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17344#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17855#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17076#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17077#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17807#L647-45 assume 1 == ~t1_pc~0; 16644#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16645#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17588#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16754#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16755#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16965#L666-45 assume !(1 == ~t2_pc~0); 16966#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 17456#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17853#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17854#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17919#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16506#L685-45 assume 1 == ~t3_pc~0; 16507#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17584#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18232#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18098#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18099#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18241#L704-45 assume !(1 == ~t4_pc~0); 16373#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 16374#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17242#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18123#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18329#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17701#L723-45 assume !(1 == ~t5_pc~0); 17702#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 18179#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18291#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17054#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 17055#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18069#L742-45 assume 1 == ~t6_pc~0; 18070#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17319#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17529#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17530#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17812#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17898#L761-45 assume !(1 == ~t7_pc~0); 17899#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 17313#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17314#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16702#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16703#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18171#L780-45 assume 1 == ~t8_pc~0; 17080#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16713#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16714#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18298#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16682#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16683#L799-45 assume !(1 == ~t9_pc~0); 16901#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 16902#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17964#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17848#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17849#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16624#L818-45 assume 1 == ~t10_pc~0; 16625#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16742#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17825#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17240#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17241#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17944#L837-45 assume !(1 == ~t11_pc~0); 17170#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 17171#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16694#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16695#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16763#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16764#L856-45 assume !(1 == ~t12_pc~0); 16765#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 16766#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17995#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17996#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17586#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 17587#L875-45 assume 1 == ~t13_pc~0; 17554#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17555#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17615#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17956#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 18212#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18156#L1427-3 assume !(1 == ~M_E~0); 17381#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17382#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17906#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17573#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17574#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16411#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16412#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18084#L1462-3 assume !(1 == ~T8_E~0); 18085#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17952#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17953#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16666#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16667#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 16809#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16979#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16980#L1502-3 assume !(1 == ~E_2~0); 17926#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18047#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17018#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16706#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16707#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16673#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16674#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17784#L1542-3 assume !(1 == ~E_10~0); 17912#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17557#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17558#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 16877#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16878#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16299#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16736#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 16737#L1947 assume !(0 == start_simulation_~tmp~3#1); 17690#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17880#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16938#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16361#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 16362#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18015#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18016#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 18176#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 17004#L1928-2 [2024-11-13 12:54:44,744 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:44,744 INFO L85 PathProgramCache]: Analyzing trace with hash -380736181, now seen corresponding path program 1 times [2024-11-13 12:54:44,744 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:44,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1034397273] [2024-11-13 12:54:44,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:44,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:44,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:44,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:44,821 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:44,821 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1034397273] [2024-11-13 12:54:44,821 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1034397273] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:44,821 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:44,821 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:44,821 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [721147959] [2024-11-13 12:54:44,821 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:44,822 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:44,822 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:44,822 INFO L85 PathProgramCache]: Analyzing trace with hash -2128870257, now seen corresponding path program 1 times [2024-11-13 12:54:44,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:44,822 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [838274538] [2024-11-13 12:54:44,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:44,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:44,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:44,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:44,923 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:44,923 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [838274538] [2024-11-13 12:54:44,923 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [838274538] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:44,923 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:44,924 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:44,925 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1366393145] [2024-11-13 12:54:44,925 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:44,925 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:44,925 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:44,926 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:54:44,926 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:54:44,926 INFO L87 Difference]: Start difference. First operand 2032 states and 2998 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:44,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:44,987 INFO L93 Difference]: Finished difference Result 2032 states and 2997 transitions. [2024-11-13 12:54:44,987 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2997 transitions. [2024-11-13 12:54:45,000 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:45,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2997 transitions. [2024-11-13 12:54:45,012 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-13 12:54:45,014 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-13 12:54:45,014 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2997 transitions. [2024-11-13 12:54:45,018 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:45,018 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2997 transitions. [2024-11-13 12:54:45,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2997 transitions. [2024-11-13 12:54:45,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-13 12:54:45,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4749015748031495) internal successors, (2997), 2031 states have internal predecessors, (2997), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:45,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2997 transitions. [2024-11-13 12:54:45,062 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2997 transitions. [2024-11-13 12:54:45,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:54:45,063 INFO L424 stractBuchiCegarLoop]: Abstraction has 2032 states and 2997 transitions. [2024-11-13 12:54:45,063 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 12:54:45,063 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2997 transitions. [2024-11-13 12:54:45,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:45,074 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:45,074 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:45,077 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:45,077 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:45,078 INFO L745 eck$LassoCheckResult]: Stem: 20700#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 20701#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 21687#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21688#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22387#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 21281#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21282#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21352#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21353#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21790#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 21791#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 21316#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 21121#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21122#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21580#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21581#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21460#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21461#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21095#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21096#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 22311#L1279-2 assume !(0 == ~T1_E~0); 20721#L1284-1 assume !(0 == ~T2_E~0); 20722#L1289-1 assume !(0 == ~T3_E~0); 21457#L1294-1 assume !(0 == ~T4_E~0); 21458#L1299-1 assume !(0 == ~T5_E~0); 21469#L1304-1 assume !(0 == ~T6_E~0); 22386#L1309-1 assume !(0 == ~T7_E~0); 22388#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20645#L1319-1 assume !(0 == ~T9_E~0); 20646#L1324-1 assume !(0 == ~T10_E~0); 20819#L1329-1 assume !(0 == ~T11_E~0); 20820#L1334-1 assume !(0 == ~T12_E~0); 22229#L1339-1 assume !(0 == ~T13_E~0); 22301#L1344-1 assume !(0 == ~E_M~0); 22302#L1349-1 assume !(0 == ~E_1~0); 21646#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 21647#L1359-1 assume !(0 == ~E_3~0); 22054#L1364-1 assume !(0 == ~E_4~0); 20945#L1369-1 assume !(0 == ~E_5~0); 20946#L1374-1 assume !(0 == ~E_6~0); 21653#L1379-1 assume !(0 == ~E_7~0); 21654#L1384-1 assume !(0 == ~E_8~0); 21731#L1389-1 assume !(0 == ~E_9~0); 22248#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 22249#L1399-1 assume !(0 == ~E_11~0); 22342#L1404-1 assume !(0 == ~E_12~0); 21043#L1409-1 assume !(0 == ~E_13~0); 21044#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22337#L628 assume !(1 == ~m_pc~0); 20944#L628-2 is_master_triggered_~__retres1~0#1 := 0; 20943#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21528#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21529#L1591 assume !(0 != activate_threads_~tmp~1#1); 22350#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21509#L647 assume 1 == ~t1_pc~0; 20869#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20870#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21560#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22017#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 22289#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22290#L666 assume 1 == ~t2_pc~0; 20718#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20719#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20860#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20861#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 21842#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21843#L685 assume !(1 == ~t3_pc~0); 21937#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21936#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22006#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21695#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21696#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21169#L704 assume 1 == ~t4_pc~0; 21170#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21707#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20509#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20510#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 21558#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21559#L723 assume !(1 == ~t5_pc~0); 21691#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21909#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22047#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21821#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 21822#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20927#L742 assume 1 == ~t6_pc~0; 20928#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21084#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20851#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20614#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 20615#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21005#L761 assume !(1 == ~t7_pc~0); 21006#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20881#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20882#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21698#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 21699#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20637#L780 assume 1 == ~t8_pc~0; 20638#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20917#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20918#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21660#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 21661#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21777#L799 assume 1 == ~t9_pc~0; 21879#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20640#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20641#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20912#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 21980#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21803#L818 assume !(1 == ~t10_pc~0); 20424#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20425#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21872#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21806#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21807#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21849#L837 assume 1 == ~t11_pc~0; 21850#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21685#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22293#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21770#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 21771#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21517#L856 assume !(1 == ~t12_pc~0); 21518#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22152#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20442#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20443#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 22130#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 22314#L875 assume 1 == ~t13_pc~0; 21467#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21085#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21086#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21023#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 21024#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21871#L1427 assume !(1 == ~M_E~0); 21856#L1427-2 assume !(1 == ~T1_E~0); 20992#L1432-1 assume !(1 == ~T2_E~0); 20993#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22059#L1442-1 assume !(1 == ~T4_E~0); 22060#L1447-1 assume !(1 == ~T5_E~0); 21918#L1452-1 assume !(1 == ~T6_E~0); 20561#L1457-1 assume !(1 == ~T7_E~0); 20562#L1462-1 assume !(1 == ~T8_E~0); 22077#L1467-1 assume !(1 == ~T9_E~0); 22098#L1472-1 assume !(1 == ~T10_E~0); 22099#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21867#L1482-1 assume !(1 == ~T12_E~0); 21868#L1487-1 assume !(1 == ~T13_E~0); 20892#L1492-1 assume !(1 == ~E_M~0); 20893#L1497-1 assume !(1 == ~E_1~0); 21263#L1502-1 assume !(1 == ~E_2~0); 21264#L1507-1 assume !(1 == ~E_3~0); 20769#L1512-1 assume !(1 == ~E_4~0); 20770#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22171#L1522-1 assume !(1 == ~E_6~0); 21506#L1527-1 assume !(1 == ~E_7~0); 21507#L1532-1 assume !(1 == ~E_8~0); 22372#L1537-1 assume !(1 == ~E_9~0); 21714#L1542-1 assume !(1 == ~E_10~0); 21535#L1547-1 assume !(1 == ~E_11~0); 21536#L1552-1 assume !(1 == ~E_12~0); 20465#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 20466#L1562-1 assume { :end_inline_reset_delta_events } true; 21075#L1928-2 [2024-11-13 12:54:45,078 INFO L747 eck$LassoCheckResult]: Loop: 21075#L1928-2 assume !false; 21573#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21150#L1254-1 assume !false; 21382#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20794#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20795#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20994#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22157#L1067 assume !(0 != eval_~tmp~0#1); 21447#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21052#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21053#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21283#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21267#L1284-3 assume !(0 == ~T2_E~0); 21268#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21248#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21249#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21641#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21642#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21129#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21130#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22120#L1324-3 assume !(0 == ~T10_E~0); 20767#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20768#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21541#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21542#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21846#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21113#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21114#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21854#L1364-3 assume !(0 == ~E_4~0); 22371#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22263#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20896#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20897#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 21111#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21112#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21418#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22273#L1404-3 assume !(0 == ~E_12~0); 22238#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 22239#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21743#L628-45 assume 1 == ~m_pc~0; 21413#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21415#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21926#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21147#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21148#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21878#L647-45 assume 1 == ~t1_pc~0; 20715#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20716#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21659#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20825#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20826#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21036#L666-45 assume !(1 == ~t2_pc~0); 21037#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 21527#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21924#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21925#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21990#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20577#L685-45 assume 1 == ~t3_pc~0; 20578#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21655#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22303#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22169#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22170#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22312#L704-45 assume 1 == ~t4_pc~0; 22193#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20445#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21313#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22194#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22400#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21772#L723-45 assume !(1 == ~t5_pc~0); 21773#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 22250#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22362#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21125#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 21126#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22140#L742-45 assume 1 == ~t6_pc~0; 22141#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21390#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21600#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21601#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21883#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21969#L761-45 assume !(1 == ~t7_pc~0); 21970#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 21384#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21385#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20773#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20774#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22242#L780-45 assume !(1 == ~t8_pc~0); 21152#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 20784#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20785#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22369#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20753#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20754#L799-45 assume 1 == ~t9_pc~0; 21539#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20973#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22035#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21919#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21920#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20695#L818-45 assume 1 == ~t10_pc~0; 20696#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20813#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21896#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21311#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21312#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22015#L837-45 assume !(1 == ~t11_pc~0); 21241#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 21242#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20765#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20766#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20834#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20835#L856-45 assume !(1 == ~t12_pc~0); 20836#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 20837#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 22066#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 22067#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 21657#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21658#L875-45 assume 1 == ~t13_pc~0; 21625#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21626#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21686#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22027#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 22283#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22227#L1427-3 assume !(1 == ~M_E~0); 21452#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21453#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21977#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21644#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21645#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20482#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20483#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22155#L1462-3 assume !(1 == ~T8_E~0); 22156#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22023#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22024#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20737#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20738#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 20880#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21050#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21051#L1502-3 assume !(1 == ~E_2~0); 21997#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22118#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21089#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20777#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20778#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20744#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20745#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21855#L1542-3 assume !(1 == ~E_10~0); 21983#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21628#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21629#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20948#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20949#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20370#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20807#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 20808#L1947 assume !(0 == start_simulation_~tmp~3#1); 21761#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21951#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 21009#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20432#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 20433#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22086#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22087#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 22247#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 21075#L1928-2 [2024-11-13 12:54:45,079 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:45,079 INFO L85 PathProgramCache]: Analyzing trace with hash 1024455497, now seen corresponding path program 1 times [2024-11-13 12:54:45,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:45,080 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192396000] [2024-11-13 12:54:45,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:45,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:45,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:45,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:45,159 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:45,161 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1192396000] [2024-11-13 12:54:45,161 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1192396000] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:45,161 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:45,161 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:45,161 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [890078257] [2024-11-13 12:54:45,161 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:45,162 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:45,164 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:45,164 INFO L85 PathProgramCache]: Analyzing trace with hash -985871090, now seen corresponding path program 1 times [2024-11-13 12:54:45,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:45,164 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1766894446] [2024-11-13 12:54:45,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:45,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:45,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:45,305 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:45,306 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:45,306 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1766894446] [2024-11-13 12:54:45,306 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1766894446] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:45,306 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:45,306 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:45,306 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1140835019] [2024-11-13 12:54:45,306 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:45,307 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:45,307 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:45,307 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:54:45,307 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:54:45,307 INFO L87 Difference]: Start difference. First operand 2032 states and 2997 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:45,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:45,360 INFO L93 Difference]: Finished difference Result 2032 states and 2996 transitions. [2024-11-13 12:54:45,360 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2996 transitions. [2024-11-13 12:54:45,375 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:45,385 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2996 transitions. [2024-11-13 12:54:45,386 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-13 12:54:45,388 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-13 12:54:45,388 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2996 transitions. [2024-11-13 12:54:45,392 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:45,392 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2996 transitions. [2024-11-13 12:54:45,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2996 transitions. [2024-11-13 12:54:45,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-13 12:54:45,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4744094488188977) internal successors, (2996), 2031 states have internal predecessors, (2996), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:45,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2996 transitions. [2024-11-13 12:54:45,437 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2996 transitions. [2024-11-13 12:54:45,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:54:45,438 INFO L424 stractBuchiCegarLoop]: Abstraction has 2032 states and 2996 transitions. [2024-11-13 12:54:45,438 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 12:54:45,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2996 transitions. [2024-11-13 12:54:45,450 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:45,450 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:45,451 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:45,453 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:45,453 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:45,454 INFO L745 eck$LassoCheckResult]: Stem: 24771#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 24772#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 25758#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25759#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26458#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 25352#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25353#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25423#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25424#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25861#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25862#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 25387#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25192#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25193#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25651#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25652#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25531#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25532#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 25166#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25167#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 26382#L1279-2 assume !(0 == ~T1_E~0); 24792#L1284-1 assume !(0 == ~T2_E~0); 24793#L1289-1 assume !(0 == ~T3_E~0); 25528#L1294-1 assume !(0 == ~T4_E~0); 25529#L1299-1 assume !(0 == ~T5_E~0); 25540#L1304-1 assume !(0 == ~T6_E~0); 26457#L1309-1 assume !(0 == ~T7_E~0); 26459#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24716#L1319-1 assume !(0 == ~T9_E~0); 24717#L1324-1 assume !(0 == ~T10_E~0); 24890#L1329-1 assume !(0 == ~T11_E~0); 24891#L1334-1 assume !(0 == ~T12_E~0); 26300#L1339-1 assume !(0 == ~T13_E~0); 26372#L1344-1 assume !(0 == ~E_M~0); 26373#L1349-1 assume !(0 == ~E_1~0); 25717#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 25718#L1359-1 assume !(0 == ~E_3~0); 26125#L1364-1 assume !(0 == ~E_4~0); 25016#L1369-1 assume !(0 == ~E_5~0); 25017#L1374-1 assume !(0 == ~E_6~0); 25724#L1379-1 assume !(0 == ~E_7~0); 25725#L1384-1 assume !(0 == ~E_8~0); 25802#L1389-1 assume !(0 == ~E_9~0); 26319#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 26320#L1399-1 assume !(0 == ~E_11~0); 26413#L1404-1 assume !(0 == ~E_12~0); 25114#L1409-1 assume !(0 == ~E_13~0); 25115#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26408#L628 assume !(1 == ~m_pc~0); 25015#L628-2 is_master_triggered_~__retres1~0#1 := 0; 25014#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25599#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25600#L1591 assume !(0 != activate_threads_~tmp~1#1); 26421#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25580#L647 assume 1 == ~t1_pc~0; 24940#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24941#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25631#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26088#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 26360#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26361#L666 assume 1 == ~t2_pc~0; 24789#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24790#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24931#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24932#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 25913#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25914#L685 assume !(1 == ~t3_pc~0); 26008#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26007#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26077#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25766#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25767#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25240#L704 assume 1 == ~t4_pc~0; 25241#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25778#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24580#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24581#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 25629#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25630#L723 assume !(1 == ~t5_pc~0); 25762#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25980#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26118#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25892#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 25893#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24998#L742 assume 1 == ~t6_pc~0; 24999#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25155#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24922#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24685#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 24686#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25076#L761 assume !(1 == ~t7_pc~0); 25077#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 24952#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24953#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25769#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 25770#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24708#L780 assume 1 == ~t8_pc~0; 24709#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24988#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24989#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25731#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 25732#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25848#L799 assume 1 == ~t9_pc~0; 25950#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24711#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24712#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24983#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 26051#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25874#L818 assume !(1 == ~t10_pc~0); 24495#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 24496#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25943#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25877#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25878#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25920#L837 assume 1 == ~t11_pc~0; 25921#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25756#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26364#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25841#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 25842#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25588#L856 assume !(1 == ~t12_pc~0); 25589#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 26223#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24513#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 24514#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 26201#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 26385#L875 assume 1 == ~t13_pc~0; 25538#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25156#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25157#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 25094#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 25095#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25942#L1427 assume !(1 == ~M_E~0); 25927#L1427-2 assume !(1 == ~T1_E~0); 25063#L1432-1 assume !(1 == ~T2_E~0); 25064#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26130#L1442-1 assume !(1 == ~T4_E~0); 26131#L1447-1 assume !(1 == ~T5_E~0); 25989#L1452-1 assume !(1 == ~T6_E~0); 24632#L1457-1 assume !(1 == ~T7_E~0); 24633#L1462-1 assume !(1 == ~T8_E~0); 26148#L1467-1 assume !(1 == ~T9_E~0); 26169#L1472-1 assume !(1 == ~T10_E~0); 26170#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25938#L1482-1 assume !(1 == ~T12_E~0); 25939#L1487-1 assume !(1 == ~T13_E~0); 24963#L1492-1 assume !(1 == ~E_M~0); 24964#L1497-1 assume !(1 == ~E_1~0); 25334#L1502-1 assume !(1 == ~E_2~0); 25335#L1507-1 assume !(1 == ~E_3~0); 24840#L1512-1 assume !(1 == ~E_4~0); 24841#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26242#L1522-1 assume !(1 == ~E_6~0); 25577#L1527-1 assume !(1 == ~E_7~0); 25578#L1532-1 assume !(1 == ~E_8~0); 26443#L1537-1 assume !(1 == ~E_9~0); 25785#L1542-1 assume !(1 == ~E_10~0); 25606#L1547-1 assume !(1 == ~E_11~0); 25607#L1552-1 assume !(1 == ~E_12~0); 24536#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 24537#L1562-1 assume { :end_inline_reset_delta_events } true; 25146#L1928-2 [2024-11-13 12:54:45,454 INFO L747 eck$LassoCheckResult]: Loop: 25146#L1928-2 assume !false; 25644#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25221#L1254-1 assume !false; 25453#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24865#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24866#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 25065#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 26228#L1067 assume !(0 != eval_~tmp~0#1); 25518#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25123#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25124#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25354#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25338#L1284-3 assume !(0 == ~T2_E~0); 25339#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25319#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25320#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25712#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25713#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25200#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25201#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26191#L1324-3 assume !(0 == ~T10_E~0); 24838#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24839#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25612#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25613#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25917#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25184#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25185#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25925#L1364-3 assume !(0 == ~E_4~0); 26442#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26334#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24967#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24968#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25182#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25183#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25489#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 26344#L1404-3 assume !(0 == ~E_12~0); 26309#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 26310#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25814#L628-45 assume 1 == ~m_pc~0; 25484#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25486#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25997#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25218#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25219#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25949#L647-45 assume 1 == ~t1_pc~0; 24786#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24787#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25730#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24896#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24897#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25107#L666-45 assume !(1 == ~t2_pc~0); 25108#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 25598#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25995#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25996#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26061#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24648#L685-45 assume 1 == ~t3_pc~0; 24649#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25726#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26374#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26240#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26241#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26383#L704-45 assume !(1 == ~t4_pc~0); 24515#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 24516#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25384#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26265#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26471#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25843#L723-45 assume !(1 == ~t5_pc~0); 25844#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 26321#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26433#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25196#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 25197#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26211#L742-45 assume 1 == ~t6_pc~0; 26212#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25461#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25671#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25672#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25954#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26040#L761-45 assume !(1 == ~t7_pc~0); 26041#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 25455#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25456#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24844#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24845#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26313#L780-45 assume 1 == ~t8_pc~0; 25222#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24855#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24856#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26440#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24824#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24825#L799-45 assume !(1 == ~t9_pc~0); 25043#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 25044#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26106#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25990#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25991#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24766#L818-45 assume !(1 == ~t10_pc~0); 24768#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 24884#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25967#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25382#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25383#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26086#L837-45 assume !(1 == ~t11_pc~0); 25312#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 25313#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24836#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24837#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24905#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24906#L856-45 assume !(1 == ~t12_pc~0); 24907#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 24908#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26137#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26138#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25728#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 25729#L875-45 assume 1 == ~t13_pc~0; 25696#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25697#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25757#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26098#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 26354#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26298#L1427-3 assume !(1 == ~M_E~0); 25523#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25524#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26048#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25715#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25716#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24553#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24554#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26226#L1462-3 assume !(1 == ~T8_E~0); 26227#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26094#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26095#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24808#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 24809#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 24951#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25121#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25122#L1502-3 assume !(1 == ~E_2~0); 26068#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26189#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25160#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24848#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24849#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24815#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24816#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25926#L1542-3 assume !(1 == ~E_10~0); 26054#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 25699#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 25700#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 25019#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25020#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24441#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24878#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 24879#L1947 assume !(0 == start_simulation_~tmp~3#1); 25832#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 26022#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 25080#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24503#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 24504#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26157#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26158#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 26318#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 25146#L1928-2 [2024-11-13 12:54:45,455 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:45,455 INFO L85 PathProgramCache]: Analyzing trace with hash -869878389, now seen corresponding path program 1 times [2024-11-13 12:54:45,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:45,455 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2112201252] [2024-11-13 12:54:45,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:45,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:45,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:45,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:45,552 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:45,552 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2112201252] [2024-11-13 12:54:45,553 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2112201252] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:45,553 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:45,553 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:45,553 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1420790279] [2024-11-13 12:54:45,553 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:45,553 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:45,554 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:45,554 INFO L85 PathProgramCache]: Analyzing trace with hash -1751227440, now seen corresponding path program 1 times [2024-11-13 12:54:45,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:45,554 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1710458928] [2024-11-13 12:54:45,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:45,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:45,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:45,676 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:45,677 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:45,677 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1710458928] [2024-11-13 12:54:45,677 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1710458928] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:45,677 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:45,677 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:45,677 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [152711344] [2024-11-13 12:54:45,677 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:45,678 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:45,678 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:45,678 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:54:45,678 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:54:45,679 INFO L87 Difference]: Start difference. First operand 2032 states and 2996 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:45,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:45,732 INFO L93 Difference]: Finished difference Result 2032 states and 2995 transitions. [2024-11-13 12:54:45,732 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2995 transitions. [2024-11-13 12:54:45,746 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:45,757 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2995 transitions. [2024-11-13 12:54:45,757 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-13 12:54:45,759 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-13 12:54:45,759 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2995 transitions. [2024-11-13 12:54:45,763 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:45,763 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2995 transitions. [2024-11-13 12:54:45,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2995 transitions. [2024-11-13 12:54:45,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-13 12:54:45,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4739173228346456) internal successors, (2995), 2031 states have internal predecessors, (2995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:45,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2995 transitions. [2024-11-13 12:54:45,807 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2995 transitions. [2024-11-13 12:54:45,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:54:45,810 INFO L424 stractBuchiCegarLoop]: Abstraction has 2032 states and 2995 transitions. [2024-11-13 12:54:45,811 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 12:54:45,811 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2995 transitions. [2024-11-13 12:54:45,821 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:45,821 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:45,821 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:45,824 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:45,824 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:45,825 INFO L745 eck$LassoCheckResult]: Stem: 28842#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 28843#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 29829#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29830#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30529#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 29423#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29424#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29494#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29495#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29932#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29933#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29458#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 29263#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29264#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29722#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29723#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29602#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29603#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29237#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29238#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 30453#L1279-2 assume !(0 == ~T1_E~0); 28863#L1284-1 assume !(0 == ~T2_E~0); 28864#L1289-1 assume !(0 == ~T3_E~0); 29599#L1294-1 assume !(0 == ~T4_E~0); 29600#L1299-1 assume !(0 == ~T5_E~0); 29611#L1304-1 assume !(0 == ~T6_E~0); 30528#L1309-1 assume !(0 == ~T7_E~0); 30530#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28787#L1319-1 assume !(0 == ~T9_E~0); 28788#L1324-1 assume !(0 == ~T10_E~0); 28961#L1329-1 assume !(0 == ~T11_E~0); 28962#L1334-1 assume !(0 == ~T12_E~0); 30371#L1339-1 assume !(0 == ~T13_E~0); 30443#L1344-1 assume !(0 == ~E_M~0); 30444#L1349-1 assume !(0 == ~E_1~0); 29788#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 29789#L1359-1 assume !(0 == ~E_3~0); 30196#L1364-1 assume !(0 == ~E_4~0); 29087#L1369-1 assume !(0 == ~E_5~0); 29088#L1374-1 assume !(0 == ~E_6~0); 29795#L1379-1 assume !(0 == ~E_7~0); 29796#L1384-1 assume !(0 == ~E_8~0); 29873#L1389-1 assume !(0 == ~E_9~0); 30390#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 30391#L1399-1 assume !(0 == ~E_11~0); 30484#L1404-1 assume !(0 == ~E_12~0); 29185#L1409-1 assume !(0 == ~E_13~0); 29186#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30479#L628 assume !(1 == ~m_pc~0); 29086#L628-2 is_master_triggered_~__retres1~0#1 := 0; 29085#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29670#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29671#L1591 assume !(0 != activate_threads_~tmp~1#1); 30492#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29651#L647 assume 1 == ~t1_pc~0; 29011#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29012#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29702#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30159#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 30431#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30432#L666 assume 1 == ~t2_pc~0; 28860#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28861#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29002#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29003#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 29984#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29985#L685 assume !(1 == ~t3_pc~0); 30079#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30078#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30148#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29837#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29838#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29311#L704 assume 1 == ~t4_pc~0; 29312#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29849#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28651#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28652#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 29700#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29701#L723 assume !(1 == ~t5_pc~0); 29833#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 30051#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30189#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29963#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 29964#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29069#L742 assume 1 == ~t6_pc~0; 29070#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29226#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28993#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28756#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 28757#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29147#L761 assume !(1 == ~t7_pc~0); 29148#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 29023#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29024#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29840#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 29841#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28779#L780 assume 1 == ~t8_pc~0; 28780#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29059#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29060#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29802#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 29803#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29919#L799 assume 1 == ~t9_pc~0; 30021#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28782#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28783#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29054#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 30122#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29945#L818 assume !(1 == ~t10_pc~0); 28566#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28567#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30014#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29948#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29949#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29991#L837 assume 1 == ~t11_pc~0; 29992#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29827#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30435#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29912#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 29913#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29659#L856 assume !(1 == ~t12_pc~0); 29660#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 30294#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28584#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28585#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 30272#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 30456#L875 assume 1 == ~t13_pc~0; 29609#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29227#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29228#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 29165#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 29166#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30013#L1427 assume !(1 == ~M_E~0); 29998#L1427-2 assume !(1 == ~T1_E~0); 29134#L1432-1 assume !(1 == ~T2_E~0); 29135#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30201#L1442-1 assume !(1 == ~T4_E~0); 30202#L1447-1 assume !(1 == ~T5_E~0); 30060#L1452-1 assume !(1 == ~T6_E~0); 28703#L1457-1 assume !(1 == ~T7_E~0); 28704#L1462-1 assume !(1 == ~T8_E~0); 30219#L1467-1 assume !(1 == ~T9_E~0); 30240#L1472-1 assume !(1 == ~T10_E~0); 30241#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 30009#L1482-1 assume !(1 == ~T12_E~0); 30010#L1487-1 assume !(1 == ~T13_E~0); 29034#L1492-1 assume !(1 == ~E_M~0); 29035#L1497-1 assume !(1 == ~E_1~0); 29405#L1502-1 assume !(1 == ~E_2~0); 29406#L1507-1 assume !(1 == ~E_3~0); 28911#L1512-1 assume !(1 == ~E_4~0); 28912#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30313#L1522-1 assume !(1 == ~E_6~0); 29648#L1527-1 assume !(1 == ~E_7~0); 29649#L1532-1 assume !(1 == ~E_8~0); 30514#L1537-1 assume !(1 == ~E_9~0); 29856#L1542-1 assume !(1 == ~E_10~0); 29677#L1547-1 assume !(1 == ~E_11~0); 29678#L1552-1 assume !(1 == ~E_12~0); 28607#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 28608#L1562-1 assume { :end_inline_reset_delta_events } true; 29217#L1928-2 [2024-11-13 12:54:45,825 INFO L747 eck$LassoCheckResult]: Loop: 29217#L1928-2 assume !false; 29715#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29292#L1254-1 assume !false; 29524#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28936#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28937#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29136#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30299#L1067 assume !(0 != eval_~tmp~0#1); 29589#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29194#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29195#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29425#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29409#L1284-3 assume !(0 == ~T2_E~0); 29410#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29390#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29391#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29783#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29784#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29271#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29272#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30262#L1324-3 assume !(0 == ~T10_E~0); 28909#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28910#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29683#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29684#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29988#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29255#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29256#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29996#L1364-3 assume !(0 == ~E_4~0); 30513#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30405#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29038#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29039#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29253#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29254#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29560#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 30415#L1404-3 assume !(0 == ~E_12~0); 30380#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 30381#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29885#L628-45 assume 1 == ~m_pc~0; 29555#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29557#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30068#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29289#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29290#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30020#L647-45 assume 1 == ~t1_pc~0; 28857#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28858#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29801#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28967#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28968#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29178#L666-45 assume !(1 == ~t2_pc~0); 29179#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 29669#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30066#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30067#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30132#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28719#L685-45 assume 1 == ~t3_pc~0; 28720#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29797#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30445#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30311#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30312#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30454#L704-45 assume !(1 == ~t4_pc~0); 28586#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 28587#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29455#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30336#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30542#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29914#L723-45 assume !(1 == ~t5_pc~0); 29915#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 30392#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30504#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29267#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 29268#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30282#L742-45 assume 1 == ~t6_pc~0; 30283#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29532#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29742#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29743#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30025#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30111#L761-45 assume !(1 == ~t7_pc~0); 30112#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 29526#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29527#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28915#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28916#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30384#L780-45 assume 1 == ~t8_pc~0; 29293#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28926#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28927#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30511#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28895#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28896#L799-45 assume 1 == ~t9_pc~0; 29681#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29115#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30177#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30061#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30062#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28837#L818-45 assume 1 == ~t10_pc~0; 28838#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28955#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30038#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29453#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29454#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30157#L837-45 assume !(1 == ~t11_pc~0); 29383#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 29384#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28907#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28908#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28976#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28977#L856-45 assume !(1 == ~t12_pc~0); 28978#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 28979#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30208#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30209#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29799#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29800#L875-45 assume 1 == ~t13_pc~0; 29767#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29768#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29828#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30169#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 30425#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30369#L1427-3 assume !(1 == ~M_E~0); 29594#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29595#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30119#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29786#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29787#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28624#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28625#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30297#L1462-3 assume !(1 == ~T8_E~0); 30298#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30165#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30166#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28879#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28880#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 29022#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29192#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29193#L1502-3 assume !(1 == ~E_2~0); 30139#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30260#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29231#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28919#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28920#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28886#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28887#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29997#L1542-3 assume !(1 == ~E_10~0); 30125#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29770#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 29771#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 29090#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29091#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28512#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28949#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 28950#L1947 assume !(0 == start_simulation_~tmp~3#1); 29903#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 30093#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 29151#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28574#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 28575#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30228#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30229#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 30389#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 29217#L1928-2 [2024-11-13 12:54:45,828 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:45,829 INFO L85 PathProgramCache]: Analyzing trace with hash 1978508041, now seen corresponding path program 1 times [2024-11-13 12:54:45,829 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:45,829 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [54696277] [2024-11-13 12:54:45,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:45,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:45,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:45,913 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:45,913 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:45,913 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [54696277] [2024-11-13 12:54:45,913 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [54696277] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:45,913 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:45,914 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:45,914 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1414649394] [2024-11-13 12:54:45,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:45,914 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:45,914 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:45,915 INFO L85 PathProgramCache]: Analyzing trace with hash -173549042, now seen corresponding path program 1 times [2024-11-13 12:54:45,915 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:45,915 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1664655773] [2024-11-13 12:54:45,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:45,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:45,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:46,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:46,011 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:46,011 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1664655773] [2024-11-13 12:54:46,012 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1664655773] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:46,013 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:46,013 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:46,013 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [26422559] [2024-11-13 12:54:46,013 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:46,013 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:46,013 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:46,014 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:54:46,014 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:54:46,014 INFO L87 Difference]: Start difference. First operand 2032 states and 2995 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:46,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:46,063 INFO L93 Difference]: Finished difference Result 2032 states and 2994 transitions. [2024-11-13 12:54:46,064 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2994 transitions. [2024-11-13 12:54:46,075 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:46,085 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2994 transitions. [2024-11-13 12:54:46,085 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-13 12:54:46,087 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-13 12:54:46,087 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2994 transitions. [2024-11-13 12:54:46,091 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:46,091 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2994 transitions. [2024-11-13 12:54:46,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2994 transitions. [2024-11-13 12:54:46,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-13 12:54:46,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4734251968503937) internal successors, (2994), 2031 states have internal predecessors, (2994), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:46,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2994 transitions. [2024-11-13 12:54:46,131 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2994 transitions. [2024-11-13 12:54:46,132 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:54:46,134 INFO L424 stractBuchiCegarLoop]: Abstraction has 2032 states and 2994 transitions. [2024-11-13 12:54:46,134 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 12:54:46,134 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2994 transitions. [2024-11-13 12:54:46,144 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:46,144 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:46,145 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:46,147 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:46,147 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:46,148 INFO L745 eck$LassoCheckResult]: Stem: 32913#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 32914#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 33900#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33901#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34600#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 33494#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33495#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33565#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33566#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34003#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34004#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33529#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33334#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 33335#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33793#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33794#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33673#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33674#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 33308#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33309#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 34524#L1279-2 assume !(0 == ~T1_E~0); 32934#L1284-1 assume !(0 == ~T2_E~0); 32935#L1289-1 assume !(0 == ~T3_E~0); 33670#L1294-1 assume !(0 == ~T4_E~0); 33671#L1299-1 assume !(0 == ~T5_E~0); 33682#L1304-1 assume !(0 == ~T6_E~0); 34599#L1309-1 assume !(0 == ~T7_E~0); 34601#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32858#L1319-1 assume !(0 == ~T9_E~0); 32859#L1324-1 assume !(0 == ~T10_E~0); 33032#L1329-1 assume !(0 == ~T11_E~0); 33033#L1334-1 assume !(0 == ~T12_E~0); 34442#L1339-1 assume !(0 == ~T13_E~0); 34514#L1344-1 assume !(0 == ~E_M~0); 34515#L1349-1 assume !(0 == ~E_1~0); 33859#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 33860#L1359-1 assume !(0 == ~E_3~0); 34267#L1364-1 assume !(0 == ~E_4~0); 33158#L1369-1 assume !(0 == ~E_5~0); 33159#L1374-1 assume !(0 == ~E_6~0); 33866#L1379-1 assume !(0 == ~E_7~0); 33867#L1384-1 assume !(0 == ~E_8~0); 33944#L1389-1 assume !(0 == ~E_9~0); 34461#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 34462#L1399-1 assume !(0 == ~E_11~0); 34555#L1404-1 assume !(0 == ~E_12~0); 33256#L1409-1 assume !(0 == ~E_13~0); 33257#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34550#L628 assume !(1 == ~m_pc~0); 33157#L628-2 is_master_triggered_~__retres1~0#1 := 0; 33156#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33741#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33742#L1591 assume !(0 != activate_threads_~tmp~1#1); 34563#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33722#L647 assume 1 == ~t1_pc~0; 33082#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33083#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33773#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34230#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 34502#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34503#L666 assume 1 == ~t2_pc~0; 32931#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32932#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33073#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33074#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 34055#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34056#L685 assume !(1 == ~t3_pc~0); 34150#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34149#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34219#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33908#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33909#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33382#L704 assume 1 == ~t4_pc~0; 33383#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33920#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32722#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32723#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 33771#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33772#L723 assume !(1 == ~t5_pc~0); 33904#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 34122#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34260#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34034#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 34035#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33140#L742 assume 1 == ~t6_pc~0; 33141#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33297#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33064#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32827#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 32828#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33218#L761 assume !(1 == ~t7_pc~0); 33219#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 33094#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33095#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33911#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 33912#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32850#L780 assume 1 == ~t8_pc~0; 32851#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33130#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33131#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33873#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 33874#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33990#L799 assume 1 == ~t9_pc~0; 34092#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32853#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32854#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33125#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 34193#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34016#L818 assume !(1 == ~t10_pc~0); 32637#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32638#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34085#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34019#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34020#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34062#L837 assume 1 == ~t11_pc~0; 34063#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33898#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34506#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33983#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 33984#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33730#L856 assume !(1 == ~t12_pc~0); 33731#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 34365#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32655#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32656#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 34343#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 34527#L875 assume 1 == ~t13_pc~0; 33680#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33298#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33299#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 33236#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 33237#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34084#L1427 assume !(1 == ~M_E~0); 34069#L1427-2 assume !(1 == ~T1_E~0); 33205#L1432-1 assume !(1 == ~T2_E~0); 33206#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34272#L1442-1 assume !(1 == ~T4_E~0); 34273#L1447-1 assume !(1 == ~T5_E~0); 34131#L1452-1 assume !(1 == ~T6_E~0); 32774#L1457-1 assume !(1 == ~T7_E~0); 32775#L1462-1 assume !(1 == ~T8_E~0); 34290#L1467-1 assume !(1 == ~T9_E~0); 34311#L1472-1 assume !(1 == ~T10_E~0); 34312#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34080#L1482-1 assume !(1 == ~T12_E~0); 34081#L1487-1 assume !(1 == ~T13_E~0); 33105#L1492-1 assume !(1 == ~E_M~0); 33106#L1497-1 assume !(1 == ~E_1~0); 33476#L1502-1 assume !(1 == ~E_2~0); 33477#L1507-1 assume !(1 == ~E_3~0); 32982#L1512-1 assume !(1 == ~E_4~0); 32983#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 34384#L1522-1 assume !(1 == ~E_6~0); 33719#L1527-1 assume !(1 == ~E_7~0); 33720#L1532-1 assume !(1 == ~E_8~0); 34585#L1537-1 assume !(1 == ~E_9~0); 33927#L1542-1 assume !(1 == ~E_10~0); 33748#L1547-1 assume !(1 == ~E_11~0); 33749#L1552-1 assume !(1 == ~E_12~0); 32678#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 32679#L1562-1 assume { :end_inline_reset_delta_events } true; 33288#L1928-2 [2024-11-13 12:54:46,148 INFO L747 eck$LassoCheckResult]: Loop: 33288#L1928-2 assume !false; 33786#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33363#L1254-1 assume !false; 33595#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33007#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 33008#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33207#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34370#L1067 assume !(0 != eval_~tmp~0#1); 33660#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33265#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33266#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33496#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33480#L1284-3 assume !(0 == ~T2_E~0); 33481#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33461#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33462#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33854#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33855#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33342#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33343#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34333#L1324-3 assume !(0 == ~T10_E~0); 32980#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32981#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 33754#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 33755#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 34059#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33326#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33327#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34067#L1364-3 assume !(0 == ~E_4~0); 34584#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34476#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33109#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33110#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33324#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33325#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 33631#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34486#L1404-3 assume !(0 == ~E_12~0); 34451#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 34452#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33956#L628-45 assume 1 == ~m_pc~0; 33626#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33628#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34139#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33360#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33361#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34091#L647-45 assume 1 == ~t1_pc~0; 32928#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32929#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33872#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33038#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33039#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33249#L666-45 assume !(1 == ~t2_pc~0); 33250#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 33740#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34137#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34138#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34203#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32790#L685-45 assume 1 == ~t3_pc~0; 32791#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33868#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34516#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34382#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34383#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34525#L704-45 assume !(1 == ~t4_pc~0); 32657#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 32658#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33526#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34407#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34613#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33985#L723-45 assume !(1 == ~t5_pc~0); 33986#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 34463#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34575#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33338#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 33339#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34353#L742-45 assume 1 == ~t6_pc~0; 34354#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33603#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33813#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33814#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34096#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34182#L761-45 assume !(1 == ~t7_pc~0); 34183#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 33597#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33598#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32986#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32987#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34455#L780-45 assume 1 == ~t8_pc~0; 33364#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32997#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32998#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34582#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32966#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32967#L799-45 assume !(1 == ~t9_pc~0); 33185#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 33186#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34248#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34132#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 34133#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32908#L818-45 assume 1 == ~t10_pc~0; 32909#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33026#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34109#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33524#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 33525#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34228#L837-45 assume 1 == ~t11_pc~0; 34512#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33455#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32978#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32979#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 33047#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33048#L856-45 assume !(1 == ~t12_pc~0); 33049#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 33050#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34279#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34280#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33870#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33871#L875-45 assume !(1 == ~t13_pc~0); 33840#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 33839#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33899#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34240#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 34496#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34440#L1427-3 assume !(1 == ~M_E~0); 33665#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33666#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34190#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33857#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33858#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32695#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32696#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34368#L1462-3 assume !(1 == ~T8_E~0); 34369#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34236#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 34237#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32950#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32951#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 33093#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33263#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33264#L1502-3 assume !(1 == ~E_2~0); 34210#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34331#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33302#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32990#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32991#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32957#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32958#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 34068#L1542-3 assume !(1 == ~E_10~0); 34196#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33841#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33842#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 33161#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33162#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32583#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33020#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 33021#L1947 assume !(0 == start_simulation_~tmp~3#1); 33974#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 34164#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 33222#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32645#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 32646#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34299#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34300#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 34460#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 33288#L1928-2 [2024-11-13 12:54:46,149 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:46,149 INFO L85 PathProgramCache]: Analyzing trace with hash -1393291829, now seen corresponding path program 1 times [2024-11-13 12:54:46,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:46,150 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083775118] [2024-11-13 12:54:46,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:46,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:46,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:46,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:46,222 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:46,222 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083775118] [2024-11-13 12:54:46,222 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1083775118] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:46,223 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:46,223 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:46,223 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [219282275] [2024-11-13 12:54:46,223 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:46,223 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:46,224 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:46,224 INFO L85 PathProgramCache]: Analyzing trace with hash 1303985679, now seen corresponding path program 1 times [2024-11-13 12:54:46,224 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:46,224 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1630648245] [2024-11-13 12:54:46,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:46,225 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:46,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:46,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:46,384 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:46,384 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1630648245] [2024-11-13 12:54:46,384 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1630648245] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:46,384 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:46,384 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:46,384 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [635909994] [2024-11-13 12:54:46,384 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:46,385 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:46,385 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:46,385 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:54:46,385 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:54:46,385 INFO L87 Difference]: Start difference. First operand 2032 states and 2994 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:46,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:46,439 INFO L93 Difference]: Finished difference Result 2032 states and 2993 transitions. [2024-11-13 12:54:46,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2993 transitions. [2024-11-13 12:54:46,454 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:46,471 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2993 transitions. [2024-11-13 12:54:46,471 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-13 12:54:46,474 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-13 12:54:46,474 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2993 transitions. [2024-11-13 12:54:46,478 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:46,478 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2993 transitions. [2024-11-13 12:54:46,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2993 transitions. [2024-11-13 12:54:46,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-13 12:54:46,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4729330708661417) internal successors, (2993), 2031 states have internal predecessors, (2993), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:46,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2993 transitions. [2024-11-13 12:54:46,538 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2993 transitions. [2024-11-13 12:54:46,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:54:46,539 INFO L424 stractBuchiCegarLoop]: Abstraction has 2032 states and 2993 transitions. [2024-11-13 12:54:46,540 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 12:54:46,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2993 transitions. [2024-11-13 12:54:46,552 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:46,552 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:46,552 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:46,556 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:46,556 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:46,556 INFO L745 eck$LassoCheckResult]: Stem: 36984#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 36985#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 37971#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37972#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38671#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 37565#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37566#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37636#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37637#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38074#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38075#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37600#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37405#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37406#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 37864#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37865#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37744#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37745#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 37379#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37380#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 38595#L1279-2 assume !(0 == ~T1_E~0); 37005#L1284-1 assume !(0 == ~T2_E~0); 37006#L1289-1 assume !(0 == ~T3_E~0); 37741#L1294-1 assume !(0 == ~T4_E~0); 37742#L1299-1 assume !(0 == ~T5_E~0); 37753#L1304-1 assume !(0 == ~T6_E~0); 38670#L1309-1 assume !(0 == ~T7_E~0); 38672#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36929#L1319-1 assume !(0 == ~T9_E~0); 36930#L1324-1 assume !(0 == ~T10_E~0); 37103#L1329-1 assume !(0 == ~T11_E~0); 37104#L1334-1 assume !(0 == ~T12_E~0); 38513#L1339-1 assume !(0 == ~T13_E~0); 38585#L1344-1 assume !(0 == ~E_M~0); 38586#L1349-1 assume !(0 == ~E_1~0); 37930#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 37931#L1359-1 assume !(0 == ~E_3~0); 38338#L1364-1 assume !(0 == ~E_4~0); 37229#L1369-1 assume !(0 == ~E_5~0); 37230#L1374-1 assume !(0 == ~E_6~0); 37937#L1379-1 assume !(0 == ~E_7~0); 37938#L1384-1 assume !(0 == ~E_8~0); 38015#L1389-1 assume !(0 == ~E_9~0); 38532#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 38533#L1399-1 assume !(0 == ~E_11~0); 38626#L1404-1 assume !(0 == ~E_12~0); 37327#L1409-1 assume !(0 == ~E_13~0); 37328#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38621#L628 assume !(1 == ~m_pc~0); 37228#L628-2 is_master_triggered_~__retres1~0#1 := 0; 37227#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37812#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37813#L1591 assume !(0 != activate_threads_~tmp~1#1); 38634#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37793#L647 assume 1 == ~t1_pc~0; 37153#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37154#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37844#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38301#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 38573#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38574#L666 assume 1 == ~t2_pc~0; 37002#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37003#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37144#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37145#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 38126#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38127#L685 assume !(1 == ~t3_pc~0); 38221#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 38220#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38290#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37979#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37980#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37453#L704 assume 1 == ~t4_pc~0; 37454#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37991#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36793#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36794#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 37842#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37843#L723 assume !(1 == ~t5_pc~0); 37975#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 38193#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38331#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38105#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 38106#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37211#L742 assume 1 == ~t6_pc~0; 37212#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37368#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37135#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36898#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 36899#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37289#L761 assume !(1 == ~t7_pc~0); 37290#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 37165#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37166#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37982#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 37983#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36921#L780 assume 1 == ~t8_pc~0; 36922#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37201#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37202#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37944#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 37945#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38061#L799 assume 1 == ~t9_pc~0; 38163#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36924#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36925#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37196#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 38264#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38087#L818 assume !(1 == ~t10_pc~0); 36708#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36709#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38156#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38090#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38091#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38133#L837 assume 1 == ~t11_pc~0; 38134#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37969#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38577#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38054#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 38055#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37801#L856 assume !(1 == ~t12_pc~0); 37802#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 38436#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36726#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36727#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 38414#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 38598#L875 assume 1 == ~t13_pc~0; 37751#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37369#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37370#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 37307#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 37308#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38155#L1427 assume !(1 == ~M_E~0); 38140#L1427-2 assume !(1 == ~T1_E~0); 37276#L1432-1 assume !(1 == ~T2_E~0); 37277#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38343#L1442-1 assume !(1 == ~T4_E~0); 38344#L1447-1 assume !(1 == ~T5_E~0); 38202#L1452-1 assume !(1 == ~T6_E~0); 36845#L1457-1 assume !(1 == ~T7_E~0); 36846#L1462-1 assume !(1 == ~T8_E~0); 38361#L1467-1 assume !(1 == ~T9_E~0); 38382#L1472-1 assume !(1 == ~T10_E~0); 38383#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38151#L1482-1 assume !(1 == ~T12_E~0); 38152#L1487-1 assume !(1 == ~T13_E~0); 37176#L1492-1 assume !(1 == ~E_M~0); 37177#L1497-1 assume !(1 == ~E_1~0); 37547#L1502-1 assume !(1 == ~E_2~0); 37548#L1507-1 assume !(1 == ~E_3~0); 37053#L1512-1 assume !(1 == ~E_4~0); 37054#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 38455#L1522-1 assume !(1 == ~E_6~0); 37790#L1527-1 assume !(1 == ~E_7~0); 37791#L1532-1 assume !(1 == ~E_8~0); 38656#L1537-1 assume !(1 == ~E_9~0); 37998#L1542-1 assume !(1 == ~E_10~0); 37819#L1547-1 assume !(1 == ~E_11~0); 37820#L1552-1 assume !(1 == ~E_12~0); 36749#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 36750#L1562-1 assume { :end_inline_reset_delta_events } true; 37359#L1928-2 [2024-11-13 12:54:46,558 INFO L747 eck$LassoCheckResult]: Loop: 37359#L1928-2 assume !false; 37857#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37434#L1254-1 assume !false; 37666#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37078#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 37079#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37278#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 38441#L1067 assume !(0 != eval_~tmp~0#1); 37731#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37336#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37337#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37567#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37551#L1284-3 assume !(0 == ~T2_E~0); 37552#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37532#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37533#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37925#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37926#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37413#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37414#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38404#L1324-3 assume !(0 == ~T10_E~0); 37051#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37052#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 37825#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 37826#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 38130#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37397#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37398#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38138#L1364-3 assume !(0 == ~E_4~0); 38655#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38547#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37180#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37181#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37395#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 37396#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37702#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38557#L1404-3 assume !(0 == ~E_12~0); 38522#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 38523#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38027#L628-45 assume 1 == ~m_pc~0; 37697#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37699#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38210#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37431#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37432#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38162#L647-45 assume 1 == ~t1_pc~0; 36999#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37000#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37943#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37109#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37110#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37320#L666-45 assume !(1 == ~t2_pc~0); 37321#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 37811#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38208#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38209#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38274#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36861#L685-45 assume 1 == ~t3_pc~0; 36862#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37939#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38587#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38453#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38454#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38596#L704-45 assume !(1 == ~t4_pc~0); 36728#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 36729#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37597#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38478#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38684#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38056#L723-45 assume !(1 == ~t5_pc~0); 38057#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 38534#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38646#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37409#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 37410#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38424#L742-45 assume 1 == ~t6_pc~0; 38425#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37674#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37884#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37885#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38167#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38253#L761-45 assume !(1 == ~t7_pc~0); 38254#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 37668#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37669#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37057#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37058#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38526#L780-45 assume 1 == ~t8_pc~0; 37435#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37068#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37069#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38653#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37037#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37038#L799-45 assume !(1 == ~t9_pc~0); 37256#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 37257#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38319#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38203#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38204#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36979#L818-45 assume 1 == ~t10_pc~0; 36980#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37097#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38180#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37595#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37596#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38299#L837-45 assume !(1 == ~t11_pc~0); 37525#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 37526#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37049#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37050#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 37118#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37119#L856-45 assume !(1 == ~t12_pc~0); 37120#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 37121#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38350#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38351#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37941#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37942#L875-45 assume 1 == ~t13_pc~0; 37909#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37910#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37970#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38311#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38567#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38511#L1427-3 assume !(1 == ~M_E~0); 37736#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37737#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38261#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37928#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37929#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36766#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36767#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38439#L1462-3 assume !(1 == ~T8_E~0); 38440#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38307#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38308#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37021#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 37022#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 37164#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37334#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37335#L1502-3 assume !(1 == ~E_2~0); 38281#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38402#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37373#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37061#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37062#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37028#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37029#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 38139#L1542-3 assume !(1 == ~E_10~0); 38267#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37912#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37913#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 37232#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37233#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36654#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37091#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 37092#L1947 assume !(0 == start_simulation_~tmp~3#1); 38045#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 38235#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 37293#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36716#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 36717#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38370#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38371#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 38531#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 37359#L1928-2 [2024-11-13 12:54:46,559 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:46,559 INFO L85 PathProgramCache]: Analyzing trace with hash -1779154231, now seen corresponding path program 1 times [2024-11-13 12:54:46,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:46,559 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1538503876] [2024-11-13 12:54:46,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:46,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:46,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:46,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:46,650 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:46,650 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1538503876] [2024-11-13 12:54:46,650 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1538503876] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:46,650 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:46,651 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:46,651 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [219936417] [2024-11-13 12:54:46,651 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:46,652 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:46,653 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:46,653 INFO L85 PathProgramCache]: Analyzing trace with hash -2128870257, now seen corresponding path program 2 times [2024-11-13 12:54:46,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:46,653 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445650163] [2024-11-13 12:54:46,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:46,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:46,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:46,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:46,766 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:46,766 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [445650163] [2024-11-13 12:54:46,767 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [445650163] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:46,767 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:46,767 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:46,767 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1944817688] [2024-11-13 12:54:46,767 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:46,767 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:46,768 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:46,768 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:54:46,768 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:54:46,768 INFO L87 Difference]: Start difference. First operand 2032 states and 2993 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:46,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:46,832 INFO L93 Difference]: Finished difference Result 2032 states and 2992 transitions. [2024-11-13 12:54:46,832 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2992 transitions. [2024-11-13 12:54:46,847 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:46,863 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2992 transitions. [2024-11-13 12:54:46,864 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-13 12:54:46,866 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-13 12:54:46,866 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2992 transitions. [2024-11-13 12:54:46,870 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:46,871 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2992 transitions. [2024-11-13 12:54:46,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2992 transitions. [2024-11-13 12:54:46,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-13 12:54:46,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4724409448818898) internal successors, (2992), 2031 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:46,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2992 transitions. [2024-11-13 12:54:46,924 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2992 transitions. [2024-11-13 12:54:46,925 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:54:46,925 INFO L424 stractBuchiCegarLoop]: Abstraction has 2032 states and 2992 transitions. [2024-11-13 12:54:46,925 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 12:54:46,925 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2992 transitions. [2024-11-13 12:54:46,935 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:46,935 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:46,935 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:46,937 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:46,938 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:46,938 INFO L745 eck$LassoCheckResult]: Stem: 41055#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 41056#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 42042#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42043#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42742#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 41636#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41637#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41707#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41708#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42145#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42146#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41671#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41476#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41477#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41935#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41936#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41815#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 41816#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 41450#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41451#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 42666#L1279-2 assume !(0 == ~T1_E~0); 41076#L1284-1 assume !(0 == ~T2_E~0); 41077#L1289-1 assume !(0 == ~T3_E~0); 41812#L1294-1 assume !(0 == ~T4_E~0); 41813#L1299-1 assume !(0 == ~T5_E~0); 41824#L1304-1 assume !(0 == ~T6_E~0); 42741#L1309-1 assume !(0 == ~T7_E~0); 42743#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41000#L1319-1 assume !(0 == ~T9_E~0); 41001#L1324-1 assume !(0 == ~T10_E~0); 41174#L1329-1 assume !(0 == ~T11_E~0); 41175#L1334-1 assume !(0 == ~T12_E~0); 42584#L1339-1 assume !(0 == ~T13_E~0); 42656#L1344-1 assume !(0 == ~E_M~0); 42657#L1349-1 assume !(0 == ~E_1~0); 42001#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 42002#L1359-1 assume !(0 == ~E_3~0); 42409#L1364-1 assume !(0 == ~E_4~0); 41300#L1369-1 assume !(0 == ~E_5~0); 41301#L1374-1 assume !(0 == ~E_6~0); 42008#L1379-1 assume !(0 == ~E_7~0); 42009#L1384-1 assume !(0 == ~E_8~0); 42086#L1389-1 assume !(0 == ~E_9~0); 42603#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 42604#L1399-1 assume !(0 == ~E_11~0); 42697#L1404-1 assume !(0 == ~E_12~0); 41398#L1409-1 assume !(0 == ~E_13~0); 41399#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42692#L628 assume !(1 == ~m_pc~0); 41299#L628-2 is_master_triggered_~__retres1~0#1 := 0; 41298#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41883#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41884#L1591 assume !(0 != activate_threads_~tmp~1#1); 42705#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41864#L647 assume 1 == ~t1_pc~0; 41224#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41225#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41915#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42372#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 42644#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42645#L666 assume 1 == ~t2_pc~0; 41073#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41074#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41215#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41216#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 42197#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42198#L685 assume !(1 == ~t3_pc~0); 42292#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 42291#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42361#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42050#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42051#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41524#L704 assume 1 == ~t4_pc~0; 41525#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 42062#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40864#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40865#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 41913#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41914#L723 assume !(1 == ~t5_pc~0); 42046#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 42264#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42402#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42176#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 42177#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41282#L742 assume 1 == ~t6_pc~0; 41283#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41439#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41206#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40969#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 40970#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41360#L761 assume !(1 == ~t7_pc~0); 41361#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 41236#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41237#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42053#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 42054#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40992#L780 assume 1 == ~t8_pc~0; 40993#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41272#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41273#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42015#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 42016#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 42132#L799 assume 1 == ~t9_pc~0; 42234#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40995#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40996#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41267#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 42335#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42158#L818 assume !(1 == ~t10_pc~0); 40779#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 40780#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42227#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42161#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 42162#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42204#L837 assume 1 == ~t11_pc~0; 42205#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42040#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42648#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42125#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 42126#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41872#L856 assume !(1 == ~t12_pc~0); 41873#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 42507#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40797#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40798#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 42485#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 42669#L875 assume 1 == ~t13_pc~0; 41822#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41440#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 41441#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 41378#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 41379#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42226#L1427 assume !(1 == ~M_E~0); 42211#L1427-2 assume !(1 == ~T1_E~0); 41347#L1432-1 assume !(1 == ~T2_E~0); 41348#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42414#L1442-1 assume !(1 == ~T4_E~0); 42415#L1447-1 assume !(1 == ~T5_E~0); 42273#L1452-1 assume !(1 == ~T6_E~0); 40916#L1457-1 assume !(1 == ~T7_E~0); 40917#L1462-1 assume !(1 == ~T8_E~0); 42432#L1467-1 assume !(1 == ~T9_E~0); 42453#L1472-1 assume !(1 == ~T10_E~0); 42454#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 42222#L1482-1 assume !(1 == ~T12_E~0); 42223#L1487-1 assume !(1 == ~T13_E~0); 41247#L1492-1 assume !(1 == ~E_M~0); 41248#L1497-1 assume !(1 == ~E_1~0); 41618#L1502-1 assume !(1 == ~E_2~0); 41619#L1507-1 assume !(1 == ~E_3~0); 41124#L1512-1 assume !(1 == ~E_4~0); 41125#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 42526#L1522-1 assume !(1 == ~E_6~0); 41861#L1527-1 assume !(1 == ~E_7~0); 41862#L1532-1 assume !(1 == ~E_8~0); 42727#L1537-1 assume !(1 == ~E_9~0); 42069#L1542-1 assume !(1 == ~E_10~0); 41890#L1547-1 assume !(1 == ~E_11~0); 41891#L1552-1 assume !(1 == ~E_12~0); 40820#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 40821#L1562-1 assume { :end_inline_reset_delta_events } true; 41430#L1928-2 [2024-11-13 12:54:46,939 INFO L747 eck$LassoCheckResult]: Loop: 41430#L1928-2 assume !false; 41928#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41505#L1254-1 assume !false; 41737#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41149#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41150#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41349#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 42512#L1067 assume !(0 != eval_~tmp~0#1); 41802#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41407#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41408#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41638#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41622#L1284-3 assume !(0 == ~T2_E~0); 41623#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41603#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41604#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41996#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41997#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41484#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41485#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42475#L1324-3 assume !(0 == ~T10_E~0); 41122#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41123#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 41896#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 41897#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 42201#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41468#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41469#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42209#L1364-3 assume !(0 == ~E_4~0); 42726#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42618#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41251#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41252#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41466#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 41467#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41773#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 42628#L1404-3 assume !(0 == ~E_12~0); 42593#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 42594#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42098#L628-45 assume 1 == ~m_pc~0; 41768#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 41770#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42281#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41502#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41503#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42233#L647-45 assume !(1 == ~t1_pc~0); 41072#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 41071#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42014#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41180#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41181#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41391#L666-45 assume !(1 == ~t2_pc~0); 41392#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 41882#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42279#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42280#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42345#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40932#L685-45 assume 1 == ~t3_pc~0; 40933#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42010#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42658#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42524#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42525#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42667#L704-45 assume 1 == ~t4_pc~0; 42548#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40800#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41668#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42549#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42755#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42127#L723-45 assume !(1 == ~t5_pc~0); 42128#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 42605#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42717#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41480#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 41481#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42495#L742-45 assume 1 == ~t6_pc~0; 42496#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41745#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41955#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41956#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42238#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42324#L761-45 assume !(1 == ~t7_pc~0); 42325#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 41739#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41740#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41128#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41129#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42597#L780-45 assume 1 == ~t8_pc~0; 41506#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41139#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41140#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42724#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41108#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41109#L799-45 assume 1 == ~t9_pc~0; 41894#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41328#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42390#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42274#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42275#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41050#L818-45 assume 1 == ~t10_pc~0; 41051#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41168#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42251#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41666#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41667#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42370#L837-45 assume !(1 == ~t11_pc~0); 41596#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 41597#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41120#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41121#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41189#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41190#L856-45 assume !(1 == ~t12_pc~0); 41191#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 41192#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42421#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42422#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 42012#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 42013#L875-45 assume 1 == ~t13_pc~0; 41980#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41981#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42041#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42382#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42638#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42582#L1427-3 assume !(1 == ~M_E~0); 41807#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41808#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42332#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41999#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42000#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40837#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40838#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42510#L1462-3 assume !(1 == ~T8_E~0); 42511#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42378#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 42379#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41092#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 41093#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 41235#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41405#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41406#L1502-3 assume !(1 == ~E_2~0); 42352#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42473#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41444#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41132#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 41133#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41099#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41100#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 42210#L1542-3 assume !(1 == ~E_10~0); 42338#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41983#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41984#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 41303#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41304#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40725#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41162#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 41163#L1947 assume !(0 == start_simulation_~tmp~3#1); 42116#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 42306#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41364#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 40787#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 40788#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42441#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42442#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 42602#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 41430#L1928-2 [2024-11-13 12:54:46,939 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:46,939 INFO L85 PathProgramCache]: Analyzing trace with hash 584687431, now seen corresponding path program 1 times [2024-11-13 12:54:46,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:46,939 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1431074854] [2024-11-13 12:54:46,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:46,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:46,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:47,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:47,007 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:47,007 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1431074854] [2024-11-13 12:54:47,007 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1431074854] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:47,008 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:47,008 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:47,008 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1429951649] [2024-11-13 12:54:47,008 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:47,008 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:47,009 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:47,009 INFO L85 PathProgramCache]: Analyzing trace with hash -568652850, now seen corresponding path program 1 times [2024-11-13 12:54:47,009 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:47,009 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [264292596] [2024-11-13 12:54:47,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:47,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:47,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:47,096 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:47,096 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:47,096 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [264292596] [2024-11-13 12:54:47,096 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [264292596] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:47,096 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:47,097 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:47,097 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1880385636] [2024-11-13 12:54:47,097 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:47,097 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:47,097 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:47,099 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:54:47,100 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:54:47,100 INFO L87 Difference]: Start difference. First operand 2032 states and 2992 transitions. cyclomatic complexity: 961 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:47,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:47,148 INFO L93 Difference]: Finished difference Result 2032 states and 2991 transitions. [2024-11-13 12:54:47,148 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2991 transitions. [2024-11-13 12:54:47,161 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:47,175 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2991 transitions. [2024-11-13 12:54:47,175 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-13 12:54:47,177 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-13 12:54:47,178 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2991 transitions. [2024-11-13 12:54:47,181 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:47,181 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2991 transitions. [2024-11-13 12:54:47,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2991 transitions. [2024-11-13 12:54:47,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-13 12:54:47,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4719488188976377) internal successors, (2991), 2031 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:47,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2991 transitions. [2024-11-13 12:54:47,230 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2991 transitions. [2024-11-13 12:54:47,231 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:54:47,231 INFO L424 stractBuchiCegarLoop]: Abstraction has 2032 states and 2991 transitions. [2024-11-13 12:54:47,231 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 12:54:47,231 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2991 transitions. [2024-11-13 12:54:47,241 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:47,242 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:47,242 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:47,246 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:47,248 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:47,249 INFO L745 eck$LassoCheckResult]: Stem: 45126#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 45127#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 46113#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46114#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46813#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 45707#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45708#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45778#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45779#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46216#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46217#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45742#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45547#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45548#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46006#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 46007#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45886#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 45887#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 45521#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45522#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 46737#L1279-2 assume !(0 == ~T1_E~0); 45147#L1284-1 assume !(0 == ~T2_E~0); 45148#L1289-1 assume !(0 == ~T3_E~0); 45883#L1294-1 assume !(0 == ~T4_E~0); 45884#L1299-1 assume !(0 == ~T5_E~0); 45895#L1304-1 assume !(0 == ~T6_E~0); 46812#L1309-1 assume !(0 == ~T7_E~0); 46814#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45071#L1319-1 assume !(0 == ~T9_E~0); 45072#L1324-1 assume !(0 == ~T10_E~0); 45245#L1329-1 assume !(0 == ~T11_E~0); 45246#L1334-1 assume !(0 == ~T12_E~0); 46655#L1339-1 assume !(0 == ~T13_E~0); 46727#L1344-1 assume !(0 == ~E_M~0); 46728#L1349-1 assume !(0 == ~E_1~0); 46072#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 46073#L1359-1 assume !(0 == ~E_3~0); 46480#L1364-1 assume !(0 == ~E_4~0); 45371#L1369-1 assume !(0 == ~E_5~0); 45372#L1374-1 assume !(0 == ~E_6~0); 46079#L1379-1 assume !(0 == ~E_7~0); 46080#L1384-1 assume !(0 == ~E_8~0); 46157#L1389-1 assume !(0 == ~E_9~0); 46674#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 46675#L1399-1 assume !(0 == ~E_11~0); 46768#L1404-1 assume !(0 == ~E_12~0); 45469#L1409-1 assume !(0 == ~E_13~0); 45470#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46763#L628 assume !(1 == ~m_pc~0); 45370#L628-2 is_master_triggered_~__retres1~0#1 := 0; 45369#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45954#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45955#L1591 assume !(0 != activate_threads_~tmp~1#1); 46776#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45935#L647 assume 1 == ~t1_pc~0; 45295#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45296#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45986#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46443#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 46715#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46716#L666 assume 1 == ~t2_pc~0; 45144#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 45145#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45286#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45287#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 46268#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46269#L685 assume !(1 == ~t3_pc~0); 46363#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46362#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46432#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46121#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46122#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45595#L704 assume 1 == ~t4_pc~0; 45596#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46133#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44935#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44936#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 45984#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45985#L723 assume !(1 == ~t5_pc~0); 46117#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 46335#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46473#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46247#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 46248#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45353#L742 assume 1 == ~t6_pc~0; 45354#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45510#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45277#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45040#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 45041#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45431#L761 assume !(1 == ~t7_pc~0); 45432#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 45307#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45308#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46124#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 46125#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45063#L780 assume 1 == ~t8_pc~0; 45064#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45343#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45344#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46086#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 46087#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46203#L799 assume 1 == ~t9_pc~0; 46305#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45066#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45067#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45338#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 46406#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46229#L818 assume !(1 == ~t10_pc~0); 44850#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 44851#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46298#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46232#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 46233#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46275#L837 assume 1 == ~t11_pc~0; 46276#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46111#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46719#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46196#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 46197#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45943#L856 assume !(1 == ~t12_pc~0); 45944#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 46578#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44868#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44869#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 46556#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46740#L875 assume 1 == ~t13_pc~0; 45893#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45511#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45512#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 45449#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 45450#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46297#L1427 assume !(1 == ~M_E~0); 46282#L1427-2 assume !(1 == ~T1_E~0); 45418#L1432-1 assume !(1 == ~T2_E~0); 45419#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46485#L1442-1 assume !(1 == ~T4_E~0); 46486#L1447-1 assume !(1 == ~T5_E~0); 46344#L1452-1 assume !(1 == ~T6_E~0); 44987#L1457-1 assume !(1 == ~T7_E~0); 44988#L1462-1 assume !(1 == ~T8_E~0); 46503#L1467-1 assume !(1 == ~T9_E~0); 46524#L1472-1 assume !(1 == ~T10_E~0); 46525#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46293#L1482-1 assume !(1 == ~T12_E~0); 46294#L1487-1 assume !(1 == ~T13_E~0); 45318#L1492-1 assume !(1 == ~E_M~0); 45319#L1497-1 assume !(1 == ~E_1~0); 45689#L1502-1 assume !(1 == ~E_2~0); 45690#L1507-1 assume !(1 == ~E_3~0); 45195#L1512-1 assume !(1 == ~E_4~0); 45196#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46597#L1522-1 assume !(1 == ~E_6~0); 45932#L1527-1 assume !(1 == ~E_7~0); 45933#L1532-1 assume !(1 == ~E_8~0); 46798#L1537-1 assume !(1 == ~E_9~0); 46140#L1542-1 assume !(1 == ~E_10~0); 45961#L1547-1 assume !(1 == ~E_11~0); 45962#L1552-1 assume !(1 == ~E_12~0); 44891#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 44892#L1562-1 assume { :end_inline_reset_delta_events } true; 45501#L1928-2 [2024-11-13 12:54:47,250 INFO L747 eck$LassoCheckResult]: Loop: 45501#L1928-2 assume !false; 45999#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45576#L1254-1 assume !false; 45808#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45220#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45221#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45420#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 46583#L1067 assume !(0 != eval_~tmp~0#1); 45873#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45478#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45479#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 45709#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 45693#L1284-3 assume !(0 == ~T2_E~0); 45694#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45674#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45675#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 46067#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46068#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45555#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45556#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46546#L1324-3 assume !(0 == ~T10_E~0); 45193#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 45194#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 45967#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 45968#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 46272#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45539#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45540#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46280#L1364-3 assume !(0 == ~E_4~0); 46797#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46689#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 45322#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 45323#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45537#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 45538#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 45844#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46699#L1404-3 assume !(0 == ~E_12~0); 46664#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 46665#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46169#L628-45 assume !(1 == ~m_pc~0); 45840#L628-47 is_master_triggered_~__retres1~0#1 := 0; 45841#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46352#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45573#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45574#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46304#L647-45 assume 1 == ~t1_pc~0; 45141#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45142#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46085#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45251#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45252#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45462#L666-45 assume !(1 == ~t2_pc~0); 45463#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 45953#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46350#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46351#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46416#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45003#L685-45 assume 1 == ~t3_pc~0; 45004#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46081#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46729#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46595#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46596#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46738#L704-45 assume !(1 == ~t4_pc~0); 44870#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 44871#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45739#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46620#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46826#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46198#L723-45 assume !(1 == ~t5_pc~0); 46199#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 46676#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46788#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45551#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 45552#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46566#L742-45 assume 1 == ~t6_pc~0; 46567#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45816#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46026#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46027#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46309#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46395#L761-45 assume !(1 == ~t7_pc~0); 46396#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 45810#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45811#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45199#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45200#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46668#L780-45 assume 1 == ~t8_pc~0; 45577#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45210#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45211#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46795#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45179#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45180#L799-45 assume !(1 == ~t9_pc~0); 45398#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 45399#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46461#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46345#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46346#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45121#L818-45 assume 1 == ~t10_pc~0; 45122#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 45239#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46322#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45737#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45738#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46441#L837-45 assume !(1 == ~t11_pc~0); 45667#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 45668#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45191#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 45192#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 45260#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45261#L856-45 assume 1 == ~t12_pc~0; 46736#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 45263#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46492#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46493#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 46083#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46084#L875-45 assume 1 == ~t13_pc~0; 46051#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 46052#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46112#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46453#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46709#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46653#L1427-3 assume !(1 == ~M_E~0); 45878#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45879#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46403#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46070#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46071#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44908#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44909#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46581#L1462-3 assume !(1 == ~T8_E~0); 46582#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46449#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46450#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45163#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 45164#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 45306#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45476#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45477#L1502-3 assume !(1 == ~E_2~0); 46423#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46544#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45515#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 45203#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 45204#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 45170#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45171#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 46281#L1542-3 assume !(1 == ~E_10~0); 46409#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 46054#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 46055#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 45374#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45375#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44796#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45233#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 45234#L1947 assume !(0 == start_simulation_~tmp~3#1); 46187#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 46377#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45435#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 44858#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 44859#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46512#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46513#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 46673#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 45501#L1928-2 [2024-11-13 12:54:47,250 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:47,251 INFO L85 PathProgramCache]: Analyzing trace with hash 1907866377, now seen corresponding path program 1 times [2024-11-13 12:54:47,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:47,251 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [955340921] [2024-11-13 12:54:47,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:47,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:47,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:47,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:47,322 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:47,322 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [955340921] [2024-11-13 12:54:47,322 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [955340921] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:47,322 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:47,322 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:47,322 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1980179327] [2024-11-13 12:54:47,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:47,323 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:47,324 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:47,324 INFO L85 PathProgramCache]: Analyzing trace with hash 660417423, now seen corresponding path program 1 times [2024-11-13 12:54:47,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:47,324 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [456169005] [2024-11-13 12:54:47,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:47,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:47,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:47,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:47,404 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:47,405 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [456169005] [2024-11-13 12:54:47,405 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [456169005] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:47,405 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:47,405 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:47,405 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [49248871] [2024-11-13 12:54:47,405 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:47,405 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:47,406 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:47,406 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:54:47,406 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:54:47,407 INFO L87 Difference]: Start difference. First operand 2032 states and 2991 transitions. cyclomatic complexity: 960 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:47,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:47,456 INFO L93 Difference]: Finished difference Result 2032 states and 2990 transitions. [2024-11-13 12:54:47,456 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2990 transitions. [2024-11-13 12:54:47,467 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:47,475 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2990 transitions. [2024-11-13 12:54:47,476 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-13 12:54:47,478 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-13 12:54:47,478 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2990 transitions. [2024-11-13 12:54:47,481 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:47,482 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2990 transitions. [2024-11-13 12:54:47,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2990 transitions. [2024-11-13 12:54:47,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-13 12:54:47,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4714566929133859) internal successors, (2990), 2031 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:47,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2990 transitions. [2024-11-13 12:54:47,521 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2990 transitions. [2024-11-13 12:54:47,521 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:54:47,522 INFO L424 stractBuchiCegarLoop]: Abstraction has 2032 states and 2990 transitions. [2024-11-13 12:54:47,522 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 12:54:47,522 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2990 transitions. [2024-11-13 12:54:47,531 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:47,531 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:47,531 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:47,534 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:47,534 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:47,534 INFO L745 eck$LassoCheckResult]: Stem: 49197#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 49198#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 50184#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50185#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50884#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 49778#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49779#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49849#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49850#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50287#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50288#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49813#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49618#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49619#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50077#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50078#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49957#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 49958#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 49592#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49593#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 50808#L1279-2 assume !(0 == ~T1_E~0); 49218#L1284-1 assume !(0 == ~T2_E~0); 49219#L1289-1 assume !(0 == ~T3_E~0); 49954#L1294-1 assume !(0 == ~T4_E~0); 49955#L1299-1 assume !(0 == ~T5_E~0); 49966#L1304-1 assume !(0 == ~T6_E~0); 50883#L1309-1 assume !(0 == ~T7_E~0); 50885#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49142#L1319-1 assume !(0 == ~T9_E~0); 49143#L1324-1 assume !(0 == ~T10_E~0); 49316#L1329-1 assume !(0 == ~T11_E~0); 49317#L1334-1 assume !(0 == ~T12_E~0); 50726#L1339-1 assume !(0 == ~T13_E~0); 50798#L1344-1 assume !(0 == ~E_M~0); 50799#L1349-1 assume !(0 == ~E_1~0); 50143#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 50144#L1359-1 assume !(0 == ~E_3~0); 50551#L1364-1 assume !(0 == ~E_4~0); 49442#L1369-1 assume !(0 == ~E_5~0); 49443#L1374-1 assume !(0 == ~E_6~0); 50150#L1379-1 assume !(0 == ~E_7~0); 50151#L1384-1 assume !(0 == ~E_8~0); 50228#L1389-1 assume !(0 == ~E_9~0); 50745#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 50746#L1399-1 assume !(0 == ~E_11~0); 50839#L1404-1 assume !(0 == ~E_12~0); 49540#L1409-1 assume !(0 == ~E_13~0); 49541#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50834#L628 assume !(1 == ~m_pc~0); 49441#L628-2 is_master_triggered_~__retres1~0#1 := 0; 49440#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50025#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50026#L1591 assume !(0 != activate_threads_~tmp~1#1); 50847#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50006#L647 assume 1 == ~t1_pc~0; 49366#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49367#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50057#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50514#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 50786#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50787#L666 assume 1 == ~t2_pc~0; 49215#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49216#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49357#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49358#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 50339#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50340#L685 assume !(1 == ~t3_pc~0); 50434#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 50433#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50503#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50192#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50193#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49666#L704 assume 1 == ~t4_pc~0; 49667#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50204#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49006#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49007#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 50055#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50056#L723 assume !(1 == ~t5_pc~0); 50188#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 50406#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50544#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50318#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 50319#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49424#L742 assume 1 == ~t6_pc~0; 49425#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49581#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49348#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49111#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 49112#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49502#L761 assume !(1 == ~t7_pc~0); 49503#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 49378#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49379#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50195#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 50196#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49134#L780 assume 1 == ~t8_pc~0; 49135#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49414#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49415#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50157#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 50158#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50274#L799 assume 1 == ~t9_pc~0; 50376#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49137#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49138#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49409#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 50477#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50300#L818 assume !(1 == ~t10_pc~0); 48921#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 48922#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50369#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50303#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50304#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50346#L837 assume 1 == ~t11_pc~0; 50347#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 50182#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50790#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50267#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 50268#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50014#L856 assume !(1 == ~t12_pc~0); 50015#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 50649#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48939#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 48940#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 50627#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50811#L875 assume 1 == ~t13_pc~0; 49964#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 49582#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 49583#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 49520#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 49521#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50368#L1427 assume !(1 == ~M_E~0); 50353#L1427-2 assume !(1 == ~T1_E~0); 49489#L1432-1 assume !(1 == ~T2_E~0); 49490#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50556#L1442-1 assume !(1 == ~T4_E~0); 50557#L1447-1 assume !(1 == ~T5_E~0); 50415#L1452-1 assume !(1 == ~T6_E~0); 49058#L1457-1 assume !(1 == ~T7_E~0); 49059#L1462-1 assume !(1 == ~T8_E~0); 50574#L1467-1 assume !(1 == ~T9_E~0); 50595#L1472-1 assume !(1 == ~T10_E~0); 50596#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50364#L1482-1 assume !(1 == ~T12_E~0); 50365#L1487-1 assume !(1 == ~T13_E~0); 49389#L1492-1 assume !(1 == ~E_M~0); 49390#L1497-1 assume !(1 == ~E_1~0); 49760#L1502-1 assume !(1 == ~E_2~0); 49761#L1507-1 assume !(1 == ~E_3~0); 49266#L1512-1 assume !(1 == ~E_4~0); 49267#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 50668#L1522-1 assume !(1 == ~E_6~0); 50003#L1527-1 assume !(1 == ~E_7~0); 50004#L1532-1 assume !(1 == ~E_8~0); 50869#L1537-1 assume !(1 == ~E_9~0); 50211#L1542-1 assume !(1 == ~E_10~0); 50032#L1547-1 assume !(1 == ~E_11~0); 50033#L1552-1 assume !(1 == ~E_12~0); 48962#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 48963#L1562-1 assume { :end_inline_reset_delta_events } true; 49572#L1928-2 [2024-11-13 12:54:47,535 INFO L747 eck$LassoCheckResult]: Loop: 49572#L1928-2 assume !false; 50070#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49647#L1254-1 assume !false; 49879#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49291#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49292#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49491#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 50654#L1067 assume !(0 != eval_~tmp~0#1); 49944#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49549#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49550#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49780#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 49764#L1284-3 assume !(0 == ~T2_E~0); 49765#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49745#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49746#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 50138#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50139#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49626#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49627#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50617#L1324-3 assume !(0 == ~T10_E~0); 49264#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 49265#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 50038#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50039#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 50343#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49610#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49611#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50351#L1364-3 assume !(0 == ~E_4~0); 50868#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50760#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 49393#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 49394#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49608#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 49609#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49915#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 50770#L1404-3 assume !(0 == ~E_12~0); 50735#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 50736#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50240#L628-45 assume 1 == ~m_pc~0; 49910#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49912#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50423#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49644#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49645#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50375#L647-45 assume 1 == ~t1_pc~0; 49212#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49213#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50156#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49322#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49323#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49533#L666-45 assume !(1 == ~t2_pc~0); 49534#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 50024#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50421#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50422#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50487#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49074#L685-45 assume 1 == ~t3_pc~0; 49075#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50152#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50800#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50666#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50667#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50809#L704-45 assume 1 == ~t4_pc~0; 50690#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48942#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49810#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50691#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50897#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50269#L723-45 assume !(1 == ~t5_pc~0); 50270#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 50747#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50859#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49622#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 49623#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50637#L742-45 assume 1 == ~t6_pc~0; 50638#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49887#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50097#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50098#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50380#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50466#L761-45 assume !(1 == ~t7_pc~0); 50467#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 49881#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49882#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49270#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49271#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50739#L780-45 assume 1 == ~t8_pc~0; 49648#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49281#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49282#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50866#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49250#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49251#L799-45 assume 1 == ~t9_pc~0; 50036#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49470#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50532#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50416#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 50417#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49192#L818-45 assume 1 == ~t10_pc~0; 49193#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49310#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50393#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49808#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49809#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50512#L837-45 assume !(1 == ~t11_pc~0); 49738#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 49739#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49262#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49263#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 49331#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49332#L856-45 assume !(1 == ~t12_pc~0); 49333#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 49334#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50563#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50564#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 50154#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50155#L875-45 assume 1 == ~t13_pc~0; 50122#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50123#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50183#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 50524#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50780#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50724#L1427-3 assume !(1 == ~M_E~0); 49949#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49950#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50474#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50141#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50142#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48979#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48980#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50652#L1462-3 assume !(1 == ~T8_E~0); 50653#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50520#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50521#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49234#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 49235#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 49377#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49547#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49548#L1502-3 assume !(1 == ~E_2~0); 50494#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50615#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49586#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49274#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49275#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49241#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49242#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50352#L1542-3 assume !(1 == ~E_10~0); 50480#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 50125#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50126#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 49445#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49446#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48867#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49304#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 49305#L1947 assume !(0 == start_simulation_~tmp~3#1); 50258#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 50448#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49506#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 48929#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 48930#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50583#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50584#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 50744#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 49572#L1928-2 [2024-11-13 12:54:47,536 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:47,536 INFO L85 PathProgramCache]: Analyzing trace with hash 10886919, now seen corresponding path program 1 times [2024-11-13 12:54:47,536 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:47,536 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [93550108] [2024-11-13 12:54:47,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:47,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:47,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:47,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:47,596 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:47,596 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [93550108] [2024-11-13 12:54:47,596 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [93550108] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:47,596 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:47,596 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:47,596 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1000277360] [2024-11-13 12:54:47,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:47,597 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:47,597 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:47,597 INFO L85 PathProgramCache]: Analyzing trace with hash 856442701, now seen corresponding path program 1 times [2024-11-13 12:54:47,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:47,597 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [877531276] [2024-11-13 12:54:47,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:47,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:47,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:47,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:47,719 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:47,719 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [877531276] [2024-11-13 12:54:47,719 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [877531276] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:47,719 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:47,719 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:47,719 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [711620955] [2024-11-13 12:54:47,719 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:47,720 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:47,720 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:47,720 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:54:47,720 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:54:47,721 INFO L87 Difference]: Start difference. First operand 2032 states and 2990 transitions. cyclomatic complexity: 959 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:47,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:47,772 INFO L93 Difference]: Finished difference Result 2032 states and 2989 transitions. [2024-11-13 12:54:47,772 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2989 transitions. [2024-11-13 12:54:47,785 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:47,794 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2989 transitions. [2024-11-13 12:54:47,794 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-13 12:54:47,796 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-13 12:54:47,797 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2989 transitions. [2024-11-13 12:54:47,800 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:47,800 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2989 transitions. [2024-11-13 12:54:47,804 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2989 transitions. [2024-11-13 12:54:47,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-13 12:54:47,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4709645669291338) internal successors, (2989), 2031 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:47,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2989 transitions. [2024-11-13 12:54:47,842 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2989 transitions. [2024-11-13 12:54:47,842 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:54:47,842 INFO L424 stractBuchiCegarLoop]: Abstraction has 2032 states and 2989 transitions. [2024-11-13 12:54:47,843 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 12:54:47,843 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2989 transitions. [2024-11-13 12:54:47,852 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-13 12:54:47,852 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:47,852 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:47,855 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:47,855 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:47,856 INFO L745 eck$LassoCheckResult]: Stem: 53268#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 53269#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 54255#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54256#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54955#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 53849#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53850#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53920#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53921#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54358#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54359#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53884#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53689#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53690#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54148#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 54149#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 54028#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 54029#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 53663#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53664#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 54879#L1279-2 assume !(0 == ~T1_E~0); 53289#L1284-1 assume !(0 == ~T2_E~0); 53290#L1289-1 assume !(0 == ~T3_E~0); 54025#L1294-1 assume !(0 == ~T4_E~0); 54026#L1299-1 assume !(0 == ~T5_E~0); 54037#L1304-1 assume !(0 == ~T6_E~0); 54954#L1309-1 assume !(0 == ~T7_E~0); 54956#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53213#L1319-1 assume !(0 == ~T9_E~0); 53214#L1324-1 assume !(0 == ~T10_E~0); 53387#L1329-1 assume !(0 == ~T11_E~0); 53388#L1334-1 assume !(0 == ~T12_E~0); 54797#L1339-1 assume !(0 == ~T13_E~0); 54869#L1344-1 assume !(0 == ~E_M~0); 54870#L1349-1 assume !(0 == ~E_1~0); 54214#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 54215#L1359-1 assume !(0 == ~E_3~0); 54622#L1364-1 assume !(0 == ~E_4~0); 53513#L1369-1 assume !(0 == ~E_5~0); 53514#L1374-1 assume !(0 == ~E_6~0); 54221#L1379-1 assume !(0 == ~E_7~0); 54222#L1384-1 assume !(0 == ~E_8~0); 54299#L1389-1 assume !(0 == ~E_9~0); 54816#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 54817#L1399-1 assume !(0 == ~E_11~0); 54910#L1404-1 assume !(0 == ~E_12~0); 53611#L1409-1 assume !(0 == ~E_13~0); 53612#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54905#L628 assume !(1 == ~m_pc~0); 53512#L628-2 is_master_triggered_~__retres1~0#1 := 0; 53511#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54096#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54097#L1591 assume !(0 != activate_threads_~tmp~1#1); 54918#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54077#L647 assume 1 == ~t1_pc~0; 53437#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53438#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54128#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54585#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 54857#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54858#L666 assume 1 == ~t2_pc~0; 53286#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 53287#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53428#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53429#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 54410#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54411#L685 assume !(1 == ~t3_pc~0); 54505#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54504#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54574#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54263#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54264#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53737#L704 assume 1 == ~t4_pc~0; 53738#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54275#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53077#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53078#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 54126#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54127#L723 assume !(1 == ~t5_pc~0); 54259#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 54477#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54615#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54389#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 54390#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53495#L742 assume 1 == ~t6_pc~0; 53496#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53652#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53419#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53182#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 53183#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53573#L761 assume !(1 == ~t7_pc~0); 53574#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53449#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53450#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54266#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 54267#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53205#L780 assume 1 == ~t8_pc~0; 53206#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53485#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53486#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54228#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 54229#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54345#L799 assume 1 == ~t9_pc~0; 54447#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53208#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53209#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53480#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 54548#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54371#L818 assume !(1 == ~t10_pc~0); 52992#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 52993#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54440#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54374#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 54375#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54417#L837 assume 1 == ~t11_pc~0; 54418#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54253#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54861#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54338#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 54339#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54085#L856 assume !(1 == ~t12_pc~0); 54086#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 54720#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53010#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53011#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 54698#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 54882#L875 assume 1 == ~t13_pc~0; 54035#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53653#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 53654#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 53591#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 53592#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54439#L1427 assume !(1 == ~M_E~0); 54424#L1427-2 assume !(1 == ~T1_E~0); 53560#L1432-1 assume !(1 == ~T2_E~0); 53561#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54627#L1442-1 assume !(1 == ~T4_E~0); 54628#L1447-1 assume !(1 == ~T5_E~0); 54486#L1452-1 assume !(1 == ~T6_E~0); 53129#L1457-1 assume !(1 == ~T7_E~0); 53130#L1462-1 assume !(1 == ~T8_E~0); 54645#L1467-1 assume !(1 == ~T9_E~0); 54666#L1472-1 assume !(1 == ~T10_E~0); 54667#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54435#L1482-1 assume !(1 == ~T12_E~0); 54436#L1487-1 assume !(1 == ~T13_E~0); 53460#L1492-1 assume !(1 == ~E_M~0); 53461#L1497-1 assume !(1 == ~E_1~0); 53831#L1502-1 assume !(1 == ~E_2~0); 53832#L1507-1 assume !(1 == ~E_3~0); 53337#L1512-1 assume !(1 == ~E_4~0); 53338#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54739#L1522-1 assume !(1 == ~E_6~0); 54074#L1527-1 assume !(1 == ~E_7~0); 54075#L1532-1 assume !(1 == ~E_8~0); 54940#L1537-1 assume !(1 == ~E_9~0); 54282#L1542-1 assume !(1 == ~E_10~0); 54103#L1547-1 assume !(1 == ~E_11~0); 54104#L1552-1 assume !(1 == ~E_12~0); 53033#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 53034#L1562-1 assume { :end_inline_reset_delta_events } true; 53643#L1928-2 [2024-11-13 12:54:47,856 INFO L747 eck$LassoCheckResult]: Loop: 53643#L1928-2 assume !false; 54141#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53718#L1254-1 assume !false; 53950#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53362#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53363#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53562#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 54725#L1067 assume !(0 != eval_~tmp~0#1); 54015#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53620#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53621#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53851#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 53835#L1284-3 assume !(0 == ~T2_E~0); 53836#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 53816#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53817#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 54209#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 54210#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53697#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53698#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54688#L1324-3 assume !(0 == ~T10_E~0); 53335#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 53336#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 54109#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 54110#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 54414#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53681#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53682#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54422#L1364-3 assume !(0 == ~E_4~0); 54939#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54831#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53464#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53465#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53679#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53680#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53986#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 54841#L1404-3 assume !(0 == ~E_12~0); 54806#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 54807#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54311#L628-45 assume 1 == ~m_pc~0; 53981#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 53983#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54494#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53715#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53716#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54446#L647-45 assume 1 == ~t1_pc~0; 53283#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53284#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54227#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53393#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53394#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53604#L666-45 assume !(1 == ~t2_pc~0); 53605#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 54095#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54492#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54493#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54558#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53145#L685-45 assume 1 == ~t3_pc~0; 53146#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54223#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54871#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54737#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54738#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54880#L704-45 assume !(1 == ~t4_pc~0); 53012#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 53013#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53881#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54762#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54968#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54340#L723-45 assume !(1 == ~t5_pc~0); 54341#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 54818#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54930#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53693#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 53694#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54708#L742-45 assume 1 == ~t6_pc~0; 54709#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53958#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54168#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54169#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54451#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54537#L761-45 assume !(1 == ~t7_pc~0); 54538#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 53952#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53953#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53341#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 53342#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54810#L780-45 assume 1 == ~t8_pc~0; 53719#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53352#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53353#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54937#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53321#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53322#L799-45 assume !(1 == ~t9_pc~0); 53540#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 53541#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54603#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54487#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 54488#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53263#L818-45 assume 1 == ~t10_pc~0; 53264#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53381#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54464#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53879#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53880#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54583#L837-45 assume !(1 == ~t11_pc~0); 53809#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 53810#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53333#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53334#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 53402#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53403#L856-45 assume !(1 == ~t12_pc~0); 53404#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 53405#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 54634#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54635#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 54225#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 54226#L875-45 assume 1 == ~t13_pc~0; 54193#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 54194#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54254#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54595#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 54851#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54795#L1427-3 assume !(1 == ~M_E~0); 54020#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54021#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54545#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54212#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54213#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53050#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53051#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54723#L1462-3 assume !(1 == ~T8_E~0); 54724#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54591#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54592#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53305#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 53306#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 53448#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53618#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53619#L1502-3 assume !(1 == ~E_2~0); 54565#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54686#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53657#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53345#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 53346#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53312#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53313#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 54423#L1542-3 assume !(1 == ~E_10~0); 54551#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 54196#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 54197#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 53516#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53517#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52938#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53375#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 53376#L1947 assume !(0 == start_simulation_~tmp~3#1); 54329#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54519#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53577#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53000#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 53001#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54654#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54655#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 54815#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 53643#L1928-2 [2024-11-13 12:54:47,857 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:47,857 INFO L85 PathProgramCache]: Analyzing trace with hash -327400631, now seen corresponding path program 1 times [2024-11-13 12:54:47,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:47,857 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [190580254] [2024-11-13 12:54:47,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:47,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:47,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:47,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:47,955 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:47,956 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [190580254] [2024-11-13 12:54:47,956 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [190580254] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:47,956 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:47,956 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 12:54:47,956 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [407654948] [2024-11-13 12:54:47,956 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:47,956 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:47,957 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:47,957 INFO L85 PathProgramCache]: Analyzing trace with hash -2128870257, now seen corresponding path program 3 times [2024-11-13 12:54:47,957 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:47,957 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1765036871] [2024-11-13 12:54:47,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:47,957 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:47,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:48,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:48,040 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:48,040 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1765036871] [2024-11-13 12:54:48,040 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1765036871] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:48,040 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:48,041 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:48,041 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [549144474] [2024-11-13 12:54:48,041 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:48,041 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:48,041 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:48,042 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:54:48,042 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:54:48,042 INFO L87 Difference]: Start difference. First operand 2032 states and 2989 transitions. cyclomatic complexity: 958 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:48,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:48,153 INFO L93 Difference]: Finished difference Result 3789 states and 5556 transitions. [2024-11-13 12:54:48,153 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3789 states and 5556 transitions. [2024-11-13 12:54:48,174 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3614 [2024-11-13 12:54:48,189 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3789 states to 3789 states and 5556 transitions. [2024-11-13 12:54:48,189 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3789 [2024-11-13 12:54:48,193 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3789 [2024-11-13 12:54:48,193 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3789 states and 5556 transitions. [2024-11-13 12:54:48,199 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:48,200 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3789 states and 5556 transitions. [2024-11-13 12:54:48,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3789 states and 5556 transitions. [2024-11-13 12:54:48,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3789 to 3789. [2024-11-13 12:54:48,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3789 states, 3789 states have (on average 1.466349960411718) internal successors, (5556), 3788 states have internal predecessors, (5556), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:48,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3789 states to 3789 states and 5556 transitions. [2024-11-13 12:54:48,286 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3789 states and 5556 transitions. [2024-11-13 12:54:48,286 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:54:48,287 INFO L424 stractBuchiCegarLoop]: Abstraction has 3789 states and 5556 transitions. [2024-11-13 12:54:48,287 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 12:54:48,287 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3789 states and 5556 transitions. [2024-11-13 12:54:48,304 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3614 [2024-11-13 12:54:48,304 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:48,304 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:48,307 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:48,308 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:48,308 INFO L745 eck$LassoCheckResult]: Stem: 59096#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 59097#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 60105#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60106#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60949#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 59685#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59686#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59757#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59758#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60213#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60214#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 59723#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59523#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59524#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59990#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 59991#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59872#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 59873#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 59497#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59498#L1279 assume !(0 == ~M_E~0); 60821#L1279-2 assume !(0 == ~T1_E~0); 59119#L1284-1 assume !(0 == ~T2_E~0); 59120#L1289-1 assume !(0 == ~T3_E~0); 59864#L1294-1 assume !(0 == ~T4_E~0); 59865#L1299-1 assume !(0 == ~T5_E~0); 59876#L1304-1 assume !(0 == ~T6_E~0); 60947#L1309-1 assume !(0 == ~T7_E~0); 60950#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59043#L1319-1 assume !(0 == ~T9_E~0); 59044#L1324-1 assume !(0 == ~T10_E~0); 59218#L1329-1 assume !(0 == ~T11_E~0); 59219#L1334-1 assume !(0 == ~T12_E~0); 60709#L1339-1 assume !(0 == ~T13_E~0); 60807#L1344-1 assume !(0 == ~E_M~0); 60808#L1349-1 assume !(0 == ~E_1~0); 60061#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 60062#L1359-1 assume !(0 == ~E_3~0); 60500#L1364-1 assume !(0 == ~E_4~0); 59346#L1369-1 assume !(0 == ~E_5~0); 59347#L1374-1 assume !(0 == ~E_6~0); 60069#L1379-1 assume !(0 == ~E_7~0); 60070#L1384-1 assume !(0 == ~E_8~0); 60149#L1389-1 assume !(0 == ~E_9~0); 60731#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 60732#L1399-1 assume !(0 == ~E_11~0); 60862#L1404-1 assume !(0 == ~E_12~0); 59445#L1409-1 assume !(0 == ~E_13~0); 59446#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60853#L628 assume !(1 == ~m_pc~0); 59345#L628-2 is_master_triggered_~__retres1~0#1 := 0; 59344#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59936#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59937#L1591 assume !(0 != activate_threads_~tmp~1#1); 60871#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59916#L647 assume 1 == ~t1_pc~0; 59270#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59271#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59970#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60458#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 60790#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60791#L666 assume 1 == ~t2_pc~0; 59116#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59117#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59261#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59262#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 60264#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60265#L685 assume !(1 == ~t3_pc~0); 60371#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 60370#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60444#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60113#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60114#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59571#L704 assume 1 == ~t4_pc~0; 59572#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 60125#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58905#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58906#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 59968#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59969#L723 assume !(1 == ~t5_pc~0); 60110#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 60344#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60492#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 60246#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 60247#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59329#L742 assume 1 == ~t6_pc~0; 59330#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59486#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59250#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59012#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 59013#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59407#L761 assume !(1 == ~t7_pc~0); 59408#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 59284#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59285#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 60116#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 60117#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59033#L780 assume 1 == ~t8_pc~0; 59034#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 59319#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59320#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 60076#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 60077#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60201#L799 assume 1 == ~t9_pc~0; 60312#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 59036#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59037#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59313#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 60417#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 60225#L818 assume !(1 == ~t10_pc~0); 58820#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 58821#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 60298#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 60228#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 60229#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60273#L837 assume 1 == ~t11_pc~0; 60274#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 60104#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 60795#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 60191#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 60192#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59927#L856 assume !(1 == ~t12_pc~0); 59928#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 60612#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58838#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 58839#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 60590#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 60825#L875 assume 1 == ~t13_pc~0; 59874#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59487#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 59488#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 59425#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 59426#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60297#L1427 assume !(1 == ~M_E~0); 60284#L1427-2 assume !(1 == ~T1_E~0); 59393#L1432-1 assume !(1 == ~T2_E~0); 59394#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60506#L1442-1 assume !(1 == ~T4_E~0); 60507#L1447-1 assume !(1 == ~T5_E~0); 60353#L1452-1 assume !(1 == ~T6_E~0); 58957#L1457-1 assume !(1 == ~T7_E~0); 58958#L1462-1 assume !(1 == ~T8_E~0); 60533#L1467-1 assume !(1 == ~T9_E~0); 60555#L1472-1 assume !(1 == ~T10_E~0); 60556#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 60293#L1482-1 assume !(1 == ~T12_E~0); 60294#L1487-1 assume !(1 == ~T13_E~0); 59293#L1492-1 assume !(1 == ~E_M~0); 59294#L1497-1 assume !(1 == ~E_1~0); 59667#L1502-1 assume !(1 == ~E_2~0); 59668#L1507-1 assume !(1 == ~E_3~0); 59167#L1512-1 assume !(1 == ~E_4~0); 59168#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 60637#L1522-1 assume !(1 == ~E_6~0); 59914#L1527-1 assume !(1 == ~E_7~0); 59915#L1532-1 assume !(1 == ~E_8~0); 60919#L1537-1 assume !(1 == ~E_9~0); 60132#L1542-1 assume !(1 == ~E_10~0); 59944#L1547-1 assume !(1 == ~E_11~0); 59945#L1552-1 assume !(1 == ~E_12~0); 58863#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 58864#L1562-1 assume { :end_inline_reset_delta_events } true; 59477#L1928-2 [2024-11-13 12:54:48,309 INFO L747 eck$LassoCheckResult]: Loop: 59477#L1928-2 assume !false; 59983#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 59552#L1254-1 assume !false; 59787#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 59192#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 59193#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 60651#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 60652#L1067 assume !(0 != eval_~tmp~0#1); 59858#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59454#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 59455#L1279-3 assume !(0 == ~M_E~0); 61033#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 59672#L1284-3 assume !(0 == ~T2_E~0); 59673#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 61032#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 61031#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 60054#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 60055#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 59532#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59533#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 60972#L1324-3 assume !(0 == ~T10_E~0); 61029#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 61028#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 59954#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 59955#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 60327#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 59515#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 59516#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 60280#L1364-3 assume !(0 == ~E_4~0); 60946#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 60748#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 59295#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 59296#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 59513#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 59514#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 59825#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 60965#L1404-3 assume !(0 == ~E_12~0); 60720#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 60721#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60162#L628-45 assume !(1 == ~m_pc~0); 60163#L628-47 is_master_triggered_~__retres1~0#1 := 0; 60913#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60914#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59549#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 59550#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60304#L647-45 assume 1 == ~t1_pc~0; 59113#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59114#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61019#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61018#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 60818#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59438#L666-45 assume 1 == ~t2_pc~0; 59440#L667-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60889#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60890#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60432#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60433#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61016#L685-45 assume 1 == ~t3_pc~0; 60066#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 60067#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61015#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60633#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60634#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60861#L704-45 assume !(1 == ~t4_pc~0); 58840#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 58841#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59718#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61011#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 61010#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60193#L723-45 assume !(1 == ~t5_pc~0); 60194#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 60733#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 61007#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59527#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 59528#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60960#L742-45 assume 1 == ~t6_pc~0; 61004#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 60278#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60279#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60313#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 60314#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60403#L761-45 assume !(1 == ~t7_pc~0); 60404#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 59789#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59790#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 61000#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 60999#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60724#L780-45 assume 1 == ~t8_pc~0; 59553#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 59182#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59183#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 60917#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 60918#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59947#L799-45 assume 1 == ~t9_pc~0; 59948#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 59374#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60977#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 60351#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 60352#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 60992#L818-45 assume 1 == ~t10_pc~0; 60457#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 59210#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 60571#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59715#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59716#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60801#L837-45 assume !(1 == ~t11_pc~0); 60802#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 59791#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59163#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59164#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 59233#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59234#L856-45 assume 1 == ~t12_pc~0; 60982#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 60631#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 60632#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 60986#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 60072#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 60073#L875-45 assume 1 == ~t13_pc~0; 60036#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 60037#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 60467#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 60468#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 60985#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60707#L1427-3 assume !(1 == ~M_E~0); 59859#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 59860#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 61524#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61520#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 61516#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 61515#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 61514#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 61513#L1462-3 assume !(1 == ~T8_E~0); 61512#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 61511#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 61510#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 61509#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 61508#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 61507#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 61506#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 61505#L1502-3 assume !(1 == ~E_2~0); 61504#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 61503#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61502#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 61501#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 61500#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 61499#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 61498#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 61497#L1542-3 assume !(1 == ~E_10~0); 61496#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 60039#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 60040#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 61491#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 61090#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 61077#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 61076#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 61075#L1947 assume !(0 == start_simulation_~tmp~3#1); 61073#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 60513#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 59411#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58828#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 58829#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60543#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60544#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 60730#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 59477#L1928-2 [2024-11-13 12:54:48,309 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:48,309 INFO L85 PathProgramCache]: Analyzing trace with hash -867830137, now seen corresponding path program 1 times [2024-11-13 12:54:48,310 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:48,310 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1758959509] [2024-11-13 12:54:48,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:48,310 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:48,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:48,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:48,435 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:48,435 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1758959509] [2024-11-13 12:54:48,435 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1758959509] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:48,435 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:48,435 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:48,435 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [903719633] [2024-11-13 12:54:48,436 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:48,437 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:48,437 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:48,437 INFO L85 PathProgramCache]: Analyzing trace with hash 987844107, now seen corresponding path program 1 times [2024-11-13 12:54:48,437 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:48,437 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [703441164] [2024-11-13 12:54:48,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:48,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:48,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:48,525 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:48,525 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:48,525 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [703441164] [2024-11-13 12:54:48,526 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [703441164] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:48,526 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:48,526 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:48,526 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [196738514] [2024-11-13 12:54:48,526 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:48,526 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:48,526 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:48,527 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 12:54:48,527 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 12:54:48,527 INFO L87 Difference]: Start difference. First operand 3789 states and 5556 transitions. cyclomatic complexity: 1768 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:48,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:48,708 INFO L93 Difference]: Finished difference Result 5538 states and 8105 transitions. [2024-11-13 12:54:48,708 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5538 states and 8105 transitions. [2024-11-13 12:54:48,739 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5343 [2024-11-13 12:54:48,760 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5538 states to 5538 states and 8105 transitions. [2024-11-13 12:54:48,760 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5538 [2024-11-13 12:54:48,766 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5538 [2024-11-13 12:54:48,766 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5538 states and 8105 transitions. [2024-11-13 12:54:48,774 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:48,774 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5538 states and 8105 transitions. [2024-11-13 12:54:48,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5538 states and 8105 transitions. [2024-11-13 12:54:48,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5538 to 3789. [2024-11-13 12:54:48,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3789 states, 3789 states have (on average 1.4655581947743468) internal successors, (5553), 3788 states have internal predecessors, (5553), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:48,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3789 states to 3789 states and 5553 transitions. [2024-11-13 12:54:48,931 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3789 states and 5553 transitions. [2024-11-13 12:54:48,932 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 12:54:48,932 INFO L424 stractBuchiCegarLoop]: Abstraction has 3789 states and 5553 transitions. [2024-11-13 12:54:48,932 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 12:54:48,933 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3789 states and 5553 transitions. [2024-11-13 12:54:48,948 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3614 [2024-11-13 12:54:48,949 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:48,949 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:48,952 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:48,952 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:48,952 INFO L745 eck$LassoCheckResult]: Stem: 68433#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 68434#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 69424#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69425#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 70148#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 69015#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69016#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69086#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69087#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69529#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 69530#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 69052#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 68854#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 68855#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 69315#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 69316#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 69200#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 69201#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 68828#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68829#L1279 assume !(0 == ~M_E~0); 70057#L1279-2 assume !(0 == ~T1_E~0); 68454#L1284-1 assume !(0 == ~T2_E~0); 68455#L1289-1 assume !(0 == ~T3_E~0); 69192#L1294-1 assume !(0 == ~T4_E~0); 69193#L1299-1 assume !(0 == ~T5_E~0); 69204#L1304-1 assume !(0 == ~T6_E~0); 70145#L1309-1 assume !(0 == ~T7_E~0); 70149#L1314-1 assume !(0 == ~T8_E~0); 68380#L1319-1 assume !(0 == ~T9_E~0); 68381#L1324-1 assume !(0 == ~T10_E~0); 68552#L1329-1 assume !(0 == ~T11_E~0); 68553#L1334-1 assume !(0 == ~T12_E~0); 69972#L1339-1 assume !(0 == ~T13_E~0); 70047#L1344-1 assume !(0 == ~E_M~0); 70048#L1349-1 assume !(0 == ~E_1~0); 69385#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 69386#L1359-1 assume !(0 == ~E_3~0); 69791#L1364-1 assume !(0 == ~E_4~0); 68678#L1369-1 assume !(0 == ~E_5~0); 68679#L1374-1 assume !(0 == ~E_6~0); 69392#L1379-1 assume !(0 == ~E_7~0); 69393#L1384-1 assume !(0 == ~E_8~0); 69468#L1389-1 assume !(0 == ~E_9~0); 69992#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 69993#L1399-1 assume !(0 == ~E_11~0); 70093#L1404-1 assume !(0 == ~E_12~0); 68776#L1409-1 assume !(0 == ~E_13~0); 68777#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70086#L628 assume !(1 == ~m_pc~0); 68677#L628-2 is_master_triggered_~__retres1~0#1 := 0; 68676#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69263#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69264#L1591 assume !(0 != activate_threads_~tmp~1#1); 70102#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69244#L647 assume 1 == ~t1_pc~0; 68605#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 68606#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69295#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69754#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 70035#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70036#L666 assume 1 == ~t2_pc~0; 68451#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 68452#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68595#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 68596#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 69579#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69580#L685 assume !(1 == ~t3_pc~0); 69674#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69673#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69743#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69433#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69434#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68902#L704 assume 1 == ~t4_pc~0; 68903#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 69444#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68242#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 68243#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 69293#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69294#L723 assume !(1 == ~t5_pc~0); 69429#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 69648#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69784#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69561#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 69562#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68661#L742 assume 1 == ~t6_pc~0; 68662#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 68817#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68584#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 68349#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 68350#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68738#L761 assume !(1 == ~t7_pc~0); 68739#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 68616#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68617#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 69435#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 69436#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68370#L780 assume 1 == ~t8_pc~0; 68371#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 68651#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68652#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69397#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 69398#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 69517#L799 assume 1 == ~t9_pc~0; 69619#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 68373#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 68374#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 68645#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 69719#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69540#L818 assume !(1 == ~t10_pc~0); 68157#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 68158#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69611#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69543#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 69544#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69586#L837 assume 1 == ~t11_pc~0; 69587#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 69423#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 70039#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 69507#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 69508#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 69255#L856 assume !(1 == ~t12_pc~0); 69256#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 69892#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 68175#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 68176#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 69872#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 70060#L875 assume 1 == ~t13_pc~0; 69202#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 68818#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 68819#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 68756#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 68757#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69608#L1427 assume !(1 == ~M_E~0); 69595#L1427-2 assume !(1 == ~T1_E~0); 68725#L1432-1 assume !(1 == ~T2_E~0); 68726#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69796#L1442-1 assume !(1 == ~T4_E~0); 69797#L1447-1 assume !(1 == ~T5_E~0); 69657#L1452-1 assume !(1 == ~T6_E~0); 68294#L1457-1 assume !(1 == ~T7_E~0); 68295#L1462-1 assume !(1 == ~T8_E~0); 69817#L1467-1 assume !(1 == ~T9_E~0); 69837#L1472-1 assume !(1 == ~T10_E~0); 69838#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69604#L1482-1 assume !(1 == ~T12_E~0); 69605#L1487-1 assume !(1 == ~T13_E~0); 68625#L1492-1 assume !(1 == ~E_M~0); 68626#L1497-1 assume !(1 == ~E_1~0); 68997#L1502-1 assume !(1 == ~E_2~0); 68998#L1507-1 assume !(1 == ~E_3~0); 68502#L1512-1 assume !(1 == ~E_4~0); 68503#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 69912#L1522-1 assume !(1 == ~E_6~0); 69242#L1527-1 assume !(1 == ~E_7~0); 69243#L1532-1 assume !(1 == ~E_8~0); 70129#L1537-1 assume !(1 == ~E_9~0); 69454#L1542-1 assume !(1 == ~E_10~0); 69271#L1547-1 assume !(1 == ~E_11~0); 69272#L1552-1 assume !(1 == ~E_12~0); 68200#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 68201#L1562-1 assume { :end_inline_reset_delta_events } true; 68808#L1928-2 [2024-11-13 12:54:48,953 INFO L747 eck$LassoCheckResult]: Loop: 68808#L1928-2 assume !false; 69308#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68883#L1254-1 assume !false; 69116#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68527#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68528#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68727#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 69897#L1067 assume !(0 != eval_~tmp~0#1); 69186#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68785#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68786#L1279-3 assume !(0 == ~M_E~0); 69017#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69001#L1284-3 assume !(0 == ~T2_E~0); 69002#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 68982#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 68983#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 69378#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 69379#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 68863#L1314-3 assume !(0 == ~T8_E~0); 68864#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 69860#L1324-3 assume !(0 == ~T10_E~0); 68500#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 68501#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 69277#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 69278#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 69583#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 68846#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 68847#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69591#L1364-3 assume !(0 == ~E_4~0); 70128#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 70007#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 68629#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 68630#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 68844#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 68845#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 69152#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 70017#L1404-3 assume !(0 == ~E_12~0); 69982#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 69983#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69480#L628-45 assume 1 == ~m_pc~0; 69147#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 69149#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69663#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 68880#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 68881#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69615#L647-45 assume 1 == ~t1_pc~0; 68448#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 68449#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69396#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68558#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68559#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68769#L666-45 assume 1 == ~t2_pc~0; 68771#L667-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 69262#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69661#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69662#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 69727#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68310#L685-45 assume 1 == ~t3_pc~0; 68311#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 69391#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70049#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69910#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69911#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70059#L704-45 assume !(1 == ~t4_pc~0); 68180#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 68181#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69047#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69935#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70161#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69509#L723-45 assume 1 == ~t5_pc~0; 69511#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 69994#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70118#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68858#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 68859#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69880#L742-45 assume !(1 == ~t6_pc~0); 69124#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 69125#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69335#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69336#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 69620#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69707#L761-45 assume 1 == ~t7_pc~0; 69709#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 69118#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69119#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68506#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 68507#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 69986#L780-45 assume !(1 == ~t8_pc~0); 68885#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 68515#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68516#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 70126#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 68486#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68487#L799-45 assume !(1 == ~t9_pc~0); 68704#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 68705#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69772#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69655#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 69656#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 68425#L818-45 assume !(1 == ~t10_pc~0); 68427#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 68544#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69633#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69042#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 69043#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69752#L837-45 assume 1 == ~t11_pc~0; 70044#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 68975#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68496#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 68497#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 68567#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 68568#L856-45 assume !(1 == ~t12_pc~0); 68569#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 68570#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 69804#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 69805#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 69394#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 69395#L875-45 assume 1 == ~t13_pc~0; 69362#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 69363#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 69421#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 69763#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 70025#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69970#L1427-3 assume !(1 == ~M_E~0); 69187#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69188#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69714#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69380#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69381#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 68215#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 68216#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 69895#L1462-3 assume !(1 == ~T8_E~0); 69896#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 69760#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 69761#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 68470#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 68471#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 68613#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 68783#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 68784#L1502-3 assume !(1 == ~E_2~0); 69734#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69858#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 68822#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 68510#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 68511#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 68477#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 68478#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 69592#L1542-3 assume !(1 == ~E_10~0); 69720#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 69365#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 69366#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 68681#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68682#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68103#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68538#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 68539#L1947 assume !(0 == start_simulation_~tmp~3#1); 69498#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69688#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68742#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68165#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 68166#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69825#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69826#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 69990#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 68808#L1928-2 [2024-11-13 12:54:48,953 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:48,954 INFO L85 PathProgramCache]: Analyzing trace with hash 1809696709, now seen corresponding path program 1 times [2024-11-13 12:54:48,954 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:48,954 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [977562198] [2024-11-13 12:54:48,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:48,954 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:48,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:49,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:49,057 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:49,057 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [977562198] [2024-11-13 12:54:49,057 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [977562198] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:49,057 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:49,057 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 12:54:49,058 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1827174954] [2024-11-13 12:54:49,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:49,058 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:49,058 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:49,058 INFO L85 PathProgramCache]: Analyzing trace with hash -1077773686, now seen corresponding path program 1 times [2024-11-13 12:54:49,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:49,058 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1774672117] [2024-11-13 12:54:49,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:49,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:49,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:49,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:49,165 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:49,165 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1774672117] [2024-11-13 12:54:49,165 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1774672117] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:49,165 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:49,165 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:49,165 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1551383373] [2024-11-13 12:54:49,166 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:49,166 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:49,166 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:49,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:54:49,166 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:54:49,167 INFO L87 Difference]: Start difference. First operand 3789 states and 5553 transitions. cyclomatic complexity: 1765 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:49,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:49,287 INFO L93 Difference]: Finished difference Result 3789 states and 5515 transitions. [2024-11-13 12:54:49,287 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3789 states and 5515 transitions. [2024-11-13 12:54:49,306 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3614 [2024-11-13 12:54:49,320 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3789 states to 3789 states and 5515 transitions. [2024-11-13 12:54:49,320 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3789 [2024-11-13 12:54:49,324 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3789 [2024-11-13 12:54:49,324 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3789 states and 5515 transitions. [2024-11-13 12:54:49,330 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:49,330 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3789 states and 5515 transitions. [2024-11-13 12:54:49,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3789 states and 5515 transitions. [2024-11-13 12:54:49,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3789 to 3789. [2024-11-13 12:54:49,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3789 states, 3789 states have (on average 1.4555291633676433) internal successors, (5515), 3788 states have internal predecessors, (5515), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:49,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3789 states to 3789 states and 5515 transitions. [2024-11-13 12:54:49,402 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3789 states and 5515 transitions. [2024-11-13 12:54:49,403 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:54:49,403 INFO L424 stractBuchiCegarLoop]: Abstraction has 3789 states and 5515 transitions. [2024-11-13 12:54:49,403 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 12:54:49,403 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3789 states and 5515 transitions. [2024-11-13 12:54:49,420 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3614 [2024-11-13 12:54:49,420 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:49,420 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:49,423 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:49,423 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:49,423 INFO L745 eck$LassoCheckResult]: Stem: 76018#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 76019#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 77016#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77017#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77773#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 76601#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76602#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76672#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76673#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77124#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 77125#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76638#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76441#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 76442#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 76902#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 76903#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 76787#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 76788#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 76416#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76417#L1279 assume !(0 == ~M_E~0); 77678#L1279-2 assume !(0 == ~T1_E~0); 76038#L1284-1 assume !(0 == ~T2_E~0); 76039#L1289-1 assume !(0 == ~T3_E~0); 76779#L1294-1 assume !(0 == ~T4_E~0); 76780#L1299-1 assume !(0 == ~T5_E~0); 76791#L1304-1 assume !(0 == ~T6_E~0); 77771#L1309-1 assume !(0 == ~T7_E~0); 77774#L1314-1 assume !(0 == ~T8_E~0); 75965#L1319-1 assume !(0 == ~T9_E~0); 75966#L1324-1 assume !(0 == ~T10_E~0); 76139#L1329-1 assume !(0 == ~T11_E~0); 76140#L1334-1 assume !(0 == ~T12_E~0); 77584#L1339-1 assume !(0 == ~T13_E~0); 77668#L1344-1 assume !(0 == ~E_M~0); 77669#L1349-1 assume !(0 == ~E_1~0); 76973#L1354-1 assume !(0 == ~E_2~0); 76974#L1359-1 assume !(0 == ~E_3~0); 77395#L1364-1 assume !(0 == ~E_4~0); 76266#L1369-1 assume !(0 == ~E_5~0); 76267#L1374-1 assume !(0 == ~E_6~0); 76980#L1379-1 assume !(0 == ~E_7~0); 76981#L1384-1 assume !(0 == ~E_8~0); 77060#L1389-1 assume !(0 == ~E_9~0); 77606#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 77607#L1399-1 assume !(0 == ~E_11~0); 77719#L1404-1 assume !(0 == ~E_12~0); 76364#L1409-1 assume !(0 == ~E_13~0); 76365#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77714#L628 assume !(1 == ~m_pc~0); 76265#L628-2 is_master_triggered_~__retres1~0#1 := 0; 76264#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76850#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76851#L1591 assume !(0 != activate_threads_~tmp~1#1); 77728#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76831#L647 assume 1 == ~t1_pc~0; 76193#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 76194#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76882#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77356#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 77656#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77657#L666 assume !(1 == ~t2_pc~0); 76037#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 76208#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76183#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76184#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 77174#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77175#L685 assume !(1 == ~t3_pc~0); 77270#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 77269#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77342#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77025#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77026#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76489#L704 assume 1 == ~t4_pc~0; 76490#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 77036#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75827#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 75828#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 76880#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76881#L723 assume !(1 == ~t5_pc~0); 77021#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 77244#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77388#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 77156#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 77157#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76249#L742 assume 1 == ~t6_pc~0; 76250#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 76405#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76172#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75933#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 75934#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76327#L761 assume !(1 == ~t7_pc~0); 76328#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 76204#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76205#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77027#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 77028#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75954#L780 assume 1 == ~t8_pc~0; 75955#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 76239#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76240#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 76985#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 76986#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77110#L799 assume 1 == ~t9_pc~0; 77214#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 75957#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75958#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 76234#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 77315#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77135#L818 assume !(1 == ~t10_pc~0); 75742#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 75743#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 77206#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 77138#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77139#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77181#L837 assume 1 == ~t11_pc~0; 77182#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 77014#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77660#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 77099#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 77100#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 76842#L856 assume !(1 == ~t12_pc~0); 76843#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 77497#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 75760#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 75761#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 77477#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 77683#L875 assume 1 == ~t13_pc~0; 76789#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 76406#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 76407#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 76345#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 76346#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77203#L1427 assume !(1 == ~M_E~0); 77190#L1427-2 assume !(1 == ~T1_E~0); 76313#L1432-1 assume !(1 == ~T2_E~0); 76314#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77400#L1442-1 assume !(1 == ~T4_E~0); 77401#L1447-1 assume !(1 == ~T5_E~0); 77253#L1452-1 assume !(1 == ~T6_E~0); 75878#L1457-1 assume !(1 == ~T7_E~0); 75879#L1462-1 assume !(1 == ~T8_E~0); 77421#L1467-1 assume !(1 == ~T9_E~0); 77441#L1472-1 assume !(1 == ~T10_E~0); 77442#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 77199#L1482-1 assume !(1 == ~T12_E~0); 77200#L1487-1 assume !(1 == ~T13_E~0); 76214#L1492-1 assume !(1 == ~E_M~0); 76215#L1497-1 assume !(1 == ~E_1~0); 76583#L1502-1 assume !(1 == ~E_2~0); 76584#L1507-1 assume !(1 == ~E_3~0); 76087#L1512-1 assume !(1 == ~E_4~0); 76088#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 77517#L1522-1 assume !(1 == ~E_6~0); 76829#L1527-1 assume !(1 == ~E_7~0); 76830#L1532-1 assume !(1 == ~E_8~0); 77755#L1537-1 assume !(1 == ~E_9~0); 77046#L1542-1 assume !(1 == ~E_10~0); 76858#L1547-1 assume !(1 == ~E_11~0); 76859#L1552-1 assume !(1 == ~E_12~0); 75785#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 75786#L1562-1 assume { :end_inline_reset_delta_events } true; 76396#L1928-2 [2024-11-13 12:54:49,424 INFO L747 eck$LassoCheckResult]: Loop: 76396#L1928-2 assume !false; 77015#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76703#L1254-1 assume !false; 76704#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 76114#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 76115#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77528#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 77529#L1067 assume !(0 != eval_~tmp~0#1); 77798#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77797#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77709#L1279-3 assume !(0 == ~M_E~0); 77710#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 79255#L1284-3 assume !(0 == ~T2_E~0); 79254#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 79253#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 79252#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 79251#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 79250#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 79249#L1314-3 assume !(0 == ~T8_E~0); 79248#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 79247#L1324-3 assume !(0 == ~T10_E~0); 79246#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 79245#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 79244#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 79243#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 79242#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 79241#L1354-3 assume !(0 == ~E_2~0); 79240#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 79239#L1364-3 assume !(0 == ~E_4~0); 79238#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 79237#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 79236#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 79235#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 79234#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 79233#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 79232#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 79231#L1404-3 assume !(0 == ~E_12~0); 79230#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 79229#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79228#L628-45 assume 1 == ~m_pc~0; 79227#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 79225#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79224#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 79223#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 79222#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 79221#L647-45 assume 1 == ~t1_pc~0; 79219#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 79218#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 79217#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 79216#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 79215#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78991#L666-45 assume !(1 == ~t2_pc~0); 78990#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 78989#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78988#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 78987#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78986#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78985#L685-45 assume 1 == ~t3_pc~0; 78983#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 78982#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78981#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78980#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78979#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78978#L704-45 assume 1 == ~t4_pc~0; 78977#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 78975#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78974#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 78973#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 78972#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78971#L723-45 assume 1 == ~t5_pc~0; 78969#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 78968#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78967#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76445#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 76446#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77485#L742-45 assume !(1 == ~t6_pc~0); 76712#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 76713#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76922#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76923#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 77215#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77302#L761-45 assume !(1 == ~t7_pc~0); 77303#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 76706#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76707#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76091#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 76092#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77789#L780-45 assume 1 == ~t8_pc~0; 78471#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 78470#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 78469#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78468#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 78467#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78466#L799-45 assume 1 == ~t9_pc~0; 78465#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 78463#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 78462#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 78461#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 78460#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 78459#L818-45 assume 1 == ~t10_pc~0; 78457#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 78456#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78455#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 78454#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 78453#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 78452#L837-45 assume 1 == ~t11_pc~0; 78451#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 78449#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 78448#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 78447#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 78446#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 78445#L856-45 assume 1 == ~t12_pc~0; 78443#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 78442#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 78441#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 78440#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 78439#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 78438#L875-45 assume 1 == ~t13_pc~0; 78437#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 78435#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 78434#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 78433#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 78432#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78431#L1427-3 assume !(1 == ~M_E~0); 77582#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77686#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77310#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76968#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 76969#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 75800#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 75801#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 77500#L1462-3 assume !(1 == ~T8_E~0); 77501#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 77362#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 77363#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 76055#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 76056#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 76201#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 76366#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 76367#L1502-3 assume !(1 == ~E_2~0); 78036#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 78034#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 78032#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 78031#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 78030#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 78029#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 78028#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 78027#L1542-3 assume !(1 == ~E_10~0); 78026#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 78025#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 77601#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 76269#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 76270#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 75688#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77940#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 77939#L1947 assume !(0 == start_simulation_~tmp~3#1); 77937#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 77407#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 76331#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 75750#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 75751#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77426#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77427#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 77604#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 76396#L1928-2 [2024-11-13 12:54:49,424 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:49,424 INFO L85 PathProgramCache]: Analyzing trace with hash 350046660, now seen corresponding path program 1 times [2024-11-13 12:54:49,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:49,424 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1472741239] [2024-11-13 12:54:49,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:49,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:49,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:49,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:49,527 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:49,527 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1472741239] [2024-11-13 12:54:49,528 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1472741239] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:49,528 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:49,528 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:49,528 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005634199] [2024-11-13 12:54:49,528 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:49,528 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:49,528 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:49,528 INFO L85 PathProgramCache]: Analyzing trace with hash 1126583301, now seen corresponding path program 1 times [2024-11-13 12:54:49,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:49,529 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [566458529] [2024-11-13 12:54:49,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:49,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:49,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:49,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:49,606 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:49,606 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [566458529] [2024-11-13 12:54:49,606 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [566458529] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:49,606 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:49,606 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:49,606 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1162603877] [2024-11-13 12:54:49,606 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:49,606 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:49,607 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:49,607 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 12:54:49,607 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 12:54:49,607 INFO L87 Difference]: Start difference. First operand 3789 states and 5515 transitions. cyclomatic complexity: 1727 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:49,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:49,866 INFO L93 Difference]: Finished difference Result 5423 states and 7875 transitions. [2024-11-13 12:54:49,866 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5423 states and 7875 transitions. [2024-11-13 12:54:49,894 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5243 [2024-11-13 12:54:49,914 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5423 states to 5423 states and 7875 transitions. [2024-11-13 12:54:49,914 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5423 [2024-11-13 12:54:49,920 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5423 [2024-11-13 12:54:49,920 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5423 states and 7875 transitions. [2024-11-13 12:54:49,928 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:49,928 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5423 states and 7875 transitions. [2024-11-13 12:54:49,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5423 states and 7875 transitions. [2024-11-13 12:54:49,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5423 to 3789. [2024-11-13 12:54:49,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3789 states, 3789 states have (on average 1.4547373977302718) internal successors, (5512), 3788 states have internal predecessors, (5512), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:50,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3789 states to 3789 states and 5512 transitions. [2024-11-13 12:54:50,007 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3789 states and 5512 transitions. [2024-11-13 12:54:50,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 12:54:50,008 INFO L424 stractBuchiCegarLoop]: Abstraction has 3789 states and 5512 transitions. [2024-11-13 12:54:50,008 INFO L331 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-13 12:54:50,008 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3789 states and 5512 transitions. [2024-11-13 12:54:50,024 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3614 [2024-11-13 12:54:50,024 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:50,024 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:50,027 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:50,027 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:50,028 INFO L745 eck$LassoCheckResult]: Stem: 85242#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 85243#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 86254#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86255#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 87045#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 85832#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 85833#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 85905#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 85906#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86360#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 86361#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 85871#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 85667#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 85668#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 86138#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 86139#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 86023#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 86024#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 85640#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 85641#L1279 assume !(0 == ~M_E~0); 86929#L1279-2 assume !(0 == ~T1_E~0); 85262#L1284-1 assume !(0 == ~T2_E~0); 85263#L1289-1 assume !(0 == ~T3_E~0); 86015#L1294-1 assume !(0 == ~T4_E~0); 86016#L1299-1 assume !(0 == ~T5_E~0); 86027#L1304-1 assume !(0 == ~T6_E~0); 87042#L1309-1 assume !(0 == ~T7_E~0); 87046#L1314-1 assume !(0 == ~T8_E~0); 85188#L1319-1 assume !(0 == ~T9_E~0); 85189#L1324-1 assume !(0 == ~T10_E~0); 85361#L1329-1 assume !(0 == ~T11_E~0); 85362#L1334-1 assume !(0 == ~T12_E~0); 86828#L1339-1 assume !(0 == ~T13_E~0); 86915#L1344-1 assume !(0 == ~E_M~0); 86916#L1349-1 assume !(0 == ~E_1~0); 86211#L1354-1 assume !(0 == ~E_2~0); 86212#L1359-1 assume !(0 == ~E_3~0); 86636#L1364-1 assume !(0 == ~E_4~0); 85489#L1369-1 assume !(0 == ~E_5~0); 85490#L1374-1 assume !(0 == ~E_6~0); 86218#L1379-1 assume !(0 == ~E_7~0); 86219#L1384-1 assume !(0 == ~E_8~0); 86298#L1389-1 assume !(0 == ~E_9~0); 86851#L1394-1 assume !(0 == ~E_10~0); 86852#L1399-1 assume !(0 == ~E_11~0); 86971#L1404-1 assume !(0 == ~E_12~0); 85587#L1409-1 assume !(0 == ~E_13~0); 85588#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86961#L628 assume !(1 == ~m_pc~0); 85488#L628-2 is_master_triggered_~__retres1~0#1 := 0; 85487#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 86086#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 86087#L1591 assume !(0 != activate_threads_~tmp~1#1); 86980#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86067#L647 assume 1 == ~t1_pc~0; 85415#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85416#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86118#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 86598#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 86903#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86904#L666 assume !(1 == ~t2_pc~0); 85261#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 85430#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85405#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 85406#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 86412#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86413#L685 assume !(1 == ~t3_pc~0); 86512#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 86511#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86583#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86263#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 86264#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85715#L704 assume 1 == ~t4_pc~0; 85716#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 86274#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85049#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 85050#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 86116#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86117#L723 assume !(1 == ~t5_pc~0); 86259#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 86483#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86629#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 86394#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 86395#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85472#L742 assume 1 == ~t6_pc~0; 85473#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 85629#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85394#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 85157#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 85158#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 85549#L761 assume !(1 == ~t7_pc~0); 85550#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 85426#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85427#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 86265#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 86266#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 85178#L780 assume 1 == ~t8_pc~0; 85179#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 85462#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85463#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86223#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 86224#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 86348#L799 assume 1 == ~t9_pc~0; 86454#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 85181#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 85182#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 85457#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 86557#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86371#L818 assume !(1 == ~t10_pc~0); 84964#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 84965#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86446#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 86374#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 86375#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 86419#L837 assume 1 == ~t11_pc~0; 86420#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 86253#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 86907#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 86338#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 86339#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 86078#L856 assume !(1 == ~t12_pc~0); 86079#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 86745#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 84982#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 84983#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 86724#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 86932#L875 assume 1 == ~t13_pc~0; 86025#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 85630#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 85631#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 85568#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 85569#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86441#L1427 assume !(1 == ~M_E~0); 86428#L1427-2 assume !(1 == ~T1_E~0); 85536#L1432-1 assume !(1 == ~T2_E~0); 85537#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86641#L1442-1 assume !(1 == ~T4_E~0); 86642#L1447-1 assume !(1 == ~T5_E~0); 86492#L1452-1 assume !(1 == ~T6_E~0); 85101#L1457-1 assume !(1 == ~T7_E~0); 85102#L1462-1 assume !(1 == ~T8_E~0); 86665#L1467-1 assume !(1 == ~T9_E~0); 86685#L1472-1 assume !(1 == ~T10_E~0); 86686#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 86437#L1482-1 assume !(1 == ~T12_E~0); 86438#L1487-1 assume !(1 == ~T13_E~0); 85436#L1492-1 assume !(1 == ~E_M~0); 85437#L1497-1 assume !(1 == ~E_1~0); 85813#L1502-1 assume !(1 == ~E_2~0); 85814#L1507-1 assume !(1 == ~E_3~0); 85311#L1512-1 assume !(1 == ~E_4~0); 85312#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 86765#L1522-1 assume !(1 == ~E_6~0); 86065#L1527-1 assume !(1 == ~E_7~0); 86066#L1532-1 assume !(1 == ~E_8~0); 87011#L1537-1 assume !(1 == ~E_9~0); 86284#L1542-1 assume !(1 == ~E_10~0); 86094#L1547-1 assume !(1 == ~E_11~0); 86095#L1552-1 assume !(1 == ~E_12~0); 85007#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 85008#L1562-1 assume { :end_inline_reset_delta_events } true; 85619#L1928-2 [2024-11-13 12:54:50,028 INFO L747 eck$LassoCheckResult]: Loop: 85619#L1928-2 assume !false; 86131#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85696#L1254-1 assume !false; 85937#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85336#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85337#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 85538#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 86750#L1067 assume !(0 != eval_~tmp~0#1); 86009#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 85596#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 85597#L1279-3 assume !(0 == ~M_E~0); 85836#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 85817#L1284-3 assume !(0 == ~T2_E~0); 85818#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 85797#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 85798#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 86204#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 86205#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 85676#L1314-3 assume !(0 == ~T8_E~0); 85677#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 86710#L1324-3 assume !(0 == ~T10_E~0); 85309#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 85310#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 86100#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 86101#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 86416#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 85659#L1354-3 assume !(0 == ~E_2~0); 85660#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 86424#L1364-3 assume !(0 == ~E_4~0); 87010#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 86867#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 85440#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 85441#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 85657#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 85658#L1394-3 assume !(0 == ~E_10~0); 85973#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 86879#L1404-3 assume !(0 == ~E_12~0); 86841#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 86842#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86310#L628-45 assume !(1 == ~m_pc~0); 85971#L628-47 is_master_triggered_~__retres1~0#1 := 0; 85972#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 86501#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 85693#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 85694#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86450#L647-45 assume 1 == ~t1_pc~0; 85257#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85258#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86222#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85368#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 85369#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 85580#L666-45 assume !(1 == ~t2_pc~0); 85581#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 86085#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86499#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 86500#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 86565#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85117#L685-45 assume !(1 == ~t3_pc~0); 85119#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 86217#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86920#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 87068#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 88638#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88636#L704-45 assume 1 == ~t4_pc~0; 88633#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 85865#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85866#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 86790#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87069#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86340#L723-45 assume !(1 == ~t5_pc~0); 86341#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 86853#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86996#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85671#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 85672#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86732#L742-45 assume !(1 == ~t6_pc~0); 85944#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 85945#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86158#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86159#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 86455#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86544#L761-45 assume !(1 == ~t7_pc~0); 86545#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 85939#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85940#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85315#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 85316#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86844#L780-45 assume 1 == ~t8_pc~0; 85697#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 85324#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85325#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 87004#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 85295#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85296#L799-45 assume 1 == ~t9_pc~0; 86097#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 85516#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86617#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 86490#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 86491#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 85235#L818-45 assume !(1 == ~t10_pc~0); 85237#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 85353#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86468#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 85862#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85863#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 86593#L837-45 assume 1 == ~t11_pc~0; 86912#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85790#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 85305#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 85306#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 85377#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 85378#L856-45 assume 1 == ~t12_pc~0; 86928#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 85380#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 86649#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86650#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 86220#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 86221#L875-45 assume 1 == ~t13_pc~0; 86188#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 86189#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86251#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 86607#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 86892#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86826#L1427-3 assume !(1 == ~M_E~0); 86010#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 86011#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86552#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86206#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86207#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 85022#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 85023#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 86748#L1462-3 assume !(1 == ~T8_E~0); 86749#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 86604#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 86605#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 85279#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 85280#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 85423#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 85594#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 85595#L1502-3 assume !(1 == ~E_2~0); 86572#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 86708#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 85634#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 85319#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 85320#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 85286#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 85287#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 86425#L1542-3 assume !(1 == ~E_10~0); 86558#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 86191#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 86192#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 85492#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85493#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 84910#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 85349#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 85350#L1947 assume !(0 == start_simulation_~tmp~3#1); 86329#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 86526#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85553#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 84972#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 84973#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86673#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86674#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 86849#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 85619#L1928-2 [2024-11-13 12:54:50,028 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:50,028 INFO L85 PathProgramCache]: Analyzing trace with hash -1492429054, now seen corresponding path program 1 times [2024-11-13 12:54:50,028 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:50,029 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1128944171] [2024-11-13 12:54:50,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:50,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:50,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:50,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:50,185 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:50,185 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1128944171] [2024-11-13 12:54:50,185 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1128944171] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:50,185 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:50,185 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 12:54:50,185 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [949890127] [2024-11-13 12:54:50,185 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:50,186 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:50,186 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:50,186 INFO L85 PathProgramCache]: Analyzing trace with hash 1643913415, now seen corresponding path program 1 times [2024-11-13 12:54:50,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:50,186 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [513004413] [2024-11-13 12:54:50,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:50,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:50,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:50,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:50,302 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:50,302 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [513004413] [2024-11-13 12:54:50,302 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [513004413] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:50,302 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:50,302 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 12:54:50,302 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1566583708] [2024-11-13 12:54:50,302 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:50,302 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:50,302 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:50,303 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:54:50,303 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:54:50,303 INFO L87 Difference]: Start difference. First operand 3789 states and 5512 transitions. cyclomatic complexity: 1724 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:50,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:50,488 INFO L93 Difference]: Finished difference Result 7171 states and 10378 transitions. [2024-11-13 12:54:50,489 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7171 states and 10378 transitions. [2024-11-13 12:54:50,527 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6993 [2024-11-13 12:54:50,555 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7171 states to 7171 states and 10378 transitions. [2024-11-13 12:54:50,555 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7171 [2024-11-13 12:54:50,563 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7171 [2024-11-13 12:54:50,563 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7171 states and 10378 transitions. [2024-11-13 12:54:50,573 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:50,573 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7171 states and 10378 transitions. [2024-11-13 12:54:50,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7171 states and 10378 transitions. [2024-11-13 12:54:50,681 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7171 to 7167. [2024-11-13 12:54:50,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7167 states, 7167 states have (on average 1.4474675596483884) internal successors, (10374), 7166 states have internal predecessors, (10374), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:50,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7167 states to 7167 states and 10374 transitions. [2024-11-13 12:54:50,717 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7167 states and 10374 transitions. [2024-11-13 12:54:50,718 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:54:50,718 INFO L424 stractBuchiCegarLoop]: Abstraction has 7167 states and 10374 transitions. [2024-11-13 12:54:50,718 INFO L331 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-13 12:54:50,718 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7167 states and 10374 transitions. [2024-11-13 12:54:50,742 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6989 [2024-11-13 12:54:50,742 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:50,742 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:50,745 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:50,745 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:50,746 INFO L745 eck$LassoCheckResult]: Stem: 96210#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 96211#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 97216#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 97217#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 98069#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 96789#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96790#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 96862#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96863#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 97324#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 97325#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 96825#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 96629#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 96630#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 97097#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 97098#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 96971#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 96972#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 96604#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96605#L1279 assume !(0 == ~M_E~0); 97944#L1279-2 assume !(0 == ~T1_E~0); 96230#L1284-1 assume !(0 == ~T2_E~0); 96231#L1289-1 assume !(0 == ~T3_E~0); 96968#L1294-1 assume !(0 == ~T4_E~0); 96969#L1299-1 assume !(0 == ~T5_E~0); 96980#L1304-1 assume !(0 == ~T6_E~0); 98068#L1309-1 assume !(0 == ~T7_E~0); 98071#L1314-1 assume !(0 == ~T8_E~0); 96154#L1319-1 assume !(0 == ~T9_E~0); 96155#L1324-1 assume !(0 == ~T10_E~0); 96331#L1329-1 assume !(0 == ~T11_E~0); 96332#L1334-1 assume !(0 == ~T12_E~0); 97835#L1339-1 assume !(0 == ~T13_E~0); 97931#L1344-1 assume !(0 == ~E_M~0); 97932#L1349-1 assume !(0 == ~E_1~0); 97173#L1354-1 assume !(0 == ~E_2~0); 97174#L1359-1 assume !(0 == ~E_3~0); 97622#L1364-1 assume !(0 == ~E_4~0); 96454#L1369-1 assume !(0 == ~E_5~0); 96455#L1374-1 assume !(0 == ~E_6~0); 97180#L1379-1 assume !(0 == ~E_7~0); 97181#L1384-1 assume !(0 == ~E_8~0); 97260#L1389-1 assume !(0 == ~E_9~0); 97857#L1394-1 assume !(0 == ~E_10~0); 97858#L1399-1 assume !(0 == ~E_11~0); 97983#L1404-1 assume !(0 == ~E_12~0); 96552#L1409-1 assume !(0 == ~E_13~0); 96553#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97976#L628 assume !(1 == ~m_pc~0); 96453#L628-2 is_master_triggered_~__retres1~0#1 := 0; 96452#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 97043#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 97044#L1591 assume !(0 != activate_threads_~tmp~1#1); 97995#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 97023#L647 assume !(1 == ~t1_pc~0); 97024#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 97075#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 97076#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 97574#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 97917#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 97918#L666 assume !(1 == ~t2_pc~0); 96229#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 96394#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96372#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 96373#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 97382#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 97383#L685 assume !(1 == ~t3_pc~0); 97482#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 97481#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 97559#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 97224#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 97225#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96677#L704 assume 1 == ~t4_pc~0; 96678#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 97236#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96018#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 96019#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 97073#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 97074#L723 assume !(1 == ~t5_pc~0); 97220#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 97453#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 97615#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 97359#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 97360#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 96436#L742 assume 1 == ~t6_pc~0; 96437#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 96593#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 96363#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 96122#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 96123#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 96514#L761 assume !(1 == ~t7_pc~0); 96515#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 96390#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 96391#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 97227#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 97228#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96146#L780 assume 1 == ~t8_pc~0; 96147#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 96427#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96428#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 97188#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 97189#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 97309#L799 assume 1 == ~t9_pc~0; 97420#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 96149#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 96150#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 96422#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 97530#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 97337#L818 assume !(1 == ~t10_pc~0); 95933#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 95934#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 97412#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 97342#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 97343#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 97389#L837 assume 1 == ~t11_pc~0; 97390#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 97214#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 97923#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 97300#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 97301#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 97032#L856 assume !(1 == ~t12_pc~0); 97033#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 97742#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 95951#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 95952#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 97713#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 97947#L875 assume 1 == ~t13_pc~0; 96978#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 96594#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 96595#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 96533#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 96534#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97411#L1427 assume !(1 == ~M_E~0); 97396#L1427-2 assume !(1 == ~T1_E~0); 96501#L1432-1 assume !(1 == ~T2_E~0); 96502#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 97629#L1442-1 assume !(1 == ~T4_E~0); 97630#L1447-1 assume !(1 == ~T5_E~0); 97462#L1452-1 assume !(1 == ~T6_E~0); 96069#L1457-1 assume !(1 == ~T7_E~0); 96070#L1462-1 assume !(1 == ~T8_E~0); 97652#L1467-1 assume !(1 == ~T9_E~0); 97676#L1472-1 assume !(1 == ~T10_E~0); 97677#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 97407#L1482-1 assume !(1 == ~T12_E~0); 97408#L1487-1 assume !(1 == ~T13_E~0); 96402#L1492-1 assume !(1 == ~E_M~0); 96403#L1497-1 assume !(1 == ~E_1~0); 96771#L1502-1 assume !(1 == ~E_2~0); 96772#L1507-1 assume !(1 == ~E_3~0); 96280#L1512-1 assume !(1 == ~E_4~0); 96281#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 97769#L1522-1 assume !(1 == ~E_6~0); 97020#L1527-1 assume !(1 == ~E_7~0); 97021#L1532-1 assume !(1 == ~E_8~0); 98036#L1537-1 assume !(1 == ~E_9~0); 97243#L1542-1 assume !(1 == ~E_10~0); 97050#L1547-1 assume !(1 == ~E_11~0); 97051#L1552-1 assume !(1 == ~E_12~0); 95974#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 95975#L1562-1 assume { :end_inline_reset_delta_events } true; 96583#L1928-2 [2024-11-13 12:54:50,746 INFO L747 eck$LassoCheckResult]: Loop: 96583#L1928-2 assume !false; 97090#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 96658#L1254-1 assume !false; 96894#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 96305#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 96306#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 96503#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 97747#L1067 assume !(0 != eval_~tmp~0#1); 97748#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 99075#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 99073#L1279-3 assume !(0 == ~M_E~0); 99070#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 99067#L1284-3 assume !(0 == ~T2_E~0); 99065#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 99063#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 99061#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 99059#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 99057#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 99054#L1314-3 assume !(0 == ~T8_E~0); 99052#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 99050#L1324-3 assume !(0 == ~T10_E~0); 99048#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 99046#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 99044#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 99041#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 99039#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 99037#L1354-3 assume !(0 == ~E_2~0); 99035#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 99033#L1364-3 assume !(0 == ~E_4~0); 99031#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 99030#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 99027#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 99025#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 99023#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 99021#L1394-3 assume !(0 == ~E_10~0); 99019#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 99017#L1404-3 assume !(0 == ~E_12~0); 99014#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 99012#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 99010#L628-45 assume 1 == ~m_pc~0; 99008#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 99005#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 99003#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 99000#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 98000#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 97418#L647-45 assume !(1 == ~t1_pc~0); 97419#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 97186#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 97187#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 96336#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 96337#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96545#L666-45 assume !(1 == ~t2_pc~0); 96546#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 97042#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 97468#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 97469#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 97541#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96085#L685-45 assume !(1 == ~t3_pc~0); 96087#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 97182#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 97934#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 97763#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 97764#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97945#L704-45 assume !(1 == ~t4_pc~0); 95953#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 95954#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96822#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 97796#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 98094#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 97304#L723-45 assume !(1 == ~t5_pc~0); 97305#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 97859#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 98017#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 96633#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 96634#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 97726#L742-45 assume !(1 == ~t6_pc~0); 96901#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 96902#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 97119#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 97120#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 97425#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 97516#L761-45 assume !(1 == ~t7_pc~0); 97517#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 96896#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 96897#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 96284#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 96285#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 97849#L780-45 assume 1 == ~t8_pc~0; 96659#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 96295#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96296#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 98029#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 96264#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 96265#L799-45 assume !(1 == ~t9_pc~0); 96481#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 96482#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 97596#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 97463#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 97464#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 96205#L818-45 assume !(1 == ~t10_pc~0); 96207#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 96324#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 97440#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 97694#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 97570#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 97571#L837-45 assume 1 == ~t11_pc~0; 97929#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 96750#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 96276#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 96277#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 96346#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 96347#L856-45 assume 1 == ~t12_pc~0; 97943#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 96349#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 97636#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 97637#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 97184#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 97185#L875-45 assume 1 == ~t13_pc~0; 97149#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 97150#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 97215#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 97585#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 97904#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97833#L1427-3 assume !(1 == ~M_E~0); 96963#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 96964#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 97950#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 100362#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 100360#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 100358#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 100356#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 100354#L1462-3 assume !(1 == ~T8_E~0); 100352#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 100349#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 100347#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 100345#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 100343#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 98998#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 98208#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 98192#L1502-3 assume !(1 == ~E_2~0); 98189#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 98186#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 98182#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 98178#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 98176#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 98173#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 98170#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 98168#L1542-3 assume !(1 == ~E_10~0); 98164#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 98165#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 99787#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 99785#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 98152#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 98138#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 98107#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 98106#L1947 assume !(0 == start_simulation_~tmp~3#1); 97497#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 97498#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 96518#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 95941#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 95942#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 97662#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 97663#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 97856#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 96583#L1928-2 [2024-11-13 12:54:50,746 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:50,747 INFO L85 PathProgramCache]: Analyzing trace with hash -121367293, now seen corresponding path program 1 times [2024-11-13 12:54:50,747 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:50,747 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [5239550] [2024-11-13 12:54:50,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:50,747 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:50,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:50,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:50,853 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:50,853 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [5239550] [2024-11-13 12:54:50,854 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [5239550] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:50,854 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:50,854 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 12:54:50,854 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1400662603] [2024-11-13 12:54:50,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:50,854 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:50,854 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:50,855 INFO L85 PathProgramCache]: Analyzing trace with hash -987036983, now seen corresponding path program 1 times [2024-11-13 12:54:50,855 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:50,855 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1341582317] [2024-11-13 12:54:50,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:50,855 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:50,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:50,963 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:50,963 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:50,963 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1341582317] [2024-11-13 12:54:50,963 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1341582317] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:50,963 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:50,963 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 12:54:50,963 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1019774931] [2024-11-13 12:54:50,963 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:50,964 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:50,964 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:50,965 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 12:54:50,965 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 12:54:50,965 INFO L87 Difference]: Start difference. First operand 7167 states and 10374 transitions. cyclomatic complexity: 3209 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:51,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:51,410 INFO L93 Difference]: Finished difference Result 7350 states and 10557 transitions. [2024-11-13 12:54:51,410 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7350 states and 10557 transitions. [2024-11-13 12:54:51,439 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7169 [2024-11-13 12:54:51,467 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7350 states to 7350 states and 10557 transitions. [2024-11-13 12:54:51,468 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7350 [2024-11-13 12:54:51,476 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7350 [2024-11-13 12:54:51,476 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7350 states and 10557 transitions. [2024-11-13 12:54:51,487 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:51,487 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7350 states and 10557 transitions. [2024-11-13 12:54:51,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7350 states and 10557 transitions. [2024-11-13 12:54:51,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7350 to 7350. [2024-11-13 12:54:51,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7350 states, 7350 states have (on average 1.4363265306122448) internal successors, (10557), 7349 states have internal predecessors, (10557), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:51,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7350 states to 7350 states and 10557 transitions. [2024-11-13 12:54:51,623 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7350 states and 10557 transitions. [2024-11-13 12:54:51,623 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 12:54:51,624 INFO L424 stractBuchiCegarLoop]: Abstraction has 7350 states and 10557 transitions. [2024-11-13 12:54:51,624 INFO L331 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-13 12:54:51,624 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7350 states and 10557 transitions. [2024-11-13 12:54:51,673 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7169 [2024-11-13 12:54:51,673 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:51,673 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:51,677 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:51,677 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:51,677 INFO L745 eck$LassoCheckResult]: Stem: 110737#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 110738#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 111758#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 111759#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 112675#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 111324#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 111325#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 111397#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 111398#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 111871#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 111872#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 111361#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 111158#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 111159#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 111639#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 111640#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 111507#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 111508#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 111133#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 111134#L1279 assume !(0 == ~M_E~0); 112538#L1279-2 assume !(0 == ~T1_E~0); 110758#L1284-1 assume !(0 == ~T2_E~0); 110759#L1289-1 assume !(0 == ~T3_E~0); 111504#L1294-1 assume !(0 == ~T4_E~0); 111505#L1299-1 assume !(0 == ~T5_E~0); 111516#L1304-1 assume !(0 == ~T6_E~0); 112674#L1309-1 assume !(0 == ~T7_E~0); 112677#L1314-1 assume !(0 == ~T8_E~0); 110682#L1319-1 assume !(0 == ~T9_E~0); 110683#L1324-1 assume !(0 == ~T10_E~0); 110857#L1329-1 assume !(0 == ~T11_E~0); 110858#L1334-1 assume !(0 == ~T12_E~0); 112416#L1339-1 assume !(0 == ~T13_E~0); 112526#L1344-1 assume !(0 == ~E_M~0); 112527#L1349-1 assume !(0 == ~E_1~0); 111713#L1354-1 assume !(0 == ~E_2~0); 111714#L1359-1 assume !(0 == ~E_3~0); 112186#L1364-1 assume !(0 == ~E_4~0); 110982#L1369-1 assume !(0 == ~E_5~0); 110983#L1374-1 assume !(0 == ~E_6~0); 111720#L1379-1 assume !(0 == ~E_7~0); 111721#L1384-1 assume !(0 == ~E_8~0); 111807#L1389-1 assume !(0 == ~E_9~0); 112440#L1394-1 assume !(0 == ~E_10~0); 112441#L1399-1 assume !(0 == ~E_11~0); 112583#L1404-1 assume !(0 == ~E_12~0); 111081#L1409-1 assume !(0 == ~E_13~0); 111082#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 112574#L628 assume !(1 == ~m_pc~0); 110981#L628-2 is_master_triggered_~__retres1~0#1 := 0; 110980#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 111582#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 111583#L1591 assume !(0 != activate_threads_~tmp~1#1); 112595#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111562#L647 assume !(1 == ~t1_pc~0); 111563#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 111617#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 111618#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 112139#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 112512#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112513#L666 assume !(1 == ~t2_pc~0); 110757#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 110922#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 110898#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 110899#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 111935#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 111936#L685 assume !(1 == ~t3_pc~0); 112046#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 112116#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112726#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 111768#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 111769#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 111209#L704 assume 1 == ~t4_pc~0; 111210#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 111783#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 110546#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 110547#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 111615#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 111616#L723 assume !(1 == ~t5_pc~0); 111763#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 112015#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 112179#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 111909#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 111910#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 110964#L742 assume 1 == ~t6_pc~0; 110965#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 111122#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 110889#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 110652#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 110653#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 111044#L761 assume !(1 == ~t7_pc~0); 111045#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 110918#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 110919#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 111772#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 111773#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 110674#L780 assume 1 == ~t8_pc~0; 110675#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 110955#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 110956#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 111730#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 111731#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 111857#L799 assume 1 == ~t9_pc~0; 111976#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 110677#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 110678#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 110950#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 112093#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 111885#L818 assume !(1 == ~t10_pc~0); 110461#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 110462#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 111967#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 111890#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 111891#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 111944#L837 assume 1 == ~t11_pc~0; 111945#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 111756#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 112516#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 111848#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 111849#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 111571#L856 assume !(1 == ~t12_pc~0); 111572#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 112314#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 110479#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 110480#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 112283#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 112543#L875 assume 1 == ~t13_pc~0; 111514#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 111123#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 111124#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 111062#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 111063#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 111966#L1427 assume !(1 == ~M_E~0); 111951#L1427-2 assume !(1 == ~T1_E~0); 111030#L1432-1 assume !(1 == ~T2_E~0); 111031#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 112193#L1442-1 assume !(1 == ~T4_E~0); 112194#L1447-1 assume !(1 == ~T5_E~0); 112027#L1452-1 assume !(1 == ~T6_E~0); 110597#L1457-1 assume !(1 == ~T7_E~0); 110598#L1462-1 assume !(1 == ~T8_E~0); 112217#L1467-1 assume !(1 == ~T9_E~0); 112246#L1472-1 assume !(1 == ~T10_E~0); 112247#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 111962#L1482-1 assume !(1 == ~T12_E~0); 111963#L1487-1 assume !(1 == ~T13_E~0); 110930#L1492-1 assume !(1 == ~E_M~0); 110931#L1497-1 assume !(1 == ~E_1~0); 111306#L1502-1 assume !(1 == ~E_2~0); 111307#L1507-1 assume !(1 == ~E_3~0); 110806#L1512-1 assume !(1 == ~E_4~0); 110807#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 112340#L1522-1 assume !(1 == ~E_6~0); 111557#L1527-1 assume !(1 == ~E_7~0); 111558#L1532-1 assume !(1 == ~E_8~0); 112642#L1537-1 assume !(1 == ~E_9~0); 111790#L1542-1 assume !(1 == ~E_10~0); 111589#L1547-1 assume !(1 == ~E_11~0); 111590#L1552-1 assume !(1 == ~E_12~0); 110502#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 110503#L1562-1 assume { :end_inline_reset_delta_events } true; 111113#L1928-2 [2024-11-13 12:54:51,678 INFO L747 eck$LassoCheckResult]: Loop: 111113#L1928-2 assume !false; 114243#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 114240#L1254-1 assume !false; 114239#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 110831#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 110832#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 112355#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 112356#L1067 assume !(0 != eval_~tmp~0#1); 111493#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 111494#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 112571#L1279-3 assume !(0 == ~M_E~0); 112572#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 117731#L1284-3 assume !(0 == ~T2_E~0); 117730#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 117729#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 117728#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 117727#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 117726#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 117725#L1314-3 assume !(0 == ~T8_E~0); 117724#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 117723#L1324-3 assume !(0 == ~T10_E~0); 117722#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 117721#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 117720#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 117719#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 117718#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 117717#L1354-3 assume !(0 == ~E_2~0); 117716#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 117715#L1364-3 assume !(0 == ~E_4~0); 117714#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 117713#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 117712#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 117711#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 117710#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 117709#L1394-3 assume !(0 == ~E_10~0); 117708#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 117707#L1404-3 assume !(0 == ~E_12~0); 117706#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 117705#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117704#L628-45 assume 1 == ~m_pc~0; 117703#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 117701#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117700#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 117699#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 117698#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117697#L647-45 assume !(1 == ~t1_pc~0); 117696#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 117695#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 117694#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 117693#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 117692#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 117690#L666-45 assume !(1 == ~t2_pc~0); 117689#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 117688#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 117687#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 117686#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 117685#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 117684#L685-45 assume 1 == ~t3_pc~0; 117683#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 117681#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 117679#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 117676#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 117675#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 117674#L704-45 assume 1 == ~t4_pc~0; 117673#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 117671#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 117670#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 117669#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 117668#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 117667#L723-45 assume 1 == ~t5_pc~0; 117665#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 117664#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 117663#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 117662#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 117661#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 117660#L742-45 assume !(1 == ~t6_pc~0); 117659#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 117657#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 117656#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 117655#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 117654#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 117653#L761-45 assume 1 == ~t7_pc~0; 117651#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 117650#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 117649#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 117648#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 117647#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 117646#L780-45 assume !(1 == ~t8_pc~0); 117643#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 117641#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 117639#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 117637#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 117194#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 117193#L799-45 assume !(1 == ~t9_pc~0); 117191#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 117190#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 117189#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 117188#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 117187#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 110732#L818-45 assume 1 == ~t10_pc~0; 110733#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 110850#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 112001#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 111356#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 111357#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 112136#L837-45 assume !(1 == ~t11_pc~0); 111282#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 111283#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 110802#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 110803#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 110872#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 110873#L856-45 assume 1 == ~t12_pc~0; 112537#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 110875#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 112202#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 112203#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 111726#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 111727#L875-45 assume 1 == ~t13_pc~0; 111690#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 111691#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 111757#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 112150#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 112498#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112414#L1427-3 assume !(1 == ~M_E~0); 111499#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 111500#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 112090#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 111711#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 111712#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 110519#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 110520#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 112317#L1462-3 assume !(1 == ~T8_E~0); 112318#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 112145#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 112146#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 110774#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 110775#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 110917#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 111088#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 111089#L1502-3 assume !(1 == ~E_2~0); 112112#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 112270#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 111127#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 110814#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 110815#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 110781#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 110782#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 111950#L1542-3 assume !(1 == ~E_10~0); 112096#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 111693#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 111694#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 110986#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 110987#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 110407#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 110844#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 110845#L1947 assume !(0 == start_simulation_~tmp~3#1); 111839#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 112061#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 114249#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 114248#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 114247#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 114246#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 114245#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 114244#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 111113#L1928-2 [2024-11-13 12:54:51,678 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:51,678 INFO L85 PathProgramCache]: Analyzing trace with hash -2061949307, now seen corresponding path program 1 times [2024-11-13 12:54:51,678 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:51,678 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [846360118] [2024-11-13 12:54:51,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:51,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:51,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:51,803 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:51,804 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:51,804 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [846360118] [2024-11-13 12:54:51,804 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [846360118] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:51,804 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:51,804 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 12:54:51,804 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [889327924] [2024-11-13 12:54:51,804 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:51,804 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:51,805 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:51,805 INFO L85 PathProgramCache]: Analyzing trace with hash 1242797062, now seen corresponding path program 1 times [2024-11-13 12:54:51,805 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:51,805 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [17432071] [2024-11-13 12:54:51,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:51,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:51,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:51,892 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:51,892 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:51,892 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [17432071] [2024-11-13 12:54:51,892 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [17432071] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:51,893 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:51,893 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:51,893 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1369939543] [2024-11-13 12:54:51,893 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:51,893 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:51,893 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:51,894 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:54:51,894 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:54:51,894 INFO L87 Difference]: Start difference. First operand 7350 states and 10557 transitions. cyclomatic complexity: 3209 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:52,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:52,141 INFO L93 Difference]: Finished difference Result 14052 states and 20097 transitions. [2024-11-13 12:54:52,141 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14052 states and 20097 transitions. [2024-11-13 12:54:52,214 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13860 [2024-11-13 12:54:52,279 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14052 states to 14052 states and 20097 transitions. [2024-11-13 12:54:52,280 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14052 [2024-11-13 12:54:52,303 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14052 [2024-11-13 12:54:52,303 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14052 states and 20097 transitions. [2024-11-13 12:54:52,327 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:52,327 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14052 states and 20097 transitions. [2024-11-13 12:54:52,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14052 states and 20097 transitions. [2024-11-13 12:54:52,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14052 to 14044. [2024-11-13 12:54:52,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14044 states, 14044 states have (on average 1.4304329250925663) internal successors, (20089), 14043 states have internal predecessors, (20089), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:52,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14044 states to 14044 states and 20089 transitions. [2024-11-13 12:54:52,615 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14044 states and 20089 transitions. [2024-11-13 12:54:52,616 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:54:52,616 INFO L424 stractBuchiCegarLoop]: Abstraction has 14044 states and 20089 transitions. [2024-11-13 12:54:52,616 INFO L331 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-13 12:54:52,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14044 states and 20089 transitions. [2024-11-13 12:54:52,670 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13852 [2024-11-13 12:54:52,670 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:52,670 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:52,674 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:52,674 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:52,675 INFO L745 eck$LassoCheckResult]: Stem: 132148#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 132149#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 133170#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 133171#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 134140#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 132735#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 132736#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 132809#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 132810#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 133282#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 133283#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 132775#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 132572#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 132573#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 133050#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 133051#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 132926#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 132927#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 132547#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 132548#L1279 assume !(0 == ~M_E~0); 133976#L1279-2 assume !(0 == ~T1_E~0); 132169#L1284-1 assume !(0 == ~T2_E~0); 132170#L1289-1 assume !(0 == ~T3_E~0); 132920#L1294-1 assume !(0 == ~T4_E~0); 132921#L1299-1 assume !(0 == ~T5_E~0); 132933#L1304-1 assume !(0 == ~T6_E~0); 134139#L1309-1 assume !(0 == ~T7_E~0); 134142#L1314-1 assume !(0 == ~T8_E~0); 132092#L1319-1 assume !(0 == ~T9_E~0); 132093#L1324-1 assume !(0 == ~T10_E~0); 132269#L1329-1 assume !(0 == ~T11_E~0); 132270#L1334-1 assume !(0 == ~T12_E~0); 133844#L1339-1 assume !(0 == ~T13_E~0); 133963#L1344-1 assume !(0 == ~E_M~0); 133964#L1349-1 assume !(0 == ~E_1~0); 133123#L1354-1 assume !(0 == ~E_2~0); 133124#L1359-1 assume !(0 == ~E_3~0); 133614#L1364-1 assume !(0 == ~E_4~0); 132392#L1369-1 assume !(0 == ~E_5~0); 132393#L1374-1 assume !(0 == ~E_6~0); 133130#L1379-1 assume !(0 == ~E_7~0); 133131#L1384-1 assume !(0 == ~E_8~0); 133217#L1389-1 assume !(0 == ~E_9~0); 133872#L1394-1 assume !(0 == ~E_10~0); 133873#L1399-1 assume !(0 == ~E_11~0); 134028#L1404-1 assume !(0 == ~E_12~0); 132496#L1409-1 assume !(0 == ~E_13~0); 132497#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 134017#L628 assume !(1 == ~m_pc~0); 132391#L628-2 is_master_triggered_~__retres1~0#1 := 0; 132390#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 132996#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 132997#L1591 assume !(0 != activate_threads_~tmp~1#1); 134039#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 132976#L647 assume !(1 == ~t1_pc~0); 132977#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 133028#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 133029#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 133565#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 133943#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 133944#L666 assume !(1 == ~t2_pc~0); 132168#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 132331#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132309#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 132310#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 133342#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 133343#L685 assume !(1 == ~t3_pc~0); 133457#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 133539#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 134055#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 133180#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 133181#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 132620#L704 assume !(1 == ~t4_pc~0); 132621#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 133192#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 131955#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 131956#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 133026#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 133027#L723 assume !(1 == ~t5_pc~0); 133176#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 133423#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 133607#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 133321#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 133322#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 132373#L742 assume 1 == ~t6_pc~0; 132374#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 132536#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 132300#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 132059#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 132060#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 132458#L761 assume !(1 == ~t7_pc~0); 132459#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 132329#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 132330#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 133183#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 133184#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 132084#L780 assume 1 == ~t8_pc~0; 132085#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 132364#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 132365#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 133139#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 133140#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 133268#L799 assume 1 == ~t9_pc~0; 133386#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 132087#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 132088#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 132359#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 133507#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 133299#L818 assume !(1 == ~t10_pc~0); 131870#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 131871#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 133376#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 133302#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 133303#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 133352#L837 assume 1 == ~t11_pc~0; 133353#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 133169#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 133950#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 133261#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 133262#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 132985#L856 assume !(1 == ~t12_pc~0); 132986#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 133739#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 131888#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 131889#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 133712#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 133982#L875 assume 1 == ~t13_pc~0; 132931#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 132537#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 132538#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 132477#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 132478#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 133375#L1427 assume !(1 == ~M_E~0); 133359#L1427-2 assume !(1 == ~T1_E~0); 132444#L1432-1 assume !(1 == ~T2_E~0); 132445#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 133622#L1442-1 assume !(1 == ~T4_E~0); 133623#L1447-1 assume !(1 == ~T5_E~0); 133439#L1452-1 assume !(1 == ~T6_E~0); 132006#L1457-1 assume !(1 == ~T7_E~0); 132007#L1462-1 assume !(1 == ~T8_E~0); 133645#L1467-1 assume !(1 == ~T9_E~0); 133670#L1472-1 assume !(1 == ~T10_E~0); 133671#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 133371#L1482-1 assume !(1 == ~T12_E~0); 133372#L1487-1 assume !(1 == ~T13_E~0); 132339#L1492-1 assume !(1 == ~E_M~0); 132340#L1497-1 assume !(1 == ~E_1~0); 132714#L1502-1 assume !(1 == ~E_2~0); 132715#L1507-1 assume !(1 == ~E_3~0); 132219#L1512-1 assume !(1 == ~E_4~0); 132220#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 133766#L1522-1 assume !(1 == ~E_6~0); 132972#L1527-1 assume !(1 == ~E_7~0); 132973#L1532-1 assume !(1 == ~E_8~0); 134100#L1537-1 assume !(1 == ~E_9~0); 133200#L1542-1 assume !(1 == ~E_10~0); 133004#L1547-1 assume !(1 == ~E_11~0); 133005#L1552-1 assume !(1 == ~E_12~0); 131911#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 131912#L1562-1 assume { :end_inline_reset_delta_events } true; 132527#L1928-2 [2024-11-13 12:54:52,675 INFO L747 eck$LassoCheckResult]: Loop: 132527#L1928-2 assume !false; 141132#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 141128#L1254-1 assume !false; 141127#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 141075#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 141063#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 141058#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 141049#L1067 assume !(0 != eval_~tmp~0#1); 141050#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 143642#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 143641#L1279-3 assume !(0 == ~M_E~0); 143638#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 143636#L1284-3 assume !(0 == ~T2_E~0); 143633#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 143631#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 143629#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 143626#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 143623#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 143620#L1314-3 assume !(0 == ~T8_E~0); 143618#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 143615#L1324-3 assume !(0 == ~T10_E~0); 143611#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 143606#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 143602#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 143599#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 143595#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 143589#L1354-3 assume !(0 == ~E_2~0); 143583#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 143578#L1364-3 assume !(0 == ~E_4~0); 143572#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 143566#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 143559#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 143553#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 143547#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 143541#L1394-3 assume !(0 == ~E_10~0); 143535#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 143529#L1404-3 assume !(0 == ~E_12~0); 143522#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 143515#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 143506#L628-45 assume !(1 == ~m_pc~0); 143498#L628-47 is_master_triggered_~__retres1~0#1 := 0; 143490#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 143483#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 143478#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 143472#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 133384#L647-45 assume !(1 == ~t1_pc~0); 133385#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 143909#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 143908#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 143907#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 143906#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 143904#L666-45 assume !(1 == ~t2_pc~0); 143903#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 143902#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 143901#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 143900#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 133521#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 132022#L685-45 assume 1 == ~t3_pc~0; 132023#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 133132#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 133966#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 134175#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 133765#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 133978#L704-45 assume !(1 == ~t4_pc~0); 134026#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 144295#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 144293#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 144291#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 144290#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 144289#L723-45 assume !(1 == ~t5_pc~0); 144288#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 144286#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 144285#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 144284#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 144282#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 144279#L742-45 assume 1 == ~t6_pc~0; 144276#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 144274#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 144272#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 144270#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 144268#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 144265#L761-45 assume 1 == ~t7_pc~0; 144262#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 144260#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 144258#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 144257#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 144256#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 144255#L780-45 assume !(1 == ~t8_pc~0); 144254#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 144252#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 144250#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 144249#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 144248#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 144245#L799-45 assume !(1 == ~t9_pc~0); 144242#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 144240#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 144238#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 144236#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 144234#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 144233#L818-45 assume !(1 == ~t10_pc~0); 144230#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 144227#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 144225#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 144223#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 144221#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 144219#L837-45 assume !(1 == ~t11_pc~0); 144215#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 144213#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 144211#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 144209#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 144205#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 144203#L856-45 assume 1 == ~t12_pc~0; 144199#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 144197#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 144195#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 144193#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 144191#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 144189#L875-45 assume 1 == ~t13_pc~0; 144186#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 144183#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 144181#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 144179#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 144177#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 133837#L1427-3 assume !(1 == ~M_E~0); 132915#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 132916#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 133504#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 133119#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 133120#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 131928#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 131929#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 144163#L1462-3 assume !(1 == ~T8_E~0); 144162#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 144161#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 144160#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 144159#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 144158#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 144157#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 144156#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 144155#L1502-3 assume !(1 == ~E_2~0); 144154#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 144153#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 132541#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 132227#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 132228#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 132194#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 132195#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 133358#L1542-3 assume !(1 == ~E_10~0); 133511#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 133104#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 133105#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 133868#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 137817#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 137805#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 141185#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 141183#L1947 assume !(0 == start_simulation_~tmp~3#1); 141180#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 141164#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 141150#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 141148#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 141147#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 141144#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 141140#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 141136#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 132527#L1928-2 [2024-11-13 12:54:52,676 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:52,676 INFO L85 PathProgramCache]: Analyzing trace with hash 846336710, now seen corresponding path program 1 times [2024-11-13 12:54:52,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:52,677 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [680225921] [2024-11-13 12:54:52,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:52,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:52,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:52,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:52,781 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:52,781 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [680225921] [2024-11-13 12:54:52,781 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [680225921] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:52,782 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:52,782 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 12:54:52,782 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1419904339] [2024-11-13 12:54:52,782 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:52,782 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:52,783 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:52,783 INFO L85 PathProgramCache]: Analyzing trace with hash 70594825, now seen corresponding path program 1 times [2024-11-13 12:54:52,783 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:52,783 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [520659780] [2024-11-13 12:54:52,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:52,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:52,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:52,888 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:52,888 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:52,888 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [520659780] [2024-11-13 12:54:52,888 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [520659780] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:52,888 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:52,888 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 12:54:52,888 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1389049022] [2024-11-13 12:54:52,888 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:52,889 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:52,889 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:52,889 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:54:52,889 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:54:52,889 INFO L87 Difference]: Start difference. First operand 14044 states and 20089 transitions. cyclomatic complexity: 6049 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:53,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:53,109 INFO L93 Difference]: Finished difference Result 26979 states and 38442 transitions. [2024-11-13 12:54:53,110 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26979 states and 38442 transitions. [2024-11-13 12:54:53,219 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26756 [2024-11-13 12:54:53,320 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26979 states to 26979 states and 38442 transitions. [2024-11-13 12:54:53,320 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26979 [2024-11-13 12:54:53,346 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26979 [2024-11-13 12:54:53,346 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26979 states and 38442 transitions. [2024-11-13 12:54:53,382 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:53,383 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26979 states and 38442 transitions. [2024-11-13 12:54:53,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26979 states and 38442 transitions. [2024-11-13 12:54:53,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26979 to 26963. [2024-11-13 12:54:53,826 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26963 states, 26963 states have (on average 1.4251381522827578) internal successors, (38426), 26962 states have internal predecessors, (38426), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:53,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26963 states to 26963 states and 38426 transitions. [2024-11-13 12:54:53,899 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26963 states and 38426 transitions. [2024-11-13 12:54:53,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:54:53,900 INFO L424 stractBuchiCegarLoop]: Abstraction has 26963 states and 38426 transitions. [2024-11-13 12:54:53,900 INFO L331 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-13 12:54:53,900 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26963 states and 38426 transitions. [2024-11-13 12:54:53,982 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26740 [2024-11-13 12:54:53,984 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:53,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:53,987 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:53,988 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:53,988 INFO L745 eck$LassoCheckResult]: Stem: 173178#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 173179#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 174177#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 174178#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 175021#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 173755#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 173756#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 173827#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 173828#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 174287#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 174288#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 173792#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 173595#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 173596#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 174063#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 174064#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 173939#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 173940#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 173568#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 173569#L1279 assume !(0 == ~M_E~0); 174901#L1279-2 assume !(0 == ~T1_E~0); 173199#L1284-1 assume !(0 == ~T2_E~0); 173200#L1289-1 assume !(0 == ~T3_E~0); 173936#L1294-1 assume !(0 == ~T4_E~0); 173937#L1299-1 assume !(0 == ~T5_E~0); 173948#L1304-1 assume !(0 == ~T6_E~0); 175019#L1309-1 assume !(0 == ~T7_E~0); 175023#L1314-1 assume !(0 == ~T8_E~0); 173123#L1319-1 assume !(0 == ~T9_E~0); 173124#L1324-1 assume !(0 == ~T10_E~0); 173298#L1329-1 assume !(0 == ~T11_E~0); 173299#L1334-1 assume !(0 == ~T12_E~0); 174793#L1339-1 assume !(0 == ~T13_E~0); 174886#L1344-1 assume !(0 == ~E_M~0); 174887#L1349-1 assume !(0 == ~E_1~0); 174132#L1354-1 assume !(0 == ~E_2~0); 174133#L1359-1 assume !(0 == ~E_3~0); 174587#L1364-1 assume !(0 == ~E_4~0); 173421#L1369-1 assume !(0 == ~E_5~0); 173422#L1374-1 assume !(0 == ~E_6~0); 174139#L1379-1 assume !(0 == ~E_7~0); 174140#L1384-1 assume !(0 == ~E_8~0); 174225#L1389-1 assume !(0 == ~E_9~0); 174818#L1394-1 assume !(0 == ~E_10~0); 174819#L1399-1 assume !(0 == ~E_11~0); 174945#L1404-1 assume !(0 == ~E_12~0); 173518#L1409-1 assume !(0 == ~E_13~0); 173519#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 174935#L628 assume !(1 == ~m_pc~0); 173420#L628-2 is_master_triggered_~__retres1~0#1 := 0; 173419#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 174009#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 174010#L1591 assume !(0 != activate_threads_~tmp~1#1); 174955#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 173989#L647 assume !(1 == ~t1_pc~0); 173990#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 174042#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 174043#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 174542#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 174873#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 174874#L666 assume !(1 == ~t2_pc~0); 173198#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 173360#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 173338#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 173339#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 174343#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 174344#L685 assume !(1 == ~t3_pc~0); 174450#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 174518#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 174965#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 174187#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 174188#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 173644#L704 assume !(1 == ~t4_pc~0); 173645#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 174199#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 172987#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 172988#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 174040#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 174041#L723 assume !(1 == ~t5_pc~0); 174183#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 174420#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 174580#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 174322#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 174323#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 173403#L742 assume !(1 == ~t6_pc~0); 173404#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 173557#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 173329#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 173091#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 173092#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 173481#L761 assume !(1 == ~t7_pc~0); 173482#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 173356#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 173357#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 174190#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 174191#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 173115#L780 assume 1 == ~t8_pc~0; 173116#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 173394#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 173395#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 174148#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 174149#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 174274#L799 assume 1 == ~t9_pc~0; 174386#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 173118#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 173119#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 173389#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 174498#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 174300#L818 assume !(1 == ~t10_pc~0); 172902#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 172903#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 174376#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 174303#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 174304#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 174351#L837 assume 1 == ~t11_pc~0; 174352#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 174174#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 174878#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 174267#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 174268#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 173998#L856 assume !(1 == ~t12_pc~0); 173999#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 174696#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 172920#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 172921#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 174671#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 174904#L875 assume 1 == ~t13_pc~0; 173946#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 173558#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 173559#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 173499#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 173500#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 174375#L1427 assume !(1 == ~M_E~0); 174359#L1427-2 assume !(1 == ~T1_E~0); 173468#L1432-1 assume !(1 == ~T2_E~0); 173469#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 174593#L1442-1 assume !(1 == ~T4_E~0); 174594#L1447-1 assume !(1 == ~T5_E~0); 174431#L1452-1 assume !(1 == ~T6_E~0); 173038#L1457-1 assume !(1 == ~T7_E~0); 173039#L1462-1 assume !(1 == ~T8_E~0); 174612#L1467-1 assume !(1 == ~T9_E~0); 174633#L1472-1 assume !(1 == ~T10_E~0); 174634#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 174371#L1482-1 assume !(1 == ~T12_E~0); 174372#L1487-1 assume !(1 == ~T13_E~0); 173368#L1492-1 assume !(1 == ~E_M~0); 173369#L1497-1 assume !(1 == ~E_1~0); 173737#L1502-1 assume !(1 == ~E_2~0); 173738#L1507-1 assume !(1 == ~E_3~0); 173248#L1512-1 assume !(1 == ~E_4~0); 173249#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 174724#L1522-1 assume !(1 == ~E_6~0); 173985#L1527-1 assume !(1 == ~E_7~0); 173986#L1532-1 assume !(1 == ~E_8~0); 174995#L1537-1 assume !(1 == ~E_9~0); 174207#L1542-1 assume !(1 == ~E_10~0); 174016#L1547-1 assume !(1 == ~E_11~0); 174017#L1552-1 assume !(1 == ~E_12~0); 172943#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 172944#L1562-1 assume { :end_inline_reset_delta_events } true; 173548#L1928-2 [2024-11-13 12:54:53,989 INFO L747 eck$LassoCheckResult]: Loop: 173548#L1928-2 assume !false; 184492#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 184488#L1254-1 assume !false; 184487#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 183980#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 183971#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 183969#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 183967#L1067 assume !(0 != eval_~tmp~0#1); 183966#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 183965#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 183950#L1279-3 assume !(0 == ~M_E~0); 183948#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 183946#L1284-3 assume !(0 == ~T2_E~0); 183944#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 183942#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 183940#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 183938#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 183936#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 183931#L1314-3 assume !(0 == ~T8_E~0); 183929#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 183927#L1324-3 assume !(0 == ~T10_E~0); 183926#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 183925#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 183924#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 183923#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 183922#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 183921#L1354-3 assume !(0 == ~E_2~0); 183919#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 183918#L1364-3 assume !(0 == ~E_4~0); 183917#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 183916#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 183915#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 183913#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 183911#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 183909#L1394-3 assume !(0 == ~E_10~0); 183907#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 183905#L1404-3 assume !(0 == ~E_12~0); 183903#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 183901#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 183899#L628-45 assume !(1 == ~m_pc~0); 183896#L628-47 is_master_triggered_~__retres1~0#1 := 0; 183894#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 183892#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 183890#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 183888#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 183886#L647-45 assume !(1 == ~t1_pc~0); 183884#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 183882#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 183880#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 183878#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 183876#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 183872#L666-45 assume !(1 == ~t2_pc~0); 183870#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 183868#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 183866#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 183864#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 183862#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 183860#L685-45 assume 1 == ~t3_pc~0; 183858#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 183859#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 183920#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 183849#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 183846#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 183844#L704-45 assume !(1 == ~t4_pc~0); 183842#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 183840#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 183838#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 183836#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 183834#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 183832#L723-45 assume !(1 == ~t5_pc~0); 183830#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 183827#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 183825#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 183824#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 183821#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 183819#L742-45 assume !(1 == ~t6_pc~0); 183817#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 183815#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 183813#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 183811#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 183809#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 183806#L761-45 assume 1 == ~t7_pc~0; 183803#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 183801#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 183800#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 183799#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 183798#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 183797#L780-45 assume 1 == ~t8_pc~0; 183794#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 183792#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 183790#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 183788#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 183785#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 183783#L799-45 assume !(1 == ~t9_pc~0); 183780#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 183778#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 183776#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 183774#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 183773#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 183770#L818-45 assume 1 == ~t10_pc~0; 183767#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 183765#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 183763#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 183761#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 183759#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 183756#L837-45 assume !(1 == ~t11_pc~0); 183751#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 183748#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 183746#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 183744#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 183742#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 183740#L856-45 assume !(1 == ~t12_pc~0); 183738#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 183735#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 183733#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 183731#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 183730#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 183729#L875-45 assume 1 == ~t13_pc~0; 183728#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 183725#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 183723#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 183721#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 183719#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 183717#L1427-3 assume !(1 == ~M_E~0); 178490#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 183714#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 183712#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 183710#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 183708#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 183621#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 183614#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 183606#L1462-3 assume !(1 == ~T8_E~0); 183584#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 183573#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 183564#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 183556#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 183270#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 183269#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 183268#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 183267#L1502-3 assume !(1 == ~E_2~0); 183266#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 183264#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 183261#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 183259#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 183257#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 183255#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 183253#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 183251#L1542-3 assume !(1 == ~E_10~0); 183248#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 183246#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 183244#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 183242#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 175336#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 175323#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 175322#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 175320#L1947 assume !(0 == start_simulation_~tmp~3#1); 175321#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 184515#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 184502#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 184501#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 184499#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 184497#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 184496#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 184495#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 173548#L1928-2 [2024-11-13 12:54:53,989 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:53,990 INFO L85 PathProgramCache]: Analyzing trace with hash -995977081, now seen corresponding path program 1 times [2024-11-13 12:54:53,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:53,990 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [999328354] [2024-11-13 12:54:53,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:53,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:54,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:54,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:54,082 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:54,083 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [999328354] [2024-11-13 12:54:54,083 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [999328354] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:54,083 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:54,083 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 12:54:54,084 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1256423041] [2024-11-13 12:54:54,084 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:54,084 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:54,084 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:54,085 INFO L85 PathProgramCache]: Analyzing trace with hash -125193975, now seen corresponding path program 1 times [2024-11-13 12:54:54,085 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:54,085 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [330461658] [2024-11-13 12:54:54,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:54,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:54,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:54,151 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:54,151 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:54,151 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [330461658] [2024-11-13 12:54:54,151 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [330461658] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:54,151 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:54,151 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:54,152 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1079091983] [2024-11-13 12:54:54,152 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:54,152 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:54,152 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:54,152 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:54:54,152 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:54:54,153 INFO L87 Difference]: Start difference. First operand 26963 states and 38426 transitions. cyclomatic complexity: 11471 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:54,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:54,651 INFO L93 Difference]: Finished difference Result 51902 states and 73699 transitions. [2024-11-13 12:54:54,651 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51902 states and 73699 transitions. [2024-11-13 12:54:54,845 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 51600 [2024-11-13 12:54:55,020 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51902 states to 51902 states and 73699 transitions. [2024-11-13 12:54:55,020 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51902 [2024-11-13 12:54:55,051 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51902 [2024-11-13 12:54:55,051 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51902 states and 73699 transitions. [2024-11-13 12:54:55,096 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:55,097 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51902 states and 73699 transitions. [2024-11-13 12:54:55,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51902 states and 73699 transitions. [2024-11-13 12:54:55,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51902 to 51870. [2024-11-13 12:54:55,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51870 states, 51870 states have (on average 1.4202236360131097) internal successors, (73667), 51869 states have internal predecessors, (73667), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:56,133 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51870 states to 51870 states and 73667 transitions. [2024-11-13 12:54:56,133 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51870 states and 73667 transitions. [2024-11-13 12:54:56,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:54:56,134 INFO L424 stractBuchiCegarLoop]: Abstraction has 51870 states and 73667 transitions. [2024-11-13 12:54:56,134 INFO L331 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-13 12:54:56,134 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51870 states and 73667 transitions. [2024-11-13 12:54:56,322 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 51568 [2024-11-13 12:54:56,323 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:54:56,323 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:54:56,326 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:56,327 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:54:56,327 INFO L745 eck$LassoCheckResult]: Stem: 252047#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 252048#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 253055#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 253056#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 253945#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 252627#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 252628#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 252699#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 252700#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 253163#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 253164#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 252663#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 252461#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 252462#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 252935#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 252936#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 252809#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 252810#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 252436#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 252437#L1279 assume !(0 == ~M_E~0); 253808#L1279-2 assume !(0 == ~T1_E~0); 252068#L1284-1 assume !(0 == ~T2_E~0); 252069#L1289-1 assume !(0 == ~T3_E~0); 252806#L1294-1 assume !(0 == ~T4_E~0); 252807#L1299-1 assume !(0 == ~T5_E~0); 252818#L1304-1 assume !(0 == ~T6_E~0); 253944#L1309-1 assume !(0 == ~T7_E~0); 253946#L1314-1 assume !(0 == ~T8_E~0); 251992#L1319-1 assume !(0 == ~T9_E~0); 251993#L1324-1 assume !(0 == ~T10_E~0); 252169#L1329-1 assume !(0 == ~T11_E~0); 252170#L1334-1 assume !(0 == ~T12_E~0); 253690#L1339-1 assume !(0 == ~T13_E~0); 253794#L1344-1 assume !(0 == ~E_M~0); 253795#L1349-1 assume !(0 == ~E_1~0); 253005#L1354-1 assume !(0 == ~E_2~0); 253006#L1359-1 assume !(0 == ~E_3~0); 253472#L1364-1 assume !(0 == ~E_4~0); 252290#L1369-1 assume !(0 == ~E_5~0); 252291#L1374-1 assume !(0 == ~E_6~0); 253012#L1379-1 assume !(0 == ~E_7~0); 253013#L1384-1 assume !(0 == ~E_8~0); 253101#L1389-1 assume !(0 == ~E_9~0); 253718#L1394-1 assume !(0 == ~E_10~0); 253719#L1399-1 assume !(0 == ~E_11~0); 253849#L1404-1 assume !(0 == ~E_12~0); 252385#L1409-1 assume !(0 == ~E_13~0); 252386#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 253840#L628 assume !(1 == ~m_pc~0); 252289#L628-2 is_master_triggered_~__retres1~0#1 := 0; 252288#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 252879#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 252880#L1591 assume !(0 != activate_threads_~tmp~1#1); 253859#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 252859#L647 assume !(1 == ~t1_pc~0); 252860#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 252912#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 252913#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 253428#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 253780#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 253781#L666 assume !(1 == ~t2_pc~0); 252067#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 252231#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 252209#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 252210#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 253221#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 253222#L685 assume !(1 == ~t3_pc~0); 253330#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 253400#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 253870#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 253064#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 253065#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 252512#L704 assume !(1 == ~t4_pc~0); 252513#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 253077#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 251859#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 251860#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 252910#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 252911#L723 assume !(1 == ~t5_pc~0); 253060#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 253299#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 253465#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 253199#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 253200#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 252273#L742 assume !(1 == ~t6_pc~0); 252274#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 252425#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 252200#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 251963#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 251964#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 252349#L761 assume !(1 == ~t7_pc~0); 252350#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 252227#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 252228#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 253067#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 253068#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 251985#L780 assume !(1 == ~t8_pc~0); 251986#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 252264#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 252265#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 253020#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 253021#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 253148#L799 assume 1 == ~t9_pc~0; 253263#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 251987#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 251988#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 252259#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 253378#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 253179#L818 assume !(1 == ~t10_pc~0); 251774#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 251775#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 253255#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 253182#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 253183#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 253229#L837 assume 1 == ~t11_pc~0; 253230#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 253053#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 253785#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 253141#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 253142#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 252868#L856 assume !(1 == ~t12_pc~0); 252869#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 253590#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 251792#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 251793#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 253565#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 253811#L875 assume 1 == ~t13_pc~0; 252816#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 252426#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 252427#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 252367#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 252368#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 253254#L1427 assume !(1 == ~M_E~0); 253238#L1427-2 assume !(1 == ~T1_E~0); 252337#L1432-1 assume !(1 == ~T2_E~0); 252338#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 253478#L1442-1 assume !(1 == ~T4_E~0); 253479#L1447-1 assume !(1 == ~T5_E~0); 253310#L1452-1 assume !(1 == ~T6_E~0); 251910#L1457-1 assume !(1 == ~T7_E~0); 251911#L1462-1 assume !(1 == ~T8_E~0); 253497#L1467-1 assume !(1 == ~T9_E~0); 253523#L1472-1 assume !(1 == ~T10_E~0); 253524#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 253250#L1482-1 assume !(1 == ~T12_E~0); 253251#L1487-1 assume !(1 == ~T13_E~0); 252239#L1492-1 assume !(1 == ~E_M~0); 252240#L1497-1 assume !(1 == ~E_1~0); 252607#L1502-1 assume !(1 == ~E_2~0); 252608#L1507-1 assume !(1 == ~E_3~0); 252118#L1512-1 assume !(1 == ~E_4~0); 252119#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 253613#L1522-1 assume !(1 == ~E_6~0); 252855#L1527-1 assume !(1 == ~E_7~0); 252856#L1532-1 assume !(1 == ~E_8~0); 253904#L1537-1 assume !(1 == ~E_9~0); 253084#L1542-1 assume !(1 == ~E_10~0); 252887#L1547-1 assume !(1 == ~E_11~0); 252888#L1552-1 assume !(1 == ~E_12~0); 251815#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 251816#L1562-1 assume { :end_inline_reset_delta_events } true; 252416#L1928-2 [2024-11-13 12:54:56,328 INFO L747 eck$LassoCheckResult]: Loop: 252416#L1928-2 assume !false; 284951#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 284947#L1254-1 assume !false; 284946#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 284938#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 284931#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 284930#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 284928#L1067 assume !(0 != eval_~tmp~0#1); 284927#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 284926#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 284925#L1279-3 assume !(0 == ~M_E~0); 284923#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 284922#L1284-3 assume !(0 == ~T2_E~0); 284921#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 284920#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 284919#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 284918#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 284916#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 284914#L1314-3 assume !(0 == ~T8_E~0); 284912#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 284910#L1324-3 assume !(0 == ~T10_E~0); 284908#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 284906#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 284904#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 284902#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 284900#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 284898#L1354-3 assume !(0 == ~E_2~0); 284896#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 284894#L1364-3 assume !(0 == ~E_4~0); 284892#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 284890#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 284888#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 284886#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 284884#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 284882#L1394-3 assume !(0 == ~E_10~0); 284880#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 284878#L1404-3 assume !(0 == ~E_12~0); 284876#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 284874#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 284872#L628-45 assume !(1 == ~m_pc~0); 284869#L628-47 is_master_triggered_~__retres1~0#1 := 0; 284867#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 284865#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 284863#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 284861#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 284859#L647-45 assume !(1 == ~t1_pc~0); 284857#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 284855#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 284852#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 284850#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 284848#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 284844#L666-45 assume !(1 == ~t2_pc~0); 284842#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 284840#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 284838#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 284836#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 284834#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 284832#L685-45 assume !(1 == ~t3_pc~0); 284829#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 284826#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 284824#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 284822#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 284819#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 284817#L704-45 assume !(1 == ~t4_pc~0); 284815#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 284811#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 284809#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 284807#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 284805#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 284802#L723-45 assume !(1 == ~t5_pc~0); 284800#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 284797#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 284795#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 284793#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 284791#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 284789#L742-45 assume !(1 == ~t6_pc~0); 284787#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 284785#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 284782#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 284780#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 284778#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 284776#L761-45 assume 1 == ~t7_pc~0; 284773#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 284771#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 284769#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 284767#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 284765#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 284763#L780-45 assume !(1 == ~t8_pc~0); 284761#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 284759#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 284756#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 284754#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 284752#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 284750#L799-45 assume 1 == ~t9_pc~0; 284748#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 284745#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 284743#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 284741#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 284739#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 284737#L818-45 assume 1 == ~t10_pc~0; 284734#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 284732#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 284729#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 284727#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 284725#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 284723#L837-45 assume !(1 == ~t11_pc~0); 284720#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 284718#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 284715#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 284713#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 284711#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 284709#L856-45 assume 1 == ~t12_pc~0; 284706#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 284704#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 284701#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 284699#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 284697#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 284695#L875-45 assume !(1 == ~t13_pc~0); 284692#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 284690#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 284687#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 284685#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 284683#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 284666#L1427-3 assume !(1 == ~M_E~0); 284664#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 284662#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 284660#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 284657#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 284655#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 284653#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 284651#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 284649#L1462-3 assume !(1 == ~T8_E~0); 284646#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 284644#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 284642#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 284640#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 284638#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 284636#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 284632#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 284630#L1502-3 assume !(1 == ~E_2~0); 284628#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 284626#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 284623#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 284621#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 284619#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 284617#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 284615#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 284613#L1542-3 assume !(1 == ~E_10~0); 284611#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 284609#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 284607#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 284604#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 284598#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 284584#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 284582#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 284579#L1947 assume !(0 == start_simulation_~tmp~3#1); 284580#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 284983#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 284969#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 284967#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 284966#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 284963#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 284959#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 284955#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 252416#L1928-2 [2024-11-13 12:54:56,329 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:56,330 INFO L85 PathProgramCache]: Analyzing trace with hash -618334264, now seen corresponding path program 1 times [2024-11-13 12:54:56,330 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:56,330 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1994743092] [2024-11-13 12:54:56,330 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:56,330 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:56,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:56,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:56,448 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:56,449 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1994743092] [2024-11-13 12:54:56,449 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1994743092] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:56,449 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:56,449 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 12:54:56,449 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [132373876] [2024-11-13 12:54:56,449 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:56,450 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:54:56,450 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:54:56,450 INFO L85 PathProgramCache]: Analyzing trace with hash 2000784780, now seen corresponding path program 1 times [2024-11-13 12:54:56,450 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:54:56,450 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2015845879] [2024-11-13 12:54:56,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:54:56,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:54:56,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:54:56,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:54:56,670 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:54:56,670 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2015845879] [2024-11-13 12:54:56,670 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2015845879] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:54:56,671 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:54:56,671 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:54:56,671 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1664343697] [2024-11-13 12:54:56,671 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:54:56,672 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:54:56,672 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:54:56,672 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:54:56,672 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:54:56,672 INFO L87 Difference]: Start difference. First operand 51870 states and 73667 transitions. cyclomatic complexity: 21813 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:57,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:54:57,124 INFO L93 Difference]: Finished difference Result 99901 states and 141392 transitions. [2024-11-13 12:54:57,125 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99901 states and 141392 transitions. [2024-11-13 12:54:57,954 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99408 [2024-11-13 12:54:58,224 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99901 states to 99901 states and 141392 transitions. [2024-11-13 12:54:58,226 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99901 [2024-11-13 12:54:58,380 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99901 [2024-11-13 12:54:58,380 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99901 states and 141392 transitions. [2024-11-13 12:54:58,453 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:54:58,453 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99901 states and 141392 transitions. [2024-11-13 12:54:58,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99901 states and 141392 transitions. [2024-11-13 12:54:59,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99901 to 99837. [2024-11-13 12:54:59,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99837 states, 99837 states have (on average 1.415587407474183) internal successors, (141328), 99836 states have internal predecessors, (141328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:54:59,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99837 states to 99837 states and 141328 transitions. [2024-11-13 12:54:59,980 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99837 states and 141328 transitions. [2024-11-13 12:54:59,984 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:54:59,985 INFO L424 stractBuchiCegarLoop]: Abstraction has 99837 states and 141328 transitions. [2024-11-13 12:54:59,985 INFO L331 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-13 12:54:59,985 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99837 states and 141328 transitions. [2024-11-13 12:55:00,517 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99344 [2024-11-13 12:55:00,517 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:55:00,517 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:55:00,519 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:55:00,519 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:55:00,520 INFO L745 eck$LassoCheckResult]: Stem: 403827#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 403828#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 404842#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 404843#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 405779#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 404408#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 404409#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 404481#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 404482#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 404961#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 404962#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 404445#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 404244#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 404245#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 404724#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 404725#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 404596#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 404597#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 404218#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 404219#L1279 assume !(0 == ~M_E~0); 405625#L1279-2 assume !(0 == ~T1_E~0); 403848#L1284-1 assume !(0 == ~T2_E~0); 403849#L1289-1 assume !(0 == ~T3_E~0); 404589#L1294-1 assume !(0 == ~T4_E~0); 404590#L1299-1 assume !(0 == ~T5_E~0); 404605#L1304-1 assume !(0 == ~T6_E~0); 405778#L1309-1 assume !(0 == ~T7_E~0); 405780#L1314-1 assume !(0 == ~T8_E~0); 403772#L1319-1 assume !(0 == ~T9_E~0); 403773#L1324-1 assume !(0 == ~T10_E~0); 403948#L1329-1 assume !(0 == ~T11_E~0); 403949#L1334-1 assume !(0 == ~T12_E~0); 405508#L1339-1 assume !(0 == ~T13_E~0); 405612#L1344-1 assume !(0 == ~E_M~0); 405613#L1349-1 assume !(0 == ~E_1~0); 404796#L1354-1 assume !(0 == ~E_2~0); 404797#L1359-1 assume !(0 == ~E_3~0); 405269#L1364-1 assume !(0 == ~E_4~0); 404070#L1369-1 assume !(0 == ~E_5~0); 404071#L1374-1 assume !(0 == ~E_6~0); 404803#L1379-1 assume !(0 == ~E_7~0); 404804#L1384-1 assume !(0 == ~E_8~0); 404891#L1389-1 assume !(0 == ~E_9~0); 405539#L1394-1 assume !(0 == ~E_10~0); 405540#L1399-1 assume !(0 == ~E_11~0); 405670#L1404-1 assume !(0 == ~E_12~0); 404167#L1409-1 assume !(0 == ~E_13~0); 404168#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 405660#L628 assume !(1 == ~m_pc~0); 404069#L628-2 is_master_triggered_~__retres1~0#1 := 0; 404068#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 404670#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 404671#L1591 assume !(0 != activate_threads_~tmp~1#1); 405680#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 404647#L647 assume !(1 == ~t1_pc~0); 404648#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 404703#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 404704#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 405223#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 405597#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 405598#L666 assume !(1 == ~t2_pc~0); 403847#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 404010#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 403988#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 403989#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 405015#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 405016#L685 assume !(1 == ~t3_pc~0); 405121#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 405198#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 405691#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 404852#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 404853#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 404293#L704 assume !(1 == ~t4_pc~0); 404294#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 404865#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 403637#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 403638#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 404701#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 404702#L723 assume !(1 == ~t5_pc~0); 404847#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 405091#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 405262#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 404994#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 404995#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 404052#L742 assume !(1 == ~t6_pc~0); 404053#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 404207#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 403979#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 403743#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 403744#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 404131#L761 assume !(1 == ~t7_pc~0); 404132#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 404006#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 404007#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 404855#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 404856#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 403765#L780 assume !(1 == ~t8_pc~0); 403766#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 404043#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 404044#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 404813#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 404814#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 404945#L799 assume !(1 == ~t9_pc~0); 404265#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 403767#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 403768#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 404038#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 405174#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 404975#L818 assume !(1 == ~t10_pc~0); 403552#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 403553#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 405050#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 404978#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 404979#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 405024#L837 assume 1 == ~t11_pc~0; 405025#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 404840#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 405602#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 404938#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 404939#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 404658#L856 assume !(1 == ~t12_pc~0); 404659#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 405401#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 403570#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 403571#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 405376#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 405629#L875 assume 1 == ~t13_pc~0; 404603#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 404208#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 404209#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 404149#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 404150#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 405049#L1427 assume !(1 == ~M_E~0); 405031#L1427-2 assume !(1 == ~T1_E~0); 404119#L1432-1 assume !(1 == ~T2_E~0); 404120#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 405278#L1442-1 assume !(1 == ~T4_E~0); 405279#L1447-1 assume !(1 == ~T5_E~0); 405102#L1452-1 assume !(1 == ~T6_E~0); 403688#L1457-1 assume !(1 == ~T7_E~0); 403689#L1462-1 assume !(1 == ~T8_E~0); 405304#L1467-1 assume !(1 == ~T9_E~0); 405331#L1472-1 assume !(1 == ~T10_E~0); 405332#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 405045#L1482-1 assume !(1 == ~T12_E~0); 405046#L1487-1 assume !(1 == ~T13_E~0); 404018#L1492-1 assume !(1 == ~E_M~0); 404019#L1497-1 assume !(1 == ~E_1~0); 404389#L1502-1 assume !(1 == ~E_2~0); 404390#L1507-1 assume !(1 == ~E_3~0); 403898#L1512-1 assume !(1 == ~E_4~0); 403899#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 405429#L1522-1 assume !(1 == ~E_6~0); 404643#L1527-1 assume !(1 == ~E_7~0); 404644#L1532-1 assume !(1 == ~E_8~0); 405731#L1537-1 assume !(1 == ~E_9~0); 404872#L1542-1 assume !(1 == ~E_10~0); 404677#L1547-1 assume !(1 == ~E_11~0); 404678#L1552-1 assume !(1 == ~E_12~0); 403593#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 403594#L1562-1 assume { :end_inline_reset_delta_events } true; 404198#L1928-2 [2024-11-13 12:55:00,520 INFO L747 eck$LassoCheckResult]: Loop: 404198#L1928-2 assume !false; 450885#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 450878#L1254-1 assume !false; 450874#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 450553#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 450540#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 450533#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 450524#L1067 assume !(0 != eval_~tmp~0#1); 450525#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 453340#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 453338#L1279-3 assume !(0 == ~M_E~0); 453336#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 453334#L1284-3 assume !(0 == ~T2_E~0); 453332#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 453330#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 453328#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 453326#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 453324#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 453322#L1314-3 assume !(0 == ~T8_E~0); 453320#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 453318#L1324-3 assume !(0 == ~T10_E~0); 453316#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 453314#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 453312#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 453310#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 453308#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 453306#L1354-3 assume !(0 == ~E_2~0); 453304#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 453302#L1364-3 assume !(0 == ~E_4~0); 453300#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 453298#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 453296#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 453295#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 453294#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 453293#L1394-3 assume !(0 == ~E_10~0); 453292#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 453291#L1404-3 assume !(0 == ~E_12~0); 453290#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 453289#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 453288#L628-45 assume !(1 == ~m_pc~0); 453286#L628-47 is_master_triggered_~__retres1~0#1 := 0; 453285#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 453284#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 453283#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 453282#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 453281#L647-45 assume !(1 == ~t1_pc~0); 453280#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 453279#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 453278#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 453277#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 453276#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 453274#L666-45 assume !(1 == ~t2_pc~0); 453273#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 453272#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 453271#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 453270#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 453269#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 453268#L685-45 assume 1 == ~t3_pc~0; 453266#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 453267#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 453265#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 453259#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 453258#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 453257#L704-45 assume !(1 == ~t4_pc~0); 453256#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 453255#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 453252#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 453250#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 453248#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 453246#L723-45 assume !(1 == ~t5_pc~0); 453244#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 453241#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 453237#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 453235#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 453233#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 453231#L742-45 assume !(1 == ~t6_pc~0); 453228#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 453226#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 453224#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 453222#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 453220#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 453218#L761-45 assume !(1 == ~t7_pc~0); 453216#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 453213#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 453211#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 453208#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 453206#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 453204#L780-45 assume !(1 == ~t8_pc~0); 453202#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 453200#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 453198#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 453196#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 453194#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 453192#L799-45 assume !(1 == ~t9_pc~0); 453190#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 453188#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 453186#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 453183#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 453181#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 453179#L818-45 assume 1 == ~t10_pc~0; 453176#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 453174#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 453172#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 453170#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 453168#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 453166#L837-45 assume 1 == ~t11_pc~0; 453164#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 453161#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 453159#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 453157#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 453155#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 453153#L856-45 assume 1 == ~t12_pc~0; 453150#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 453148#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 453146#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 453143#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 453141#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 453139#L875-45 assume !(1 == ~t13_pc~0); 453136#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 453134#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 453132#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 453129#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 453127#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 453013#L1427-3 assume !(1 == ~M_E~0); 453010#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 453008#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 453006#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 453004#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 453002#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 453000#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 452998#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 452996#L1462-3 assume !(1 == ~T8_E~0); 452994#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 452992#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 452990#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 452988#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 452986#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 452984#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 452982#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 452980#L1502-3 assume !(1 == ~E_2~0); 452978#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 452976#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 452973#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 452971#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 452969#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 452967#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 452965#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 452963#L1542-3 assume !(1 == ~E_10~0); 452960#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 452958#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 452956#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 452954#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 452946#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 452932#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 452930#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 452927#L1947 assume !(0 == start_simulation_~tmp~3#1); 452923#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 452914#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 452900#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 452898#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 452897#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 450949#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 450945#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 450941#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 404198#L1928-2 [2024-11-13 12:55:00,521 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:55:00,521 INFO L85 PathProgramCache]: Analyzing trace with hash -1649665079, now seen corresponding path program 1 times [2024-11-13 12:55:00,521 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:55:00,521 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [148390170] [2024-11-13 12:55:00,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:55:00,522 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:55:00,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:55:00,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:55:00,620 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:55:00,620 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [148390170] [2024-11-13 12:55:00,620 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [148390170] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:55:00,620 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:55:00,620 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 12:55:00,620 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [8465870] [2024-11-13 12:55:00,620 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:55:00,621 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:55:00,621 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:55:00,621 INFO L85 PathProgramCache]: Analyzing trace with hash 338978954, now seen corresponding path program 1 times [2024-11-13 12:55:00,621 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:55:00,621 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1065658441] [2024-11-13 12:55:00,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:55:00,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:55:00,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:55:00,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:55:00,688 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:55:00,688 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1065658441] [2024-11-13 12:55:00,689 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1065658441] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:55:00,689 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:55:00,689 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:55:00,689 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1812690080] [2024-11-13 12:55:00,689 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:55:00,689 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:55:00,690 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:55:00,690 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 12:55:00,690 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 12:55:00,690 INFO L87 Difference]: Start difference. First operand 99837 states and 141328 transitions. cyclomatic complexity: 41523 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:55:01,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:55:01,747 INFO L93 Difference]: Finished difference Result 102336 states and 143827 transitions. [2024-11-13 12:55:01,748 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102336 states and 143827 transitions. [2024-11-13 12:55:02,171 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 101840 [2024-11-13 12:55:02,557 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102336 states to 102336 states and 143827 transitions. [2024-11-13 12:55:02,557 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 102336 [2024-11-13 12:55:02,626 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 102336 [2024-11-13 12:55:02,627 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102336 states and 143827 transitions. [2024-11-13 12:55:02,703 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:55:02,703 INFO L218 hiAutomatonCegarLoop]: Abstraction has 102336 states and 143827 transitions. [2024-11-13 12:55:02,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102336 states and 143827 transitions. [2024-11-13 12:55:03,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102336 to 102336. [2024-11-13 12:55:03,827 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 102336 states, 102336 states have (on average 1.4054389462163852) internal successors, (143827), 102335 states have internal predecessors, (143827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:55:04,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102336 states to 102336 states and 143827 transitions. [2024-11-13 12:55:04,393 INFO L240 hiAutomatonCegarLoop]: Abstraction has 102336 states and 143827 transitions. [2024-11-13 12:55:04,393 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 12:55:04,394 INFO L424 stractBuchiCegarLoop]: Abstraction has 102336 states and 143827 transitions. [2024-11-13 12:55:04,395 INFO L331 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-13 12:55:04,395 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 102336 states and 143827 transitions. [2024-11-13 12:55:04,650 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 101840 [2024-11-13 12:55:04,650 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:55:04,650 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:55:04,652 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:55:04,653 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:55:04,653 INFO L745 eck$LassoCheckResult]: Stem: 606010#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 606011#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 607036#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 607037#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 607964#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 606590#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 606591#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 606665#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 606666#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 607151#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 607152#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 606630#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 606429#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 606430#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 606912#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 606913#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 606787#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 606788#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 606404#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 606405#L1279 assume !(0 == ~M_E~0); 607821#L1279-2 assume !(0 == ~T1_E~0); 606031#L1284-1 assume !(0 == ~T2_E~0); 606032#L1289-1 assume !(0 == ~T3_E~0); 606778#L1294-1 assume !(0 == ~T4_E~0); 606779#L1299-1 assume !(0 == ~T5_E~0); 606791#L1304-1 assume !(0 == ~T6_E~0); 607960#L1309-1 assume !(0 == ~T7_E~0); 607965#L1314-1 assume !(0 == ~T8_E~0); 605956#L1319-1 assume !(0 == ~T9_E~0); 605957#L1324-1 assume !(0 == ~T10_E~0); 606131#L1329-1 assume !(0 == ~T11_E~0); 606132#L1334-1 assume !(0 == ~T12_E~0); 607697#L1339-1 assume !(0 == ~T13_E~0); 607803#L1344-1 assume !(0 == ~E_M~0); 607804#L1349-1 assume !(0 == ~E_1~0); 606988#L1354-1 assume !(0 == ~E_2~0); 606989#L1359-1 assume !(0 == ~E_3~0); 607466#L1364-1 assume !(0 == ~E_4~0); 606252#L1369-1 assume !(0 == ~E_5~0); 606253#L1374-1 assume !(0 == ~E_6~0); 606997#L1379-1 assume !(0 == ~E_7~0); 606998#L1384-1 assume !(0 == ~E_8~0); 607081#L1389-1 assume !(0 == ~E_9~0); 607728#L1394-1 assume !(0 == ~E_10~0); 607729#L1399-1 assume !(0 == ~E_11~0); 607862#L1404-1 assume !(0 == ~E_12~0); 606350#L1409-1 assume !(0 == ~E_13~0); 606351#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 607855#L628 assume !(1 == ~m_pc~0); 606251#L628-2 is_master_triggered_~__retres1~0#1 := 0; 606250#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 606856#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 606857#L1591 assume !(0 != activate_threads_~tmp~1#1); 607872#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 606833#L647 assume !(1 == ~t1_pc~0); 606834#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 606890#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 606891#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 607421#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 607788#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 607789#L666 assume !(1 == ~t2_pc~0); 606030#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 606195#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 606173#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 606174#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 607205#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 607206#L685 assume !(1 == ~t3_pc~0); 607320#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 607393#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 607886#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 607046#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 607047#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 606479#L704 assume !(1 == ~t4_pc~0); 606480#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 607057#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 605819#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 605820#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 606888#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 606889#L723 assume !(1 == ~t5_pc~0); 607041#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 607290#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 607459#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 607187#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 607188#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 606236#L742 assume !(1 == ~t6_pc~0); 606237#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 606393#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 606162#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 605926#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 605927#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 606312#L761 assume !(1 == ~t7_pc~0); 606313#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 606191#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 606192#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 607048#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 607049#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 605947#L780 assume !(1 == ~t8_pc~0); 605948#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 606226#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 606227#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 607003#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 607004#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 607137#L799 assume !(1 == ~t9_pc~0); 606450#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 605949#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 605950#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 606221#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 607370#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 607163#L818 assume !(1 == ~t10_pc~0); 605734#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 605735#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 607243#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 607166#L1671 assume !(0 != activate_threads_~tmp___9~0#1); 607167#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 607215#L837 assume 1 == ~t11_pc~0; 607216#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 607033#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 607792#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 607127#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 607128#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 606846#L856 assume !(1 == ~t12_pc~0); 606847#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 607594#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 605752#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 605753#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 607569#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 607825#L875 assume 1 == ~t13_pc~0; 606789#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 606394#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 606395#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 606331#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 606332#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 607240#L1427 assume !(1 == ~M_E~0); 607226#L1427-2 assume !(1 == ~T1_E~0); 606299#L1432-1 assume !(1 == ~T2_E~0); 606300#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 607473#L1442-1 assume !(1 == ~T4_E~0); 607474#L1447-1 assume !(1 == ~T5_E~0); 607301#L1452-1 assume !(1 == ~T6_E~0); 605870#L1457-1 assume !(1 == ~T7_E~0); 605871#L1462-1 assume !(1 == ~T8_E~0); 607498#L1467-1 assume !(1 == ~T9_E~0); 607527#L1472-1 assume !(1 == ~T10_E~0); 607528#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 607236#L1482-1 assume !(1 == ~T12_E~0); 607237#L1487-1 assume !(1 == ~T13_E~0); 606201#L1492-1 assume !(1 == ~E_M~0); 606202#L1497-1 assume !(1 == ~E_1~0); 606572#L1502-1 assume !(1 == ~E_2~0); 606573#L1507-1 assume !(1 == ~E_3~0); 606080#L1512-1 assume !(1 == ~E_4~0); 606081#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 607621#L1522-1 assume !(1 == ~E_6~0); 606831#L1527-1 assume !(1 == ~E_7~0); 606832#L1532-1 assume !(1 == ~E_8~0); 607920#L1537-1 assume !(1 == ~E_9~0); 607067#L1542-1 assume !(1 == ~E_10~0); 606864#L1547-1 assume !(1 == ~E_11~0); 606865#L1552-1 assume !(1 == ~E_12~0); 605777#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 605778#L1562-1 assume { :end_inline_reset_delta_events } true; 606383#L1928-2 [2024-11-13 12:55:04,653 INFO L747 eck$LassoCheckResult]: Loop: 606383#L1928-2 assume !false; 637618#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 637613#L1254-1 assume !false; 637610#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 637587#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 637579#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 637578#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 637574#L1067 assume !(0 != eval_~tmp~0#1); 637573#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 637572#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 637571#L1279-3 assume !(0 == ~M_E~0); 637570#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 637569#L1284-3 assume !(0 == ~T2_E~0); 637568#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 637567#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 637566#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 637565#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 637564#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 637563#L1314-3 assume !(0 == ~T8_E~0); 637561#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 637560#L1324-3 assume !(0 == ~T10_E~0); 637559#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 637557#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 637556#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 637555#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 637554#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 637553#L1354-3 assume !(0 == ~E_2~0); 637552#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 637551#L1364-3 assume !(0 == ~E_4~0); 637550#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 637548#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 637547#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 637546#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 637544#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 637543#L1394-3 assume !(0 == ~E_10~0); 637542#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 637541#L1404-3 assume !(0 == ~E_12~0); 637540#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 637539#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 637538#L628-45 assume 1 == ~m_pc~0; 637537#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 637534#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 637531#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 637529#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 637527#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 637525#L647-45 assume !(1 == ~t1_pc~0); 637523#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 637521#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 637519#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 637517#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 637515#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 637511#L666-45 assume !(1 == ~t2_pc~0); 637508#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 637506#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 637504#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 637502#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 637500#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 637498#L685-45 assume 1 == ~t3_pc~0; 637496#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 637497#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 637545#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 637485#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 637482#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 637480#L704-45 assume !(1 == ~t4_pc~0); 637478#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 637476#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 637474#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 637472#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 637470#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 637468#L723-45 assume 1 == ~t5_pc~0; 637465#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 637462#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 637460#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 637458#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 637456#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 637454#L742-45 assume !(1 == ~t6_pc~0); 637452#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 637450#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 637448#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 637446#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 637444#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 637442#L761-45 assume 1 == ~t7_pc~0; 637439#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 637436#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 637434#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 637432#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 637430#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 637428#L780-45 assume !(1 == ~t8_pc~0); 637426#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 637424#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 637422#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 637420#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 637418#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 637416#L799-45 assume !(1 == ~t9_pc~0); 637414#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 637412#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 637410#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 637408#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 637406#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 637404#L818-45 assume !(1 == ~t10_pc~0); 637401#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 637397#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 637395#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 637393#L1671-45 assume !(0 != activate_threads_~tmp___9~0#1); 637390#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 637387#L837-45 assume 1 == ~t11_pc~0; 637385#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 637382#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 637379#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 637377#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 637375#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 637373#L856-45 assume !(1 == ~t12_pc~0); 637371#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 637368#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 637365#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 637363#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 637361#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 637359#L875-45 assume 1 == ~t13_pc~0; 637357#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 637354#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 637351#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 637349#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 637347#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 637345#L1427-3 assume !(1 == ~M_E~0); 637015#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 637343#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 637339#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 637337#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 637335#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 637334#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 637331#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 637328#L1462-3 assume !(1 == ~T8_E~0); 637324#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 637320#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 637319#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 637318#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 637317#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 637315#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 637313#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 637312#L1502-3 assume !(1 == ~E_2~0); 637311#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 637310#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 637309#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 637308#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 637307#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 637306#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 637305#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 637304#L1542-3 assume !(1 == ~E_10~0); 637303#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 637302#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 637301#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 637300#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 637298#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 637285#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 637284#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 637282#L1947 assume !(0 == start_simulation_~tmp~3#1); 637283#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 637647#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 637632#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 637630#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 637628#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 637625#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 637623#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 637621#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 606383#L1928-2 [2024-11-13 12:55:04,654 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:55:04,654 INFO L85 PathProgramCache]: Analyzing trace with hash -1665183797, now seen corresponding path program 1 times [2024-11-13 12:55:04,654 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:55:04,654 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1997223052] [2024-11-13 12:55:04,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:55:04,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:55:04,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:55:04,743 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:55:04,743 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:55:04,743 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1997223052] [2024-11-13 12:55:04,743 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1997223052] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:55:04,743 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:55:04,744 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:55:04,744 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1627650408] [2024-11-13 12:55:04,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:55:04,744 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:55:04,744 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:55:04,745 INFO L85 PathProgramCache]: Analyzing trace with hash -985392182, now seen corresponding path program 1 times [2024-11-13 12:55:04,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:55:04,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [190104001] [2024-11-13 12:55:04,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:55:04,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:55:04,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:55:04,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:55:04,824 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:55:04,824 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [190104001] [2024-11-13 12:55:04,824 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [190104001] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:55:04,825 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:55:04,825 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 12:55:04,825 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2065395724] [2024-11-13 12:55:04,825 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:55:04,825 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:55:04,825 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:55:04,825 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 12:55:04,825 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 12:55:04,826 INFO L87 Difference]: Start difference. First operand 102336 states and 143827 transitions. cyclomatic complexity: 41523 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:55:06,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:55:06,365 INFO L93 Difference]: Finished difference Result 283579 states and 396169 transitions. [2024-11-13 12:55:06,365 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 283579 states and 396169 transitions. [2024-11-13 12:55:07,974 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 281936 [2024-11-13 12:55:08,970 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 283579 states to 283579 states and 396169 transitions. [2024-11-13 12:55:08,970 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 283579 [2024-11-13 12:55:09,082 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 283579 [2024-11-13 12:55:09,082 INFO L73 IsDeterministic]: Start isDeterministic. Operand 283579 states and 396169 transitions. [2024-11-13 12:55:09,172 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:55:09,172 INFO L218 hiAutomatonCegarLoop]: Abstraction has 283579 states and 396169 transitions. [2024-11-13 12:55:09,306 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 283579 states and 396169 transitions. [2024-11-13 12:55:11,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 283579 to 281787. [2024-11-13 12:55:11,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 281787 states, 281787 states have (on average 1.397740137053874) internal successors, (393865), 281786 states have internal predecessors, (393865), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:55:12,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 281787 states to 281787 states and 393865 transitions. [2024-11-13 12:55:12,911 INFO L240 hiAutomatonCegarLoop]: Abstraction has 281787 states and 393865 transitions. [2024-11-13 12:55:12,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 12:55:12,912 INFO L424 stractBuchiCegarLoop]: Abstraction has 281787 states and 393865 transitions. [2024-11-13 12:55:12,912 INFO L331 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-13 12:55:12,913 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 281787 states and 393865 transitions. [2024-11-13 12:55:13,629 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 280528 [2024-11-13 12:55:13,629 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:55:13,629 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:55:13,631 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:55:13,631 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:55:13,632 INFO L745 eck$LassoCheckResult]: Stem: 991936#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 991937#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 992962#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 992963#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 993911#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 992519#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 992520#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 992591#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 992592#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 993072#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 993073#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 992554#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 992353#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 992354#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 992837#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 992838#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 992709#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 992710#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 992327#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 992328#L1279 assume !(0 == ~M_E~0); 993763#L1279-2 assume !(0 == ~T1_E~0); 991958#L1284-1 assume !(0 == ~T2_E~0); 991959#L1289-1 assume !(0 == ~T3_E~0); 992706#L1294-1 assume !(0 == ~T4_E~0); 992707#L1299-1 assume !(0 == ~T5_E~0); 992719#L1304-1 assume !(0 == ~T6_E~0); 993908#L1309-1 assume !(0 == ~T7_E~0); 993912#L1314-1 assume !(0 == ~T8_E~0); 991881#L1319-1 assume !(0 == ~T9_E~0); 991882#L1324-1 assume !(0 == ~T10_E~0); 992059#L1329-1 assume !(0 == ~T11_E~0); 992060#L1334-1 assume !(0 == ~T12_E~0); 993632#L1339-1 assume !(0 == ~T13_E~0); 993752#L1344-1 assume !(0 == ~E_M~0); 993753#L1349-1 assume !(0 == ~E_1~0); 992914#L1354-1 assume !(0 == ~E_2~0); 992915#L1359-1 assume !(0 == ~E_3~0); 993389#L1364-1 assume !(0 == ~E_4~0); 992181#L1369-1 assume !(0 == ~E_5~0); 992182#L1374-1 assume !(0 == ~E_6~0); 992922#L1379-1 assume !(0 == ~E_7~0); 992923#L1384-1 assume !(0 == ~E_8~0); 993012#L1389-1 assume !(0 == ~E_9~0); 993664#L1394-1 assume !(0 == ~E_10~0); 993665#L1399-1 assume !(0 == ~E_11~0); 993805#L1404-1 assume !(0 == ~E_12~0); 992275#L1409-1 assume !(0 == ~E_13~0); 992276#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 993799#L628 assume !(1 == ~m_pc~0); 992180#L628-2 is_master_triggered_~__retres1~0#1 := 0; 992179#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 992782#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 992783#L1591 assume !(0 != activate_threads_~tmp~1#1); 993814#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 992758#L647 assume !(1 == ~t1_pc~0); 992759#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 992815#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 992816#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 993341#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 993731#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 993732#L666 assume !(1 == ~t2_pc~0); 991957#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 992121#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 992099#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 992100#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 993131#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 993132#L685 assume !(1 == ~t3_pc~0); 993311#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 993312#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 993322#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 992974#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 992975#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 992402#L704 assume !(1 == ~t4_pc~0); 992403#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 992988#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 991745#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 991746#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 992813#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 992814#L723 assume !(1 == ~t5_pc~0); 992969#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 993207#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 993381#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 993109#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 993110#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 992164#L742 assume !(1 == ~t6_pc~0); 992165#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 992316#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 992090#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 991852#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 991853#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 992241#L761 assume !(1 == ~t7_pc~0); 992242#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 992117#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 992118#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 992977#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 992978#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 991874#L780 assume !(1 == ~t8_pc~0); 991875#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 992155#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 992156#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 992931#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 992932#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 993059#L799 assume !(1 == ~t9_pc~0); 992374#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 991876#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 991877#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 992150#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 993283#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 993089#L818 assume !(1 == ~t10_pc~0); 991660#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 991661#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 993165#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 993092#L1671 assume !(0 != activate_threads_~tmp___9~0#1); 993093#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 993140#L837 assume !(1 == ~t11_pc~0); 992959#L837-2 is_transmit11_triggered_~__retres1~11#1 := 0; 992960#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 993737#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 993052#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 993053#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 992768#L856 assume !(1 == ~t12_pc~0); 992769#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 993530#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 991678#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 991679#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 993500#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 993766#L875 assume 1 == ~t13_pc~0; 992717#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 992317#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 992318#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 992257#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 992258#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 993164#L1427 assume !(1 == ~M_E~0); 993148#L1427-2 assume !(1 == ~T1_E~0); 992229#L1432-1 assume !(1 == ~T2_E~0); 992230#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 993395#L1442-1 assume !(1 == ~T4_E~0); 993396#L1447-1 assume !(1 == ~T5_E~0); 993221#L1452-1 assume !(1 == ~T6_E~0); 991797#L1457-1 assume !(1 == ~T7_E~0); 991798#L1462-1 assume !(1 == ~T8_E~0); 993424#L1467-1 assume !(1 == ~T9_E~0); 993454#L1472-1 assume !(1 == ~T10_E~0); 993455#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 993160#L1482-1 assume !(1 == ~T12_E~0); 993161#L1487-1 assume !(1 == ~T13_E~0); 992130#L1492-1 assume !(1 == ~E_M~0); 992131#L1497-1 assume !(1 == ~E_1~0); 992499#L1502-1 assume !(1 == ~E_2~0); 992500#L1507-1 assume !(1 == ~E_3~0); 992008#L1512-1 assume !(1 == ~E_4~0); 992009#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 993555#L1522-1 assume !(1 == ~E_6~0); 992755#L1527-1 assume !(1 == ~E_7~0); 992756#L1532-1 assume !(1 == ~E_8~0); 993871#L1537-1 assume !(1 == ~E_9~0); 992995#L1542-1 assume !(1 == ~E_10~0); 992790#L1547-1 assume !(1 == ~E_11~0); 992791#L1552-1 assume !(1 == ~E_12~0); 991701#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 991702#L1562-1 assume { :end_inline_reset_delta_events } true; 992307#L1928-2 [2024-11-13 12:55:13,632 INFO L747 eck$LassoCheckResult]: Loop: 992307#L1928-2 assume !false; 1162495#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1162489#L1254-1 assume !false; 1162487#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1162469#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1162461#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1162459#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1162456#L1067 assume !(0 != eval_~tmp~0#1); 1162454#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1162452#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1162448#L1279-3 assume !(0 == ~M_E~0); 1162446#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1162444#L1284-3 assume !(0 == ~T2_E~0); 1162442#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1162439#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1162437#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1162435#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1162433#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1162431#L1314-3 assume !(0 == ~T8_E~0); 1162429#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1162427#L1324-3 assume !(0 == ~T10_E~0); 1162425#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1162423#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1162420#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1162418#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1162416#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1162414#L1354-3 assume !(0 == ~E_2~0); 1162412#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1162410#L1364-3 assume !(0 == ~E_4~0); 1162407#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1162405#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1162403#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1162401#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1162399#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1162395#L1394-3 assume !(0 == ~E_10~0); 1162393#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1162391#L1404-3 assume !(0 == ~E_12~0); 1162390#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1162387#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1162386#L628-45 assume 1 == ~m_pc~0; 1162385#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1162383#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1162382#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1162380#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1162379#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1162378#L647-45 assume !(1 == ~t1_pc~0); 1162375#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 1162374#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1162373#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1162372#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1162371#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1162369#L666-45 assume !(1 == ~t2_pc~0); 1162368#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 1162367#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1162366#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1162365#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1162364#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1162363#L685-45 assume !(1 == ~t3_pc~0); 1162362#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 1162361#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1162360#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1162358#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 1162357#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1162356#L704-45 assume !(1 == ~t4_pc~0); 1162355#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 1162354#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1162353#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1162352#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1162350#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1162349#L723-45 assume 1 == ~t5_pc~0; 1162347#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1162346#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1162345#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1162344#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 1162343#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1162342#L742-45 assume !(1 == ~t6_pc~0); 1162340#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 1162337#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1162335#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1162333#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1162331#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1162329#L761-45 assume !(1 == ~t7_pc~0); 1162327#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 1162324#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1162322#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1162320#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1162318#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1162316#L780-45 assume !(1 == ~t8_pc~0); 1162313#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 1162311#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1162309#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1162307#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1162305#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1162303#L799-45 assume !(1 == ~t9_pc~0); 1162301#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 1162299#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1162297#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1162295#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1162293#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1162291#L818-45 assume 1 == ~t10_pc~0; 1162289#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1162290#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1162351#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1162280#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1162278#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1162276#L837-45 assume !(1 == ~t11_pc~0); 1162274#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 1162271#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1162269#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1162267#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1162265#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1162263#L856-45 assume !(1 == ~t12_pc~0); 1162261#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 1162258#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1162256#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1162254#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1162252#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1162250#L875-45 assume !(1 == ~t13_pc~0); 1162247#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 1162244#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1162242#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1162240#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1162238#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1162236#L1427-3 assume !(1 == ~M_E~0); 1161869#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1162233#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1162231#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1162229#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1162227#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1162225#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1162223#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1162221#L1462-3 assume !(1 == ~T8_E~0); 1162219#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1162217#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1162215#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1162213#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1162212#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1162208#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1162206#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1162204#L1502-3 assume !(1 == ~E_2~0); 1162202#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1162199#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1162197#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1162195#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1162193#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1162191#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1162189#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1162187#L1542-3 assume !(1 == ~E_10~0); 1162185#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1162183#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1162180#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1162178#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1162170#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1162156#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1162154#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1162151#L1947 assume !(0 == start_simulation_~tmp~3#1); 1162152#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1162522#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1162508#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1162506#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 1162504#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1162502#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1162500#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1162498#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 992307#L1928-2 [2024-11-13 12:55:13,633 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:55:13,633 INFO L85 PathProgramCache]: Analyzing trace with hash 736341324, now seen corresponding path program 1 times [2024-11-13 12:55:13,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:55:13,633 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1858813494] [2024-11-13 12:55:13,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:55:13,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:55:13,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:55:13,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:55:13,721 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:55:13,721 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1858813494] [2024-11-13 12:55:13,721 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1858813494] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:55:13,721 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:55:13,721 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 12:55:13,721 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [172661112] [2024-11-13 12:55:13,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:55:13,722 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:55:13,722 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:55:13,722 INFO L85 PathProgramCache]: Analyzing trace with hash 278071949, now seen corresponding path program 1 times [2024-11-13 12:55:13,722 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:55:13,722 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [382506942] [2024-11-13 12:55:13,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:55:13,723 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:55:13,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:55:13,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:55:13,787 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:55:13,787 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [382506942] [2024-11-13 12:55:13,787 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [382506942] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:55:13,787 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:55:13,787 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:55:13,788 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [411791645] [2024-11-13 12:55:13,788 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:55:13,788 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:55:13,788 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:55:13,789 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:55:13,789 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:55:13,789 INFO L87 Difference]: Start difference. First operand 281787 states and 393865 transitions. cyclomatic complexity: 112142 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:55:16,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:55:16,951 INFO L93 Difference]: Finished difference Result 541610 states and 754806 transitions. [2024-11-13 12:55:16,951 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 541610 states and 754806 transitions. [2024-11-13 12:55:19,194 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 538880 [2024-11-13 12:55:20,880 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 541610 states to 541610 states and 754806 transitions. [2024-11-13 12:55:20,880 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 541610 [2024-11-13 12:55:21,086 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 541610 [2024-11-13 12:55:21,086 INFO L73 IsDeterministic]: Start isDeterministic. Operand 541610 states and 754806 transitions. [2024-11-13 12:55:21,314 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:55:21,314 INFO L218 hiAutomatonCegarLoop]: Abstraction has 541610 states and 754806 transitions. [2024-11-13 12:55:21,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 541610 states and 754806 transitions. [2024-11-13 12:55:25,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 541610 to 541226.