./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.14.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ae7ee9b-cd1b-4b6f-a99a-e8d2faf04dd4/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ae7ee9b-cd1b-4b6f-a99a-e8d2faf04dd4/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ae7ee9b-cd1b-4b6f-a99a-e8d2faf04dd4/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ae7ee9b-cd1b-4b6f-a99a-e8d2faf04dd4/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.14.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ae7ee9b-cd1b-4b6f-a99a-e8d2faf04dd4/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ae7ee9b-cd1b-4b6f-a99a-e8d2faf04dd4/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 78a96934dff25285973ef889167a345947d7e73ab8a2ec405d96bd61e690530f --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 14:57:08,179 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 14:57:08,284 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ae7ee9b-cd1b-4b6f-a99a-e8d2faf04dd4/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 14:57:08,290 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 14:57:08,290 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 14:57:08,330 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 14:57:08,331 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 14:57:08,331 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 14:57:08,332 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 14:57:08,332 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 14:57:08,333 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 14:57:08,333 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 14:57:08,333 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 14:57:08,333 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 14:57:08,333 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 14:57:08,333 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 14:57:08,333 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 14:57:08,334 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 14:57:08,334 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 14:57:08,334 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 14:57:08,334 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 14:57:08,334 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 14:57:08,334 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 14:57:08,334 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 14:57:08,334 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 14:57:08,336 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 14:57:08,336 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 14:57:08,337 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 14:57:08,337 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 14:57:08,337 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 14:57:08,337 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 14:57:08,337 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 14:57:08,337 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 14:57:08,337 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 14:57:08,338 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 14:57:08,338 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 14:57:08,338 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 14:57:08,338 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 14:57:08,339 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 14:57:08,339 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ae7ee9b-cd1b-4b6f-a99a-e8d2faf04dd4/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 78a96934dff25285973ef889167a345947d7e73ab8a2ec405d96bd61e690530f [2024-11-13 14:57:08,680 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 14:57:08,691 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 14:57:08,693 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 14:57:08,695 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 14:57:08,695 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 14:57:08,696 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ae7ee9b-cd1b-4b6f-a99a-e8d2faf04dd4/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/token_ring.14.cil.c Unable to find full path for "g++" [2024-11-13 14:57:10,691 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 14:57:10,990 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 14:57:10,995 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ae7ee9b-cd1b-4b6f-a99a-e8d2faf04dd4/sv-benchmarks/c/systemc/token_ring.14.cil.c [2024-11-13 14:57:11,011 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ae7ee9b-cd1b-4b6f-a99a-e8d2faf04dd4/bin/uautomizer-verify-qhAvR1uOyd/data/68244dbb3/4f96d627839a426c9a940f82cb742913/FLAGe0ab698e4 [2024-11-13 14:57:11,038 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ae7ee9b-cd1b-4b6f-a99a-e8d2faf04dd4/bin/uautomizer-verify-qhAvR1uOyd/data/68244dbb3/4f96d627839a426c9a940f82cb742913 [2024-11-13 14:57:11,041 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 14:57:11,044 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 14:57:11,046 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 14:57:11,046 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 14:57:11,055 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 14:57:11,056 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 02:57:11" (1/1) ... [2024-11-13 14:57:11,058 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@755ef848 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:57:11, skipping insertion in model container [2024-11-13 14:57:11,058 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 02:57:11" (1/1) ... [2024-11-13 14:57:11,106 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 14:57:11,481 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 14:57:11,504 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 14:57:11,652 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 14:57:11,684 INFO L204 MainTranslator]: Completed translation [2024-11-13 14:57:11,685 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:57:11 WrapperNode [2024-11-13 14:57:11,685 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 14:57:11,686 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 14:57:11,686 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 14:57:11,686 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 14:57:11,694 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:57:11" (1/1) ... [2024-11-13 14:57:11,714 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:57:11" (1/1) ... [2024-11-13 14:57:11,880 INFO L138 Inliner]: procedures = 52, calls = 69, calls flagged for inlining = 64, calls inlined = 272, statements flattened = 4158 [2024-11-13 14:57:11,881 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 14:57:11,881 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 14:57:11,881 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 14:57:11,882 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 14:57:11,892 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:57:11" (1/1) ... [2024-11-13 14:57:11,892 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:57:11" (1/1) ... [2024-11-13 14:57:11,903 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:57:11" (1/1) ... [2024-11-13 14:57:11,938 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 14:57:11,938 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:57:11" (1/1) ... [2024-11-13 14:57:11,938 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:57:11" (1/1) ... [2024-11-13 14:57:11,980 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:57:11" (1/1) ... [2024-11-13 14:57:12,026 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:57:11" (1/1) ... [2024-11-13 14:57:12,032 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:57:11" (1/1) ... [2024-11-13 14:57:12,044 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:57:11" (1/1) ... [2024-11-13 14:57:12,071 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 14:57:12,072 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 14:57:12,072 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 14:57:12,072 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 14:57:12,073 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:57:11" (1/1) ... [2024-11-13 14:57:12,084 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 14:57:12,101 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ae7ee9b-cd1b-4b6f-a99a-e8d2faf04dd4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 14:57:12,119 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ae7ee9b-cd1b-4b6f-a99a-e8d2faf04dd4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 14:57:12,125 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0ae7ee9b-cd1b-4b6f-a99a-e8d2faf04dd4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 14:57:12,155 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 14:57:12,155 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 14:57:12,155 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 14:57:12,155 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 14:57:12,347 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 14:57:12,349 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 14:57:16,275 INFO L? ?]: Removed 886 outVars from TransFormulas that were not future-live. [2024-11-13 14:57:16,275 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 14:57:16,358 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 14:57:16,361 INFO L316 CfgBuilder]: Removed 15 assume(true) statements. [2024-11-13 14:57:16,361 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 02:57:16 BoogieIcfgContainer [2024-11-13 14:57:16,361 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 14:57:16,363 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 14:57:16,363 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 14:57:16,368 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 14:57:16,369 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 14:57:16,369 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 02:57:11" (1/3) ... [2024-11-13 14:57:16,370 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@21c06d9d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 02:57:16, skipping insertion in model container [2024-11-13 14:57:16,370 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 14:57:16,371 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:57:11" (2/3) ... [2024-11-13 14:57:16,371 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@21c06d9d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 02:57:16, skipping insertion in model container [2024-11-13 14:57:16,371 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 14:57:16,371 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 02:57:16" (3/3) ... [2024-11-13 14:57:16,372 INFO L333 chiAutomizerObserver]: Analyzing ICFG token_ring.14.cil.c [2024-11-13 14:57:16,496 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 14:57:16,496 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 14:57:16,496 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 14:57:16,497 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 14:57:16,497 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 14:57:16,497 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 14:57:16,497 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 14:57:16,497 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 14:57:16,515 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1811 states, 1810 states have (on average 1.4950276243093923) internal successors, (2706), 1810 states have internal predecessors, (2706), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:16,621 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1644 [2024-11-13 14:57:16,621 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:16,622 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:16,636 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:16,637 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:16,637 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 14:57:16,641 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1811 states, 1810 states have (on average 1.4950276243093923) internal successors, (2706), 1810 states have internal predecessors, (2706), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:16,673 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1644 [2024-11-13 14:57:16,674 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:16,674 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:16,684 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:16,685 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:16,696 INFO L745 eck$LassoCheckResult]: Stem: 135#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1716#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 657#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1711#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1369#L848true assume !(1 == ~m_i~0);~m_st~0 := 2; 1480#L848-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 436#L853-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 308#L858-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2#L863-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 753#L868-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 842#L873-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1612#L878-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1578#L883-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1663#L888-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 387#L893-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 776#L898-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1788#L903-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 703#L908-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 411#L1201true assume !(0 == ~M_E~0); 1189#L1201-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1609#L1206-1true assume !(0 == ~T2_E~0); 1161#L1211-1true assume !(0 == ~T3_E~0); 1311#L1216-1true assume !(0 == ~T4_E~0); 296#L1221-1true assume !(0 == ~T5_E~0); 1253#L1226-1true assume !(0 == ~T6_E~0); 99#L1231-1true assume !(0 == ~T7_E~0); 1392#L1236-1true assume !(0 == ~T8_E~0); 1234#L1241-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 321#L1246-1true assume !(0 == ~T10_E~0); 409#L1251-1true assume !(0 == ~T11_E~0); 876#L1256-1true assume !(0 == ~T12_E~0); 6#L1261-1true assume !(0 == ~E_M~0); 1582#L1266-1true assume !(0 == ~E_1~0); 1521#L1271-1true assume !(0 == ~E_2~0); 830#L1276-1true assume !(0 == ~E_3~0); 1516#L1281-1true assume 0 == ~E_4~0;~E_4~0 := 1; 788#L1286-1true assume !(0 == ~E_5~0); 237#L1291-1true assume !(0 == ~E_6~0); 1607#L1296-1true assume !(0 == ~E_7~0); 614#L1301-1true assume !(0 == ~E_8~0); 1104#L1306-1true assume !(0 == ~E_9~0); 1078#L1311-1true assume !(0 == ~E_10~0); 212#L1316-1true assume !(0 == ~E_11~0); 1465#L1321-1true assume 0 == ~E_12~0;~E_12~0 := 1; 628#L1326-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 745#L593true assume 1 == ~m_pc~0; 862#L594true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1479#L604true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 545#is_master_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 796#L1492true assume !(0 != activate_threads_~tmp~1#1); 1236#L1492-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1127#L612true assume !(1 == ~t1_pc~0); 1671#L612-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1547#L623true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 925#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 149#L1500true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 443#L1500-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 395#L631true assume 1 == ~t2_pc~0; 353#L632true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41#L642true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 219#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 523#L1508true assume !(0 != activate_threads_~tmp___1~0#1); 1317#L1508-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 188#L650true assume !(1 == ~t3_pc~0); 962#L650-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1226#L661true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 903#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22#L1516true assume !(0 != activate_threads_~tmp___2~0#1); 972#L1516-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 772#L669true assume 1 == ~t4_pc~0; 1279#L670true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1797#L680true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 115#L1524true assume !(0 != activate_threads_~tmp___3~0#1); 244#L1524-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 988#L688true assume !(1 == ~t5_pc~0); 125#L688-2true is_transmit5_triggered_~__retres1~5#1 := 0; 1478#L699true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1453#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 671#L1532true assume !(0 != activate_threads_~tmp___4~0#1); 782#L1532-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1301#L707true assume 1 == ~t6_pc~0; 1349#L708true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 502#L718true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 213#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1375#L1540true assume !(0 != activate_threads_~tmp___5~0#1); 732#L1540-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 410#L726true assume 1 == ~t7_pc~0; 346#L727true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 915#L737true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1734#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1312#L1548true assume !(0 != activate_threads_~tmp___6~0#1); 56#L1548-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 293#L745true assume !(1 == ~t8_pc~0); 1114#L745-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1201#L756true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1396#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 550#L1556true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1025#L1556-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1802#L764true assume 1 == ~t9_pc~0; 407#L765true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 799#L775true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 255#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1439#L1564true assume !(0 != activate_threads_~tmp___8~0#1); 68#L1564-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1394#L783true assume !(1 == ~t10_pc~0); 93#L783-2true is_transmit10_triggered_~__retres1~10#1 := 0; 191#L794true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1217#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 382#L1572true assume !(0 != activate_threads_~tmp___9~0#1); 1177#L1572-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1282#L802true assume 1 == ~t11_pc~0; 1148#L803true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39#L813true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1310#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 297#L1580true assume !(0 != activate_threads_~tmp___10~0#1); 365#L1580-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 533#L821true assume !(1 == ~t12_pc~0); 605#L821-2true is_transmit12_triggered_~__retres1~12#1 := 0; 1339#L832true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1252#L1588true assume !(0 != activate_threads_~tmp___11~0#1); 1257#L1588-2true havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 805#L1339true assume !(1 == ~M_E~0); 1462#L1339-2true assume !(1 == ~T1_E~0); 1322#L1344-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1736#L1349-1true assume !(1 == ~T3_E~0); 624#L1354-1true assume !(1 == ~T4_E~0); 995#L1359-1true assume !(1 == ~T5_E~0); 1557#L1364-1true assume !(1 == ~T6_E~0); 272#L1369-1true assume !(1 == ~T7_E~0); 965#L1374-1true assume !(1 == ~T8_E~0); 626#L1379-1true assume !(1 == ~T9_E~0); 700#L1384-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1776#L1389-1true assume !(1 == ~T11_E~0); 1241#L1394-1true assume !(1 == ~T12_E~0); 1638#L1399-1true assume !(1 == ~E_M~0); 1442#L1404-1true assume !(1 == ~E_1~0); 324#L1409-1true assume !(1 == ~E_2~0); 1410#L1414-1true assume !(1 == ~E_3~0); 863#L1419-1true assume !(1 == ~E_4~0); 120#L1424-1true assume 1 == ~E_5~0;~E_5~0 := 2; 632#L1429-1true assume !(1 == ~E_6~0); 1269#L1434-1true assume !(1 == ~E_7~0); 1614#L1439-1true assume !(1 == ~E_8~0); 142#L1444-1true assume !(1 == ~E_9~0); 818#L1449-1true assume !(1 == ~E_10~0); 357#L1454-1true assume !(1 == ~E_11~0); 1309#L1459-1true assume !(1 == ~E_12~0); 730#L1464-1true assume { :end_inline_reset_delta_events } true; 492#L1810-2true [2024-11-13 14:57:16,706 INFO L747 eck$LassoCheckResult]: Loop: 492#L1810-2true assume !false; 1346#L1811true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 877#L1176-1true assume false; 496#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 325#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1058#L1201-3true assume 0 == ~M_E~0;~M_E~0 := 1; 822#L1201-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1611#L1206-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 728#L1211-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 186#L1216-3true assume !(0 == ~T4_E~0); 470#L1221-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1023#L1226-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 230#L1231-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 373#L1236-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1786#L1241-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1345#L1246-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1152#L1251-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 807#L1256-3true assume !(0 == ~T12_E~0); 196#L1261-3true assume 0 == ~E_M~0;~E_M~0 := 1; 517#L1266-3true assume 0 == ~E_1~0;~E_1~0 := 1; 226#L1271-3true assume 0 == ~E_2~0;~E_2~0 := 1; 490#L1276-3true assume 0 == ~E_3~0;~E_3~0 := 1; 456#L1281-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1211#L1286-3true assume 0 == ~E_5~0;~E_5~0 := 1; 860#L1291-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1624#L1296-3true assume !(0 == ~E_7~0); 1548#L1301-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1429#L1306-3true assume 0 == ~E_9~0;~E_9~0 := 1; 528#L1311-3true assume 0 == ~E_10~0;~E_10~0 := 1; 154#L1316-3true assume 0 == ~E_11~0;~E_11~0 := 1; 197#L1321-3true assume 0 == ~E_12~0;~E_12~0 := 1; 604#L1326-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1221#L593-42true assume !(1 == ~m_pc~0); 734#L593-44true is_master_triggered_~__retres1~0#1 := 0; 1771#L604-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 388#is_master_triggered_returnLabel#15true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1733#L1492-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 102#L1492-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 690#L612-42true assume !(1 == ~t1_pc~0); 1099#L612-44true is_transmit1_triggered_~__retres1~1#1 := 0; 1595#L623-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1625#is_transmit1_triggered_returnLabel#15true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 148#L1500-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1767#L1500-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 577#L631-42true assume 1 == ~t2_pc~0; 34#L632-14true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 566#L642-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 570#is_transmit2_triggered_returnLabel#15true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 489#L1508-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1645#L1508-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 239#L650-42true assume !(1 == ~t3_pc~0); 130#L650-44true is_transmit3_triggered_~__retres1~3#1 := 0; 1729#L661-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 890#is_transmit3_triggered_returnLabel#15true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 352#L1516-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1379#L1516-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1278#L669-42true assume !(1 == ~t4_pc~0); 18#L669-44true is_transmit4_triggered_~__retres1~4#1 := 0; 1000#L680-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 974#is_transmit4_triggered_returnLabel#15true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 872#L1524-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 781#L1524-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 859#L688-42true assume !(1 == ~t5_pc~0); 1106#L688-44true is_transmit5_triggered_~__retres1~5#1 := 0; 1358#L699-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 617#is_transmit5_triggered_returnLabel#15true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 114#L1532-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1436#L1532-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31#L707-42true assume 1 == ~t6_pc~0; 1447#L708-14true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1705#L718-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 193#is_transmit6_triggered_returnLabel#15true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1300#L1540-42true assume !(0 != activate_threads_~tmp___5~0#1); 756#L1540-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1033#L726-42true assume !(1 == ~t7_pc~0); 1801#L726-44true is_transmit7_triggered_~__retres1~7#1 := 0; 1075#L737-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 634#is_transmit7_triggered_returnLabel#15true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 531#L1548-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 608#L1548-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1197#L745-42true assume 1 == ~t8_pc~0; 638#L746-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1433#L756-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 773#is_transmit8_triggered_returnLabel#15true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26#L1556-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 428#L1556-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 514#L764-42true assume !(1 == ~t9_pc~0); 1297#L764-44true is_transmit9_triggered_~__retres1~9#1 := 0; 794#L775-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1651#is_transmit9_triggered_returnLabel#15true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 161#L1564-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 192#L1564-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 243#L783-42true assume 1 == ~t10_pc~0; 7#L784-14true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 316#L794-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 768#is_transmit10_triggered_returnLabel#15true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1550#L1572-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1528#L1572-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 959#L802-42true assume 1 == ~t11_pc~0; 276#L803-14true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 71#L813-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1366#is_transmit11_triggered_returnLabel#15true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46#L1580-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1565#L1580-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 803#L821-42true assume 1 == ~t12_pc~0; 1703#L822-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1010#L832-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 602#is_transmit12_triggered_returnLabel#15true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1165#L1588-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 557#L1588-44true havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 549#L1339-3true assume 1 == ~M_E~0;~M_E~0 := 2; 673#L1339-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 810#L1344-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 771#L1349-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 344#L1354-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 778#L1359-3true assume !(1 == ~T5_E~0); 1620#L1364-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1512#L1369-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1267#L1374-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 241#L1379-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1156#L1384-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 343#L1389-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 482#L1394-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1719#L1399-3true assume !(1 == ~E_M~0); 1288#L1404-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1233#L1409-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1344#L1414-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1363#L1419-3true assume 1 == ~E_4~0;~E_4~0 := 2; 963#L1424-3true assume 1 == ~E_5~0;~E_5~0 := 2; 171#L1429-3true assume 1 == ~E_6~0;~E_6~0 := 2; 777#L1434-3true assume 1 == ~E_7~0;~E_7~0 := 2; 930#L1439-3true assume !(1 == ~E_8~0); 136#L1444-3true assume 1 == ~E_9~0;~E_9~0 := 2; 201#L1449-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1428#L1454-3true assume 1 == ~E_11~0;~E_11~0 := 2; 774#L1459-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1785#L1464-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 503#L921-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1740#L988-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 189#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1464#L1829true assume !(0 == start_simulation_~tmp~3#1); 82#L1829-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1040#L921-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 552#L988-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 789#L1784true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1559#L1791true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1239#stop_simulation_returnLabel#1true start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 218#L1842true assume !(0 != start_simulation_~tmp___0~1#1); 492#L1810-2true [2024-11-13 14:57:16,719 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:16,720 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 1 times [2024-11-13 14:57:16,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:16,730 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2010068466] [2024-11-13 14:57:16,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:16,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:16,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:17,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:17,178 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:17,179 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2010068466] [2024-11-13 14:57:17,182 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2010068466] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:17,182 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:17,182 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:17,184 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1405321787] [2024-11-13 14:57:17,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:17,189 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:17,189 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:17,191 INFO L85 PathProgramCache]: Analyzing trace with hash 924264573, now seen corresponding path program 1 times [2024-11-13 14:57:17,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:17,191 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1139068874] [2024-11-13 14:57:17,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:17,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:17,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:17,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:17,317 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:17,321 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1139068874] [2024-11-13 14:57:17,321 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1139068874] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:17,321 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:17,321 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:57:17,321 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [950628881] [2024-11-13 14:57:17,321 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:17,323 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:17,323 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:17,358 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-13 14:57:17,359 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-13 14:57:17,365 INFO L87 Difference]: Start difference. First operand has 1811 states, 1810 states have (on average 1.4950276243093923) internal successors, (2706), 1810 states have internal predecessors, (2706), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:17,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:17,485 INFO L93 Difference]: Finished difference Result 1807 states and 2670 transitions. [2024-11-13 14:57:17,486 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1807 states and 2670 transitions. [2024-11-13 14:57:17,506 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:17,529 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1807 states to 1801 states and 2664 transitions. [2024-11-13 14:57:17,531 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-13 14:57:17,534 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-13 14:57:17,537 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2664 transitions. [2024-11-13 14:57:17,552 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:17,552 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2664 transitions. [2024-11-13 14:57:17,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2664 transitions. [2024-11-13 14:57:17,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-13 14:57:17,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4791782343142699) internal successors, (2664), 1800 states have internal predecessors, (2664), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:17,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2664 transitions. [2024-11-13 14:57:17,663 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2664 transitions. [2024-11-13 14:57:17,666 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-13 14:57:17,672 INFO L424 stractBuchiCegarLoop]: Abstraction has 1801 states and 2664 transitions. [2024-11-13 14:57:17,672 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 14:57:17,672 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2664 transitions. [2024-11-13 14:57:17,685 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:17,685 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:17,686 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:17,691 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:17,691 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:17,691 INFO L745 eck$LassoCheckResult]: Stem: 3915#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 3916#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 4760#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4761#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5347#L848 assume !(1 == ~m_i~0);~m_st~0 := 2; 5348#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4441#L853-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4230#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3627#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3628#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4872#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4971#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5409#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5410#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4366#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4367#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4898#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4823#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4403#L1201 assume !(0 == ~M_E~0); 4404#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5256#L1206-1 assume !(0 == ~T2_E~0); 5239#L1211-1 assume !(0 == ~T3_E~0); 5240#L1216-1 assume !(0 == ~T4_E~0); 4211#L1221-1 assume !(0 == ~T5_E~0); 4212#L1226-1 assume !(0 == ~T6_E~0); 3841#L1231-1 assume !(0 == ~T7_E~0); 3842#L1236-1 assume !(0 == ~T8_E~0); 5280#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4251#L1246-1 assume !(0 == ~T10_E~0); 4252#L1251-1 assume !(0 == ~T11_E~0); 4401#L1256-1 assume !(0 == ~T12_E~0); 3636#L1261-1 assume !(0 == ~E_M~0); 3637#L1266-1 assume !(0 == ~E_1~0); 5394#L1271-1 assume !(0 == ~E_2~0); 4955#L1276-1 assume !(0 == ~E_3~0); 4956#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4910#L1286-1 assume !(0 == ~E_5~0); 4107#L1291-1 assume !(0 == ~E_6~0); 4108#L1296-1 assume !(0 == ~E_7~0); 4696#L1301-1 assume !(0 == ~E_8~0); 4697#L1306-1 assume !(0 == ~E_9~0); 5175#L1311-1 assume !(0 == ~E_10~0); 4058#L1316-1 assume !(0 == ~E_11~0); 4059#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 4715#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4716#L593 assume 1 == ~m_pc~0; 4865#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3940#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4604#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4605#L1492 assume !(0 != activate_threads_~tmp~1#1); 4920#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5208#L612 assume !(1 == ~t1_pc~0); 5209#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5343#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5053#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3943#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3944#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4382#L631 assume 1 == ~t2_pc~0; 4309#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3717#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3718#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4072#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 4568#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4019#L650 assume !(1 == ~t3_pc~0); 4020#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4738#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5032#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3674#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 3675#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4891#L669 assume 1 == ~t4_pc~0; 4892#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5247#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3757#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3758#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 3878#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4117#L688 assume !(1 == ~t5_pc~0); 3897#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3898#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5375#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4780#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 4781#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4905#L707 assume 1 == ~t6_pc~0; 5314#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4537#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4060#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4061#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 4851#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4402#L726 assume 1 == ~t7_pc~0; 4297#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3984#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5044#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5318#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 3747#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3748#L745 assume !(1 == ~t8_pc~0); 4204#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4224#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5262#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4613#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4614#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5132#L764 assume 1 == ~t9_pc~0; 4400#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4234#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4133#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4134#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 3773#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3774#L783 assume !(1 == ~t10_pc~0); 3828#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3829#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4026#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4356#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 4357#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5249#L802 assume 1 == ~t11_pc~0; 5231#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3714#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3715#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4213#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 4214#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4331#L821 assume !(1 == ~t12_pc~0); 4582#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4688#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3721#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3722#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 5291#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4928#L1339 assume !(1 == ~M_E~0); 4929#L1339-2 assume !(1 == ~T1_E~0); 5321#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5322#L1349-1 assume !(1 == ~T3_E~0); 4708#L1354-1 assume !(1 == ~T4_E~0); 4709#L1359-1 assume !(1 == ~T5_E~0); 5108#L1364-1 assume !(1 == ~T6_E~0); 4165#L1369-1 assume !(1 == ~T7_E~0); 4166#L1374-1 assume !(1 == ~T8_E~0); 4711#L1379-1 assume !(1 == ~T9_E~0); 4712#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4820#L1389-1 assume !(1 == ~T11_E~0); 5285#L1394-1 assume !(1 == ~T12_E~0); 5286#L1399-1 assume !(1 == ~E_M~0); 5367#L1404-1 assume !(1 == ~E_1~0); 4258#L1409-1 assume !(1 == ~E_2~0); 4259#L1414-1 assume !(1 == ~E_3~0); 4991#L1419-1 assume !(1 == ~E_4~0); 3887#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 3888#L1429-1 assume !(1 == ~E_6~0); 4723#L1434-1 assume !(1 == ~E_7~0); 5303#L1439-1 assume !(1 == ~E_8~0); 3929#L1444-1 assume !(1 == ~E_9~0); 3930#L1449-1 assume !(1 == ~E_10~0); 4315#L1454-1 assume !(1 == ~E_11~0); 4316#L1459-1 assume !(1 == ~E_12~0); 4850#L1464-1 assume { :end_inline_reset_delta_events } true; 4071#L1810-2 [2024-11-13 14:57:17,694 INFO L747 eck$LassoCheckResult]: Loop: 4071#L1810-2 assume !false; 4521#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4619#L1176-1 assume !false; 5001#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4565#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3755#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 5055#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5226#L1003 assume !(0 != eval_~tmp~0#1); 4528#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4260#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4261#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4945#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4946#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4848#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4014#L1216-3 assume !(0 == ~T4_E~0); 4015#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4493#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4093#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4094#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4345#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5334#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5234#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4933#L1256-3 assume !(0 == ~T12_E~0); 4034#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4035#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4085#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4086#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4469#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4470#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4988#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4989#L1296-3 assume !(0 == ~E_7~0); 5406#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5364#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4573#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3954#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3955#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4036#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4687#L593-42 assume 1 == ~m_pc~0; 5074#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4853#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4368#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4369#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3848#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3849#L612-42 assume !(1 == ~t1_pc~0); 4807#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 5188#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5415#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3941#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3942#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4650#L631-42 assume 1 == ~t2_pc~0; 3701#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3702#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4635#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4519#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4520#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4112#L650-42 assume 1 == ~t3_pc~0; 3666#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3667#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5021#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4307#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4308#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5305#L669-42 assume !(1 == ~t4_pc~0); 3664#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 3665#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5090#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4999#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4903#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4904#L688-42 assume 1 == ~t5_pc~0; 4986#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5191#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4699#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3876#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3877#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3694#L707-42 assume 1 == ~t6_pc~0; 3696#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5370#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4028#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4029#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 4874#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4875#L726-42 assume 1 == ~t7_pc~0; 5141#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5172#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4726#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4577#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4578#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4691#L745-42 assume 1 == ~t8_pc~0; 4729#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4730#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4894#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3682#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3683#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4428#L764-42 assume 1 == ~t9_pc~0; 4556#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4917#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4918#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3966#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3967#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4027#L783-42 assume 1 == ~t10_pc~0; 3638#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3640#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4243#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4886#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5397#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5080#L802-42 assume 1 == ~t11_pc~0; 4174#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3780#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3781#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3727#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3728#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4925#L821-42 assume !(1 == ~t12_pc~0); 4283#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 4284#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4684#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4685#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4621#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4611#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4612#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4784#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4890#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4293#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4294#L1359-3 assume !(1 == ~T5_E~0); 4900#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5391#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5301#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4114#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4115#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4291#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4292#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4507#L1399-3 assume !(1 == ~E_M~0); 5310#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5278#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5279#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5333#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5083#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3988#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3989#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4899#L1439-3 assume !(1 == ~E_8~0); 3917#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3918#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4039#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4895#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4896#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4538#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3821#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4022#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4023#L1829 assume !(0 == start_simulation_~tmp~3#1); 3802#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3803#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4617#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3707#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 3708#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4911#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5284#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4070#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 4071#L1810-2 [2024-11-13 14:57:17,695 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:17,697 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 2 times [2024-11-13 14:57:17,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:17,697 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1917017052] [2024-11-13 14:57:17,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:17,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:17,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:17,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:17,882 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:17,882 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1917017052] [2024-11-13 14:57:17,882 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1917017052] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:17,882 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:17,882 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:17,883 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1330174376] [2024-11-13 14:57:17,883 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:17,883 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:17,883 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:17,884 INFO L85 PathProgramCache]: Analyzing trace with hash -754464488, now seen corresponding path program 1 times [2024-11-13 14:57:17,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:17,884 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [805066362] [2024-11-13 14:57:17,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:17,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:17,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:18,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:18,076 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:18,076 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [805066362] [2024-11-13 14:57:18,077 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [805066362] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:18,077 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:18,077 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:18,077 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [284893156] [2024-11-13 14:57:18,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:18,077 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:18,082 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:18,082 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:57:18,082 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:57:18,083 INFO L87 Difference]: Start difference. First operand 1801 states and 2664 transitions. cyclomatic complexity: 864 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:18,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:18,158 INFO L93 Difference]: Finished difference Result 1801 states and 2663 transitions. [2024-11-13 14:57:18,159 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2663 transitions. [2024-11-13 14:57:18,193 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:18,204 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2663 transitions. [2024-11-13 14:57:18,204 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-13 14:57:18,208 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-13 14:57:18,208 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2663 transitions. [2024-11-13 14:57:18,215 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:18,215 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2663 transitions. [2024-11-13 14:57:18,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2663 transitions. [2024-11-13 14:57:18,242 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-13 14:57:18,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.478622987229317) internal successors, (2663), 1800 states have internal predecessors, (2663), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:18,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2663 transitions. [2024-11-13 14:57:18,254 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2663 transitions. [2024-11-13 14:57:18,254 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:57:18,255 INFO L424 stractBuchiCegarLoop]: Abstraction has 1801 states and 2663 transitions. [2024-11-13 14:57:18,255 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 14:57:18,255 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2663 transitions. [2024-11-13 14:57:18,265 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:18,265 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:18,265 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:18,268 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:18,268 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:18,268 INFO L745 eck$LassoCheckResult]: Stem: 7524#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 7525#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 8369#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8370#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8956#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 8957#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8050#L853-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7839#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7236#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7237#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8481#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8580#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9018#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9019#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7975#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7976#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8507#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8432#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8012#L1201 assume !(0 == ~M_E~0); 8013#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8865#L1206-1 assume !(0 == ~T2_E~0); 8848#L1211-1 assume !(0 == ~T3_E~0); 8849#L1216-1 assume !(0 == ~T4_E~0); 7820#L1221-1 assume !(0 == ~T5_E~0); 7821#L1226-1 assume !(0 == ~T6_E~0); 7450#L1231-1 assume !(0 == ~T7_E~0); 7451#L1236-1 assume !(0 == ~T8_E~0); 8889#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7860#L1246-1 assume !(0 == ~T10_E~0); 7861#L1251-1 assume !(0 == ~T11_E~0); 8010#L1256-1 assume !(0 == ~T12_E~0); 7245#L1261-1 assume !(0 == ~E_M~0); 7246#L1266-1 assume !(0 == ~E_1~0); 9003#L1271-1 assume !(0 == ~E_2~0); 8564#L1276-1 assume !(0 == ~E_3~0); 8565#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8519#L1286-1 assume !(0 == ~E_5~0); 7716#L1291-1 assume !(0 == ~E_6~0); 7717#L1296-1 assume !(0 == ~E_7~0); 8305#L1301-1 assume !(0 == ~E_8~0); 8306#L1306-1 assume !(0 == ~E_9~0); 8784#L1311-1 assume !(0 == ~E_10~0); 7667#L1316-1 assume !(0 == ~E_11~0); 7668#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 8324#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8325#L593 assume 1 == ~m_pc~0; 8474#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7549#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8213#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8214#L1492 assume !(0 != activate_threads_~tmp~1#1); 8529#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8817#L612 assume !(1 == ~t1_pc~0); 8818#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8952#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8662#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7552#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7553#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7991#L631 assume 1 == ~t2_pc~0; 7918#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7326#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7327#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7681#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 8177#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7628#L650 assume !(1 == ~t3_pc~0); 7629#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8347#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8641#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7283#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 7284#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8500#L669 assume 1 == ~t4_pc~0; 8501#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8856#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7366#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7367#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 7487#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7726#L688 assume !(1 == ~t5_pc~0); 7506#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7507#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8984#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8389#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 8390#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8514#L707 assume 1 == ~t6_pc~0; 8923#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8146#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7669#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7670#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 8460#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8011#L726 assume 1 == ~t7_pc~0; 7906#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7593#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8653#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8927#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 7356#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7357#L745 assume !(1 == ~t8_pc~0); 7813#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7833#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8871#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8222#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8223#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8741#L764 assume 1 == ~t9_pc~0; 8009#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7843#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7742#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7743#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 7382#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7383#L783 assume !(1 == ~t10_pc~0); 7437#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7438#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7635#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7965#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 7966#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8858#L802 assume 1 == ~t11_pc~0; 8840#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7323#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7324#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7822#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 7823#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7940#L821 assume !(1 == ~t12_pc~0); 8191#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8297#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7330#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7331#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 8900#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8537#L1339 assume !(1 == ~M_E~0); 8538#L1339-2 assume !(1 == ~T1_E~0); 8930#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8931#L1349-1 assume !(1 == ~T3_E~0); 8317#L1354-1 assume !(1 == ~T4_E~0); 8318#L1359-1 assume !(1 == ~T5_E~0); 8717#L1364-1 assume !(1 == ~T6_E~0); 7774#L1369-1 assume !(1 == ~T7_E~0); 7775#L1374-1 assume !(1 == ~T8_E~0); 8320#L1379-1 assume !(1 == ~T9_E~0); 8321#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8429#L1389-1 assume !(1 == ~T11_E~0); 8894#L1394-1 assume !(1 == ~T12_E~0); 8895#L1399-1 assume !(1 == ~E_M~0); 8976#L1404-1 assume !(1 == ~E_1~0); 7867#L1409-1 assume !(1 == ~E_2~0); 7868#L1414-1 assume !(1 == ~E_3~0); 8600#L1419-1 assume !(1 == ~E_4~0); 7496#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 7497#L1429-1 assume !(1 == ~E_6~0); 8332#L1434-1 assume !(1 == ~E_7~0); 8912#L1439-1 assume !(1 == ~E_8~0); 7538#L1444-1 assume !(1 == ~E_9~0); 7539#L1449-1 assume !(1 == ~E_10~0); 7924#L1454-1 assume !(1 == ~E_11~0); 7925#L1459-1 assume !(1 == ~E_12~0); 8459#L1464-1 assume { :end_inline_reset_delta_events } true; 7680#L1810-2 [2024-11-13 14:57:18,269 INFO L747 eck$LassoCheckResult]: Loop: 7680#L1810-2 assume !false; 8130#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8228#L1176-1 assume !false; 8610#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8174#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7364#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 8664#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8835#L1003 assume !(0 != eval_~tmp~0#1); 8137#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7869#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7870#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8554#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8555#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8457#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7623#L1216-3 assume !(0 == ~T4_E~0); 7624#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8102#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7702#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7703#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7954#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8943#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8843#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8542#L1256-3 assume !(0 == ~T12_E~0); 7643#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7644#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7694#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7695#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8078#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8079#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8597#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8598#L1296-3 assume !(0 == ~E_7~0); 9015#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8973#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8182#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7563#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7564#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 7645#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8296#L593-42 assume 1 == ~m_pc~0; 8683#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8462#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7977#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7978#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7457#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7458#L612-42 assume !(1 == ~t1_pc~0); 8416#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 8797#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9024#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7550#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7551#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8259#L631-42 assume !(1 == ~t2_pc~0); 7312#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 7311#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8244#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8128#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8129#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7721#L650-42 assume 1 == ~t3_pc~0; 7275#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7276#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8630#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7916#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7917#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8914#L669-42 assume 1 == ~t4_pc~0; 8196#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7274#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8699#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8608#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8512#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8513#L688-42 assume 1 == ~t5_pc~0; 8595#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8800#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8308#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7485#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7486#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7303#L707-42 assume !(1 == ~t6_pc~0); 7304#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 8979#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7637#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7638#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 8483#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8484#L726-42 assume 1 == ~t7_pc~0; 8750#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8781#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8335#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8186#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8187#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8300#L745-42 assume 1 == ~t8_pc~0; 8338#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8339#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8503#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7291#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7292#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8037#L764-42 assume 1 == ~t9_pc~0; 8165#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8526#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8527#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7575#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7576#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7636#L783-42 assume !(1 == ~t10_pc~0); 7248#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 7249#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7852#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8495#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9006#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8689#L802-42 assume 1 == ~t11_pc~0; 7783#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7389#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7390#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7336#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7337#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8534#L821-42 assume !(1 == ~t12_pc~0); 7892#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 7893#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8293#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8294#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8230#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8220#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8221#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8393#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8499#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7902#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7903#L1359-3 assume !(1 == ~T5_E~0); 8509#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9000#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8910#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7723#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7724#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7900#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7901#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8116#L1399-3 assume !(1 == ~E_M~0); 8919#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8887#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8888#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8942#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8692#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7597#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7598#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8508#L1439-3 assume !(1 == ~E_8~0); 7526#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7527#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7648#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8504#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8505#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8147#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7430#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7631#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 7632#L1829 assume !(0 == start_simulation_~tmp~3#1); 7411#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7412#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 8226#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7316#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 7317#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8520#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8893#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 7679#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 7680#L1810-2 [2024-11-13 14:57:18,269 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:18,269 INFO L85 PathProgramCache]: Analyzing trace with hash -494851220, now seen corresponding path program 1 times [2024-11-13 14:57:18,269 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:18,269 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2114955601] [2024-11-13 14:57:18,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:18,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:18,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:18,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:18,341 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:18,341 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2114955601] [2024-11-13 14:57:18,341 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2114955601] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:18,341 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:18,341 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:18,341 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1749446474] [2024-11-13 14:57:18,341 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:18,342 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:18,342 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:18,342 INFO L85 PathProgramCache]: Analyzing trace with hash 116071706, now seen corresponding path program 1 times [2024-11-13 14:57:18,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:18,342 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1415594589] [2024-11-13 14:57:18,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:18,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:18,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:18,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:18,488 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:18,488 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1415594589] [2024-11-13 14:57:18,488 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1415594589] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:18,488 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:18,488 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:18,488 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [636558870] [2024-11-13 14:57:18,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:18,489 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:18,489 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:18,489 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:57:18,489 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:57:18,489 INFO L87 Difference]: Start difference. First operand 1801 states and 2663 transitions. cyclomatic complexity: 863 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:18,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:18,542 INFO L93 Difference]: Finished difference Result 1801 states and 2662 transitions. [2024-11-13 14:57:18,542 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2662 transitions. [2024-11-13 14:57:18,555 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:18,565 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2662 transitions. [2024-11-13 14:57:18,565 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-13 14:57:18,567 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-13 14:57:18,568 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2662 transitions. [2024-11-13 14:57:18,571 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:18,571 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2662 transitions. [2024-11-13 14:57:18,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2662 transitions. [2024-11-13 14:57:18,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-13 14:57:18,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4780677401443643) internal successors, (2662), 1800 states have internal predecessors, (2662), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:18,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2662 transitions. [2024-11-13 14:57:18,638 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2662 transitions. [2024-11-13 14:57:18,640 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:57:18,642 INFO L424 stractBuchiCegarLoop]: Abstraction has 1801 states and 2662 transitions. [2024-11-13 14:57:18,642 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 14:57:18,642 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2662 transitions. [2024-11-13 14:57:18,652 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:18,652 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:18,653 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:18,655 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:18,655 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:18,656 INFO L745 eck$LassoCheckResult]: Stem: 11133#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 11134#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11978#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11979#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12565#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 12566#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11659#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11448#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10845#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10846#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12090#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12189#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12627#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12628#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11584#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11585#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12116#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12041#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11621#L1201 assume !(0 == ~M_E~0); 11622#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12474#L1206-1 assume !(0 == ~T2_E~0); 12457#L1211-1 assume !(0 == ~T3_E~0); 12458#L1216-1 assume !(0 == ~T4_E~0); 11429#L1221-1 assume !(0 == ~T5_E~0); 11430#L1226-1 assume !(0 == ~T6_E~0); 11059#L1231-1 assume !(0 == ~T7_E~0); 11060#L1236-1 assume !(0 == ~T8_E~0); 12498#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11469#L1246-1 assume !(0 == ~T10_E~0); 11470#L1251-1 assume !(0 == ~T11_E~0); 11619#L1256-1 assume !(0 == ~T12_E~0); 10854#L1261-1 assume !(0 == ~E_M~0); 10855#L1266-1 assume !(0 == ~E_1~0); 12612#L1271-1 assume !(0 == ~E_2~0); 12173#L1276-1 assume !(0 == ~E_3~0); 12174#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12128#L1286-1 assume !(0 == ~E_5~0); 11325#L1291-1 assume !(0 == ~E_6~0); 11326#L1296-1 assume !(0 == ~E_7~0); 11914#L1301-1 assume !(0 == ~E_8~0); 11915#L1306-1 assume !(0 == ~E_9~0); 12393#L1311-1 assume !(0 == ~E_10~0); 11276#L1316-1 assume !(0 == ~E_11~0); 11277#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 11933#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11934#L593 assume 1 == ~m_pc~0; 12083#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11158#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11822#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11823#L1492 assume !(0 != activate_threads_~tmp~1#1); 12138#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12426#L612 assume !(1 == ~t1_pc~0); 12427#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12561#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12271#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11161#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11162#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11600#L631 assume 1 == ~t2_pc~0; 11527#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10935#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10936#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11290#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 11786#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11237#L650 assume !(1 == ~t3_pc~0); 11238#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11956#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12250#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10892#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 10893#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12109#L669 assume 1 == ~t4_pc~0; 12110#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12465#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10975#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10976#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 11096#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11335#L688 assume !(1 == ~t5_pc~0); 11115#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11116#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12593#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11998#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 11999#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12123#L707 assume 1 == ~t6_pc~0; 12532#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11755#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11278#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11279#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 12069#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11620#L726 assume 1 == ~t7_pc~0; 11515#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11202#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12262#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12536#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 10965#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10966#L745 assume !(1 == ~t8_pc~0); 11422#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11442#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12480#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11831#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11832#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12350#L764 assume 1 == ~t9_pc~0; 11618#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11452#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11351#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11352#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 10991#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10992#L783 assume !(1 == ~t10_pc~0); 11046#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11047#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11244#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11574#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 11575#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12467#L802 assume 1 == ~t11_pc~0; 12449#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10932#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10933#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11431#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 11432#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11549#L821 assume !(1 == ~t12_pc~0); 11800#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 11906#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10939#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 10940#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 12509#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12146#L1339 assume !(1 == ~M_E~0); 12147#L1339-2 assume !(1 == ~T1_E~0); 12539#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12540#L1349-1 assume !(1 == ~T3_E~0); 11926#L1354-1 assume !(1 == ~T4_E~0); 11927#L1359-1 assume !(1 == ~T5_E~0); 12326#L1364-1 assume !(1 == ~T6_E~0); 11383#L1369-1 assume !(1 == ~T7_E~0); 11384#L1374-1 assume !(1 == ~T8_E~0); 11929#L1379-1 assume !(1 == ~T9_E~0); 11930#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12038#L1389-1 assume !(1 == ~T11_E~0); 12503#L1394-1 assume !(1 == ~T12_E~0); 12504#L1399-1 assume !(1 == ~E_M~0); 12585#L1404-1 assume !(1 == ~E_1~0); 11476#L1409-1 assume !(1 == ~E_2~0); 11477#L1414-1 assume !(1 == ~E_3~0); 12209#L1419-1 assume !(1 == ~E_4~0); 11105#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 11106#L1429-1 assume !(1 == ~E_6~0); 11941#L1434-1 assume !(1 == ~E_7~0); 12521#L1439-1 assume !(1 == ~E_8~0); 11147#L1444-1 assume !(1 == ~E_9~0); 11148#L1449-1 assume !(1 == ~E_10~0); 11533#L1454-1 assume !(1 == ~E_11~0); 11534#L1459-1 assume !(1 == ~E_12~0); 12068#L1464-1 assume { :end_inline_reset_delta_events } true; 11289#L1810-2 [2024-11-13 14:57:18,656 INFO L747 eck$LassoCheckResult]: Loop: 11289#L1810-2 assume !false; 11739#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11837#L1176-1 assume !false; 12219#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11783#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10973#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 12273#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12444#L1003 assume !(0 != eval_~tmp~0#1); 11746#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11478#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11479#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12163#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12164#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12066#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11232#L1216-3 assume !(0 == ~T4_E~0); 11233#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11711#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11311#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11312#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11563#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12552#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12452#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12151#L1256-3 assume !(0 == ~T12_E~0); 11252#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11253#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11303#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11304#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11687#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11688#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12206#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12207#L1296-3 assume !(0 == ~E_7~0); 12624#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12582#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11791#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11172#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11173#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11254#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11905#L593-42 assume 1 == ~m_pc~0; 12292#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12071#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11586#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11587#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11066#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11067#L612-42 assume !(1 == ~t1_pc~0); 12025#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 12406#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12633#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11159#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11160#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11868#L631-42 assume 1 == ~t2_pc~0; 10919#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10920#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11853#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11737#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11738#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11330#L650-42 assume 1 == ~t3_pc~0; 10884#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10885#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12239#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11525#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11526#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12523#L669-42 assume !(1 == ~t4_pc~0); 10882#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 10883#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12308#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12217#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12121#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12122#L688-42 assume 1 == ~t5_pc~0; 12204#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12409#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11917#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11094#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11095#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10912#L707-42 assume !(1 == ~t6_pc~0); 10913#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 12588#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11246#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11247#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 12092#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12093#L726-42 assume 1 == ~t7_pc~0; 12359#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12390#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11944#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11795#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11796#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11909#L745-42 assume 1 == ~t8_pc~0; 11947#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11948#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12112#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10900#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10901#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11646#L764-42 assume 1 == ~t9_pc~0; 11774#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12135#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12136#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11184#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11185#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11245#L783-42 assume 1 == ~t10_pc~0; 10856#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10858#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11461#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12104#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12615#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12298#L802-42 assume 1 == ~t11_pc~0; 11392#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10998#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10999#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 10945#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10946#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12143#L821-42 assume 1 == ~t12_pc~0; 12144#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11502#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11902#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11903#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 11839#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11829#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11830#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12002#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12108#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11511#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11512#L1359-3 assume !(1 == ~T5_E~0); 12118#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12609#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12519#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11332#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11333#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11509#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11510#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11725#L1399-3 assume !(1 == ~E_M~0); 12528#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12496#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12497#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12551#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12301#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11206#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11207#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12117#L1439-3 assume !(1 == ~E_8~0); 11135#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 11136#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 11257#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12113#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12114#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11756#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11039#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11240#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11241#L1829 assume !(0 == start_simulation_~tmp~3#1); 11020#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11021#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11835#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10925#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 10926#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12129#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12502#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 11288#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 11289#L1810-2 [2024-11-13 14:57:18,657 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:18,657 INFO L85 PathProgramCache]: Analyzing trace with hash -833138770, now seen corresponding path program 1 times [2024-11-13 14:57:18,657 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:18,657 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1535142480] [2024-11-13 14:57:18,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:18,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:18,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:18,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:18,769 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:18,769 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1535142480] [2024-11-13 14:57:18,769 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1535142480] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:18,769 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:18,769 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:18,770 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1222875775] [2024-11-13 14:57:18,770 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:18,770 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:18,770 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:18,770 INFO L85 PathProgramCache]: Analyzing trace with hash 1579007128, now seen corresponding path program 1 times [2024-11-13 14:57:18,771 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:18,771 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [59929458] [2024-11-13 14:57:18,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:18,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:18,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:18,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:18,906 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:18,906 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [59929458] [2024-11-13 14:57:18,906 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [59929458] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:18,906 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:18,907 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:18,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1135291160] [2024-11-13 14:57:18,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:18,907 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:18,907 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:18,907 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:57:18,908 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:57:18,908 INFO L87 Difference]: Start difference. First operand 1801 states and 2662 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:18,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:18,957 INFO L93 Difference]: Finished difference Result 1801 states and 2661 transitions. [2024-11-13 14:57:18,957 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2661 transitions. [2024-11-13 14:57:18,969 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:18,979 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2661 transitions. [2024-11-13 14:57:18,979 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-13 14:57:18,981 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-13 14:57:18,981 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2661 transitions. [2024-11-13 14:57:18,984 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:18,985 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2661 transitions. [2024-11-13 14:57:18,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2661 transitions. [2024-11-13 14:57:19,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-13 14:57:19,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4775124930594115) internal successors, (2661), 1800 states have internal predecessors, (2661), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:19,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2661 transitions. [2024-11-13 14:57:19,023 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2661 transitions. [2024-11-13 14:57:19,024 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:57:19,024 INFO L424 stractBuchiCegarLoop]: Abstraction has 1801 states and 2661 transitions. [2024-11-13 14:57:19,024 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 14:57:19,024 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2661 transitions. [2024-11-13 14:57:19,035 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:19,035 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:19,038 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:19,043 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:19,043 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:19,043 INFO L745 eck$LassoCheckResult]: Stem: 14742#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 14743#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 15587#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15588#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16174#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 16175#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15268#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15057#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14454#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 14455#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15699#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15798#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16236#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16237#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15193#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15194#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15725#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 15650#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15230#L1201 assume !(0 == ~M_E~0); 15231#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16083#L1206-1 assume !(0 == ~T2_E~0); 16066#L1211-1 assume !(0 == ~T3_E~0); 16067#L1216-1 assume !(0 == ~T4_E~0); 15038#L1221-1 assume !(0 == ~T5_E~0); 15039#L1226-1 assume !(0 == ~T6_E~0); 14668#L1231-1 assume !(0 == ~T7_E~0); 14669#L1236-1 assume !(0 == ~T8_E~0); 16107#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 15078#L1246-1 assume !(0 == ~T10_E~0); 15079#L1251-1 assume !(0 == ~T11_E~0); 15228#L1256-1 assume !(0 == ~T12_E~0); 14463#L1261-1 assume !(0 == ~E_M~0); 14464#L1266-1 assume !(0 == ~E_1~0); 16221#L1271-1 assume !(0 == ~E_2~0); 15782#L1276-1 assume !(0 == ~E_3~0); 15783#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 15737#L1286-1 assume !(0 == ~E_5~0); 14934#L1291-1 assume !(0 == ~E_6~0); 14935#L1296-1 assume !(0 == ~E_7~0); 15523#L1301-1 assume !(0 == ~E_8~0); 15524#L1306-1 assume !(0 == ~E_9~0); 16002#L1311-1 assume !(0 == ~E_10~0); 14885#L1316-1 assume !(0 == ~E_11~0); 14886#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 15542#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15543#L593 assume 1 == ~m_pc~0; 15692#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14767#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15431#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15432#L1492 assume !(0 != activate_threads_~tmp~1#1); 15747#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16035#L612 assume !(1 == ~t1_pc~0); 16036#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16170#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15880#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14770#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14771#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15209#L631 assume 1 == ~t2_pc~0; 15136#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14544#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14545#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14899#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 15395#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14846#L650 assume !(1 == ~t3_pc~0); 14847#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15565#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15859#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14501#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 14502#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15718#L669 assume 1 == ~t4_pc~0; 15719#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16074#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14584#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14585#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 14705#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14944#L688 assume !(1 == ~t5_pc~0); 14724#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 14725#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16202#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15607#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 15608#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15732#L707 assume 1 == ~t6_pc~0; 16141#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15364#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14887#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14888#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 15678#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15229#L726 assume 1 == ~t7_pc~0; 15124#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14811#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15871#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16145#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 14574#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14575#L745 assume !(1 == ~t8_pc~0); 15031#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 15051#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16089#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15440#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15441#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15959#L764 assume 1 == ~t9_pc~0; 15227#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15061#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14960#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14961#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 14600#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14601#L783 assume !(1 == ~t10_pc~0); 14655#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14656#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14853#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15183#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 15184#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16076#L802 assume 1 == ~t11_pc~0; 16058#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14541#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14542#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15040#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 15041#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15158#L821 assume !(1 == ~t12_pc~0); 15409#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 15515#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14548#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 14549#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 16118#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15755#L1339 assume !(1 == ~M_E~0); 15756#L1339-2 assume !(1 == ~T1_E~0); 16148#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16149#L1349-1 assume !(1 == ~T3_E~0); 15535#L1354-1 assume !(1 == ~T4_E~0); 15536#L1359-1 assume !(1 == ~T5_E~0); 15935#L1364-1 assume !(1 == ~T6_E~0); 14992#L1369-1 assume !(1 == ~T7_E~0); 14993#L1374-1 assume !(1 == ~T8_E~0); 15538#L1379-1 assume !(1 == ~T9_E~0); 15539#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15647#L1389-1 assume !(1 == ~T11_E~0); 16112#L1394-1 assume !(1 == ~T12_E~0); 16113#L1399-1 assume !(1 == ~E_M~0); 16194#L1404-1 assume !(1 == ~E_1~0); 15085#L1409-1 assume !(1 == ~E_2~0); 15086#L1414-1 assume !(1 == ~E_3~0); 15818#L1419-1 assume !(1 == ~E_4~0); 14714#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14715#L1429-1 assume !(1 == ~E_6~0); 15550#L1434-1 assume !(1 == ~E_7~0); 16130#L1439-1 assume !(1 == ~E_8~0); 14756#L1444-1 assume !(1 == ~E_9~0); 14757#L1449-1 assume !(1 == ~E_10~0); 15142#L1454-1 assume !(1 == ~E_11~0); 15143#L1459-1 assume !(1 == ~E_12~0); 15677#L1464-1 assume { :end_inline_reset_delta_events } true; 14898#L1810-2 [2024-11-13 14:57:19,053 INFO L747 eck$LassoCheckResult]: Loop: 14898#L1810-2 assume !false; 15348#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15446#L1176-1 assume !false; 15828#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15392#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14582#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15882#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16053#L1003 assume !(0 != eval_~tmp~0#1); 15355#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15087#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15088#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15772#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15773#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15675#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14841#L1216-3 assume !(0 == ~T4_E~0); 14842#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15320#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14920#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14921#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15172#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16161#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16061#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 15760#L1256-3 assume !(0 == ~T12_E~0); 14861#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14862#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14912#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14913#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15296#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15297#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15815#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15816#L1296-3 assume !(0 == ~E_7~0); 16233#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16191#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15400#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14781#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14782#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 14863#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15514#L593-42 assume 1 == ~m_pc~0; 15901#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15680#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15195#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15196#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14675#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14676#L612-42 assume !(1 == ~t1_pc~0); 15634#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 16015#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16242#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14768#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14769#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15477#L631-42 assume 1 == ~t2_pc~0; 14528#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14529#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15462#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15346#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15347#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14939#L650-42 assume 1 == ~t3_pc~0; 14493#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14494#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15848#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15134#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15135#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16132#L669-42 assume 1 == ~t4_pc~0; 15414#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14492#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15917#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15826#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15730#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15731#L688-42 assume 1 == ~t5_pc~0; 15813#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16018#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15526#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14703#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14704#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14521#L707-42 assume !(1 == ~t6_pc~0); 14522#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 16197#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14855#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14856#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 15701#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15702#L726-42 assume 1 == ~t7_pc~0; 15968#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15999#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15553#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15404#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15405#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15518#L745-42 assume 1 == ~t8_pc~0; 15556#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15557#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15721#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14509#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14510#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15255#L764-42 assume 1 == ~t9_pc~0; 15383#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15744#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15745#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14793#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14794#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14854#L783-42 assume 1 == ~t10_pc~0; 14465#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14467#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15070#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15713#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16224#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15907#L802-42 assume 1 == ~t11_pc~0; 15001#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14607#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14608#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14554#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14555#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15752#L821-42 assume !(1 == ~t12_pc~0); 15110#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 15111#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15511#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15512#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 15448#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15438#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15439#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15611#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15717#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15120#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15121#L1359-3 assume !(1 == ~T5_E~0); 15727#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16218#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16128#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14941#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14942#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15118#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15119#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15334#L1399-3 assume !(1 == ~E_M~0); 16137#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16105#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16106#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16160#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15910#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14815#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14816#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15726#L1439-3 assume !(1 == ~E_8~0); 14744#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14745#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 14866#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 15722#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 15723#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15365#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14648#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14849#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 14850#L1829 assume !(0 == start_simulation_~tmp~3#1); 14629#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 14630#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 15444#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14534#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 14535#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15738#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16111#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 14897#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 14898#L1810-2 [2024-11-13 14:57:19,053 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:19,054 INFO L85 PathProgramCache]: Analyzing trace with hash -1259693268, now seen corresponding path program 1 times [2024-11-13 14:57:19,054 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:19,054 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1534420839] [2024-11-13 14:57:19,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:19,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:19,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:19,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:19,150 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:19,150 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1534420839] [2024-11-13 14:57:19,150 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1534420839] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:19,150 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:19,150 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:19,150 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1108094082] [2024-11-13 14:57:19,151 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:19,151 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:19,151 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:19,151 INFO L85 PathProgramCache]: Analyzing trace with hash -411655528, now seen corresponding path program 1 times [2024-11-13 14:57:19,151 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:19,151 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [201172040] [2024-11-13 14:57:19,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:19,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:19,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:19,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:19,284 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:19,284 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [201172040] [2024-11-13 14:57:19,284 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [201172040] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:19,284 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:19,284 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:19,284 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2069369393] [2024-11-13 14:57:19,284 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:19,285 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:19,285 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:19,285 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:57:19,285 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:57:19,285 INFO L87 Difference]: Start difference. First operand 1801 states and 2661 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:19,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:19,344 INFO L93 Difference]: Finished difference Result 1801 states and 2660 transitions. [2024-11-13 14:57:19,345 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2660 transitions. [2024-11-13 14:57:19,360 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:19,371 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2660 transitions. [2024-11-13 14:57:19,371 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-13 14:57:19,373 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-13 14:57:19,373 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2660 transitions. [2024-11-13 14:57:19,377 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:19,377 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2660 transitions. [2024-11-13 14:57:19,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2660 transitions. [2024-11-13 14:57:19,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-13 14:57:19,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4769572459744587) internal successors, (2660), 1800 states have internal predecessors, (2660), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:19,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2660 transitions. [2024-11-13 14:57:19,424 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2660 transitions. [2024-11-13 14:57:19,424 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:57:19,426 INFO L424 stractBuchiCegarLoop]: Abstraction has 1801 states and 2660 transitions. [2024-11-13 14:57:19,426 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 14:57:19,426 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2660 transitions. [2024-11-13 14:57:19,438 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:19,438 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:19,438 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:19,441 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:19,441 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:19,443 INFO L745 eck$LassoCheckResult]: Stem: 18351#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 18352#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 19197#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19198#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19783#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 19784#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18878#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18666#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18063#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18064#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 19308#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19408#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19845#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19846#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18802#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18803#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19334#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 19259#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18839#L1201 assume !(0 == ~M_E~0); 18840#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19692#L1206-1 assume !(0 == ~T2_E~0); 19675#L1211-1 assume !(0 == ~T3_E~0); 19676#L1216-1 assume !(0 == ~T4_E~0); 18650#L1221-1 assume !(0 == ~T5_E~0); 18651#L1226-1 assume !(0 == ~T6_E~0); 18277#L1231-1 assume !(0 == ~T7_E~0); 18278#L1236-1 assume !(0 == ~T8_E~0); 19716#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18690#L1246-1 assume !(0 == ~T10_E~0); 18691#L1251-1 assume !(0 == ~T11_E~0); 18837#L1256-1 assume !(0 == ~T12_E~0); 18072#L1261-1 assume !(0 == ~E_M~0); 18073#L1266-1 assume !(0 == ~E_1~0); 19830#L1271-1 assume !(0 == ~E_2~0); 19391#L1276-1 assume !(0 == ~E_3~0); 19392#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19346#L1286-1 assume !(0 == ~E_5~0); 18543#L1291-1 assume !(0 == ~E_6~0); 18544#L1296-1 assume !(0 == ~E_7~0); 19132#L1301-1 assume !(0 == ~E_8~0); 19133#L1306-1 assume !(0 == ~E_9~0); 19611#L1311-1 assume !(0 == ~E_10~0); 18494#L1316-1 assume !(0 == ~E_11~0); 18495#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 19151#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19152#L593 assume 1 == ~m_pc~0; 19301#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18376#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19040#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19041#L1492 assume !(0 != activate_threads_~tmp~1#1); 19356#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19644#L612 assume !(1 == ~t1_pc~0); 19645#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19779#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19490#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18379#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18380#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18818#L631 assume 1 == ~t2_pc~0; 18745#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18153#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18154#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18508#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 19004#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18457#L650 assume !(1 == ~t3_pc~0); 18458#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19174#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19468#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18110#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 18111#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19327#L669 assume 1 == ~t4_pc~0; 19328#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19684#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18197#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18198#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 18314#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18553#L688 assume !(1 == ~t5_pc~0); 18333#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 18334#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19811#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19218#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 19219#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19344#L707 assume 1 == ~t6_pc~0; 19750#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18973#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18496#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18497#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 19289#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18838#L726 assume 1 == ~t7_pc~0; 18735#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18420#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19481#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19755#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 18183#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18184#L745 assume !(1 == ~t8_pc~0); 18640#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 18660#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19698#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19049#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19050#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19568#L764 assume 1 == ~t9_pc~0; 18836#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18670#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18569#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18570#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 18209#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18210#L783 assume !(1 == ~t10_pc~0); 18264#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 18265#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18462#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18797#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 18798#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19685#L802 assume 1 == ~t11_pc~0; 19667#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18150#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18151#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18647#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 18648#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18767#L821 assume !(1 == ~t12_pc~0); 19018#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 19124#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18157#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18158#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 19727#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19364#L1339 assume !(1 == ~M_E~0); 19365#L1339-2 assume !(1 == ~T1_E~0); 19757#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19758#L1349-1 assume !(1 == ~T3_E~0); 19144#L1354-1 assume !(1 == ~T4_E~0); 19145#L1359-1 assume !(1 == ~T5_E~0); 19544#L1364-1 assume !(1 == ~T6_E~0); 18601#L1369-1 assume !(1 == ~T7_E~0); 18602#L1374-1 assume !(1 == ~T8_E~0); 19147#L1379-1 assume !(1 == ~T9_E~0); 19148#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19256#L1389-1 assume !(1 == ~T11_E~0); 19721#L1394-1 assume !(1 == ~T12_E~0); 19722#L1399-1 assume !(1 == ~E_M~0); 19803#L1404-1 assume !(1 == ~E_1~0); 18694#L1409-1 assume !(1 == ~E_2~0); 18695#L1414-1 assume !(1 == ~E_3~0); 19427#L1419-1 assume !(1 == ~E_4~0); 18323#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18324#L1429-1 assume !(1 == ~E_6~0); 19159#L1434-1 assume !(1 == ~E_7~0); 19739#L1439-1 assume !(1 == ~E_8~0); 18365#L1444-1 assume !(1 == ~E_9~0); 18366#L1449-1 assume !(1 == ~E_10~0); 18751#L1454-1 assume !(1 == ~E_11~0); 18752#L1459-1 assume !(1 == ~E_12~0); 19286#L1464-1 assume { :end_inline_reset_delta_events } true; 18507#L1810-2 [2024-11-13 14:57:19,444 INFO L747 eck$LassoCheckResult]: Loop: 18507#L1810-2 assume !false; 18957#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19055#L1176-1 assume !false; 19437#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19001#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18191#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 19491#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19662#L1003 assume !(0 != eval_~tmp~0#1); 18964#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18696#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18697#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19381#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19382#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19284#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18450#L1216-3 assume !(0 == ~T4_E~0); 18451#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18929#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18529#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18530#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18781#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19770#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19670#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 19369#L1256-3 assume !(0 == ~T12_E~0); 18470#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18471#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18521#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18522#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18905#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18906#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19424#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19425#L1296-3 assume !(0 == ~E_7~0); 19842#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19800#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19009#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 18390#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18391#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 18472#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19123#L593-42 assume 1 == ~m_pc~0; 19510#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19288#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18804#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18805#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18284#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18285#L612-42 assume !(1 == ~t1_pc~0); 19243#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 19624#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19851#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18377#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18378#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19086#L631-42 assume 1 == ~t2_pc~0; 18137#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18138#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19071#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18955#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18956#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18548#L650-42 assume 1 == ~t3_pc~0; 18102#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18103#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19457#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18743#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18744#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19741#L669-42 assume !(1 == ~t4_pc~0); 18100#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 18101#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19526#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19435#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19339#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19340#L688-42 assume 1 == ~t5_pc~0; 19422#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19627#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19135#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18312#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18313#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18130#L707-42 assume !(1 == ~t6_pc~0); 18131#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 19806#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18464#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18465#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 19310#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19311#L726-42 assume 1 == ~t7_pc~0; 19577#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19608#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19162#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19013#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19014#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19127#L745-42 assume 1 == ~t8_pc~0; 19165#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19166#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19330#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18118#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18119#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18864#L764-42 assume 1 == ~t9_pc~0; 18992#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19353#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19354#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18402#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18403#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18463#L783-42 assume 1 == ~t10_pc~0; 18074#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18076#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18679#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19322#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19833#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19516#L802-42 assume 1 == ~t11_pc~0; 18610#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18216#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18217#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18163#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18164#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19361#L821-42 assume 1 == ~t12_pc~0; 19362#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 18720#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19120#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19121#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 19057#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19047#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19048#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19220#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19326#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18729#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18730#L1359-3 assume !(1 == ~T5_E~0); 19336#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19827#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19737#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18550#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18551#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18727#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18728#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18943#L1399-3 assume !(1 == ~E_M~0); 19746#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19714#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19715#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19769#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19519#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18424#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18425#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19335#L1439-3 assume !(1 == ~E_8~0); 18353#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18354#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 18475#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 19331#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 19332#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18974#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18257#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18455#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 18456#L1829 assume !(0 == start_simulation_~tmp~3#1); 18238#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18239#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 19053#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18143#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 18144#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19347#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19720#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 18506#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 18507#L1810-2 [2024-11-13 14:57:19,445 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:19,445 INFO L85 PathProgramCache]: Analyzing trace with hash -719263762, now seen corresponding path program 1 times [2024-11-13 14:57:19,445 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:19,445 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1422228295] [2024-11-13 14:57:19,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:19,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:19,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:19,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:19,530 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:19,530 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1422228295] [2024-11-13 14:57:19,530 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1422228295] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:19,530 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:19,530 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:19,531 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [493686965] [2024-11-13 14:57:19,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:19,531 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:19,531 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:19,531 INFO L85 PathProgramCache]: Analyzing trace with hash 1579007128, now seen corresponding path program 2 times [2024-11-13 14:57:19,532 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:19,532 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1432121837] [2024-11-13 14:57:19,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:19,532 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:19,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:19,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:19,650 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:19,650 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1432121837] [2024-11-13 14:57:19,651 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1432121837] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:19,651 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:19,651 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:19,651 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1521644526] [2024-11-13 14:57:19,651 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:19,651 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:19,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:19,652 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:57:19,652 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:57:19,652 INFO L87 Difference]: Start difference. First operand 1801 states and 2660 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:19,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:19,699 INFO L93 Difference]: Finished difference Result 1801 states and 2659 transitions. [2024-11-13 14:57:19,699 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2659 transitions. [2024-11-13 14:57:19,710 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:19,719 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2659 transitions. [2024-11-13 14:57:19,719 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-13 14:57:19,721 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-13 14:57:19,721 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2659 transitions. [2024-11-13 14:57:19,724 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:19,725 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2659 transitions. [2024-11-13 14:57:19,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2659 transitions. [2024-11-13 14:57:19,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-13 14:57:19,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4764019988895059) internal successors, (2659), 1800 states have internal predecessors, (2659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:19,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2659 transitions. [2024-11-13 14:57:19,765 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2659 transitions. [2024-11-13 14:57:19,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:57:19,768 INFO L424 stractBuchiCegarLoop]: Abstraction has 1801 states and 2659 transitions. [2024-11-13 14:57:19,768 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 14:57:19,769 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2659 transitions. [2024-11-13 14:57:19,781 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:19,782 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:19,782 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:19,784 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:19,785 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:19,785 INFO L745 eck$LassoCheckResult]: Stem: 21960#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 21961#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 22805#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22806#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23392#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 23393#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22487#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22275#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21672#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21673#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22917#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 23017#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23454#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23455#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22411#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22412#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22943#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22868#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22448#L1201 assume !(0 == ~M_E~0); 22449#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23301#L1206-1 assume !(0 == ~T2_E~0); 23284#L1211-1 assume !(0 == ~T3_E~0); 23285#L1216-1 assume !(0 == ~T4_E~0); 22257#L1221-1 assume !(0 == ~T5_E~0); 22258#L1226-1 assume !(0 == ~T6_E~0); 21886#L1231-1 assume !(0 == ~T7_E~0); 21887#L1236-1 assume !(0 == ~T8_E~0); 23325#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22299#L1246-1 assume !(0 == ~T10_E~0); 22300#L1251-1 assume !(0 == ~T11_E~0); 22446#L1256-1 assume !(0 == ~T12_E~0); 21681#L1261-1 assume !(0 == ~E_M~0); 21682#L1266-1 assume !(0 == ~E_1~0); 23439#L1271-1 assume !(0 == ~E_2~0); 23000#L1276-1 assume !(0 == ~E_3~0); 23001#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 22955#L1286-1 assume !(0 == ~E_5~0); 22152#L1291-1 assume !(0 == ~E_6~0); 22153#L1296-1 assume !(0 == ~E_7~0); 22741#L1301-1 assume !(0 == ~E_8~0); 22742#L1306-1 assume !(0 == ~E_9~0); 23220#L1311-1 assume !(0 == ~E_10~0); 22103#L1316-1 assume !(0 == ~E_11~0); 22104#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 22760#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22761#L593 assume 1 == ~m_pc~0; 22910#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21985#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22649#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22650#L1492 assume !(0 != activate_threads_~tmp~1#1); 22965#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23253#L612 assume !(1 == ~t1_pc~0); 23254#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23388#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23098#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21988#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21989#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22427#L631 assume 1 == ~t2_pc~0; 22354#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21762#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21763#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22117#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 22613#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22066#L650 assume !(1 == ~t3_pc~0); 22067#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22783#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23077#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21719#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 21720#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22936#L669 assume 1 == ~t4_pc~0; 22937#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23293#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21806#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21807#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 21923#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22162#L688 assume !(1 == ~t5_pc~0); 21942#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21943#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23420#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22825#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 22826#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22953#L707 assume 1 == ~t6_pc~0; 23359#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22582#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22105#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22106#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 22898#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22447#L726 assume 1 == ~t7_pc~0; 22344#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22029#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23090#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23363#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 21792#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21793#L745 assume !(1 == ~t8_pc~0); 22249#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22269#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23307#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22658#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22659#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23177#L764 assume 1 == ~t9_pc~0; 22445#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22279#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22178#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22179#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 21818#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21819#L783 assume !(1 == ~t10_pc~0); 21873#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21874#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22071#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22406#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 22407#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23294#L802 assume 1 == ~t11_pc~0; 23276#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21759#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21760#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 22259#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 22260#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22376#L821 assume !(1 == ~t12_pc~0); 22627#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22733#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21768#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21769#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 23336#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22973#L1339 assume !(1 == ~M_E~0); 22974#L1339-2 assume !(1 == ~T1_E~0); 23366#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23367#L1349-1 assume !(1 == ~T3_E~0); 22754#L1354-1 assume !(1 == ~T4_E~0); 22755#L1359-1 assume !(1 == ~T5_E~0); 23155#L1364-1 assume !(1 == ~T6_E~0); 22210#L1369-1 assume !(1 == ~T7_E~0); 22211#L1374-1 assume !(1 == ~T8_E~0); 22756#L1379-1 assume !(1 == ~T9_E~0); 22757#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22865#L1389-1 assume !(1 == ~T11_E~0); 23330#L1394-1 assume !(1 == ~T12_E~0); 23331#L1399-1 assume !(1 == ~E_M~0); 23412#L1404-1 assume !(1 == ~E_1~0); 22303#L1409-1 assume !(1 == ~E_2~0); 22304#L1414-1 assume !(1 == ~E_3~0); 23036#L1419-1 assume !(1 == ~E_4~0); 21932#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 21933#L1429-1 assume !(1 == ~E_6~0); 22768#L1434-1 assume !(1 == ~E_7~0); 23348#L1439-1 assume !(1 == ~E_8~0); 21974#L1444-1 assume !(1 == ~E_9~0); 21975#L1449-1 assume !(1 == ~E_10~0); 22362#L1454-1 assume !(1 == ~E_11~0); 22363#L1459-1 assume !(1 == ~E_12~0); 22895#L1464-1 assume { :end_inline_reset_delta_events } true; 22116#L1810-2 [2024-11-13 14:57:19,786 INFO L747 eck$LassoCheckResult]: Loop: 22116#L1810-2 assume !false; 22566#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22664#L1176-1 assume !false; 23046#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22612#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21800#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 23100#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 23273#L1003 assume !(0 != eval_~tmp~0#1); 22573#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22305#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22306#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22990#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22991#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22893#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22059#L1216-3 assume !(0 == ~T4_E~0); 22060#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22538#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22140#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22141#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22391#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23379#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 23279#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22978#L1256-3 assume !(0 == ~T12_E~0); 22079#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22080#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22130#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22131#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22514#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22515#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23034#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23035#L1296-3 assume !(0 == ~E_7~0); 23451#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23409#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22618#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21999#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22000#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 22081#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22732#L593-42 assume !(1 == ~m_pc~0); 22896#L593-44 is_master_triggered_~__retres1~0#1 := 0; 22897#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22413#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22414#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21890#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21891#L612-42 assume !(1 == ~t1_pc~0); 22850#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 23232#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23460#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21986#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21987#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22694#L631-42 assume 1 == ~t2_pc~0; 21746#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21747#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22680#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22564#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22565#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22157#L650-42 assume !(1 == ~t3_pc~0); 21713#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 21712#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23066#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22352#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22353#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23350#L669-42 assume 1 == ~t4_pc~0; 22632#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21708#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23135#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23044#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22948#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22949#L688-42 assume 1 == ~t5_pc~0; 23031#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23236#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22744#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21918#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21919#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21739#L707-42 assume !(1 == ~t6_pc~0); 21740#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 23415#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22073#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22074#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 22919#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22920#L726-42 assume 1 == ~t7_pc~0; 23186#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23217#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22771#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22622#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22623#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22736#L745-42 assume 1 == ~t8_pc~0; 22773#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22774#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22939#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21727#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21728#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22471#L764-42 assume 1 == ~t9_pc~0; 22601#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22962#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22963#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22011#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22012#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22072#L783-42 assume 1 == ~t10_pc~0; 21683#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21685#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22288#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22931#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23442#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23125#L802-42 assume 1 == ~t11_pc~0; 22219#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21825#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21826#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21772#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21773#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22970#L821-42 assume !(1 == ~t12_pc~0); 22328#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 22329#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 22729#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 22730#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 22666#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22656#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22657#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22829#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22935#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22338#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22339#L1359-3 assume !(1 == ~T5_E~0); 22945#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23436#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23346#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22158#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22159#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22336#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22337#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22552#L1399-3 assume !(1 == ~E_M~0); 23355#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23323#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23324#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23378#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23128#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22033#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22034#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22944#L1439-3 assume !(1 == ~E_8~0); 21962#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21963#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22084#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 22940#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 22941#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22583#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21866#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22064#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 22065#L1829 assume !(0 == start_simulation_~tmp~3#1); 21847#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 21848#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22662#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21752#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 21753#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22956#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23329#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 22115#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 22116#L1810-2 [2024-11-13 14:57:19,787 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:19,787 INFO L85 PathProgramCache]: Analyzing trace with hash -563283220, now seen corresponding path program 1 times [2024-11-13 14:57:19,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:19,787 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059169639] [2024-11-13 14:57:19,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:19,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:19,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:19,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:19,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:19,885 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2059169639] [2024-11-13 14:57:19,885 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2059169639] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:19,885 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:19,885 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:19,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [923885002] [2024-11-13 14:57:19,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:19,886 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:19,886 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:19,887 INFO L85 PathProgramCache]: Analyzing trace with hash 1190257242, now seen corresponding path program 1 times [2024-11-13 14:57:19,887 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:19,887 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [160888047] [2024-11-13 14:57:19,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:19,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:19,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:19,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:19,982 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:19,982 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [160888047] [2024-11-13 14:57:19,982 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [160888047] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:19,982 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:19,982 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:19,982 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2040098757] [2024-11-13 14:57:19,982 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:19,983 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:19,983 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:19,983 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:57:19,985 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:57:19,985 INFO L87 Difference]: Start difference. First operand 1801 states and 2659 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:20,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:20,036 INFO L93 Difference]: Finished difference Result 1801 states and 2658 transitions. [2024-11-13 14:57:20,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2658 transitions. [2024-11-13 14:57:20,047 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:20,057 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2658 transitions. [2024-11-13 14:57:20,057 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-13 14:57:20,059 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-13 14:57:20,060 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2658 transitions. [2024-11-13 14:57:20,063 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:20,063 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2658 transitions. [2024-11-13 14:57:20,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2658 transitions. [2024-11-13 14:57:20,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-13 14:57:20,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.475846751804553) internal successors, (2658), 1800 states have internal predecessors, (2658), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:20,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2658 transitions. [2024-11-13 14:57:20,102 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2658 transitions. [2024-11-13 14:57:20,103 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:57:20,105 INFO L424 stractBuchiCegarLoop]: Abstraction has 1801 states and 2658 transitions. [2024-11-13 14:57:20,105 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 14:57:20,105 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2658 transitions. [2024-11-13 14:57:20,113 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:20,113 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:20,113 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:20,115 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:20,116 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:20,118 INFO L745 eck$LassoCheckResult]: Stem: 25569#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 25570#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 26414#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26415#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27001#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 27002#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26096#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25884#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25281#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25282#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26526#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26626#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 27063#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27064#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26020#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26021#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26552#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26477#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26057#L1201 assume !(0 == ~M_E~0); 26058#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26910#L1206-1 assume !(0 == ~T2_E~0); 26893#L1211-1 assume !(0 == ~T3_E~0); 26894#L1216-1 assume !(0 == ~T4_E~0); 25866#L1221-1 assume !(0 == ~T5_E~0); 25867#L1226-1 assume !(0 == ~T6_E~0); 25495#L1231-1 assume !(0 == ~T7_E~0); 25496#L1236-1 assume !(0 == ~T8_E~0); 26934#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25905#L1246-1 assume !(0 == ~T10_E~0); 25906#L1251-1 assume !(0 == ~T11_E~0); 26055#L1256-1 assume !(0 == ~T12_E~0); 25290#L1261-1 assume !(0 == ~E_M~0); 25291#L1266-1 assume !(0 == ~E_1~0); 27048#L1271-1 assume !(0 == ~E_2~0); 26609#L1276-1 assume !(0 == ~E_3~0); 26610#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 26564#L1286-1 assume !(0 == ~E_5~0); 25761#L1291-1 assume !(0 == ~E_6~0); 25762#L1296-1 assume !(0 == ~E_7~0); 26350#L1301-1 assume !(0 == ~E_8~0); 26351#L1306-1 assume !(0 == ~E_9~0); 26829#L1311-1 assume !(0 == ~E_10~0); 25712#L1316-1 assume !(0 == ~E_11~0); 25713#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 26369#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26370#L593 assume 1 == ~m_pc~0; 26519#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25594#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26258#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26259#L1492 assume !(0 != activate_threads_~tmp~1#1); 26574#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26862#L612 assume !(1 == ~t1_pc~0); 26863#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26997#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26707#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25597#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25598#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26036#L631 assume 1 == ~t2_pc~0; 25963#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25371#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25372#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25726#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 26222#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25675#L650 assume !(1 == ~t3_pc~0); 25676#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26392#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26686#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25328#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 25329#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26545#L669 assume 1 == ~t4_pc~0; 26546#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26902#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25415#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25416#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 25532#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25771#L688 assume !(1 == ~t5_pc~0); 25551#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25552#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27029#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26434#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 26435#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26562#L707 assume 1 == ~t6_pc~0; 26968#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26191#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25714#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25715#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 26505#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26056#L726 assume 1 == ~t7_pc~0; 25953#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25638#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26699#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26972#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 25401#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25402#L745 assume !(1 == ~t8_pc~0); 25858#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25878#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26916#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26267#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26268#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26786#L764 assume 1 == ~t9_pc~0; 26054#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25888#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25787#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25788#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 25427#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25428#L783 assume !(1 == ~t10_pc~0); 25482#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25483#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25680#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26015#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 26016#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26903#L802 assume 1 == ~t11_pc~0; 26885#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25368#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25369#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25868#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 25869#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25985#L821 assume !(1 == ~t12_pc~0); 26236#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 26342#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25377#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25378#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 26945#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26582#L1339 assume !(1 == ~M_E~0); 26583#L1339-2 assume !(1 == ~T1_E~0); 26975#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26976#L1349-1 assume !(1 == ~T3_E~0); 26363#L1354-1 assume !(1 == ~T4_E~0); 26364#L1359-1 assume !(1 == ~T5_E~0); 26762#L1364-1 assume !(1 == ~T6_E~0); 25819#L1369-1 assume !(1 == ~T7_E~0); 25820#L1374-1 assume !(1 == ~T8_E~0); 26365#L1379-1 assume !(1 == ~T9_E~0); 26366#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26474#L1389-1 assume !(1 == ~T11_E~0); 26939#L1394-1 assume !(1 == ~T12_E~0); 26940#L1399-1 assume !(1 == ~E_M~0); 27021#L1404-1 assume !(1 == ~E_1~0); 25912#L1409-1 assume !(1 == ~E_2~0); 25913#L1414-1 assume !(1 == ~E_3~0); 26645#L1419-1 assume !(1 == ~E_4~0); 25541#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 25542#L1429-1 assume !(1 == ~E_6~0); 26377#L1434-1 assume !(1 == ~E_7~0); 26957#L1439-1 assume !(1 == ~E_8~0); 25583#L1444-1 assume !(1 == ~E_9~0); 25584#L1449-1 assume !(1 == ~E_10~0); 25971#L1454-1 assume !(1 == ~E_11~0); 25972#L1459-1 assume !(1 == ~E_12~0); 26504#L1464-1 assume { :end_inline_reset_delta_events } true; 25725#L1810-2 [2024-11-13 14:57:20,118 INFO L747 eck$LassoCheckResult]: Loop: 25725#L1810-2 assume !false; 26175#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26273#L1176-1 assume !false; 26655#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26220#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25409#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 26709#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 26882#L1003 assume !(0 != eval_~tmp~0#1); 26182#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25914#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25915#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26599#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26600#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26502#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25668#L1216-3 assume !(0 == ~T4_E~0); 25669#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26147#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25747#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25748#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26000#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26988#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26888#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26587#L1256-3 assume !(0 == ~T12_E~0); 25688#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25689#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25739#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25740#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26123#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26124#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26643#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26644#L1296-3 assume !(0 == ~E_7~0); 27060#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27018#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26227#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25608#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25609#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 25690#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26341#L593-42 assume 1 == ~m_pc~0; 26729#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26507#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26024#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26025#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25505#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25506#L612-42 assume !(1 == ~t1_pc~0); 26461#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 26843#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27069#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25595#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25596#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26304#L631-42 assume !(1 == ~t2_pc~0); 25360#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 25359#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26289#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26173#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26174#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25766#L650-42 assume 1 == ~t3_pc~0; 25323#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25324#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26675#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25961#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25962#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26959#L669-42 assume 1 == ~t4_pc~0; 26244#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25319#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26744#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26653#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26557#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26558#L688-42 assume 1 == ~t5_pc~0; 26640#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26845#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26352#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25527#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25528#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25341#L707-42 assume !(1 == ~t6_pc~0); 25342#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 27024#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25682#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25683#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 26528#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26529#L726-42 assume 1 == ~t7_pc~0; 26792#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26826#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26380#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26231#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26232#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26345#L745-42 assume !(1 == ~t8_pc~0); 26384#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 26383#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26548#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25336#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25337#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26080#L764-42 assume 1 == ~t9_pc~0; 26210#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26571#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26572#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25620#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25621#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25681#L783-42 assume 1 == ~t10_pc~0; 25292#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25294#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25895#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26540#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 27051#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26734#L802-42 assume 1 == ~t11_pc~0; 25828#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25434#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25435#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25381#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25382#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26579#L821-42 assume !(1 == ~t12_pc~0); 25937#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 25938#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26338#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26339#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 26275#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26262#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26263#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26438#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26544#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25947#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25948#L1359-3 assume !(1 == ~T5_E~0); 26554#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27045#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26955#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25767#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25768#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25945#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25946#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26161#L1399-3 assume !(1 == ~E_M~0); 26964#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26932#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26933#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26987#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26737#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25642#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25643#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26553#L1439-3 assume !(1 == ~E_8~0); 25571#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25572#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25693#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 26549#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 26550#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26192#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25475#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25673#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 25674#L1829 assume !(0 == start_simulation_~tmp~3#1); 25456#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25457#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 26271#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25361#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 25362#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26565#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26938#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 25724#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 25725#L1810-2 [2024-11-13 14:57:20,119 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:20,119 INFO L85 PathProgramCache]: Analyzing trace with hash -973893586, now seen corresponding path program 1 times [2024-11-13 14:57:20,119 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:20,119 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1613878837] [2024-11-13 14:57:20,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:20,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:20,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:20,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:20,199 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:20,199 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1613878837] [2024-11-13 14:57:20,199 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1613878837] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:20,199 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:20,199 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:20,200 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [808164920] [2024-11-13 14:57:20,200 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:20,200 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:20,200 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:20,200 INFO L85 PathProgramCache]: Analyzing trace with hash 1013433242, now seen corresponding path program 1 times [2024-11-13 14:57:20,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:20,201 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876979505] [2024-11-13 14:57:20,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:20,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:20,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:20,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:20,307 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:20,307 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1876979505] [2024-11-13 14:57:20,308 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1876979505] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:20,309 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:20,309 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:20,309 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765050492] [2024-11-13 14:57:20,309 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:20,309 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:20,310 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:20,310 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:57:20,310 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:57:20,310 INFO L87 Difference]: Start difference. First operand 1801 states and 2658 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:20,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:20,357 INFO L93 Difference]: Finished difference Result 1801 states and 2657 transitions. [2024-11-13 14:57:20,358 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2657 transitions. [2024-11-13 14:57:20,368 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:20,377 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2657 transitions. [2024-11-13 14:57:20,377 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-13 14:57:20,379 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-13 14:57:20,379 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2657 transitions. [2024-11-13 14:57:20,384 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:20,384 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2657 transitions. [2024-11-13 14:57:20,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2657 transitions. [2024-11-13 14:57:20,411 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-13 14:57:20,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4752915047196002) internal successors, (2657), 1800 states have internal predecessors, (2657), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:20,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2657 transitions. [2024-11-13 14:57:20,427 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2657 transitions. [2024-11-13 14:57:20,427 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:57:20,428 INFO L424 stractBuchiCegarLoop]: Abstraction has 1801 states and 2657 transitions. [2024-11-13 14:57:20,428 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 14:57:20,428 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2657 transitions. [2024-11-13 14:57:20,438 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:20,439 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:20,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:20,442 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:20,442 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:20,445 INFO L745 eck$LassoCheckResult]: Stem: 29178#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 29179#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 30023#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30024#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30610#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 30611#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29704#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29493#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28890#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28891#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30135#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30234#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30672#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 30673#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29629#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29630#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 30161#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 30086#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29666#L1201 assume !(0 == ~M_E~0); 29667#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30519#L1206-1 assume !(0 == ~T2_E~0); 30502#L1211-1 assume !(0 == ~T3_E~0); 30503#L1216-1 assume !(0 == ~T4_E~0); 29474#L1221-1 assume !(0 == ~T5_E~0); 29475#L1226-1 assume !(0 == ~T6_E~0); 29104#L1231-1 assume !(0 == ~T7_E~0); 29105#L1236-1 assume !(0 == ~T8_E~0); 30543#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29514#L1246-1 assume !(0 == ~T10_E~0); 29515#L1251-1 assume !(0 == ~T11_E~0); 29664#L1256-1 assume !(0 == ~T12_E~0); 28899#L1261-1 assume !(0 == ~E_M~0); 28900#L1266-1 assume !(0 == ~E_1~0); 30657#L1271-1 assume !(0 == ~E_2~0); 30218#L1276-1 assume !(0 == ~E_3~0); 30219#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 30173#L1286-1 assume !(0 == ~E_5~0); 29370#L1291-1 assume !(0 == ~E_6~0); 29371#L1296-1 assume !(0 == ~E_7~0); 29959#L1301-1 assume !(0 == ~E_8~0); 29960#L1306-1 assume !(0 == ~E_9~0); 30438#L1311-1 assume !(0 == ~E_10~0); 29321#L1316-1 assume !(0 == ~E_11~0); 29322#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 29978#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29979#L593 assume 1 == ~m_pc~0; 30128#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29203#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29867#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29868#L1492 assume !(0 != activate_threads_~tmp~1#1); 30183#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30471#L612 assume !(1 == ~t1_pc~0); 30472#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30606#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30316#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29206#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29207#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29645#L631 assume 1 == ~t2_pc~0; 29572#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28980#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28981#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29335#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 29831#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29284#L650 assume !(1 == ~t3_pc~0); 29285#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30001#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30295#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28937#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 28938#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30154#L669 assume 1 == ~t4_pc~0; 30155#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30510#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29022#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29023#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 29141#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29380#L688 assume !(1 == ~t5_pc~0); 29160#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 29161#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30638#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30043#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 30044#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30168#L707 assume 1 == ~t6_pc~0; 30577#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29800#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29323#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29324#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 30114#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29665#L726 assume 1 == ~t7_pc~0; 29560#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29247#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30307#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30581#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 29010#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29011#L745 assume !(1 == ~t8_pc~0); 29467#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29487#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30525#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29876#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29877#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30395#L764 assume 1 == ~t9_pc~0; 29663#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29497#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29396#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29397#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 29036#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29037#L783 assume !(1 == ~t10_pc~0); 29091#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29092#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29289#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29619#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 29620#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30512#L802 assume 1 == ~t11_pc~0; 30494#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28977#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28978#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29476#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 29477#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29594#L821 assume !(1 == ~t12_pc~0); 29845#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29951#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28986#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28987#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 30554#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30191#L1339 assume !(1 == ~M_E~0); 30192#L1339-2 assume !(1 == ~T1_E~0); 30584#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30585#L1349-1 assume !(1 == ~T3_E~0); 29971#L1354-1 assume !(1 == ~T4_E~0); 29972#L1359-1 assume !(1 == ~T5_E~0); 30371#L1364-1 assume !(1 == ~T6_E~0); 29428#L1369-1 assume !(1 == ~T7_E~0); 29429#L1374-1 assume !(1 == ~T8_E~0); 29974#L1379-1 assume !(1 == ~T9_E~0); 29975#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30083#L1389-1 assume !(1 == ~T11_E~0); 30548#L1394-1 assume !(1 == ~T12_E~0); 30549#L1399-1 assume !(1 == ~E_M~0); 30630#L1404-1 assume !(1 == ~E_1~0); 29521#L1409-1 assume !(1 == ~E_2~0); 29522#L1414-1 assume !(1 == ~E_3~0); 30254#L1419-1 assume !(1 == ~E_4~0); 29150#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 29151#L1429-1 assume !(1 == ~E_6~0); 29986#L1434-1 assume !(1 == ~E_7~0); 30566#L1439-1 assume !(1 == ~E_8~0); 29192#L1444-1 assume !(1 == ~E_9~0); 29193#L1449-1 assume !(1 == ~E_10~0); 29578#L1454-1 assume !(1 == ~E_11~0); 29579#L1459-1 assume !(1 == ~E_12~0); 30113#L1464-1 assume { :end_inline_reset_delta_events } true; 29334#L1810-2 [2024-11-13 14:57:20,446 INFO L747 eck$LassoCheckResult]: Loop: 29334#L1810-2 assume !false; 29784#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29882#L1176-1 assume !false; 30264#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29828#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29018#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 30318#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 30489#L1003 assume !(0 != eval_~tmp~0#1); 29791#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29523#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29524#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30208#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30209#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30111#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29277#L1216-3 assume !(0 == ~T4_E~0); 29278#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29756#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29356#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29357#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29609#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30597#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30497#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 30196#L1256-3 assume !(0 == ~T12_E~0); 29297#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29298#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29348#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29349#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29732#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29733#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30252#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30253#L1296-3 assume !(0 == ~E_7~0); 30669#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30627#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29836#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29217#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 29218#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 29299#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29950#L593-42 assume 1 == ~m_pc~0; 30338#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 30116#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29631#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29632#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29111#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29112#L612-42 assume !(1 == ~t1_pc~0); 30070#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 30451#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30678#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29204#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29205#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29913#L631-42 assume 1 == ~t2_pc~0; 28967#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28968#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29898#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29782#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29783#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29375#L650-42 assume 1 == ~t3_pc~0; 28932#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28933#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30284#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29570#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29571#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30568#L669-42 assume 1 == ~t4_pc~0; 29853#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28928#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30353#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30262#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30166#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30167#L688-42 assume 1 == ~t5_pc~0; 30249#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30454#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29962#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29139#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29140#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28957#L707-42 assume !(1 == ~t6_pc~0); 28958#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 30635#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29291#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29292#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 30137#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30138#L726-42 assume 1 == ~t7_pc~0; 30404#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30435#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29989#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29840#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29841#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29954#L745-42 assume 1 == ~t8_pc~0; 29995#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29996#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30157#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28945#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28946#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29691#L764-42 assume 1 == ~t9_pc~0; 29819#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30180#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30181#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29229#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29230#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29290#L783-42 assume 1 == ~t10_pc~0; 28901#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28903#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29504#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30149#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30660#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30343#L802-42 assume 1 == ~t11_pc~0; 29437#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29043#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29044#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28990#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28991#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30188#L821-42 assume !(1 == ~t12_pc~0); 29544#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 29545#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 29947#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29948#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29884#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29871#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29872#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30047#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30153#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29556#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29557#L1359-3 assume !(1 == ~T5_E~0); 30163#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30654#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30564#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29376#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29377#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29554#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29555#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 29770#L1399-3 assume !(1 == ~E_M~0); 30573#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30541#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30542#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30596#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30346#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29251#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29252#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30162#L1439-3 assume !(1 == ~E_8~0); 29180#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29181#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29302#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 30158#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 30159#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29801#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29084#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29282#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 29283#L1829 assume !(0 == start_simulation_~tmp~3#1); 29065#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29066#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29880#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28970#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 28971#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30174#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30547#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 29333#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 29334#L1810-2 [2024-11-13 14:57:20,446 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:20,447 INFO L85 PathProgramCache]: Analyzing trace with hash 813976236, now seen corresponding path program 1 times [2024-11-13 14:57:20,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:20,447 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967252197] [2024-11-13 14:57:20,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:20,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:20,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:20,556 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:20,557 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:20,557 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [967252197] [2024-11-13 14:57:20,557 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [967252197] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:20,557 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:20,557 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:20,558 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2050606470] [2024-11-13 14:57:20,558 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:20,558 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:20,559 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:20,559 INFO L85 PathProgramCache]: Analyzing trace with hash -411655528, now seen corresponding path program 2 times [2024-11-13 14:57:20,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:20,559 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209621815] [2024-11-13 14:57:20,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:20,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:20,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:20,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:20,651 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:20,651 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1209621815] [2024-11-13 14:57:20,651 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1209621815] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:20,651 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:20,652 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:20,652 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1402291885] [2024-11-13 14:57:20,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:20,652 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:20,652 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:20,653 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:57:20,653 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:57:20,653 INFO L87 Difference]: Start difference. First operand 1801 states and 2657 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:20,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:20,699 INFO L93 Difference]: Finished difference Result 1801 states and 2656 transitions. [2024-11-13 14:57:20,699 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2656 transitions. [2024-11-13 14:57:20,709 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:20,717 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2656 transitions. [2024-11-13 14:57:20,717 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-13 14:57:20,719 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-13 14:57:20,719 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2656 transitions. [2024-11-13 14:57:20,723 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:20,723 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2656 transitions. [2024-11-13 14:57:20,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2656 transitions. [2024-11-13 14:57:20,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-13 14:57:20,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4747362576346474) internal successors, (2656), 1800 states have internal predecessors, (2656), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:20,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2656 transitions. [2024-11-13 14:57:20,760 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2656 transitions. [2024-11-13 14:57:20,760 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:57:20,761 INFO L424 stractBuchiCegarLoop]: Abstraction has 1801 states and 2656 transitions. [2024-11-13 14:57:20,762 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 14:57:20,762 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2656 transitions. [2024-11-13 14:57:20,770 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:20,770 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:20,770 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:20,773 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:20,773 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:20,774 INFO L745 eck$LassoCheckResult]: Stem: 32787#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 32788#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 33632#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33633#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34219#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 34220#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33313#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33102#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32499#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32500#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33744#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33843#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34281#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 34282#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33238#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33239#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33770#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33695#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33275#L1201 assume !(0 == ~M_E~0); 33276#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34128#L1206-1 assume !(0 == ~T2_E~0); 34111#L1211-1 assume !(0 == ~T3_E~0); 34112#L1216-1 assume !(0 == ~T4_E~0); 33083#L1221-1 assume !(0 == ~T5_E~0); 33084#L1226-1 assume !(0 == ~T6_E~0); 32713#L1231-1 assume !(0 == ~T7_E~0); 32714#L1236-1 assume !(0 == ~T8_E~0); 34152#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33123#L1246-1 assume !(0 == ~T10_E~0); 33124#L1251-1 assume !(0 == ~T11_E~0); 33273#L1256-1 assume !(0 == ~T12_E~0); 32508#L1261-1 assume !(0 == ~E_M~0); 32509#L1266-1 assume !(0 == ~E_1~0); 34266#L1271-1 assume !(0 == ~E_2~0); 33827#L1276-1 assume !(0 == ~E_3~0); 33828#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 33782#L1286-1 assume !(0 == ~E_5~0); 32979#L1291-1 assume !(0 == ~E_6~0); 32980#L1296-1 assume !(0 == ~E_7~0); 33568#L1301-1 assume !(0 == ~E_8~0); 33569#L1306-1 assume !(0 == ~E_9~0); 34047#L1311-1 assume !(0 == ~E_10~0); 32930#L1316-1 assume !(0 == ~E_11~0); 32931#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 33587#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33588#L593 assume 1 == ~m_pc~0; 33737#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32812#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33476#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33477#L1492 assume !(0 != activate_threads_~tmp~1#1); 33792#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34080#L612 assume !(1 == ~t1_pc~0); 34081#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34215#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33925#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32815#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32816#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33254#L631 assume 1 == ~t2_pc~0; 33181#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32589#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32590#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32944#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 33440#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32891#L650 assume !(1 == ~t3_pc~0); 32892#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33610#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33904#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32546#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 32547#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33763#L669 assume 1 == ~t4_pc~0; 33764#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34119#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32629#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32630#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 32750#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32989#L688 assume !(1 == ~t5_pc~0); 32769#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32770#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34247#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33652#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 33653#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33777#L707 assume 1 == ~t6_pc~0; 34186#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33409#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32932#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32933#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 33723#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33274#L726 assume 1 == ~t7_pc~0; 33169#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32856#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33916#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34190#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 32619#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32620#L745 assume !(1 == ~t8_pc~0); 33076#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 33096#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34134#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33485#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33486#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34004#L764 assume 1 == ~t9_pc~0; 33272#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33106#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33005#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33006#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 32645#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32646#L783 assume !(1 == ~t10_pc~0); 32700#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32701#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32898#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33228#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 33229#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34121#L802 assume 1 == ~t11_pc~0; 34103#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32586#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32587#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33085#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 33086#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33203#L821 assume !(1 == ~t12_pc~0); 33454#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33560#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32593#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32594#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 34163#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33800#L1339 assume !(1 == ~M_E~0); 33801#L1339-2 assume !(1 == ~T1_E~0); 34193#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34194#L1349-1 assume !(1 == ~T3_E~0); 33580#L1354-1 assume !(1 == ~T4_E~0); 33581#L1359-1 assume !(1 == ~T5_E~0); 33980#L1364-1 assume !(1 == ~T6_E~0); 33037#L1369-1 assume !(1 == ~T7_E~0); 33038#L1374-1 assume !(1 == ~T8_E~0); 33583#L1379-1 assume !(1 == ~T9_E~0); 33584#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33692#L1389-1 assume !(1 == ~T11_E~0); 34157#L1394-1 assume !(1 == ~T12_E~0); 34158#L1399-1 assume !(1 == ~E_M~0); 34239#L1404-1 assume !(1 == ~E_1~0); 33130#L1409-1 assume !(1 == ~E_2~0); 33131#L1414-1 assume !(1 == ~E_3~0); 33863#L1419-1 assume !(1 == ~E_4~0); 32759#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 32760#L1429-1 assume !(1 == ~E_6~0); 33595#L1434-1 assume !(1 == ~E_7~0); 34175#L1439-1 assume !(1 == ~E_8~0); 32801#L1444-1 assume !(1 == ~E_9~0); 32802#L1449-1 assume !(1 == ~E_10~0); 33187#L1454-1 assume !(1 == ~E_11~0); 33188#L1459-1 assume !(1 == ~E_12~0); 33722#L1464-1 assume { :end_inline_reset_delta_events } true; 32943#L1810-2 [2024-11-13 14:57:20,774 INFO L747 eck$LassoCheckResult]: Loop: 32943#L1810-2 assume !false; 33393#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33491#L1176-1 assume !false; 33873#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33437#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32627#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33927#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 34098#L1003 assume !(0 != eval_~tmp~0#1); 33400#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33132#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33133#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33817#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33818#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33720#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32886#L1216-3 assume !(0 == ~T4_E~0); 32887#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33365#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32965#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32966#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33217#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34206#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34106#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33805#L1256-3 assume !(0 == ~T12_E~0); 32906#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32907#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32957#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32958#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33341#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33342#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33860#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33861#L1296-3 assume !(0 == ~E_7~0); 34278#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34236#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33445#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 32826#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32827#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 32908#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33559#L593-42 assume 1 == ~m_pc~0; 33946#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33725#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33240#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33241#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32720#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32721#L612-42 assume 1 == ~t1_pc~0; 33680#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34060#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34287#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32813#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32814#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33522#L631-42 assume 1 == ~t2_pc~0; 32573#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32574#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33507#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33391#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33392#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32984#L650-42 assume 1 == ~t3_pc~0; 32538#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32539#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33893#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33179#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33180#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34177#L669-42 assume 1 == ~t4_pc~0; 33459#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32537#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33962#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33871#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33775#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33776#L688-42 assume 1 == ~t5_pc~0; 33858#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34063#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33571#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32748#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32749#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32566#L707-42 assume !(1 == ~t6_pc~0); 32567#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 34242#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32900#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32901#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 33746#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33747#L726-42 assume 1 == ~t7_pc~0; 34013#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34044#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33598#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33449#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33450#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33563#L745-42 assume 1 == ~t8_pc~0; 33601#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33602#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33766#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32554#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32555#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33300#L764-42 assume 1 == ~t9_pc~0; 33428#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33789#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33790#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32838#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32839#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32899#L783-42 assume 1 == ~t10_pc~0; 32510#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32512#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33115#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33758#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34269#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33952#L802-42 assume 1 == ~t11_pc~0; 33046#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32652#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32653#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32599#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32600#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33797#L821-42 assume !(1 == ~t12_pc~0); 33155#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 33156#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33556#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33557#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33493#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33483#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33484#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33656#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33762#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33165#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33166#L1359-3 assume !(1 == ~T5_E~0); 33772#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34263#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34173#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32986#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32987#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33163#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33164#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33379#L1399-3 assume !(1 == ~E_M~0); 34182#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34150#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34151#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34205#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33955#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32860#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32861#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33771#L1439-3 assume !(1 == ~E_8~0); 32789#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32790#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32911#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33767#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33768#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33410#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32693#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32894#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 32895#L1829 assume !(0 == start_simulation_~tmp~3#1); 32674#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32675#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 33489#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32579#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 32580#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33783#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34156#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 32942#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 32943#L1810-2 [2024-11-13 14:57:20,775 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:20,775 INFO L85 PathProgramCache]: Analyzing trace with hash -1345107858, now seen corresponding path program 1 times [2024-11-13 14:57:20,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:20,776 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [557260441] [2024-11-13 14:57:20,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:20,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:20,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:20,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:20,844 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:20,844 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [557260441] [2024-11-13 14:57:20,844 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [557260441] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:20,844 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:20,844 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:20,844 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1125958062] [2024-11-13 14:57:20,844 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:20,846 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:20,847 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:20,847 INFO L85 PathProgramCache]: Analyzing trace with hash -1136734953, now seen corresponding path program 1 times [2024-11-13 14:57:20,847 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:20,847 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [107783153] [2024-11-13 14:57:20,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:20,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:20,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:20,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:20,926 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:20,926 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [107783153] [2024-11-13 14:57:20,927 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [107783153] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:20,927 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:20,927 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:20,927 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1170147706] [2024-11-13 14:57:20,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:20,927 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:20,927 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:20,928 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:57:20,928 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:57:20,928 INFO L87 Difference]: Start difference. First operand 1801 states and 2656 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:20,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:20,975 INFO L93 Difference]: Finished difference Result 1801 states and 2655 transitions. [2024-11-13 14:57:20,975 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2655 transitions. [2024-11-13 14:57:20,985 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:20,997 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2655 transitions. [2024-11-13 14:57:20,999 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-13 14:57:21,001 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-13 14:57:21,002 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2655 transitions. [2024-11-13 14:57:21,005 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:21,005 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2655 transitions. [2024-11-13 14:57:21,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2655 transitions. [2024-11-13 14:57:21,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-13 14:57:21,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4741810105496946) internal successors, (2655), 1800 states have internal predecessors, (2655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:21,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2655 transitions. [2024-11-13 14:57:21,042 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2655 transitions. [2024-11-13 14:57:21,043 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:57:21,043 INFO L424 stractBuchiCegarLoop]: Abstraction has 1801 states and 2655 transitions. [2024-11-13 14:57:21,044 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 14:57:21,044 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2655 transitions. [2024-11-13 14:57:21,052 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:21,052 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:21,052 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:21,055 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:21,055 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:21,055 INFO L745 eck$LassoCheckResult]: Stem: 36396#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 36397#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 37241#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37242#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37828#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 37829#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36922#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36711#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36108#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36109#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37353#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37452#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37890#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37891#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36847#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36848#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37379#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37304#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36884#L1201 assume !(0 == ~M_E~0); 36885#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37737#L1206-1 assume !(0 == ~T2_E~0); 37720#L1211-1 assume !(0 == ~T3_E~0); 37721#L1216-1 assume !(0 == ~T4_E~0); 36692#L1221-1 assume !(0 == ~T5_E~0); 36693#L1226-1 assume !(0 == ~T6_E~0); 36322#L1231-1 assume !(0 == ~T7_E~0); 36323#L1236-1 assume !(0 == ~T8_E~0); 37761#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36732#L1246-1 assume !(0 == ~T10_E~0); 36733#L1251-1 assume !(0 == ~T11_E~0); 36882#L1256-1 assume !(0 == ~T12_E~0); 36117#L1261-1 assume !(0 == ~E_M~0); 36118#L1266-1 assume !(0 == ~E_1~0); 37875#L1271-1 assume !(0 == ~E_2~0); 37436#L1276-1 assume !(0 == ~E_3~0); 37437#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 37391#L1286-1 assume !(0 == ~E_5~0); 36588#L1291-1 assume !(0 == ~E_6~0); 36589#L1296-1 assume !(0 == ~E_7~0); 37177#L1301-1 assume !(0 == ~E_8~0); 37178#L1306-1 assume !(0 == ~E_9~0); 37656#L1311-1 assume !(0 == ~E_10~0); 36539#L1316-1 assume !(0 == ~E_11~0); 36540#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 37196#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37197#L593 assume 1 == ~m_pc~0; 37346#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36421#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37085#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37086#L1492 assume !(0 != activate_threads_~tmp~1#1); 37401#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37689#L612 assume !(1 == ~t1_pc~0); 37690#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 37824#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37534#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36424#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36425#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36863#L631 assume 1 == ~t2_pc~0; 36790#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36198#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36199#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36553#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 37049#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36500#L650 assume !(1 == ~t3_pc~0); 36501#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37219#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37513#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36155#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 36156#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37372#L669 assume 1 == ~t4_pc~0; 37373#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37728#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36238#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36239#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 36359#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36598#L688 assume !(1 == ~t5_pc~0); 36378#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36379#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37856#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37261#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 37262#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37386#L707 assume 1 == ~t6_pc~0; 37795#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37018#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36541#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36542#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 37332#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36883#L726 assume 1 == ~t7_pc~0; 36778#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36465#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37525#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37799#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 36228#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36229#L745 assume !(1 == ~t8_pc~0); 36685#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36705#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37743#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37094#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37095#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37613#L764 assume 1 == ~t9_pc~0; 36881#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36715#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36614#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36615#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 36254#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36255#L783 assume !(1 == ~t10_pc~0); 36309#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36310#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36507#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36837#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 36838#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37730#L802 assume 1 == ~t11_pc~0; 37712#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36195#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36196#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36694#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 36695#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36812#L821 assume !(1 == ~t12_pc~0); 37063#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 37169#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36202#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36203#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 37772#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37409#L1339 assume !(1 == ~M_E~0); 37410#L1339-2 assume !(1 == ~T1_E~0); 37802#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37803#L1349-1 assume !(1 == ~T3_E~0); 37189#L1354-1 assume !(1 == ~T4_E~0); 37190#L1359-1 assume !(1 == ~T5_E~0); 37589#L1364-1 assume !(1 == ~T6_E~0); 36646#L1369-1 assume !(1 == ~T7_E~0); 36647#L1374-1 assume !(1 == ~T8_E~0); 37192#L1379-1 assume !(1 == ~T9_E~0); 37193#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37301#L1389-1 assume !(1 == ~T11_E~0); 37766#L1394-1 assume !(1 == ~T12_E~0); 37767#L1399-1 assume !(1 == ~E_M~0); 37848#L1404-1 assume !(1 == ~E_1~0); 36739#L1409-1 assume !(1 == ~E_2~0); 36740#L1414-1 assume !(1 == ~E_3~0); 37472#L1419-1 assume !(1 == ~E_4~0); 36368#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 36369#L1429-1 assume !(1 == ~E_6~0); 37204#L1434-1 assume !(1 == ~E_7~0); 37784#L1439-1 assume !(1 == ~E_8~0); 36410#L1444-1 assume !(1 == ~E_9~0); 36411#L1449-1 assume !(1 == ~E_10~0); 36796#L1454-1 assume !(1 == ~E_11~0); 36797#L1459-1 assume !(1 == ~E_12~0); 37331#L1464-1 assume { :end_inline_reset_delta_events } true; 36552#L1810-2 [2024-11-13 14:57:21,056 INFO L747 eck$LassoCheckResult]: Loop: 36552#L1810-2 assume !false; 37002#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37100#L1176-1 assume !false; 37482#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37046#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36236#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37536#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37707#L1003 assume !(0 != eval_~tmp~0#1); 37009#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36741#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36742#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37426#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37427#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37329#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36495#L1216-3 assume !(0 == ~T4_E~0); 36496#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36974#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36574#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36575#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36826#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37815#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37715#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37414#L1256-3 assume !(0 == ~T12_E~0); 36515#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36516#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36566#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36567#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36950#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36951#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37469#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37470#L1296-3 assume !(0 == ~E_7~0); 37887#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37845#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 37054#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36435#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36436#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 36517#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37168#L593-42 assume 1 == ~m_pc~0; 37555#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37334#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36849#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36850#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36329#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36330#L612-42 assume !(1 == ~t1_pc~0); 37288#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 37669#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37896#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36422#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36423#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37131#L631-42 assume 1 == ~t2_pc~0; 36182#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36183#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37116#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37000#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37001#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36593#L650-42 assume 1 == ~t3_pc~0; 36147#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36148#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37502#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36788#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36789#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37786#L669-42 assume !(1 == ~t4_pc~0); 36145#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 36146#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37571#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37480#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37384#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37385#L688-42 assume 1 == ~t5_pc~0; 37467#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37672#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37180#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36357#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36358#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36175#L707-42 assume !(1 == ~t6_pc~0); 36176#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 37851#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36509#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36510#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 37355#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37356#L726-42 assume 1 == ~t7_pc~0; 37622#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37653#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37207#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37058#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37059#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37172#L745-42 assume 1 == ~t8_pc~0; 37210#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37211#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37375#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36163#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36164#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36909#L764-42 assume 1 == ~t9_pc~0; 37037#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37398#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37399#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36447#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36448#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36508#L783-42 assume 1 == ~t10_pc~0; 36119#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 36121#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36724#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37367#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37878#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37561#L802-42 assume !(1 == ~t11_pc~0); 36656#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 36261#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36262#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36208#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36209#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37406#L821-42 assume !(1 == ~t12_pc~0); 36764#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 36765#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37165#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37166#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37102#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37092#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37093#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37265#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37371#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36774#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36775#L1359-3 assume !(1 == ~T5_E~0); 37381#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37872#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37782#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36595#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36596#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36772#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36773#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36988#L1399-3 assume !(1 == ~E_M~0); 37791#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37759#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37760#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37814#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37564#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36469#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36470#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37380#L1439-3 assume !(1 == ~E_8~0); 36398#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36399#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36520#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37376#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37377#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37019#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36302#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36503#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 36504#L1829 assume !(0 == start_simulation_~tmp~3#1); 36283#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36284#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37098#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36188#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 36189#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37392#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37765#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 36551#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 36552#L1810-2 [2024-11-13 14:57:21,056 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:21,057 INFO L85 PathProgramCache]: Analyzing trace with hash -1762996560, now seen corresponding path program 1 times [2024-11-13 14:57:21,057 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:21,057 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1997335533] [2024-11-13 14:57:21,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:21,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:21,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:21,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:21,140 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:21,140 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1997335533] [2024-11-13 14:57:21,140 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1997335533] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:21,140 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:21,140 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:21,140 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1528285429] [2024-11-13 14:57:21,140 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:21,141 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:21,141 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:21,141 INFO L85 PathProgramCache]: Analyzing trace with hash -1395311782, now seen corresponding path program 1 times [2024-11-13 14:57:21,141 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:21,141 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1119862365] [2024-11-13 14:57:21,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:21,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:21,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:21,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:21,232 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:21,232 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1119862365] [2024-11-13 14:57:21,233 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1119862365] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:21,233 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:21,233 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:21,233 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [824019355] [2024-11-13 14:57:21,233 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:21,233 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:21,233 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:21,234 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:57:21,234 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:57:21,234 INFO L87 Difference]: Start difference. First operand 1801 states and 2655 transitions. cyclomatic complexity: 855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:21,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:21,281 INFO L93 Difference]: Finished difference Result 1801 states and 2654 transitions. [2024-11-13 14:57:21,281 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2654 transitions. [2024-11-13 14:57:21,291 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:21,304 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2654 transitions. [2024-11-13 14:57:21,304 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-13 14:57:21,306 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-13 14:57:21,307 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2654 transitions. [2024-11-13 14:57:21,310 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:21,310 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2654 transitions. [2024-11-13 14:57:21,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2654 transitions. [2024-11-13 14:57:21,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-13 14:57:21,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4736257634647418) internal successors, (2654), 1800 states have internal predecessors, (2654), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:21,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2654 transitions. [2024-11-13 14:57:21,358 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2654 transitions. [2024-11-13 14:57:21,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:57:21,359 INFO L424 stractBuchiCegarLoop]: Abstraction has 1801 states and 2654 transitions. [2024-11-13 14:57:21,359 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 14:57:21,359 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2654 transitions. [2024-11-13 14:57:21,368 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:21,368 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:21,368 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:21,370 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:21,371 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:21,371 INFO L745 eck$LassoCheckResult]: Stem: 40005#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 40006#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 40850#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40851#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41437#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 41438#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40531#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40320#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39717#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39718#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40962#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41061#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41499#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41500#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40456#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40457#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40988#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40913#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40493#L1201 assume !(0 == ~M_E~0); 40494#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41346#L1206-1 assume !(0 == ~T2_E~0); 41329#L1211-1 assume !(0 == ~T3_E~0); 41330#L1216-1 assume !(0 == ~T4_E~0); 40301#L1221-1 assume !(0 == ~T5_E~0); 40302#L1226-1 assume !(0 == ~T6_E~0); 39931#L1231-1 assume !(0 == ~T7_E~0); 39932#L1236-1 assume !(0 == ~T8_E~0); 41370#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40341#L1246-1 assume !(0 == ~T10_E~0); 40342#L1251-1 assume !(0 == ~T11_E~0); 40491#L1256-1 assume !(0 == ~T12_E~0); 39726#L1261-1 assume !(0 == ~E_M~0); 39727#L1266-1 assume !(0 == ~E_1~0); 41484#L1271-1 assume !(0 == ~E_2~0); 41045#L1276-1 assume !(0 == ~E_3~0); 41046#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 41000#L1286-1 assume !(0 == ~E_5~0); 40197#L1291-1 assume !(0 == ~E_6~0); 40198#L1296-1 assume !(0 == ~E_7~0); 40786#L1301-1 assume !(0 == ~E_8~0); 40787#L1306-1 assume !(0 == ~E_9~0); 41265#L1311-1 assume !(0 == ~E_10~0); 40148#L1316-1 assume !(0 == ~E_11~0); 40149#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 40805#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40806#L593 assume 1 == ~m_pc~0; 40955#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40030#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40694#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40695#L1492 assume !(0 != activate_threads_~tmp~1#1); 41010#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41298#L612 assume !(1 == ~t1_pc~0); 41299#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41433#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41143#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40033#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40034#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40472#L631 assume 1 == ~t2_pc~0; 40399#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39807#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39808#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40162#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 40658#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40109#L650 assume !(1 == ~t3_pc~0); 40110#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40828#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41122#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39764#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 39765#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40981#L669 assume 1 == ~t4_pc~0; 40982#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41337#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39847#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39848#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 39968#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40207#L688 assume !(1 == ~t5_pc~0); 39987#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39988#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41465#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40870#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 40871#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40995#L707 assume 1 == ~t6_pc~0; 41404#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40627#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40150#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40151#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 40941#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40492#L726 assume 1 == ~t7_pc~0; 40387#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40074#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41134#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41408#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 39837#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39838#L745 assume !(1 == ~t8_pc~0); 40294#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 40314#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41352#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40703#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40704#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41222#L764 assume 1 == ~t9_pc~0; 40490#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40324#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40223#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40224#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 39863#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39864#L783 assume !(1 == ~t10_pc~0); 39918#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39919#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40116#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40446#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 40447#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41339#L802 assume 1 == ~t11_pc~0; 41321#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39804#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39805#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40303#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 40304#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40421#L821 assume !(1 == ~t12_pc~0); 40672#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40778#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39811#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39812#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 41381#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41018#L1339 assume !(1 == ~M_E~0); 41019#L1339-2 assume !(1 == ~T1_E~0); 41411#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41412#L1349-1 assume !(1 == ~T3_E~0); 40798#L1354-1 assume !(1 == ~T4_E~0); 40799#L1359-1 assume !(1 == ~T5_E~0); 41198#L1364-1 assume !(1 == ~T6_E~0); 40255#L1369-1 assume !(1 == ~T7_E~0); 40256#L1374-1 assume !(1 == ~T8_E~0); 40801#L1379-1 assume !(1 == ~T9_E~0); 40802#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40910#L1389-1 assume !(1 == ~T11_E~0); 41375#L1394-1 assume !(1 == ~T12_E~0); 41376#L1399-1 assume !(1 == ~E_M~0); 41457#L1404-1 assume !(1 == ~E_1~0); 40348#L1409-1 assume !(1 == ~E_2~0); 40349#L1414-1 assume !(1 == ~E_3~0); 41081#L1419-1 assume !(1 == ~E_4~0); 39977#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 39978#L1429-1 assume !(1 == ~E_6~0); 40813#L1434-1 assume !(1 == ~E_7~0); 41393#L1439-1 assume !(1 == ~E_8~0); 40019#L1444-1 assume !(1 == ~E_9~0); 40020#L1449-1 assume !(1 == ~E_10~0); 40405#L1454-1 assume !(1 == ~E_11~0); 40406#L1459-1 assume !(1 == ~E_12~0); 40940#L1464-1 assume { :end_inline_reset_delta_events } true; 40161#L1810-2 [2024-11-13 14:57:21,372 INFO L747 eck$LassoCheckResult]: Loop: 40161#L1810-2 assume !false; 40611#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40709#L1176-1 assume !false; 41091#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40655#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39845#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41145#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 41316#L1003 assume !(0 != eval_~tmp~0#1); 40618#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40350#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40351#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41035#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41036#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40938#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40104#L1216-3 assume !(0 == ~T4_E~0); 40105#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40583#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40183#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40184#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40435#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41424#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41324#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41023#L1256-3 assume !(0 == ~T12_E~0); 40124#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 40125#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40175#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40176#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40559#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40560#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 41078#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41079#L1296-3 assume !(0 == ~E_7~0); 41496#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41454#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40663#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40044#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40045#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 40126#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40777#L593-42 assume 1 == ~m_pc~0; 41164#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40943#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40458#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40459#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39938#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39939#L612-42 assume !(1 == ~t1_pc~0); 40897#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 41278#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41505#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40031#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40032#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40740#L631-42 assume !(1 == ~t2_pc~0); 39793#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 39792#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40725#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40609#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40610#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40202#L650-42 assume 1 == ~t3_pc~0; 39756#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39757#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41111#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40397#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40398#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41395#L669-42 assume 1 == ~t4_pc~0; 40677#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39755#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41180#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41089#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40993#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40994#L688-42 assume 1 == ~t5_pc~0; 41076#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41281#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40789#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39966#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 39967#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39784#L707-42 assume !(1 == ~t6_pc~0); 39785#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 41460#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40118#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40119#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 40964#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40965#L726-42 assume !(1 == ~t7_pc~0); 41232#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 41262#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40816#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40667#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40668#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40781#L745-42 assume 1 == ~t8_pc~0; 40819#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40820#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40984#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39772#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39773#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40518#L764-42 assume 1 == ~t9_pc~0; 40646#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41007#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41008#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40056#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 40057#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40117#L783-42 assume 1 == ~t10_pc~0; 39728#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 39730#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40333#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40976#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41487#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41170#L802-42 assume 1 == ~t11_pc~0; 40264#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39870#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39871#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39817#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39818#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41015#L821-42 assume !(1 == ~t12_pc~0); 40373#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 40374#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40774#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40775#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40711#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40701#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40702#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40874#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40980#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40383#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40384#L1359-3 assume !(1 == ~T5_E~0); 40990#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41481#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41391#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 40204#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40205#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40381#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40382#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 40597#L1399-3 assume !(1 == ~E_M~0); 41400#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41368#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41369#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41423#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41173#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40078#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40079#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40989#L1439-3 assume !(1 == ~E_8~0); 40007#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40008#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40129#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40985#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 40986#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40628#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39911#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40112#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 40113#L1829 assume !(0 == start_simulation_~tmp~3#1); 39892#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 39893#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40707#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39797#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 39798#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41001#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41374#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 40160#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 40161#L1810-2 [2024-11-13 14:57:21,372 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:21,373 INFO L85 PathProgramCache]: Analyzing trace with hash 1133017134, now seen corresponding path program 1 times [2024-11-13 14:57:21,373 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:21,373 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [787651101] [2024-11-13 14:57:21,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:21,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:21,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:21,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:21,447 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:21,448 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [787651101] [2024-11-13 14:57:21,448 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [787651101] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:21,449 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:21,449 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:21,449 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2123040052] [2024-11-13 14:57:21,450 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:21,452 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:21,453 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:21,453 INFO L85 PathProgramCache]: Analyzing trace with hash 16903898, now seen corresponding path program 1 times [2024-11-13 14:57:21,453 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:21,453 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248149574] [2024-11-13 14:57:21,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:21,454 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:21,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:21,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:21,549 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:21,549 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [248149574] [2024-11-13 14:57:21,549 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [248149574] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:21,549 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:21,549 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:21,549 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [645970160] [2024-11-13 14:57:21,549 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:21,550 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:21,550 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:21,550 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:57:21,550 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:57:21,550 INFO L87 Difference]: Start difference. First operand 1801 states and 2654 transitions. cyclomatic complexity: 854 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:21,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:21,599 INFO L93 Difference]: Finished difference Result 1801 states and 2653 transitions. [2024-11-13 14:57:21,599 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2653 transitions. [2024-11-13 14:57:21,609 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:21,622 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2653 transitions. [2024-11-13 14:57:21,622 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-13 14:57:21,624 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-13 14:57:21,624 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2653 transitions. [2024-11-13 14:57:21,627 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:21,628 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2653 transitions. [2024-11-13 14:57:21,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2653 transitions. [2024-11-13 14:57:21,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-13 14:57:21,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.473070516379789) internal successors, (2653), 1800 states have internal predecessors, (2653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:21,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2653 transitions. [2024-11-13 14:57:21,672 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2653 transitions. [2024-11-13 14:57:21,673 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:57:21,674 INFO L424 stractBuchiCegarLoop]: Abstraction has 1801 states and 2653 transitions. [2024-11-13 14:57:21,674 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 14:57:21,675 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2653 transitions. [2024-11-13 14:57:21,683 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:21,684 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:21,684 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:21,686 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:21,687 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:21,687 INFO L745 eck$LassoCheckResult]: Stem: 43614#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 43615#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 44459#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44460#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45046#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 45047#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44140#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43929#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43326#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43327#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44571#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44670#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45108#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45109#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44065#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 44066#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 44597#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 44522#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44102#L1201 assume !(0 == ~M_E~0); 44103#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44955#L1206-1 assume !(0 == ~T2_E~0); 44938#L1211-1 assume !(0 == ~T3_E~0); 44939#L1216-1 assume !(0 == ~T4_E~0); 43910#L1221-1 assume !(0 == ~T5_E~0); 43911#L1226-1 assume !(0 == ~T6_E~0); 43540#L1231-1 assume !(0 == ~T7_E~0); 43541#L1236-1 assume !(0 == ~T8_E~0); 44979#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43950#L1246-1 assume !(0 == ~T10_E~0); 43951#L1251-1 assume !(0 == ~T11_E~0); 44100#L1256-1 assume !(0 == ~T12_E~0); 43335#L1261-1 assume !(0 == ~E_M~0); 43336#L1266-1 assume !(0 == ~E_1~0); 45093#L1271-1 assume !(0 == ~E_2~0); 44654#L1276-1 assume !(0 == ~E_3~0); 44655#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 44609#L1286-1 assume !(0 == ~E_5~0); 43806#L1291-1 assume !(0 == ~E_6~0); 43807#L1296-1 assume !(0 == ~E_7~0); 44395#L1301-1 assume !(0 == ~E_8~0); 44396#L1306-1 assume !(0 == ~E_9~0); 44874#L1311-1 assume !(0 == ~E_10~0); 43757#L1316-1 assume !(0 == ~E_11~0); 43758#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 44414#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44415#L593 assume 1 == ~m_pc~0; 44564#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 43639#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44303#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44304#L1492 assume !(0 != activate_threads_~tmp~1#1); 44619#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44907#L612 assume !(1 == ~t1_pc~0); 44908#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 45042#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44752#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43642#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43643#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44081#L631 assume 1 == ~t2_pc~0; 44008#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43416#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43417#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43771#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 44267#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43718#L650 assume !(1 == ~t3_pc~0); 43719#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44437#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44731#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43373#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 43374#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44590#L669 assume 1 == ~t4_pc~0; 44591#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44946#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43456#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43457#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 43577#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43816#L688 assume !(1 == ~t5_pc~0); 43596#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 43597#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45074#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44479#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 44480#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44604#L707 assume 1 == ~t6_pc~0; 45013#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44236#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43759#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43760#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 44550#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44101#L726 assume 1 == ~t7_pc~0; 43996#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43683#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44743#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45017#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 43446#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43447#L745 assume !(1 == ~t8_pc~0); 43903#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 43923#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44961#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44312#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44313#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44831#L764 assume 1 == ~t9_pc~0; 44099#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43933#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43832#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43833#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 43472#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43473#L783 assume !(1 == ~t10_pc~0); 43527#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 43528#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43725#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44055#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 44056#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44948#L802 assume 1 == ~t11_pc~0; 44930#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43413#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43414#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43912#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 43913#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44030#L821 assume !(1 == ~t12_pc~0); 44281#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 44387#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43420#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 43421#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 44990#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44627#L1339 assume !(1 == ~M_E~0); 44628#L1339-2 assume !(1 == ~T1_E~0); 45020#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 45021#L1349-1 assume !(1 == ~T3_E~0); 44407#L1354-1 assume !(1 == ~T4_E~0); 44408#L1359-1 assume !(1 == ~T5_E~0); 44807#L1364-1 assume !(1 == ~T6_E~0); 43864#L1369-1 assume !(1 == ~T7_E~0); 43865#L1374-1 assume !(1 == ~T8_E~0); 44410#L1379-1 assume !(1 == ~T9_E~0); 44411#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 44519#L1389-1 assume !(1 == ~T11_E~0); 44984#L1394-1 assume !(1 == ~T12_E~0); 44985#L1399-1 assume !(1 == ~E_M~0); 45066#L1404-1 assume !(1 == ~E_1~0); 43957#L1409-1 assume !(1 == ~E_2~0); 43958#L1414-1 assume !(1 == ~E_3~0); 44690#L1419-1 assume !(1 == ~E_4~0); 43586#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 43587#L1429-1 assume !(1 == ~E_6~0); 44422#L1434-1 assume !(1 == ~E_7~0); 45002#L1439-1 assume !(1 == ~E_8~0); 43628#L1444-1 assume !(1 == ~E_9~0); 43629#L1449-1 assume !(1 == ~E_10~0); 44014#L1454-1 assume !(1 == ~E_11~0); 44015#L1459-1 assume !(1 == ~E_12~0); 44549#L1464-1 assume { :end_inline_reset_delta_events } true; 43770#L1810-2 [2024-11-13 14:57:21,688 INFO L747 eck$LassoCheckResult]: Loop: 43770#L1810-2 assume !false; 44220#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44318#L1176-1 assume !false; 44700#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44264#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43454#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44754#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 44925#L1003 assume !(0 != eval_~tmp~0#1); 44227#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43959#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43960#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44644#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44645#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44547#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43713#L1216-3 assume !(0 == ~T4_E~0); 43714#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44192#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43792#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43793#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44044#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45033#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44933#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44632#L1256-3 assume !(0 == ~T12_E~0); 43733#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 43734#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43784#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43785#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44168#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44169#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44687#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44688#L1296-3 assume !(0 == ~E_7~0); 45105#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45063#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 44272#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 43653#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43654#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 43735#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44386#L593-42 assume 1 == ~m_pc~0; 44773#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 44552#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44067#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44068#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43547#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43548#L612-42 assume !(1 == ~t1_pc~0); 44506#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 44887#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45114#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43640#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43641#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44349#L631-42 assume 1 == ~t2_pc~0; 43400#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43401#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44334#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44218#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 44219#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43811#L650-42 assume 1 == ~t3_pc~0; 43365#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43366#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44720#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44006#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44007#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45004#L669-42 assume !(1 == ~t4_pc~0); 43363#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 43364#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44789#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44698#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44602#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44603#L688-42 assume 1 == ~t5_pc~0; 44685#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44890#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44398#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43575#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 43576#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43393#L707-42 assume !(1 == ~t6_pc~0); 43394#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 45069#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43727#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43728#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 44573#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44574#L726-42 assume 1 == ~t7_pc~0; 44840#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 44871#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44425#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44276#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 44277#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44390#L745-42 assume 1 == ~t8_pc~0; 44428#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44429#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44593#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43381#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43382#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44127#L764-42 assume !(1 == ~t9_pc~0); 44256#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 44616#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44617#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43665#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43666#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43726#L783-42 assume 1 == ~t10_pc~0; 43337#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 43339#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43942#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44585#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45096#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44779#L802-42 assume 1 == ~t11_pc~0; 43873#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43479#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43480#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43426#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43427#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44624#L821-42 assume 1 == ~t12_pc~0; 44625#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 43983#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44383#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44384#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 44320#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44310#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 44311#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44483#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44589#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43992#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43993#L1359-3 assume !(1 == ~T5_E~0); 44599#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 45090#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 45000#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 43813#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 43814#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43990#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43991#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 44206#L1399-3 assume !(1 == ~E_M~0); 45009#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44977#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44978#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45032#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44782#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43687#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43688#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44598#L1439-3 assume !(1 == ~E_8~0); 43616#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43617#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43738#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44594#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44595#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44237#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43520#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43721#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 43722#L1829 assume !(0 == start_simulation_~tmp~3#1); 43501#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43502#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44316#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43406#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 43407#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44610#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44983#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 43769#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 43770#L1810-2 [2024-11-13 14:57:21,688 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:21,688 INFO L85 PathProgramCache]: Analyzing trace with hash -1544509712, now seen corresponding path program 1 times [2024-11-13 14:57:21,688 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:21,689 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2121448805] [2024-11-13 14:57:21,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:21,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:21,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:21,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:21,795 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:21,795 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2121448805] [2024-11-13 14:57:21,796 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2121448805] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:21,796 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:21,796 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:57:21,797 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [300866603] [2024-11-13 14:57:21,797 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:21,798 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:21,798 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:21,798 INFO L85 PathProgramCache]: Analyzing trace with hash -2139031527, now seen corresponding path program 1 times [2024-11-13 14:57:21,799 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:21,799 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694930281] [2024-11-13 14:57:21,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:21,799 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:21,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:21,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:21,900 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:21,900 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [694930281] [2024-11-13 14:57:21,900 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [694930281] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:21,900 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:21,901 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:21,901 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [937407434] [2024-11-13 14:57:21,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:21,902 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:21,902 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:21,903 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:57:21,903 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:57:21,903 INFO L87 Difference]: Start difference. First operand 1801 states and 2653 transitions. cyclomatic complexity: 853 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:21,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:21,978 INFO L93 Difference]: Finished difference Result 1801 states and 2648 transitions. [2024-11-13 14:57:21,978 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2648 transitions. [2024-11-13 14:57:21,991 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:22,001 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2648 transitions. [2024-11-13 14:57:22,001 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-13 14:57:22,003 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-13 14:57:22,003 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2648 transitions. [2024-11-13 14:57:22,007 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:22,007 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2648 transitions. [2024-11-13 14:57:22,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2648 transitions. [2024-11-13 14:57:22,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-13 14:57:22,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.470294280955025) internal successors, (2648), 1800 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:22,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2648 transitions. [2024-11-13 14:57:22,062 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2648 transitions. [2024-11-13 14:57:22,063 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:57:22,065 INFO L424 stractBuchiCegarLoop]: Abstraction has 1801 states and 2648 transitions. [2024-11-13 14:57:22,065 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 14:57:22,065 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2648 transitions. [2024-11-13 14:57:22,076 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-13 14:57:22,076 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:22,077 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:22,085 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:22,086 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:22,086 INFO L745 eck$LassoCheckResult]: Stem: 47223#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 47224#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 48068#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48069#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48655#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 48656#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47749#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47538#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46935#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46936#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48180#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48279#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48717#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48718#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47674#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47675#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 48206#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 48131#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47711#L1201 assume !(0 == ~M_E~0); 47712#L1201-2 assume !(0 == ~T1_E~0); 48564#L1206-1 assume !(0 == ~T2_E~0); 48547#L1211-1 assume !(0 == ~T3_E~0); 48548#L1216-1 assume !(0 == ~T4_E~0); 47519#L1221-1 assume !(0 == ~T5_E~0); 47520#L1226-1 assume !(0 == ~T6_E~0); 47149#L1231-1 assume !(0 == ~T7_E~0); 47150#L1236-1 assume !(0 == ~T8_E~0); 48588#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47559#L1246-1 assume !(0 == ~T10_E~0); 47560#L1251-1 assume !(0 == ~T11_E~0); 47709#L1256-1 assume !(0 == ~T12_E~0); 46944#L1261-1 assume !(0 == ~E_M~0); 46945#L1266-1 assume !(0 == ~E_1~0); 48702#L1271-1 assume !(0 == ~E_2~0); 48263#L1276-1 assume !(0 == ~E_3~0); 48264#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 48218#L1286-1 assume !(0 == ~E_5~0); 47415#L1291-1 assume !(0 == ~E_6~0); 47416#L1296-1 assume !(0 == ~E_7~0); 48004#L1301-1 assume !(0 == ~E_8~0); 48005#L1306-1 assume !(0 == ~E_9~0); 48483#L1311-1 assume !(0 == ~E_10~0); 47366#L1316-1 assume !(0 == ~E_11~0); 47367#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 48023#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48024#L593 assume 1 == ~m_pc~0; 48173#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47248#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47912#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47913#L1492 assume !(0 != activate_threads_~tmp~1#1); 48228#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48516#L612 assume !(1 == ~t1_pc~0); 48517#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48651#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48361#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47251#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47252#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47690#L631 assume 1 == ~t2_pc~0; 47617#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47025#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47026#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47380#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 47876#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47327#L650 assume !(1 == ~t3_pc~0); 47328#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48046#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48340#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46982#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 46983#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48199#L669 assume 1 == ~t4_pc~0; 48200#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48555#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47065#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47066#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 47186#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47425#L688 assume !(1 == ~t5_pc~0); 47205#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 47206#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48683#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48088#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 48089#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48213#L707 assume 1 == ~t6_pc~0; 48622#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47845#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47368#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47369#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 48159#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47710#L726 assume 1 == ~t7_pc~0; 47605#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47292#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48352#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48626#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 47055#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47056#L745 assume !(1 == ~t8_pc~0); 47512#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47532#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48570#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47921#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47922#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48440#L764 assume 1 == ~t9_pc~0; 47708#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47542#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47441#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47442#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 47081#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47082#L783 assume !(1 == ~t10_pc~0); 47136#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 47137#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47334#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47664#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 47665#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48557#L802 assume 1 == ~t11_pc~0; 48539#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 47022#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47023#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47521#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 47522#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47639#L821 assume !(1 == ~t12_pc~0); 47890#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 47996#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47029#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47030#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 48599#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48236#L1339 assume !(1 == ~M_E~0); 48237#L1339-2 assume !(1 == ~T1_E~0); 48629#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48630#L1349-1 assume !(1 == ~T3_E~0); 48016#L1354-1 assume !(1 == ~T4_E~0); 48017#L1359-1 assume !(1 == ~T5_E~0); 48416#L1364-1 assume !(1 == ~T6_E~0); 47473#L1369-1 assume !(1 == ~T7_E~0); 47474#L1374-1 assume !(1 == ~T8_E~0); 48019#L1379-1 assume !(1 == ~T9_E~0); 48020#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 48128#L1389-1 assume !(1 == ~T11_E~0); 48593#L1394-1 assume !(1 == ~T12_E~0); 48594#L1399-1 assume !(1 == ~E_M~0); 48675#L1404-1 assume !(1 == ~E_1~0); 47566#L1409-1 assume !(1 == ~E_2~0); 47567#L1414-1 assume !(1 == ~E_3~0); 48299#L1419-1 assume !(1 == ~E_4~0); 47195#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 47196#L1429-1 assume !(1 == ~E_6~0); 48031#L1434-1 assume !(1 == ~E_7~0); 48611#L1439-1 assume !(1 == ~E_8~0); 47237#L1444-1 assume !(1 == ~E_9~0); 47238#L1449-1 assume !(1 == ~E_10~0); 47623#L1454-1 assume !(1 == ~E_11~0); 47624#L1459-1 assume !(1 == ~E_12~0); 48158#L1464-1 assume { :end_inline_reset_delta_events } true; 47379#L1810-2 [2024-11-13 14:57:22,086 INFO L747 eck$LassoCheckResult]: Loop: 47379#L1810-2 assume !false; 47829#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47927#L1176-1 assume !false; 48309#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47873#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47063#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 48363#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 48534#L1003 assume !(0 != eval_~tmp~0#1); 47836#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47568#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47569#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 48253#L1201-5 assume !(0 == ~T1_E~0); 48254#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 48156#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47322#L1216-3 assume !(0 == ~T4_E~0); 47323#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47801#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47401#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47402#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47653#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48642#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 48542#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48241#L1256-3 assume !(0 == ~T12_E~0); 47342#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 47343#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47393#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47394#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47777#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47778#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 48296#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 48297#L1296-3 assume !(0 == ~E_7~0); 48714#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 48672#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47881#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 47262#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47263#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 47344#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47995#L593-42 assume !(1 == ~m_pc~0); 48160#L593-44 is_master_triggered_~__retres1~0#1 := 0; 48161#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47676#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47677#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47156#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47157#L612-42 assume !(1 == ~t1_pc~0); 48115#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 48496#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48723#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47249#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47250#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47958#L631-42 assume 1 == ~t2_pc~0; 47009#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47010#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47943#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47827#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47828#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47420#L650-42 assume !(1 == ~t3_pc~0); 46976#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 46975#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48329#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47615#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47616#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48613#L669-42 assume 1 == ~t4_pc~0; 47895#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46973#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48398#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48307#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48211#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48212#L688-42 assume 1 == ~t5_pc~0; 48294#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48499#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48007#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47184#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 47185#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47002#L707-42 assume !(1 == ~t6_pc~0); 47003#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 48678#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47336#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47337#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 48182#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48183#L726-42 assume 1 == ~t7_pc~0; 48449#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48480#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48034#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47885#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47886#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47999#L745-42 assume 1 == ~t8_pc~0; 48037#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48038#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48202#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46990#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 46991#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47736#L764-42 assume 1 == ~t9_pc~0; 47864#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48225#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48226#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47274#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47275#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47335#L783-42 assume 1 == ~t10_pc~0; 46946#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46948#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47551#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48194#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48705#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48388#L802-42 assume 1 == ~t11_pc~0; 47482#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 47088#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47089#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47035#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 47036#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48233#L821-42 assume !(1 == ~t12_pc~0); 47591#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 47592#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47992#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47993#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47929#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47919#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47920#L1339-5 assume !(1 == ~T1_E~0); 48092#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48198#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47601#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47602#L1359-3 assume !(1 == ~T5_E~0); 48208#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48699#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48609#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47422#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47423#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47599#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47600#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47815#L1399-3 assume !(1 == ~E_M~0); 48618#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48586#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48587#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48641#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48391#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47296#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47297#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 48207#L1439-3 assume !(1 == ~E_8~0); 47225#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47226#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47347#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 48203#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 48204#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47846#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47129#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47330#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 47331#L1829 assume !(0 == start_simulation_~tmp~3#1); 47110#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47111#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47925#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47015#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 47016#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48219#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48592#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 47378#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 47379#L1810-2 [2024-11-13 14:57:22,087 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:22,087 INFO L85 PathProgramCache]: Analyzing trace with hash -2089382286, now seen corresponding path program 1 times [2024-11-13 14:57:22,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:22,087 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [904853901] [2024-11-13 14:57:22,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:22,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:22,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:22,225 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:22,226 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:22,226 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [904853901] [2024-11-13 14:57:22,226 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [904853901] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:22,226 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:22,226 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:22,226 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [927210623] [2024-11-13 14:57:22,226 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:22,227 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:22,227 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:22,228 INFO L85 PathProgramCache]: Analyzing trace with hash 587452442, now seen corresponding path program 1 times [2024-11-13 14:57:22,229 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:22,229 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [833243157] [2024-11-13 14:57:22,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:22,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:22,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:22,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:22,313 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:22,313 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [833243157] [2024-11-13 14:57:22,313 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [833243157] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:22,313 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:22,313 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:22,315 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [385981597] [2024-11-13 14:57:22,315 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:22,315 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:22,315 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:22,316 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 14:57:22,316 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 14:57:22,317 INFO L87 Difference]: Start difference. First operand 1801 states and 2648 transitions. cyclomatic complexity: 848 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:22,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:22,555 INFO L93 Difference]: Finished difference Result 3463 states and 5084 transitions. [2024-11-13 14:57:22,555 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3463 states and 5084 transitions. [2024-11-13 14:57:22,576 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3276 [2024-11-13 14:57:22,598 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3463 states to 3463 states and 5084 transitions. [2024-11-13 14:57:22,598 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3463 [2024-11-13 14:57:22,602 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3463 [2024-11-13 14:57:22,602 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3463 states and 5084 transitions. [2024-11-13 14:57:22,608 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:22,608 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3463 states and 5084 transitions. [2024-11-13 14:57:22,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3463 states and 5084 transitions. [2024-11-13 14:57:22,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3463 to 3463. [2024-11-13 14:57:22,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3463 states, 3463 states have (on average 1.4680912503609587) internal successors, (5084), 3462 states have internal predecessors, (5084), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:22,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3463 states to 3463 states and 5084 transitions. [2024-11-13 14:57:22,723 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3463 states and 5084 transitions. [2024-11-13 14:57:22,724 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 14:57:22,725 INFO L424 stractBuchiCegarLoop]: Abstraction has 3463 states and 5084 transitions. [2024-11-13 14:57:22,725 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 14:57:22,726 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3463 states and 5084 transitions. [2024-11-13 14:57:22,741 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3276 [2024-11-13 14:57:22,742 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:22,742 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:22,746 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:22,746 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:22,747 INFO L745 eck$LassoCheckResult]: Stem: 52497#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 52498#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 53345#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53346#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53940#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 53941#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53025#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52813#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52209#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52210#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53457#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53557#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 54020#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 54021#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 52949#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 52950#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53483#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 53408#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52986#L1201 assume !(0 == ~M_E~0); 52987#L1201-2 assume !(0 == ~T1_E~0); 53844#L1206-1 assume !(0 == ~T2_E~0); 53826#L1211-1 assume !(0 == ~T3_E~0); 53827#L1216-1 assume !(0 == ~T4_E~0); 52795#L1221-1 assume !(0 == ~T5_E~0); 52796#L1226-1 assume !(0 == ~T6_E~0); 52423#L1231-1 assume !(0 == ~T7_E~0); 52424#L1236-1 assume !(0 == ~T8_E~0); 53870#L1241-1 assume !(0 == ~T9_E~0); 52837#L1246-1 assume !(0 == ~T10_E~0); 52838#L1251-1 assume !(0 == ~T11_E~0); 52984#L1256-1 assume !(0 == ~T12_E~0); 52218#L1261-1 assume !(0 == ~E_M~0); 52219#L1266-1 assume !(0 == ~E_1~0); 54000#L1271-1 assume !(0 == ~E_2~0); 53540#L1276-1 assume !(0 == ~E_3~0); 53541#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 53495#L1286-1 assume !(0 == ~E_5~0); 52689#L1291-1 assume !(0 == ~E_6~0); 52690#L1296-1 assume !(0 == ~E_7~0); 53280#L1301-1 assume !(0 == ~E_8~0); 53281#L1306-1 assume !(0 == ~E_9~0); 53762#L1311-1 assume !(0 == ~E_10~0); 52640#L1316-1 assume !(0 == ~E_11~0); 52641#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 53299#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53300#L593 assume 1 == ~m_pc~0; 53450#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 52522#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53187#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53188#L1492 assume !(0 != activate_threads_~tmp~1#1); 53505#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53795#L612 assume !(1 == ~t1_pc~0); 53796#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53936#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53638#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52525#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52526#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52965#L631 assume 1 == ~t2_pc~0; 52892#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52299#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52300#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52654#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 53151#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52603#L650 assume !(1 == ~t3_pc~0); 52604#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53322#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53617#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52256#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 52257#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53476#L669 assume 1 == ~t4_pc~0; 53477#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53835#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52343#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52344#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 52460#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52699#L688 assume !(1 == ~t5_pc~0); 52479#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52480#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53969#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53366#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 53367#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53493#L707 assume 1 == ~t6_pc~0; 53904#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53120#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52642#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52643#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 53438#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52985#L726 assume 1 == ~t7_pc~0; 52882#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52566#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53630#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53910#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 52329#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52330#L745 assume !(1 == ~t8_pc~0); 52787#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 52807#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53851#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53196#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53197#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53718#L764 assume 1 == ~t9_pc~0; 52983#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52817#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52716#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52717#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 52355#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52356#L783 assume !(1 == ~t10_pc~0); 52410#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 52411#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52608#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52944#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 52945#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53836#L802 assume 1 == ~t11_pc~0; 53818#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 52296#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52297#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52797#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 52798#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 52914#L821 assume !(1 == ~t12_pc~0); 53165#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 53272#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52305#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 52306#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 53881#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53513#L1339 assume !(1 == ~M_E~0); 53514#L1339-2 assume !(1 == ~T1_E~0); 53912#L1344-1 assume !(1 == ~T2_E~0); 53913#L1349-1 assume !(1 == ~T3_E~0); 54167#L1354-1 assume !(1 == ~T4_E~0); 54165#L1359-1 assume !(1 == ~T5_E~0); 54163#L1364-1 assume !(1 == ~T6_E~0); 54162#L1369-1 assume !(1 == ~T7_E~0); 54161#L1374-1 assume !(1 == ~T8_E~0); 54160#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 53298#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 53405#L1389-1 assume !(1 == ~T11_E~0); 53875#L1394-1 assume !(1 == ~T12_E~0); 53876#L1399-1 assume !(1 == ~E_M~0); 54154#L1404-1 assume !(1 == ~E_1~0); 54152#L1409-1 assume !(1 == ~E_2~0); 54150#L1414-1 assume !(1 == ~E_3~0); 54147#L1419-1 assume !(1 == ~E_4~0); 54145#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54143#L1429-1 assume !(1 == ~E_6~0); 54141#L1434-1 assume !(1 == ~E_7~0); 54139#L1439-1 assume !(1 == ~E_8~0); 54138#L1444-1 assume !(1 == ~E_9~0); 54124#L1449-1 assume !(1 == ~E_10~0); 54100#L1454-1 assume !(1 == ~E_11~0); 54092#L1459-1 assume !(1 == ~E_12~0); 53435#L1464-1 assume { :end_inline_reset_delta_events } true; 52653#L1810-2 [2024-11-13 14:57:22,747 INFO L747 eck$LassoCheckResult]: Loop: 52653#L1810-2 assume !false; 53104#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53202#L1176-1 assume !false; 53586#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53150#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52337#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 53640#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53815#L1003 assume !(0 != eval_~tmp~0#1); 53111#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52843#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52844#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53530#L1201-5 assume !(0 == ~T1_E~0); 53531#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 53434#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52596#L1216-3 assume !(0 == ~T4_E~0); 52597#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53076#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52675#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 52676#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52928#L1241-3 assume !(0 == ~T9_E~0); 53927#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 53821#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 53518#L1256-3 assume !(0 == ~T12_E~0); 52616#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 52617#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52667#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52668#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53052#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53053#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53573#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53574#L1296-3 assume !(0 == ~E_7~0); 54014#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53958#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53156#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 52536#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 52537#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 52618#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53271#L593-42 assume 1 == ~m_pc~0; 53659#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 53437#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52951#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52952#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52430#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52431#L612-42 assume 1 == ~t1_pc~0; 53392#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53775#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54027#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52523#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52524#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53234#L631-42 assume 1 == ~t2_pc~0; 52283#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52284#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53218#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53102#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53103#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52694#L650-42 assume 1 == ~t3_pc~0; 52248#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 52249#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53606#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52890#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 52891#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53895#L669-42 assume 1 == ~t4_pc~0; 53170#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 52247#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53676#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53584#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53488#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53489#L688-42 assume 1 == ~t5_pc~0; 53571#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53778#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53283#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52455#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 52456#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52276#L707-42 assume !(1 == ~t6_pc~0); 52277#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 53964#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52610#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52611#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 53459#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53460#L726-42 assume !(1 == ~t7_pc~0); 53728#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 53759#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53310#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53160#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 53161#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53275#L745-42 assume 1 == ~t8_pc~0; 53313#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53314#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53479#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52264#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52265#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53011#L764-42 assume 1 == ~t9_pc~0; 53139#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53502#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53503#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52548#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 52549#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52609#L783-42 assume 1 == ~t10_pc~0; 52220#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 52222#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52826#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53471#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 54003#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53666#L802-42 assume 1 == ~t11_pc~0; 52757#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 52362#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52363#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52309#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 52310#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53510#L821-42 assume !(1 == ~t12_pc~0); 52866#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 52867#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53268#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53269#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 53204#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53194#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 53195#L1339-5 assume !(1 == ~T1_E~0); 53368#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53475#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52876#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52877#L1359-3 assume !(1 == ~T5_E~0); 53485#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53995#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53891#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 52695#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52696#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52874#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 52875#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 53090#L1399-3 assume !(1 == ~E_M~0); 53900#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53868#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53869#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53926#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53669#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52570#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 52571#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53484#L1439-3 assume !(1 == ~E_8~0); 52499#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 52500#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 52621#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53480#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 53481#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53121#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52403#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52601#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 52602#L1829 assume !(0 == start_simulation_~tmp~3#1); 54342#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 54129#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 54123#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54122#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 54121#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54016#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53874#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 52652#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 52653#L1810-2 [2024-11-13 14:57:22,748 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:22,748 INFO L85 PathProgramCache]: Analyzing trace with hash 907144632, now seen corresponding path program 1 times [2024-11-13 14:57:22,748 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:22,749 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1495670487] [2024-11-13 14:57:22,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:22,749 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:22,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:22,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:22,863 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:22,863 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1495670487] [2024-11-13 14:57:22,864 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1495670487] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:22,864 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:22,864 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:22,864 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1921753887] [2024-11-13 14:57:22,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:22,864 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:22,865 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:22,865 INFO L85 PathProgramCache]: Analyzing trace with hash -199486630, now seen corresponding path program 1 times [2024-11-13 14:57:22,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:22,865 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [236596782] [2024-11-13 14:57:22,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:22,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:22,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:22,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:22,947 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:22,947 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [236596782] [2024-11-13 14:57:22,947 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [236596782] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:22,947 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:22,947 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:22,948 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1329735694] [2024-11-13 14:57:22,948 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:22,948 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:22,948 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:22,948 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 14:57:22,949 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 14:57:22,949 INFO L87 Difference]: Start difference. First operand 3463 states and 5084 transitions. cyclomatic complexity: 1623 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:23,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:23,240 INFO L93 Difference]: Finished difference Result 6581 states and 9651 transitions. [2024-11-13 14:57:23,240 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6581 states and 9651 transitions. [2024-11-13 14:57:23,279 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6366 [2024-11-13 14:57:23,309 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6581 states to 6581 states and 9651 transitions. [2024-11-13 14:57:23,309 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6581 [2024-11-13 14:57:23,316 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6581 [2024-11-13 14:57:23,316 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6581 states and 9651 transitions. [2024-11-13 14:57:23,327 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:23,327 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6581 states and 9651 transitions. [2024-11-13 14:57:23,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6581 states and 9651 transitions. [2024-11-13 14:57:23,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6581 to 6579. [2024-11-13 14:57:23,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6579 states, 6579 states have (on average 1.4666362669098647) internal successors, (9649), 6578 states have internal predecessors, (9649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:23,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6579 states to 6579 states and 9649 transitions. [2024-11-13 14:57:23,482 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6579 states and 9649 transitions. [2024-11-13 14:57:23,483 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 14:57:23,483 INFO L424 stractBuchiCegarLoop]: Abstraction has 6579 states and 9649 transitions. [2024-11-13 14:57:23,483 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 14:57:23,483 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6579 states and 9649 transitions. [2024-11-13 14:57:23,589 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6366 [2024-11-13 14:57:23,590 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:23,590 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:23,592 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:23,592 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:23,593 INFO L745 eck$LassoCheckResult]: Stem: 62551#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 62552#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 63397#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 63398#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64010#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 64011#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63078#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62867#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62263#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62264#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 63511#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 63612#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 64084#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 64085#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 63003#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 63004#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 63537#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 63461#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63040#L1201 assume !(0 == ~M_E~0); 63041#L1201-2 assume !(0 == ~T1_E~0); 63915#L1206-1 assume !(0 == ~T2_E~0); 63895#L1211-1 assume !(0 == ~T3_E~0); 63896#L1216-1 assume !(0 == ~T4_E~0); 62848#L1221-1 assume !(0 == ~T5_E~0); 62849#L1226-1 assume !(0 == ~T6_E~0); 62477#L1231-1 assume !(0 == ~T7_E~0); 62478#L1236-1 assume !(0 == ~T8_E~0); 63939#L1241-1 assume !(0 == ~T9_E~0); 62888#L1246-1 assume !(0 == ~T10_E~0); 62889#L1251-1 assume !(0 == ~T11_E~0); 63038#L1256-1 assume !(0 == ~T12_E~0); 62272#L1261-1 assume !(0 == ~E_M~0); 62273#L1266-1 assume !(0 == ~E_1~0); 64067#L1271-1 assume !(0 == ~E_2~0); 63596#L1276-1 assume !(0 == ~E_3~0); 63597#L1281-1 assume !(0 == ~E_4~0); 63549#L1286-1 assume !(0 == ~E_5~0); 62743#L1291-1 assume !(0 == ~E_6~0); 62744#L1296-1 assume !(0 == ~E_7~0); 63333#L1301-1 assume !(0 == ~E_8~0); 63334#L1306-1 assume !(0 == ~E_9~0); 63827#L1311-1 assume !(0 == ~E_10~0); 62694#L1316-1 assume !(0 == ~E_11~0); 62695#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 63352#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63353#L593 assume 1 == ~m_pc~0; 63504#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 62576#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63241#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63242#L1492 assume !(0 != activate_threads_~tmp~1#1); 63559#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63862#L612 assume !(1 == ~t1_pc~0); 63863#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 64006#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63699#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62579#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62580#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63019#L631 assume 1 == ~t2_pc~0; 62946#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 62353#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62354#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62708#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 63205#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62655#L650 assume !(1 == ~t3_pc~0); 62656#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 63375#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63677#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62310#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 62311#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63530#L669 assume 1 == ~t4_pc~0; 63531#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 63903#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62393#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62394#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 62514#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62754#L688 assume !(1 == ~t5_pc~0); 62533#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 62534#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64043#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63417#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 63418#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63544#L707 assume 1 == ~t6_pc~0; 63974#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 63174#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62696#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62697#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 63490#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63039#L726 assume 1 == ~t7_pc~0; 62934#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62620#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63689#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 63978#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 62383#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62384#L745 assume !(1 == ~t8_pc~0); 62841#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 62861#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 63921#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 63250#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 63251#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63783#L764 assume 1 == ~t9_pc~0; 63037#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62871#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62770#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62771#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 62409#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62410#L783 assume !(1 == ~t10_pc~0); 62464#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 62465#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62662#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62993#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 62994#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 63906#L802 assume 1 == ~t11_pc~0; 63887#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 62350#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 62351#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 62850#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 62851#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62968#L821 assume !(1 == ~t12_pc~0); 63219#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 63325#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 62357#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 62358#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 63950#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63567#L1339 assume !(1 == ~M_E~0); 63568#L1339-2 assume !(1 == ~T1_E~0); 63981#L1344-1 assume !(1 == ~T2_E~0); 63982#L1349-1 assume !(1 == ~T3_E~0); 64594#L1354-1 assume !(1 == ~T4_E~0); 63757#L1359-1 assume !(1 == ~T5_E~0); 63758#L1364-1 assume !(1 == ~T6_E~0); 62802#L1369-1 assume !(1 == ~T7_E~0); 62803#L1374-1 assume !(1 == ~T8_E~0); 64444#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 64380#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 64378#L1389-1 assume !(1 == ~T11_E~0); 64326#L1394-1 assume !(1 == ~T12_E~0); 64324#L1399-1 assume !(1 == ~E_M~0); 64323#L1404-1 assume !(1 == ~E_1~0); 62895#L1409-1 assume !(1 == ~E_2~0); 62896#L1414-1 assume !(1 == ~E_3~0); 64289#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 64286#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 64238#L1429-1 assume !(1 == ~E_6~0); 64202#L1434-1 assume !(1 == ~E_7~0); 64200#L1439-1 assume !(1 == ~E_8~0); 64198#L1444-1 assume !(1 == ~E_9~0); 64185#L1449-1 assume !(1 == ~E_10~0); 64168#L1454-1 assume !(1 == ~E_11~0); 64159#L1459-1 assume !(1 == ~E_12~0); 64151#L1464-1 assume { :end_inline_reset_delta_events } true; 64144#L1810-2 [2024-11-13 14:57:23,593 INFO L747 eck$LassoCheckResult]: Loop: 64144#L1810-2 assume !false; 64140#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 64139#L1176-1 assume !false; 64138#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 64134#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 64124#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 64123#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 64121#L1003 assume !(0 != eval_~tmp~0#1); 64120#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 64119#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 64118#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 64117#L1201-5 assume !(0 == ~T1_E~0); 64115#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 64116#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 65458#L1216-3 assume !(0 == ~T4_E~0); 65456#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 65454#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 65451#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 65449#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 65447#L1241-3 assume !(0 == ~T9_E~0); 65445#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 65443#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 65441#L1256-3 assume !(0 == ~T12_E~0); 65438#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 65436#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 65434#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 65432#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 65430#L1281-3 assume !(0 == ~E_4~0); 65428#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 65425#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 65423#L1296-3 assume !(0 == ~E_7~0); 65421#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 65419#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 65417#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 65415#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 65412#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 65410#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65408#L593-42 assume 1 == ~m_pc~0; 65405#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 65403#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65401#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65398#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 65396#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65394#L612-42 assume 1 == ~t1_pc~0; 65392#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 65389#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65388#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65387#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 65385#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65382#L631-42 assume 1 == ~t2_pc~0; 65379#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 65377#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65375#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65373#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65371#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65368#L650-42 assume !(1 == ~t3_pc~0); 65365#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 65363#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65361#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65359#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 65357#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65354#L669-42 assume 1 == ~t4_pc~0; 65351#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 65349#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65347#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65345#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 65343#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65340#L688-42 assume !(1 == ~t5_pc~0); 65337#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 65335#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65333#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65331#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 65329#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65326#L707-42 assume 1 == ~t6_pc~0; 65323#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 65321#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65319#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65317#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 65315#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65312#L726-42 assume 1 == ~t7_pc~0; 65309#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65307#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65305#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65303#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 65301#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65298#L745-42 assume !(1 == ~t8_pc~0); 65296#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 65293#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65291#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65289#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 65287#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65284#L764-42 assume 1 == ~t9_pc~0; 65281#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 65279#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65277#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 65275#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 65273#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 65270#L783-42 assume !(1 == ~t10_pc~0); 65267#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 65265#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 65263#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65261#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 65259#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65256#L802-42 assume 1 == ~t11_pc~0; 65253#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65251#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65249#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 65248#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 65247#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 65246#L821-42 assume !(1 == ~t12_pc~0); 64739#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 64737#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 64735#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 64733#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 64698#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64695#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 64693#L1339-5 assume !(1 == ~T1_E~0); 64691#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63576#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64632#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64630#L1359-3 assume !(1 == ~T5_E~0); 64628#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 64626#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64624#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 64623#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 64620#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 64618#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 64616#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 64614#L1399-3 assume !(1 == ~E_M~0); 64612#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 64610#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 64607#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 64605#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 64602#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 64600#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 64598#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 64597#L1439-3 assume !(1 == ~E_8~0); 64596#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 64595#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 64593#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 64509#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 64506#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 64434#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 64373#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 64369#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 64316#L1829 assume !(0 == start_simulation_~tmp~3#1); 64265#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 64228#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 64197#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 64184#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 64180#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 64167#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 64158#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 64150#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 64144#L1810-2 [2024-11-13 14:57:23,594 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:23,594 INFO L85 PathProgramCache]: Analyzing trace with hash -1065863428, now seen corresponding path program 1 times [2024-11-13 14:57:23,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:23,594 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1938116864] [2024-11-13 14:57:23,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:23,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:23,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:23,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:23,703 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:23,703 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1938116864] [2024-11-13 14:57:23,703 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1938116864] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:23,703 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:23,703 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:23,703 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [257061233] [2024-11-13 14:57:23,703 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:23,704 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:23,704 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:23,705 INFO L85 PathProgramCache]: Analyzing trace with hash -158029026, now seen corresponding path program 1 times [2024-11-13 14:57:23,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:23,705 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [106371082] [2024-11-13 14:57:23,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:23,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:23,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:23,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:23,793 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:23,793 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [106371082] [2024-11-13 14:57:23,794 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [106371082] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:23,794 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:23,794 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:23,794 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [708752905] [2024-11-13 14:57:23,794 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:23,794 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:23,795 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:23,795 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 14:57:23,795 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 14:57:23,795 INFO L87 Difference]: Start difference. First operand 6579 states and 9649 transitions. cyclomatic complexity: 3074 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:24,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:24,086 INFO L93 Difference]: Finished difference Result 12589 states and 18436 transitions. [2024-11-13 14:57:24,087 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12589 states and 18436 transitions. [2024-11-13 14:57:24,155 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12360 [2024-11-13 14:57:24,207 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12589 states to 12589 states and 18436 transitions. [2024-11-13 14:57:24,207 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12589 [2024-11-13 14:57:24,221 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12589 [2024-11-13 14:57:24,222 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12589 states and 18436 transitions. [2024-11-13 14:57:24,240 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:24,240 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12589 states and 18436 transitions. [2024-11-13 14:57:24,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12589 states and 18436 transitions. [2024-11-13 14:57:24,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12589 to 12585. [2024-11-13 14:57:24,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12585 states, 12585 states have (on average 1.464600715137068) internal successors, (18432), 12584 states have internal predecessors, (18432), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:24,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12585 states to 12585 states and 18432 transitions. [2024-11-13 14:57:24,543 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12585 states and 18432 transitions. [2024-11-13 14:57:24,543 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 14:57:24,544 INFO L424 stractBuchiCegarLoop]: Abstraction has 12585 states and 18432 transitions. [2024-11-13 14:57:24,544 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 14:57:24,544 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12585 states and 18432 transitions. [2024-11-13 14:57:24,586 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12360 [2024-11-13 14:57:24,586 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:24,586 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:24,589 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:24,589 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:24,589 INFO L745 eck$LassoCheckResult]: Stem: 81731#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 81732#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 82596#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 82597#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 83253#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 83254#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82264#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82052#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81441#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81442#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 82708#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 82811#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 83343#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 83344#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 82189#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 82190#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 82735#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 82659#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 82226#L1201 assume !(0 == ~M_E~0); 82227#L1201-2 assume !(0 == ~T1_E~0); 83129#L1206-1 assume !(0 == ~T2_E~0); 83110#L1211-1 assume !(0 == ~T3_E~0); 83111#L1216-1 assume !(0 == ~T4_E~0); 82033#L1221-1 assume !(0 == ~T5_E~0); 82034#L1226-1 assume !(0 == ~T6_E~0); 81657#L1231-1 assume !(0 == ~T7_E~0); 81658#L1236-1 assume !(0 == ~T8_E~0); 83159#L1241-1 assume !(0 == ~T9_E~0); 82074#L1246-1 assume !(0 == ~T10_E~0); 82075#L1251-1 assume !(0 == ~T11_E~0); 82224#L1256-1 assume !(0 == ~T12_E~0); 81450#L1261-1 assume !(0 == ~E_M~0); 81451#L1266-1 assume !(0 == ~E_1~0); 83321#L1271-1 assume !(0 == ~E_2~0); 82795#L1276-1 assume !(0 == ~E_3~0); 82796#L1281-1 assume !(0 == ~E_4~0); 82749#L1286-1 assume !(0 == ~E_5~0); 81924#L1291-1 assume !(0 == ~E_6~0); 81925#L1296-1 assume !(0 == ~E_7~0); 82528#L1301-1 assume !(0 == ~E_8~0); 82529#L1306-1 assume !(0 == ~E_9~0); 83038#L1311-1 assume !(0 == ~E_10~0); 81875#L1316-1 assume !(0 == ~E_11~0); 81876#L1321-1 assume !(0 == ~E_12~0); 82548#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82549#L593 assume 1 == ~m_pc~0; 82701#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 81756#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82433#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 82434#L1492 assume !(0 != activate_threads_~tmp~1#1); 82759#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83074#L612 assume !(1 == ~t1_pc~0); 83075#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 83249#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82904#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81759#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 81760#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82205#L631 assume 1 == ~t2_pc~0; 82132#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 81532#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81533#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81889#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 82396#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81836#L650 assume !(1 == ~t3_pc~0); 81837#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 82574#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82879#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 81488#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 81489#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82728#L669 assume 1 == ~t4_pc~0; 82729#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 83120#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81572#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 81573#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 81694#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81935#L688 assume !(1 == ~t5_pc~0); 81713#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 81714#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 83293#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 82616#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 82617#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82744#L707 assume 1 == ~t6_pc~0; 83205#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 82365#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81877#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 81878#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 82687#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82225#L726 assume 1 == ~t7_pc~0; 82120#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 81800#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82893#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 83212#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 81562#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 81563#L745 assume !(1 == ~t8_pc~0); 82026#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 82046#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 83138#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 82442#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 82443#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82994#L764 assume 1 == ~t9_pc~0; 82223#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 82056#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81953#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 81954#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 81588#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 81589#L783 assume !(1 == ~t10_pc~0); 81644#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 81645#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 81843#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 82179#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 82180#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 83122#L802 assume 1 == ~t11_pc~0; 83100#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 81528#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 81529#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 82035#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 82036#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 82154#L821 assume !(1 == ~t12_pc~0); 82411#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 82520#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 81536#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 81537#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 83176#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82767#L1339 assume !(1 == ~M_E~0); 82768#L1339-2 assume !(1 == ~T1_E~0); 83217#L1344-1 assume !(1 == ~T2_E~0); 83218#L1349-1 assume !(1 == ~T3_E~0); 83683#L1354-1 assume !(1 == ~T4_E~0); 83682#L1359-1 assume !(1 == ~T5_E~0); 83681#L1364-1 assume !(1 == ~T6_E~0); 83680#L1369-1 assume !(1 == ~T7_E~0); 83679#L1374-1 assume !(1 == ~T8_E~0); 82543#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 82544#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 82656#L1389-1 assume !(1 == ~T11_E~0); 83165#L1394-1 assume !(1 == ~T12_E~0); 83166#L1399-1 assume !(1 == ~E_M~0); 83284#L1404-1 assume !(1 == ~E_1~0); 83285#L1409-1 assume !(1 == ~E_2~0); 83607#L1414-1 assume !(1 == ~E_3~0); 83604#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 83542#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 83540#L1429-1 assume !(1 == ~E_6~0); 83538#L1434-1 assume !(1 == ~E_7~0); 83536#L1439-1 assume !(1 == ~E_8~0); 83494#L1444-1 assume !(1 == ~E_9~0); 83458#L1449-1 assume !(1 == ~E_10~0); 83442#L1454-1 assume !(1 == ~E_11~0); 83432#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 83424#L1464-1 assume { :end_inline_reset_delta_events } true; 83417#L1810-2 [2024-11-13 14:57:24,590 INFO L747 eck$LassoCheckResult]: Loop: 83417#L1810-2 assume !false; 83413#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 83412#L1176-1 assume !false; 83411#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 83407#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 83397#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 83396#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 83394#L1003 assume !(0 != eval_~tmp~0#1); 83393#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 83392#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 83391#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 83390#L1201-5 assume !(0 == ~T1_E~0); 83388#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 83389#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 93791#L1216-3 assume !(0 == ~T4_E~0); 93790#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 93789#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 93788#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 93787#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 93786#L1241-3 assume !(0 == ~T9_E~0); 93785#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 93784#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 93783#L1256-3 assume !(0 == ~T12_E~0); 93782#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 93781#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 93780#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 93779#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 93778#L1281-3 assume !(0 == ~E_4~0); 93777#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 93776#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 93775#L1296-3 assume !(0 == ~E_7~0); 93256#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 93255#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 82401#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 82402#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 92933#L1321-3 assume !(0 == ~E_12~0); 92932#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92931#L593-42 assume 1 == ~m_pc~0; 92929#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 83385#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82191#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 82192#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 81664#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81665#L612-42 assume !(1 == ~t1_pc~0); 82643#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 83052#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 83351#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81757#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 81758#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82481#L631-42 assume 1 == ~t2_pc~0; 81515#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 81516#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82465#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 82346#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 82347#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81929#L650-42 assume 1 == ~t3_pc~0; 81480#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 81481#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82868#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82130#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 82131#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 92238#L669-42 assume 1 == ~t4_pc~0; 82416#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 81479#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82947#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82845#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 82742#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82743#L688-42 assume !(1 == ~t5_pc~0); 82827#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 83055#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82531#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 81692#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 81693#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 81508#L707-42 assume !(1 == ~t6_pc~0); 81509#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 83288#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81845#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 81846#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 82710#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82711#L726-42 assume 1 == ~t7_pc~0; 83003#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 83035#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82559#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 82406#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 82407#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 82523#L745-42 assume 1 == ~t8_pc~0; 82565#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 82566#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82731#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 81496#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 81497#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82251#L764-42 assume !(1 == ~t9_pc~0); 82385#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 82756#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 82757#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 81782#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 81783#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 81844#L783-42 assume !(1 == ~t10_pc~0); 81453#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 81454#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 82066#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 82722#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 83336#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 84048#L802-42 assume !(1 == ~t11_pc~0); 83919#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 83916#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 83913#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 83811#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 83809#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 83807#L821-42 assume 1 == ~t12_pc~0; 83805#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 83801#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 83799#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 83797#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 83795#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83793#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 83792#L1339-5 assume !(1 == ~T1_E~0); 83791#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 82776#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 83675#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 83673#L1359-3 assume !(1 == ~T5_E~0); 83671#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 83669#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 83667#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 83666#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 83662#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 83609#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 83608#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 83606#L1399-3 assume !(1 == ~E_M~0); 83603#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 83602#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 83601#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 83597#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 83593#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 83591#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 83589#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 83587#L1439-3 assume !(1 == ~E_8~0); 83585#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 83583#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 83581#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 83580#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 83578#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 83530#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 83522#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 83519#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 83517#L1829 assume !(0 == start_simulation_~tmp~3#1); 83514#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 83485#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 83477#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 83457#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 83454#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 83441#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 83431#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 83423#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 83417#L1810-2 [2024-11-13 14:57:24,590 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:24,591 INFO L85 PathProgramCache]: Analyzing trace with hash 1087243328, now seen corresponding path program 1 times [2024-11-13 14:57:24,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:24,591 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1033853983] [2024-11-13 14:57:24,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:24,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:24,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:24,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:24,703 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:24,703 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1033853983] [2024-11-13 14:57:24,703 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1033853983] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:24,703 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:24,703 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:57:24,703 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1402364575] [2024-11-13 14:57:24,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:24,704 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:24,704 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:24,704 INFO L85 PathProgramCache]: Analyzing trace with hash 1067374945, now seen corresponding path program 1 times [2024-11-13 14:57:24,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:24,705 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1999559071] [2024-11-13 14:57:24,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:24,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:24,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:24,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:24,791 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:24,792 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1999559071] [2024-11-13 14:57:24,792 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1999559071] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:24,792 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:24,792 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:24,792 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1291203533] [2024-11-13 14:57:24,792 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:24,792 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:24,793 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:24,793 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:57:24,793 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:57:24,793 INFO L87 Difference]: Start difference. First operand 12585 states and 18432 transitions. cyclomatic complexity: 5855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:25,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:25,140 INFO L93 Difference]: Finished difference Result 24792 states and 36094 transitions. [2024-11-13 14:57:25,140 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24792 states and 36094 transitions. [2024-11-13 14:57:25,268 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24552 [2024-11-13 14:57:25,390 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24792 states to 24792 states and 36094 transitions. [2024-11-13 14:57:25,390 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24792 [2024-11-13 14:57:25,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24792 [2024-11-13 14:57:25,421 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24792 states and 36094 transitions. [2024-11-13 14:57:25,463 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:25,463 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24792 states and 36094 transitions. [2024-11-13 14:57:25,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24792 states and 36094 transitions. [2024-11-13 14:57:25,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24792 to 24072. [2024-11-13 14:57:25,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24072 states, 24072 states have (on average 1.4572116982386174) internal successors, (35078), 24071 states have internal predecessors, (35078), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:26,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24072 states to 24072 states and 35078 transitions. [2024-11-13 14:57:26,020 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24072 states and 35078 transitions. [2024-11-13 14:57:26,020 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:57:26,021 INFO L424 stractBuchiCegarLoop]: Abstraction has 24072 states and 35078 transitions. [2024-11-13 14:57:26,021 INFO L331 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-13 14:57:26,021 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24072 states and 35078 transitions. [2024-11-13 14:57:26,101 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23832 [2024-11-13 14:57:26,101 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:26,101 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:26,104 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:26,104 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:26,105 INFO L745 eck$LassoCheckResult]: Stem: 119113#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 119114#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 120021#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 120022#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 120775#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 120776#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 119660#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 119442#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 118825#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 118826#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 120153#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 120259#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 120895#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 120896#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 119583#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 119584#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 120180#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 120094#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 119621#L1201 assume !(0 == ~M_E~0); 119622#L1201-2 assume !(0 == ~T1_E~0); 120626#L1206-1 assume !(0 == ~T2_E~0); 120598#L1211-1 assume !(0 == ~T3_E~0); 120599#L1216-1 assume !(0 == ~T4_E~0); 119421#L1221-1 assume !(0 == ~T5_E~0); 119422#L1226-1 assume !(0 == ~T6_E~0); 119037#L1231-1 assume !(0 == ~T7_E~0); 119038#L1236-1 assume !(0 == ~T8_E~0); 120670#L1241-1 assume !(0 == ~T9_E~0); 119463#L1246-1 assume !(0 == ~T10_E~0); 119464#L1251-1 assume !(0 == ~T11_E~0); 119619#L1256-1 assume !(0 == ~T12_E~0); 118833#L1261-1 assume !(0 == ~E_M~0); 118834#L1266-1 assume !(0 == ~E_1~0); 120863#L1271-1 assume !(0 == ~E_2~0); 120242#L1276-1 assume !(0 == ~E_3~0); 120243#L1281-1 assume !(0 == ~E_4~0); 120194#L1286-1 assume !(0 == ~E_5~0); 119308#L1291-1 assume !(0 == ~E_6~0); 119309#L1296-1 assume !(0 == ~E_7~0); 119951#L1301-1 assume !(0 == ~E_8~0); 119952#L1306-1 assume !(0 == ~E_9~0); 120509#L1311-1 assume !(0 == ~E_10~0); 119258#L1316-1 assume !(0 == ~E_11~0); 119259#L1321-1 assume !(0 == ~E_12~0); 119972#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 119973#L593 assume !(1 == ~m_pc~0); 119137#L593-2 is_master_triggered_~__retres1~0#1 := 0; 119138#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119846#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 119847#L1492 assume !(0 != activate_threads_~tmp~1#1); 120204#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 120558#L612 assume !(1 == ~t1_pc~0); 120559#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 120771#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 120361#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 119141#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 119142#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119600#L631 assume 1 == ~t2_pc~0; 119521#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 118914#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 118915#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 119272#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 119805#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 119217#L650 assume !(1 == ~t3_pc~0); 119218#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 119996#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 120334#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 118871#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 118872#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 120173#L669 assume 1 == ~t4_pc~0; 120174#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 120611#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 118954#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 118955#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 119074#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 119321#L688 assume !(1 == ~t5_pc~0); 119093#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 119094#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 120828#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 120045#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 120046#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 120187#L707 assume 1 == ~t6_pc~0; 120721#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 119771#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 119260#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 119261#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 120125#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 119620#L726 assume 1 == ~t7_pc~0; 119509#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 119182#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 120351#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 120727#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 118944#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 118945#L745 assume !(1 == ~t8_pc~0); 119414#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 119435#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 120636#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 119856#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 119857#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 120459#L764 assume 1 == ~t9_pc~0; 119618#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 119446#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 119337#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 119338#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 118970#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 118971#L783 assume !(1 == ~t10_pc~0); 119025#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 119026#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 119224#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 119572#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 119573#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 120614#L802 assume 1 == ~t11_pc~0; 120586#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 118911#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 118912#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 119423#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 119424#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 119544#L821 assume !(1 == ~t12_pc~0); 119821#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 119942#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 118918#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 118919#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 120683#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 120213#L1339 assume !(1 == ~M_E~0); 120214#L1339-2 assume !(1 == ~T1_E~0); 120731#L1344-1 assume !(1 == ~T2_E~0); 120732#L1349-1 assume !(1 == ~T3_E~0); 133187#L1354-1 assume !(1 == ~T4_E~0); 133186#L1359-1 assume !(1 == ~T5_E~0); 133185#L1364-1 assume !(1 == ~T6_E~0); 133184#L1369-1 assume !(1 == ~T7_E~0); 133180#L1374-1 assume !(1 == ~T8_E~0); 133177#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 133175#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 133174#L1389-1 assume !(1 == ~T11_E~0); 133173#L1394-1 assume !(1 == ~T12_E~0); 133172#L1399-1 assume !(1 == ~E_M~0); 133171#L1404-1 assume !(1 == ~E_1~0); 133170#L1409-1 assume !(1 == ~E_2~0); 133166#L1414-1 assume !(1 == ~E_3~0); 133163#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 133164#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 133747#L1429-1 assume !(1 == ~E_6~0); 133745#L1434-1 assume !(1 == ~E_7~0); 133744#L1439-1 assume !(1 == ~E_8~0); 133740#L1444-1 assume !(1 == ~E_9~0); 133738#L1449-1 assume !(1 == ~E_10~0); 133736#L1454-1 assume !(1 == ~E_11~0); 133735#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 120124#L1464-1 assume { :end_inline_reset_delta_events } true; 119271#L1810-2 [2024-11-13 14:57:26,105 INFO L747 eck$LassoCheckResult]: Loop: 119271#L1810-2 assume !false; 119752#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 119862#L1176-1 assume !false; 120292#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 119801#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 118952#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 120363#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 120579#L1003 assume !(0 != eval_~tmp~0#1); 119760#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 119472#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 119473#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 120232#L1201-5 assume !(0 == ~T1_E~0); 120233#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 120121#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 120122#L1216-3 assume !(0 == ~T4_E~0); 119717#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 119718#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 119293#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 119294#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 120973#L1241-3 assume !(0 == ~T9_E~0); 120974#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 120590#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 120591#L1256-3 assume !(0 == ~T12_E~0); 119232#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 119233#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 119285#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 119286#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 119691#L1281-3 assume !(0 == ~E_4~0); 119692#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 120276#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 120277#L1296-3 assume !(0 == ~E_7~0); 120881#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 120882#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 119811#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 119812#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 119234#L1321-3 assume !(0 == ~E_12~0); 119235#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 120653#L593-42 assume !(1 == ~m_pc~0); 120654#L593-44 is_master_triggered_~__retres1~0#1 := 0; 120971#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119585#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 119586#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 119044#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119045#L612-42 assume !(1 == ~t1_pc~0); 120529#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 120530#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 120919#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 120920#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 120969#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 120970#L631-42 assume 1 == ~t2_pc~0; 118898#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 118899#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 119887#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 119888#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 120928#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 120929#L650-42 assume !(1 == ~t3_pc~0); 118865#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 118864#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 120315#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 120316#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 120782#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 120783#L669-42 assume 1 == ~t4_pc~0; 119826#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 118862#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 120408#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 120290#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 120185#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 120186#L688-42 assume !(1 == ~t5_pc~0); 120275#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 120764#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 119955#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 119072#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 119073#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 118891#L707-42 assume 1 == ~t6_pc~0; 118893#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 120823#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 119226#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 119227#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 120155#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 120156#L726-42 assume 1 == ~t7_pc~0; 142228#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 142225#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 142223#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 142221#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 142219#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 142218#L745-42 assume 1 == ~t8_pc~0; 142216#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 142215#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 142214#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 142213#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 142212#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 142211#L764-42 assume 1 == ~t9_pc~0; 120937#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 120201#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 120202#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 120931#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 142207#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 142205#L783-42 assume !(1 == ~t10_pc~0); 142202#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 142201#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 142200#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 142198#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 142197#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 142196#L802-42 assume 1 == ~t11_pc~0; 142194#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 118977#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 118978#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 118924#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 118925#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 120210#L821-42 assume 1 == ~t12_pc~0; 120211#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 119496#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 119937#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 119938#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 142180#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 142178#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 142177#L1339-5 assume !(1 == ~T1_E~0); 142176#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 120223#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 142172#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 142170#L1359-3 assume !(1 == ~T5_E~0); 142168#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 142167#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 142166#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 142164#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 119318#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 142163#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 142162#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 142153#L1399-3 assume !(1 == ~E_M~0); 120714#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 120668#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 120669#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 120752#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 120399#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 119186#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 119187#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 120181#L1439-3 assume !(1 == ~E_8~0); 119115#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 119116#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 119239#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 120177#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 120178#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 119772#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 119018#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 119220#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 119221#L1829 assume !(0 == start_simulation_~tmp~3#1); 118999#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 119000#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 119860#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 118904#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 118905#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 120195#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 120674#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 119270#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 119271#L1810-2 [2024-11-13 14:57:26,106 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:26,106 INFO L85 PathProgramCache]: Analyzing trace with hash 1374703233, now seen corresponding path program 1 times [2024-11-13 14:57:26,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:26,106 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [116671284] [2024-11-13 14:57:26,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:26,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:26,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:26,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:26,304 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:26,304 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [116671284] [2024-11-13 14:57:26,304 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [116671284] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:26,304 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:26,304 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:57:26,304 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1794355347] [2024-11-13 14:57:26,305 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:26,305 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:26,305 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:26,305 INFO L85 PathProgramCache]: Analyzing trace with hash -1561760928, now seen corresponding path program 1 times [2024-11-13 14:57:26,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:26,306 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [532103885] [2024-11-13 14:57:26,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:26,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:26,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:26,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:26,379 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:26,379 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [532103885] [2024-11-13 14:57:26,379 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [532103885] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:26,379 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:26,379 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:26,379 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2052968474] [2024-11-13 14:57:26,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:26,380 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:26,380 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:26,380 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 14:57:26,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 14:57:26,381 INFO L87 Difference]: Start difference. First operand 24072 states and 35078 transitions. cyclomatic complexity: 11022 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:26,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:26,917 INFO L93 Difference]: Finished difference Result 24723 states and 35729 transitions. [2024-11-13 14:57:26,918 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24723 states and 35729 transitions. [2024-11-13 14:57:27,026 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24480 [2024-11-13 14:57:27,131 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24723 states to 24723 states and 35729 transitions. [2024-11-13 14:57:27,131 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24723 [2024-11-13 14:57:27,158 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24723 [2024-11-13 14:57:27,158 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24723 states and 35729 transitions. [2024-11-13 14:57:27,188 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:27,188 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24723 states and 35729 transitions. [2024-11-13 14:57:27,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24723 states and 35729 transitions. [2024-11-13 14:57:27,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24723 to 24723. [2024-11-13 14:57:27,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24723 states, 24723 states have (on average 1.4451725114266067) internal successors, (35729), 24722 states have internal predecessors, (35729), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:27,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24723 states to 24723 states and 35729 transitions. [2024-11-13 14:57:27,736 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24723 states and 35729 transitions. [2024-11-13 14:57:27,737 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 14:57:27,737 INFO L424 stractBuchiCegarLoop]: Abstraction has 24723 states and 35729 transitions. [2024-11-13 14:57:27,737 INFO L331 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-13 14:57:27,737 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24723 states and 35729 transitions. [2024-11-13 14:57:27,817 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24480 [2024-11-13 14:57:27,818 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:27,818 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:27,820 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:27,821 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:27,821 INFO L745 eck$LassoCheckResult]: Stem: 167915#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 167916#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 168794#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 168795#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 169480#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 169481#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 168459#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 168241#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 167629#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 167630#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 168923#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 169029#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 169582#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 169583#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 168381#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 168382#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 168951#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 168868#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 168419#L1201 assume !(0 == ~M_E~0); 168420#L1201-2 assume !(0 == ~T1_E~0); 169362#L1206-1 assume !(0 == ~T2_E~0); 169336#L1211-1 assume !(0 == ~T3_E~0); 169337#L1216-1 assume !(0 == ~T4_E~0); 168220#L1221-1 assume !(0 == ~T5_E~0); 168221#L1226-1 assume !(0 == ~T6_E~0); 167841#L1231-1 assume !(0 == ~T7_E~0); 167842#L1236-1 assume !(0 == ~T8_E~0); 169391#L1241-1 assume !(0 == ~T9_E~0); 168262#L1246-1 assume !(0 == ~T10_E~0); 168263#L1251-1 assume !(0 == ~T11_E~0); 168417#L1256-1 assume !(0 == ~T12_E~0); 167637#L1261-1 assume !(0 == ~E_M~0); 167638#L1266-1 assume !(0 == ~E_1~0); 169559#L1271-1 assume !(0 == ~E_2~0); 169011#L1276-1 assume !(0 == ~E_3~0); 169012#L1281-1 assume !(0 == ~E_4~0); 168964#L1286-1 assume !(0 == ~E_5~0); 168111#L1291-1 assume !(0 == ~E_6~0); 168112#L1296-1 assume !(0 == ~E_7~0); 168726#L1301-1 assume !(0 == ~E_8~0); 168727#L1306-1 assume !(0 == ~E_9~0); 169260#L1311-1 assume !(0 == ~E_10~0); 168060#L1316-1 assume !(0 == ~E_11~0); 168061#L1321-1 assume !(0 == ~E_12~0); 168746#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 168747#L593 assume !(1 == ~m_pc~0); 167939#L593-2 is_master_triggered_~__retres1~0#1 := 0; 167940#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 168627#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 168628#L1492 assume !(0 != activate_threads_~tmp~1#1); 168975#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 169300#L612 assume !(1 == ~t1_pc~0); 169301#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 169575#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 169121#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 167943#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 167944#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 168398#L631 assume 1 == ~t2_pc~0; 168320#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 167718#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 167719#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 168074#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 168590#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 168019#L650 assume !(1 == ~t3_pc~0); 168020#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 168769#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 169097#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 167675#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 167676#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 168944#L669 assume 1 == ~t4_pc~0; 168945#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 169349#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 167758#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 167759#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 167878#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 168122#L688 assume !(1 == ~t5_pc~0); 167897#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 167898#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 169527#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 168817#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 168818#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 168958#L707 assume 1 == ~t6_pc~0; 169434#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 168558#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 168062#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 168063#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 168897#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 168418#L726 assume 1 == ~t7_pc~0; 168308#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 167984#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 169110#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 169440#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 167748#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 167749#L745 assume !(1 == ~t8_pc~0); 168213#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 168234#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 169371#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 168636#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 168637#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 169213#L764 assume 1 == ~t9_pc~0; 168416#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 168245#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 168140#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 168141#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 167774#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 167775#L783 assume !(1 == ~t10_pc~0); 167829#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 167830#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 168026#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 168370#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 168371#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 169352#L802 assume 1 == ~t11_pc~0; 169325#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 167715#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 167716#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 168222#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 168223#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 168343#L821 assume !(1 == ~t12_pc~0); 168604#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 168717#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 167722#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 167723#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 169402#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 168983#L1339 assume !(1 == ~M_E~0); 168984#L1339-2 assume !(1 == ~T1_E~0); 169444#L1344-1 assume !(1 == ~T2_E~0); 169445#L1349-1 assume !(1 == ~T3_E~0); 168739#L1354-1 assume !(1 == ~T4_E~0); 168740#L1359-1 assume !(1 == ~T5_E~0); 169189#L1364-1 assume !(1 == ~T6_E~0); 169578#L1369-1 assume !(1 == ~T7_E~0); 172981#L1374-1 assume !(1 == ~T8_E~0); 172978#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 172976#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 172974#L1389-1 assume !(1 == ~T11_E~0); 172972#L1394-1 assume !(1 == ~T12_E~0); 172970#L1399-1 assume !(1 == ~E_M~0); 172968#L1404-1 assume !(1 == ~E_1~0); 168269#L1409-1 assume !(1 == ~E_2~0); 168270#L1414-1 assume !(1 == ~E_3~0); 169503#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 172909#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 172907#L1429-1 assume !(1 == ~E_6~0); 172618#L1434-1 assume !(1 == ~E_7~0); 172604#L1439-1 assume !(1 == ~E_8~0); 172532#L1444-1 assume !(1 == ~E_9~0); 172511#L1449-1 assume !(1 == ~E_10~0); 172498#L1454-1 assume !(1 == ~E_11~0); 172487#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 172479#L1464-1 assume { :end_inline_reset_delta_events } true; 172472#L1810-2 [2024-11-13 14:57:27,822 INFO L747 eck$LassoCheckResult]: Loop: 172472#L1810-2 assume !false; 172468#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 172467#L1176-1 assume !false; 172466#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 172459#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 172446#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 172442#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 172437#L1003 assume !(0 != eval_~tmp~0#1); 172438#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 173704#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 173702#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 173699#L1201-5 assume !(0 == ~T1_E~0); 173697#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 173695#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 173693#L1216-3 assume !(0 == ~T4_E~0); 173691#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 173689#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 173686#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 173684#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 173682#L1241-3 assume !(0 == ~T9_E~0); 173680#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 173678#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 173676#L1256-3 assume !(0 == ~T12_E~0); 173674#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 173672#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 173670#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 173668#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 173666#L1281-3 assume !(0 == ~E_4~0); 173664#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 173662#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 173660#L1296-3 assume !(0 == ~E_7~0); 173659#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 173658#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 173657#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 173656#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 173655#L1321-3 assume !(0 == ~E_12~0); 173654#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 173653#L593-42 assume !(1 == ~m_pc~0); 173652#L593-44 is_master_triggered_~__retres1~0#1 := 0; 173651#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 173650#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 173648#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 173647#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 173646#L612-42 assume 1 == ~t1_pc~0; 173644#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 173643#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 173642#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 173639#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 173637#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 173635#L631-42 assume 1 == ~t2_pc~0; 173632#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 173630#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 173628#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 173626#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 173624#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 173622#L650-42 assume !(1 == ~t3_pc~0); 173619#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 173617#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 173615#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 173613#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 173611#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 173609#L669-42 assume 1 == ~t4_pc~0; 173606#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 173604#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 173602#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 173598#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 173596#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 173594#L688-42 assume !(1 == ~t5_pc~0); 173591#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 173588#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 173586#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 173584#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 173581#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 173579#L707-42 assume 1 == ~t6_pc~0; 173576#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 173574#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 173572#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 173570#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 173569#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 173568#L726-42 assume 1 == ~t7_pc~0; 173566#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 173565#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 173564#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 173563#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 173562#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 173561#L745-42 assume 1 == ~t8_pc~0; 173558#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 173556#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 173554#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 173552#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 173550#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 173547#L764-42 assume 1 == ~t9_pc~0; 173544#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 173542#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 173540#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 173538#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 173536#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 173535#L783-42 assume !(1 == ~t10_pc~0); 173531#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 173529#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 173527#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 173525#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 173523#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 173521#L802-42 assume 1 == ~t11_pc~0; 173516#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 173514#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 173511#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 173509#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 173507#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 173505#L821-42 assume !(1 == ~t12_pc~0); 173502#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 173500#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 173499#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 173496#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 173494#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 173492#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 173490#L1339-5 assume !(1 == ~T1_E~0); 173488#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 168992#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 173484#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 173482#L1359-3 assume !(1 == ~T5_E~0); 173480#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 173478#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 173476#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 172819#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 172816#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 172814#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 172812#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 172810#L1399-3 assume !(1 == ~E_M~0); 172808#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 172806#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 172804#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 172800#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 172797#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 172795#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 172793#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 172791#L1439-3 assume !(1 == ~E_8~0); 172789#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 172787#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 172785#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 172784#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 172781#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 172772#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 172763#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 172761#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 172757#L1829 assume !(0 == start_simulation_~tmp~3#1); 172754#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 172609#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 172603#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 172531#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 172510#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 172497#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 172486#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 172478#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 172472#L1810-2 [2024-11-13 14:57:27,822 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:27,822 INFO L85 PathProgramCache]: Analyzing trace with hash -1568878845, now seen corresponding path program 1 times [2024-11-13 14:57:27,823 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:27,823 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [762889253] [2024-11-13 14:57:27,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:27,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:27,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:27,902 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:27,902 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:27,902 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [762889253] [2024-11-13 14:57:27,902 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [762889253] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:27,903 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:27,903 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:57:27,903 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1998678556] [2024-11-13 14:57:27,903 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:27,903 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:27,904 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:27,904 INFO L85 PathProgramCache]: Analyzing trace with hash 1134649248, now seen corresponding path program 1 times [2024-11-13 14:57:27,904 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:27,904 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [837482431] [2024-11-13 14:57:27,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:27,904 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:27,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:27,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:27,975 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:27,975 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [837482431] [2024-11-13 14:57:27,975 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [837482431] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:27,975 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:27,975 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:27,975 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1165724827] [2024-11-13 14:57:27,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:27,976 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:27,977 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:27,977 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:57:27,977 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:57:27,977 INFO L87 Difference]: Start difference. First operand 24723 states and 35729 transitions. cyclomatic complexity: 11022 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:28,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:28,498 INFO L93 Difference]: Finished difference Result 47474 states and 68320 transitions. [2024-11-13 14:57:28,498 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47474 states and 68320 transitions. [2024-11-13 14:57:28,817 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 47184 [2024-11-13 14:57:29,106 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47474 states to 47474 states and 68320 transitions. [2024-11-13 14:57:29,106 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 47474 [2024-11-13 14:57:29,177 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 47474 [2024-11-13 14:57:29,177 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47474 states and 68320 transitions. [2024-11-13 14:57:29,266 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:29,266 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47474 states and 68320 transitions. [2024-11-13 14:57:29,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47474 states and 68320 transitions. [2024-11-13 14:57:30,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47474 to 47442. [2024-11-13 14:57:30,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47442 states, 47442 states have (on average 1.4393996880401332) internal successors, (68288), 47441 states have internal predecessors, (68288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:30,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47442 states to 47442 states and 68288 transitions. [2024-11-13 14:57:30,297 INFO L240 hiAutomatonCegarLoop]: Abstraction has 47442 states and 68288 transitions. [2024-11-13 14:57:30,297 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:57:30,298 INFO L424 stractBuchiCegarLoop]: Abstraction has 47442 states and 68288 transitions. [2024-11-13 14:57:30,298 INFO L331 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-13 14:57:30,298 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47442 states and 68288 transitions. [2024-11-13 14:57:30,593 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 47152 [2024-11-13 14:57:30,593 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:30,593 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:30,596 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:30,596 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:30,597 INFO L745 eck$LassoCheckResult]: Stem: 240119#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 240120#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 240987#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 240988#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 241630#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 241631#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 240653#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 240437#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 239833#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 239834#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 241102#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 241210#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 241708#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 241709#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 240571#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 240572#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 241131#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 241053#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 240611#L1201 assume !(0 == ~M_E~0); 240612#L1201-2 assume !(0 == ~T1_E~0); 241520#L1206-1 assume !(0 == ~T2_E~0); 241500#L1211-1 assume !(0 == ~T3_E~0); 241501#L1216-1 assume !(0 == ~T4_E~0); 240419#L1221-1 assume !(0 == ~T5_E~0); 240420#L1226-1 assume !(0 == ~T6_E~0); 240045#L1231-1 assume !(0 == ~T7_E~0); 240046#L1236-1 assume !(0 == ~T8_E~0); 241547#L1241-1 assume !(0 == ~T9_E~0); 240460#L1246-1 assume !(0 == ~T10_E~0); 240461#L1251-1 assume !(0 == ~T11_E~0); 240609#L1256-1 assume !(0 == ~T12_E~0); 239841#L1261-1 assume !(0 == ~E_M~0); 239842#L1266-1 assume !(0 == ~E_1~0); 241690#L1271-1 assume !(0 == ~E_2~0); 241191#L1276-1 assume !(0 == ~E_3~0); 241192#L1281-1 assume !(0 == ~E_4~0); 241143#L1286-1 assume !(0 == ~E_5~0); 240311#L1291-1 assume !(0 == ~E_6~0); 240312#L1296-1 assume !(0 == ~E_7~0); 240923#L1301-1 assume !(0 == ~E_8~0); 240924#L1306-1 assume !(0 == ~E_9~0); 241430#L1311-1 assume !(0 == ~E_10~0); 240262#L1316-1 assume !(0 == ~E_11~0); 240263#L1321-1 assume !(0 == ~E_12~0); 240942#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 240943#L593 assume !(1 == ~m_pc~0); 240143#L593-2 is_master_triggered_~__retres1~0#1 := 0; 240144#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 240820#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 240821#L1492 assume !(0 != activate_threads_~tmp~1#1); 241154#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 241467#L612 assume !(1 == ~t1_pc~0); 241468#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 241702#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 241300#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 240147#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 240148#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 240588#L631 assume !(1 == ~t2_pc~0); 240589#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 239921#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 239922#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 240276#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 240781#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 240225#L650 assume !(1 == ~t3_pc~0); 240226#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 240965#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 241277#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 239879#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 239880#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 241124#L669 assume 1 == ~t4_pc~0; 241125#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 241509#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 239965#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 239966#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 240082#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 240322#L688 assume !(1 == ~t5_pc~0); 240101#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 240102#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 241664#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 241010#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 241011#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 241141#L707 assume 1 == ~t6_pc~0; 241590#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 240750#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 240264#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 240265#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 241084#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 240610#L726 assume 1 == ~t7_pc~0; 240506#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 240188#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 241290#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 241596#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 239951#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 239952#L745 assume !(1 == ~t8_pc~0); 240412#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 240431#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 241526#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 240829#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 240830#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 241386#L764 assume 1 == ~t9_pc~0; 240608#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 240441#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 240340#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 240341#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 239977#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 239978#L783 assume !(1 == ~t10_pc~0); 240032#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 240033#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 240230#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 240566#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 240567#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 241510#L802 assume 1 == ~t11_pc~0; 241491#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 239918#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 239919#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 240421#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 240422#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 240536#L821 assume !(1 == ~t12_pc~0); 240795#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 240914#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 239927#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 239928#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 241560#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 241163#L1339 assume !(1 == ~M_E~0); 241164#L1339-2 assume !(1 == ~T1_E~0); 241599#L1344-1 assume !(1 == ~T2_E~0); 241600#L1349-1 assume !(1 == ~T3_E~0); 258359#L1354-1 assume !(1 == ~T4_E~0); 258358#L1359-1 assume !(1 == ~T5_E~0); 258357#L1364-1 assume !(1 == ~T6_E~0); 258356#L1369-1 assume !(1 == ~T7_E~0); 258355#L1374-1 assume !(1 == ~T8_E~0); 258353#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 258354#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 268062#L1389-1 assume !(1 == ~T11_E~0); 268061#L1394-1 assume !(1 == ~T12_E~0); 268060#L1399-1 assume !(1 == ~E_M~0); 268059#L1404-1 assume !(1 == ~E_1~0); 268056#L1409-1 assume !(1 == ~E_2~0); 268054#L1414-1 assume !(1 == ~E_3~0); 268051#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 268052#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 272119#L1429-1 assume !(1 == ~E_6~0); 272105#L1434-1 assume !(1 == ~E_7~0); 272103#L1439-1 assume !(1 == ~E_8~0); 272101#L1444-1 assume !(1 == ~E_9~0); 272099#L1449-1 assume !(1 == ~E_10~0); 272097#L1454-1 assume !(1 == ~E_11~0); 272095#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 241081#L1464-1 assume { :end_inline_reset_delta_events } true; 240275#L1810-2 [2024-11-13 14:57:30,597 INFO L747 eck$LassoCheckResult]: Loop: 240275#L1810-2 assume !false; 240734#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 240837#L1176-1 assume !false; 241244#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 240780#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 239959#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 241301#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 241488#L1003 assume !(0 != eval_~tmp~0#1); 241581#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 287273#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 287272#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 287271#L1201-5 assume !(0 == ~T1_E~0); 287270#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 287269#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 287268#L1216-3 assume !(0 == ~T4_E~0); 287266#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 287264#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 287262#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 287260#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 287258#L1241-3 assume !(0 == ~T9_E~0); 287255#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 287253#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 287251#L1256-3 assume !(0 == ~T12_E~0); 287249#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 287247#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 287245#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 287242#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 287240#L1281-3 assume !(0 == ~E_4~0); 287238#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 287236#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 287234#L1296-3 assume !(0 == ~E_7~0); 287232#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 287229#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 287227#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 287225#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 286176#L1321-3 assume !(0 == ~E_12~0); 286094#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 284310#L593-42 assume !(1 == ~m_pc~0); 284307#L593-44 is_master_triggered_~__retres1~0#1 := 0; 284301#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 284297#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 284293#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 284289#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 284285#L612-42 assume 1 == ~t1_pc~0; 284280#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 284271#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 284267#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 284264#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 284262#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 240870#L631-42 assume !(1 == ~t2_pc~0); 240871#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 286915#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 286914#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 286913#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 286912#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 286911#L650-42 assume !(1 == ~t3_pc~0); 286909#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 286323#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 286322#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 285960#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 241635#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 241578#L669-42 assume 1 == ~t4_pc~0; 240800#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 239870#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 241340#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 241242#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 241136#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 241137#L688-42 assume !(1 == ~t5_pc~0); 241226#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 241448#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 240926#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 240080#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 240081#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 239899#L707-42 assume 1 == ~t6_pc~0; 239901#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 241659#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 240232#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 240233#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 241104#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 241105#L726-42 assume 1 == ~t7_pc~0; 241395#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 241427#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 240953#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 240790#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 240791#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 240918#L745-42 assume 1 == ~t8_pc~0; 240955#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 240956#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 241127#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 239887#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 239888#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 240637#L764-42 assume !(1 == ~t9_pc~0); 240770#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 241150#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 241151#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 240170#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 240171#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 240231#L783-42 assume 1 == ~t10_pc~0; 239843#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 239845#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 240449#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 241119#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 241693#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 241330#L802-42 assume !(1 == ~t11_pc~0); 240383#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 239984#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 239985#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 239931#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 239932#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 241160#L821-42 assume !(1 == ~t12_pc~0); 240490#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 240491#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 240910#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 240911#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 240839#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 240827#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 240828#L1339-5 assume !(1 == ~T1_E~0); 241012#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 241123#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 240500#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 240501#L1359-3 assume !(1 == ~T5_E~0); 241133#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 241685#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 241571#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 240319#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 240320#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 240498#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 240499#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 240721#L1399-3 assume !(1 == ~E_M~0); 241584#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 241545#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 241546#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 241616#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 241333#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 240192#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 240193#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 241132#L1439-3 assume !(1 == ~E_8~0); 240121#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 240122#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 240243#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 241128#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 241129#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 240751#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 240025#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 240223#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 240224#L1829 assume !(0 == start_simulation_~tmp~3#1); 240006#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 240007#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 240833#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 239911#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 239912#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 241144#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 241704#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 240274#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 240275#L1810-2 [2024-11-13 14:57:30,598 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:30,598 INFO L85 PathProgramCache]: Analyzing trace with hash -451693884, now seen corresponding path program 1 times [2024-11-13 14:57:30,599 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:30,599 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [385767704] [2024-11-13 14:57:30,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:30,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:30,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:30,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:30,693 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:30,693 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [385767704] [2024-11-13 14:57:30,694 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [385767704] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:30,694 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:30,694 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:57:30,694 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [855739418] [2024-11-13 14:57:30,694 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:30,694 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:30,695 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:30,695 INFO L85 PathProgramCache]: Analyzing trace with hash -342070750, now seen corresponding path program 1 times [2024-11-13 14:57:30,695 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:30,695 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1087059469] [2024-11-13 14:57:30,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:30,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:30,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:30,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:30,767 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:30,767 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1087059469] [2024-11-13 14:57:30,768 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1087059469] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:30,768 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:30,768 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:30,768 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [856758518] [2024-11-13 14:57:30,768 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:30,768 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:30,769 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:30,769 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:57:30,769 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:57:30,769 INFO L87 Difference]: Start difference. First operand 47442 states and 68288 transitions. cyclomatic complexity: 20878 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:31,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:31,311 INFO L93 Difference]: Finished difference Result 91201 states and 130769 transitions. [2024-11-13 14:57:31,311 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91201 states and 130769 transitions. [2024-11-13 14:57:31,819 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 90784 [2024-11-13 14:57:32,164 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91201 states to 91201 states and 130769 transitions. [2024-11-13 14:57:32,164 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 91201 [2024-11-13 14:57:32,376 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 91201 [2024-11-13 14:57:32,377 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91201 states and 130769 transitions. [2024-11-13 14:57:32,439 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:32,439 INFO L218 hiAutomatonCegarLoop]: Abstraction has 91201 states and 130769 transitions. [2024-11-13 14:57:32,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91201 states and 130769 transitions. [2024-11-13 14:57:33,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91201 to 91137. [2024-11-13 14:57:33,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91137 states, 91137 states have (on average 1.434159561978121) internal successors, (130705), 91136 states have internal predecessors, (130705), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:33,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91137 states to 91137 states and 130705 transitions. [2024-11-13 14:57:33,870 INFO L240 hiAutomatonCegarLoop]: Abstraction has 91137 states and 130705 transitions. [2024-11-13 14:57:33,871 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:57:33,871 INFO L424 stractBuchiCegarLoop]: Abstraction has 91137 states and 130705 transitions. [2024-11-13 14:57:33,871 INFO L331 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-13 14:57:33,871 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91137 states and 130705 transitions. [2024-11-13 14:57:34,389 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 90720 [2024-11-13 14:57:34,389 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:34,389 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:34,392 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:34,392 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:34,393 INFO L745 eck$LassoCheckResult]: Stem: 378768#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 378769#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 379639#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 379640#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 380302#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 380303#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 379304#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 379087#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 378483#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 378484#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 379761#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 379869#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 380404#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 380405#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 379224#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 379225#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 379789#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 379707#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 379264#L1201 assume !(0 == ~M_E~0); 379265#L1201-2 assume !(0 == ~T1_E~0); 380184#L1206-1 assume !(0 == ~T2_E~0); 380161#L1211-1 assume !(0 == ~T3_E~0); 380162#L1216-1 assume !(0 == ~T4_E~0); 379068#L1221-1 assume !(0 == ~T5_E~0); 379069#L1226-1 assume !(0 == ~T6_E~0); 378694#L1231-1 assume !(0 == ~T7_E~0); 378695#L1236-1 assume !(0 == ~T8_E~0); 380214#L1241-1 assume !(0 == ~T9_E~0); 379108#L1246-1 assume !(0 == ~T10_E~0); 379109#L1251-1 assume !(0 == ~T11_E~0); 379262#L1256-1 assume !(0 == ~T12_E~0); 378491#L1261-1 assume !(0 == ~E_M~0); 378492#L1266-1 assume !(0 == ~E_1~0); 380380#L1271-1 assume !(0 == ~E_2~0); 379850#L1276-1 assume !(0 == ~E_3~0); 379851#L1281-1 assume !(0 == ~E_4~0); 379801#L1286-1 assume !(0 == ~E_5~0); 378959#L1291-1 assume !(0 == ~E_6~0); 378960#L1296-1 assume !(0 == ~E_7~0); 379573#L1301-1 assume !(0 == ~E_8~0); 379574#L1306-1 assume !(0 == ~E_9~0); 380087#L1311-1 assume !(0 == ~E_10~0); 378910#L1316-1 assume !(0 == ~E_11~0); 378911#L1321-1 assume !(0 == ~E_12~0); 379592#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 379593#L593 assume !(1 == ~m_pc~0); 378792#L593-2 is_master_triggered_~__retres1~0#1 := 0; 378793#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 379472#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 379473#L1492 assume !(0 != activate_threads_~tmp~1#1); 379813#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 380123#L612 assume !(1 == ~t1_pc~0); 380124#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 380394#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 379956#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 378796#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 378797#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 379240#L631 assume !(1 == ~t2_pc~0); 379241#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 378570#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 378571#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 378924#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 379434#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 378871#L650 assume !(1 == ~t3_pc~0); 378872#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 379617#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 379933#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 378529#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 378530#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 379783#L669 assume !(1 == ~t4_pc~0); 379784#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 380171#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 378610#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 378611#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 378731#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 378970#L688 assume !(1 == ~t5_pc~0); 378750#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 378751#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 380345#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 379660#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 379661#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 379796#L707 assume 1 == ~t6_pc~0; 380257#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 379403#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 378912#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 378913#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 379737#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 379263#L726 assume 1 == ~t7_pc~0; 379155#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 378836#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 379945#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 380265#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 378600#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 378601#L745 assume !(1 == ~t8_pc~0); 379062#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 379081#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 380192#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 379481#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 379482#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 380041#L764 assume 1 == ~t9_pc~0; 379261#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 379091#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 378987#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 378988#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 378626#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 378627#L783 assume !(1 == ~t10_pc~0); 378681#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 378682#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 378878#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 379214#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 379215#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 380173#L802 assume 1 == ~t11_pc~0; 380150#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 378567#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 378568#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 379070#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 379071#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 379188#L821 assume !(1 == ~t12_pc~0); 379449#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 379564#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 378574#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 378575#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 380226#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 379821#L1339 assume !(1 == ~M_E~0); 379822#L1339-2 assume !(1 == ~T1_E~0); 380269#L1344-1 assume !(1 == ~T2_E~0); 380270#L1349-1 assume !(1 == ~T3_E~0); 379585#L1354-1 assume !(1 == ~T4_E~0); 379586#L1359-1 assume !(1 == ~T5_E~0); 380015#L1364-1 assume !(1 == ~T6_E~0); 379021#L1369-1 assume !(1 == ~T7_E~0); 379022#L1374-1 assume !(1 == ~T8_E~0); 379988#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 387946#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 387945#L1389-1 assume !(1 == ~T11_E~0); 387842#L1394-1 assume !(1 == ~T12_E~0); 387840#L1399-1 assume !(1 == ~E_M~0); 387838#L1404-1 assume !(1 == ~E_1~0); 387836#L1409-1 assume !(1 == ~E_2~0); 387835#L1414-1 assume !(1 == ~E_3~0); 387708#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 387617#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 387615#L1429-1 assume !(1 == ~E_6~0); 387613#L1434-1 assume !(1 == ~E_7~0); 387526#L1439-1 assume !(1 == ~E_8~0); 387524#L1444-1 assume !(1 == ~E_9~0); 387499#L1449-1 assume !(1 == ~E_10~0); 387489#L1454-1 assume !(1 == ~E_11~0); 387451#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 380264#L1464-1 assume { :end_inline_reset_delta_events } true; 400220#L1810-2 [2024-11-13 14:57:34,393 INFO L747 eck$LassoCheckResult]: Loop: 400220#L1810-2 assume !false; 400090#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 400088#L1176-1 assume !false; 400075#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 400017#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 400006#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 400004#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 400001#L1003 assume !(0 != eval_~tmp~0#1); 400002#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 403243#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 403237#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 403233#L1201-5 assume !(0 == ~T1_E~0); 403229#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 403224#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 403220#L1216-3 assume !(0 == ~T4_E~0); 403216#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 403211#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 403206#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 403201#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 403195#L1241-3 assume !(0 == ~T9_E~0); 403191#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 403186#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 403179#L1256-3 assume !(0 == ~T12_E~0); 403174#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 403169#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 403163#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 403159#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 403155#L1281-3 assume !(0 == ~E_4~0); 403149#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 403144#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 403139#L1296-3 assume !(0 == ~E_7~0); 403133#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 403129#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 403125#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 403120#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 403116#L1321-3 assume !(0 == ~E_12~0); 403110#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 384219#L593-42 assume !(1 == ~m_pc~0); 384220#L593-44 is_master_triggered_~__retres1~0#1 := 0; 384209#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 384210#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 384205#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 384206#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 384196#L612-42 assume !(1 == ~t1_pc~0); 384197#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 384190#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 384191#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 384184#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 384183#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 384172#L631-42 assume !(1 == ~t2_pc~0); 384173#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 384163#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 384164#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 384155#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 384156#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 384148#L650-42 assume !(1 == ~t3_pc~0); 384149#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 384140#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 384141#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 384134#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 384135#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 384127#L669-42 assume !(1 == ~t4_pc~0); 384128#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 384121#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 384122#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 384113#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 384114#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 384105#L688-42 assume !(1 == ~t5_pc~0); 384107#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 384097#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 384098#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 384091#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 384092#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 384084#L707-42 assume !(1 == ~t6_pc~0); 384085#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 384077#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 384078#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 384071#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 384072#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 384063#L726-42 assume !(1 == ~t7_pc~0); 384065#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 384056#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 384057#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 384051#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 384048#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 384046#L745-42 assume !(1 == ~t8_pc~0); 384044#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 384041#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 384038#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 384034#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 384030#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 384027#L764-42 assume 1 == ~t9_pc~0; 384023#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 384021#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 384018#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 384016#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 384013#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 384009#L783-42 assume 1 == ~t10_pc~0; 384011#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 401428#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 401425#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 401423#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 401421#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 401419#L802-42 assume 1 == ~t11_pc~0; 401416#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 401414#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 401411#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 401409#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 401407#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 401405#L821-42 assume !(1 == ~t12_pc~0); 401402#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 401400#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 401397#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 401395#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 401393#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 401391#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 401389#L1339-5 assume !(1 == ~T1_E~0); 401387#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 383963#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 401383#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 401381#L1359-3 assume !(1 == ~T5_E~0); 401379#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 401377#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 401375#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 401373#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 399270#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 401371#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 401369#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 401367#L1399-3 assume !(1 == ~E_M~0); 401365#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 401363#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 401361#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 401359#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 383930#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 401357#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 401355#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 401353#L1439-3 assume !(1 == ~E_8~0); 401351#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 401349#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 401347#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 401341#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 387990#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 400916#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 400898#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 400888#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 400877#L1829 assume !(0 == start_simulation_~tmp~3#1); 400872#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 400239#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 400233#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 400231#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 400229#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 400227#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 400225#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 400222#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 400220#L1810-2 [2024-11-13 14:57:34,393 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:34,393 INFO L85 PathProgramCache]: Analyzing trace with hash 1008300037, now seen corresponding path program 1 times [2024-11-13 14:57:34,394 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:34,394 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1792473143] [2024-11-13 14:57:34,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:34,395 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:34,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:34,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:34,474 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:34,475 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1792473143] [2024-11-13 14:57:34,475 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1792473143] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:34,475 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:34,475 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:57:34,475 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [232100339] [2024-11-13 14:57:34,475 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:34,476 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:34,476 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:34,476 INFO L85 PathProgramCache]: Analyzing trace with hash -673999257, now seen corresponding path program 1 times [2024-11-13 14:57:34,476 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:34,476 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [356867586] [2024-11-13 14:57:34,476 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:34,476 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:34,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:34,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:34,661 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:34,661 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [356867586] [2024-11-13 14:57:34,661 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [356867586] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:34,662 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:34,662 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:34,662 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [192912551] [2024-11-13 14:57:34,662 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:34,662 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:34,663 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:34,663 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:57:34,663 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:57:34,663 INFO L87 Difference]: Start difference. First operand 91137 states and 130705 transitions. cyclomatic complexity: 39632 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:35,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:35,615 INFO L93 Difference]: Finished difference Result 175200 states and 250358 transitions. [2024-11-13 14:57:35,615 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 175200 states and 250358 transitions. [2024-11-13 14:57:36,472 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 174464 [2024-11-13 14:57:37,342 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 175200 states to 175200 states and 250358 transitions. [2024-11-13 14:57:37,342 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 175200 [2024-11-13 14:57:37,441 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 175200 [2024-11-13 14:57:37,441 INFO L73 IsDeterministic]: Start isDeterministic. Operand 175200 states and 250358 transitions. [2024-11-13 14:57:37,583 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:37,584 INFO L218 hiAutomatonCegarLoop]: Abstraction has 175200 states and 250358 transitions. [2024-11-13 14:57:37,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175200 states and 250358 transitions. [2024-11-13 14:57:39,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175200 to 175072. [2024-11-13 14:57:39,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 175072 states, 175072 states have (on average 1.4292976603911534) internal successors, (250230), 175071 states have internal predecessors, (250230), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:40,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175072 states to 175072 states and 250230 transitions. [2024-11-13 14:57:40,255 INFO L240 hiAutomatonCegarLoop]: Abstraction has 175072 states and 250230 transitions. [2024-11-13 14:57:40,256 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:57:40,256 INFO L424 stractBuchiCegarLoop]: Abstraction has 175072 states and 250230 transitions. [2024-11-13 14:57:40,256 INFO L331 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-13 14:57:40,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 175072 states and 250230 transitions. [2024-11-13 14:57:41,206 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 174336 [2024-11-13 14:57:41,206 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:41,207 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:41,209 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:41,209 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:41,209 INFO L745 eck$LassoCheckResult]: Stem: 645112#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 645113#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 646011#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 646012#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 646792#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 646793#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 645653#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 645435#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 644827#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 644828#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 646141#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 646262#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 646914#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 646915#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 645573#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 645574#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 646170#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 646087#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 645612#L1201 assume !(0 == ~M_E~0); 645613#L1201-2 assume !(0 == ~T1_E~0); 646638#L1206-1 assume !(0 == ~T2_E~0); 646606#L1211-1 assume !(0 == ~T3_E~0); 646607#L1216-1 assume !(0 == ~T4_E~0); 645416#L1221-1 assume !(0 == ~T5_E~0); 645417#L1226-1 assume !(0 == ~T6_E~0); 645038#L1231-1 assume !(0 == ~T7_E~0); 645039#L1236-1 assume !(0 == ~T8_E~0); 646680#L1241-1 assume !(0 == ~T9_E~0); 645459#L1246-1 assume !(0 == ~T10_E~0); 645460#L1251-1 assume !(0 == ~T11_E~0); 645610#L1256-1 assume !(0 == ~T12_E~0); 644835#L1261-1 assume !(0 == ~E_M~0); 644836#L1266-1 assume !(0 == ~E_1~0); 646882#L1271-1 assume !(0 == ~E_2~0); 646239#L1276-1 assume !(0 == ~E_3~0); 646240#L1281-1 assume !(0 == ~E_4~0); 646187#L1286-1 assume !(0 == ~E_5~0); 645306#L1291-1 assume !(0 == ~E_6~0); 645307#L1296-1 assume !(0 == ~E_7~0); 645939#L1301-1 assume !(0 == ~E_8~0); 645940#L1306-1 assume !(0 == ~E_9~0); 646521#L1311-1 assume !(0 == ~E_10~0); 645257#L1316-1 assume !(0 == ~E_11~0); 645258#L1321-1 assume !(0 == ~E_12~0); 645961#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 645962#L593 assume !(1 == ~m_pc~0); 645136#L593-2 is_master_triggered_~__retres1~0#1 := 0; 645137#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 645834#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 645835#L1492 assume !(0 != activate_threads_~tmp~1#1); 646201#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 646566#L612 assume !(1 == ~t1_pc~0); 646567#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 646904#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 646369#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 645140#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 645141#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 645590#L631 assume !(1 == ~t2_pc~0); 645591#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 644915#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 644916#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 645271#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 645791#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 645217#L650 assume !(1 == ~t3_pc~0); 645218#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 645987#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 646338#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 644873#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 644874#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 646164#L669 assume !(1 == ~t4_pc~0); 646165#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 646626#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 644959#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 644960#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 645075#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 645318#L688 assume !(1 == ~t5_pc~0); 645094#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 645095#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 646840#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 646037#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 646038#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 646183#L707 assume !(1 == ~t6_pc~0); 646447#L707-2 is_transmit6_triggered_~__retres1~6#1 := 0; 645756#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 645259#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 645260#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 646119#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 645611#L726 assume 1 == ~t7_pc~0; 645505#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 645180#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 646357#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 646740#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 644945#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 644946#L745 assume !(1 == ~t8_pc~0); 645409#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 645428#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 646649#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 645843#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 645844#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 646466#L764 assume 1 == ~t9_pc~0; 645609#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 645439#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 645334#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 645335#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 644971#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 644972#L783 assume !(1 == ~t10_pc~0); 645026#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 645027#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 645222#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 645568#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 645569#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 646627#L802 assume 1 == ~t11_pc~0; 646596#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 644911#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 644912#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 645418#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 645419#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 645536#L821 assume !(1 == ~t12_pc~0); 645808#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 645926#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 644921#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 644922#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 646695#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 646209#L1339 assume !(1 == ~M_E~0); 646210#L1339-2 assume !(1 == ~T1_E~0); 646744#L1344-1 assume !(1 == ~T2_E~0); 646745#L1349-1 assume !(1 == ~T3_E~0); 661088#L1354-1 assume !(1 == ~T4_E~0); 661086#L1359-1 assume !(1 == ~T5_E~0); 661083#L1364-1 assume !(1 == ~T6_E~0); 661081#L1369-1 assume !(1 == ~T7_E~0); 661079#L1374-1 assume !(1 == ~T8_E~0); 661077#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 646083#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 646084#L1389-1 assume !(1 == ~T11_E~0); 646685#L1394-1 assume !(1 == ~T12_E~0); 646686#L1399-1 assume !(1 == ~E_M~0); 658795#L1404-1 assume !(1 == ~E_1~0); 658791#L1409-1 assume !(1 == ~E_2~0); 658789#L1414-1 assume !(1 == ~E_3~0); 658786#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 658787#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 658813#L1429-1 assume !(1 == ~E_6~0); 658811#L1434-1 assume !(1 == ~E_7~0); 658809#L1439-1 assume !(1 == ~E_8~0); 658808#L1444-1 assume !(1 == ~E_9~0); 658807#L1449-1 assume !(1 == ~E_10~0); 658805#L1454-1 assume !(1 == ~E_11~0); 658803#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 646738#L1464-1 assume { :end_inline_reset_delta_events } true; 702976#L1810-2 [2024-11-13 14:57:41,209 INFO L747 eck$LassoCheckResult]: Loop: 702976#L1810-2 assume !false; 702965#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 702956#L1176-1 assume !false; 702947#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 694216#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 694205#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 694203#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 694200#L1003 assume !(0 != eval_~tmp~0#1); 694201#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 704499#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 704497#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 704495#L1201-5 assume !(0 == ~T1_E~0); 704493#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 704491#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 704489#L1216-3 assume !(0 == ~T4_E~0); 704487#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 704485#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 704483#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 704481#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 704479#L1241-3 assume !(0 == ~T9_E~0); 704477#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 704475#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 704473#L1256-3 assume !(0 == ~T12_E~0); 704471#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 704469#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 704467#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 704465#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 704461#L1281-3 assume !(0 == ~E_4~0); 704459#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 704457#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 704455#L1296-3 assume !(0 == ~E_7~0); 704452#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 704450#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 704448#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 704446#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 704444#L1321-3 assume !(0 == ~E_12~0); 704442#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 704440#L593-42 assume !(1 == ~m_pc~0); 704438#L593-44 is_master_triggered_~__retres1~0#1 := 0; 704436#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 704435#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 704434#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 704433#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 704431#L612-42 assume !(1 == ~t1_pc~0); 704428#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 704427#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 704425#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 704423#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 704420#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 704418#L631-42 assume !(1 == ~t2_pc~0); 704416#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 704414#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 704412#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 704410#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 704408#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 704406#L650-42 assume !(1 == ~t3_pc~0); 704403#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 704401#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 704399#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 704396#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 704394#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 704392#L669-42 assume !(1 == ~t4_pc~0); 704390#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 704388#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 704386#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 704384#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 704381#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 704379#L688-42 assume !(1 == ~t5_pc~0); 704376#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 704374#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 704372#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 704370#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 704368#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 704366#L707-42 assume !(1 == ~t6_pc~0); 704364#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 704362#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 704360#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 704297#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 704289#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 704280#L726-42 assume 1 == ~t7_pc~0; 704270#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 704261#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 704254#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 704247#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 704239#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 704232#L745-42 assume 1 == ~t8_pc~0; 704224#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 704216#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 704208#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 704201#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 704193#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 704185#L764-42 assume !(1 == ~t9_pc~0); 704178#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 704169#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 704162#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 704155#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 704147#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 704140#L783-42 assume !(1 == ~t10_pc~0); 704131#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 704122#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 704113#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 704105#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 704096#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 704087#L802-42 assume 1 == ~t11_pc~0; 704078#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 704069#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 704060#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 704052#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 704043#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 704034#L821-42 assume 1 == ~t12_pc~0; 704026#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 704016#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 704007#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 703999#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 703989#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 703980#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 703972#L1339-5 assume !(1 == ~T1_E~0); 703963#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 659865#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 703945#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 703934#L1359-3 assume !(1 == ~T5_E~0); 703925#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 703917#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 703909#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 703900#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 703891#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 703882#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 703874#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 703867#L1399-3 assume !(1 == ~E_M~0); 703859#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 703851#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 703844#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 703835#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 699765#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 703819#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 703810#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 703803#L1439-3 assume !(1 == ~E_8~0); 703797#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 703789#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 703784#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 703780#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 659811#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 703628#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 703615#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 703610#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 703605#L1829 assume !(0 == start_simulation_~tmp~3#1); 703603#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 703096#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 703090#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 703088#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 703086#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 703085#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 703014#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 703000#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 702976#L1810-2 [2024-11-13 14:57:41,210 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:41,211 INFO L85 PathProgramCache]: Analyzing trace with hash 2145928902, now seen corresponding path program 1 times [2024-11-13 14:57:41,211 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:41,211 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1587866018] [2024-11-13 14:57:41,211 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:41,211 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:41,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:41,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:41,319 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:41,319 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1587866018] [2024-11-13 14:57:41,320 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1587866018] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:41,320 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:41,320 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:41,320 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [619762983] [2024-11-13 14:57:41,320 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:41,321 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:41,321 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:41,322 INFO L85 PathProgramCache]: Analyzing trace with hash -262053978, now seen corresponding path program 1 times [2024-11-13 14:57:41,322 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:41,322 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2002758364] [2024-11-13 14:57:41,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:41,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:41,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:41,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:41,387 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:41,387 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2002758364] [2024-11-13 14:57:41,388 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2002758364] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:41,388 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:41,388 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:41,388 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1055647115] [2024-11-13 14:57:41,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:41,388 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:41,388 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:41,389 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 14:57:41,389 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 14:57:41,389 INFO L87 Difference]: Start difference. First operand 175072 states and 250230 transitions. cyclomatic complexity: 75286 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:43,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:57:43,718 INFO L93 Difference]: Finished difference Result 495454 states and 702928 transitions. [2024-11-13 14:57:43,718 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 495454 states and 702928 transitions. [2024-11-13 14:57:46,613 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 492672 [2024-11-13 14:57:48,267 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 495454 states to 495454 states and 702928 transitions. [2024-11-13 14:57:48,267 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 495454 [2024-11-13 14:57:48,459 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 495454 [2024-11-13 14:57:48,459 INFO L73 IsDeterministic]: Start isDeterministic. Operand 495454 states and 702928 transitions. [2024-11-13 14:57:48,600 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:57:48,600 INFO L218 hiAutomatonCegarLoop]: Abstraction has 495454 states and 702928 transitions. [2024-11-13 14:57:48,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 495454 states and 702928 transitions. [2024-11-13 14:57:52,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 495454 to 489182. [2024-11-13 14:57:54,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 489182 states, 489182 states have (on average 1.4196761123671762) internal successors, (694480), 489181 states have internal predecessors, (694480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:57:55,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 489182 states to 489182 states and 694480 transitions. [2024-11-13 14:57:55,492 INFO L240 hiAutomatonCegarLoop]: Abstraction has 489182 states and 694480 transitions. [2024-11-13 14:57:55,492 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 14:57:55,493 INFO L424 stractBuchiCegarLoop]: Abstraction has 489182 states and 694480 transitions. [2024-11-13 14:57:55,493 INFO L331 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-13 14:57:55,493 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 489182 states and 694480 transitions. [2024-11-13 14:57:57,380 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 487168 [2024-11-13 14:57:57,380 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:57:57,380 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:57:57,381 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:57,382 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:57:57,382 INFO L745 eck$LassoCheckResult]: Stem: 1315652#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1315653#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1316536#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1316537#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1317245#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 1317246#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1316187#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1315973#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1315363#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1315364#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1316663#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1316769#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1317341#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1317342#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1316109#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1316110#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1316690#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1316605#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1316148#L1201 assume !(0 == ~M_E~0); 1316149#L1201-2 assume !(0 == ~T1_E~0); 1317116#L1206-1 assume !(0 == ~T2_E~0); 1317093#L1211-1 assume !(0 == ~T3_E~0); 1317094#L1216-1 assume !(0 == ~T4_E~0); 1315955#L1221-1 assume !(0 == ~T5_E~0); 1315956#L1226-1 assume !(0 == ~T6_E~0); 1315574#L1231-1 assume !(0 == ~T7_E~0); 1315575#L1236-1 assume !(0 == ~T8_E~0); 1317155#L1241-1 assume !(0 == ~T9_E~0); 1315997#L1246-1 assume !(0 == ~T10_E~0); 1315998#L1251-1 assume !(0 == ~T11_E~0); 1316146#L1256-1 assume !(0 == ~T12_E~0); 1315371#L1261-1 assume !(0 == ~E_M~0); 1315372#L1266-1 assume !(0 == ~E_1~0); 1317316#L1271-1 assume !(0 == ~E_2~0); 1316750#L1276-1 assume !(0 == ~E_3~0); 1316751#L1281-1 assume !(0 == ~E_4~0); 1316704#L1286-1 assume !(0 == ~E_5~0); 1315843#L1291-1 assume !(0 == ~E_6~0); 1315844#L1296-1 assume !(0 == ~E_7~0); 1316466#L1301-1 assume !(0 == ~E_8~0); 1316467#L1306-1 assume !(0 == ~E_9~0); 1317021#L1311-1 assume !(0 == ~E_10~0); 1315794#L1316-1 assume !(0 == ~E_11~0); 1315795#L1321-1 assume !(0 == ~E_12~0); 1316486#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1316487#L593 assume !(1 == ~m_pc~0); 1315676#L593-2 is_master_triggered_~__retres1~0#1 := 0; 1315677#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1316363#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1316364#L1492 assume !(0 != activate_threads_~tmp~1#1); 1316715#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1317060#L612 assume !(1 == ~t1_pc~0); 1317061#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1317330#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1316866#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1315680#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 1315681#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1316126#L631 assume !(1 == ~t2_pc~0); 1316127#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1315451#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1315452#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1315808#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 1316321#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1315758#L650 assume !(1 == ~t3_pc~0); 1315759#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1316902#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1316841#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1315408#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 1315409#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1316684#L669 assume !(1 == ~t4_pc~0); 1316685#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1317103#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1315495#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1315496#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 1315611#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1315853#L688 assume !(1 == ~t5_pc~0); 1315630#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1315631#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1317287#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1316559#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 1316560#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1316702#L707 assume !(1 == ~t6_pc~0); 1316945#L707-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1316288#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1315796#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1315797#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 1316645#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1316147#L726 assume !(1 == ~t7_pc~0); 1315719#L726-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1315720#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1316856#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1317205#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 1315481#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1315482#L745 assume !(1 == ~t8_pc~0); 1315946#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1315967#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1317123#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1316371#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1316372#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1316968#L764 assume 1 == ~t9_pc~0; 1316145#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1315977#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1315871#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1315872#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 1315507#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1315508#L783 assume !(1 == ~t10_pc~0); 1315562#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1315563#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1315762#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1316104#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 1316105#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1317104#L802 assume 1 == ~t11_pc~0; 1317083#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1315448#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1315449#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1315957#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 1315958#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1316074#L821 assume !(1 == ~t12_pc~0); 1316339#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1316455#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1315457#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1315458#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 1317166#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1316723#L1339 assume !(1 == ~M_E~0); 1316724#L1339-2 assume !(1 == ~T1_E~0); 1317208#L1344-1 assume !(1 == ~T2_E~0); 1317209#L1349-1 assume !(1 == ~T3_E~0); 1493533#L1354-1 assume !(1 == ~T4_E~0); 1493531#L1359-1 assume !(1 == ~T5_E~0); 1493529#L1364-1 assume !(1 == ~T6_E~0); 1493527#L1369-1 assume !(1 == ~T7_E~0); 1493525#L1374-1 assume !(1 == ~T8_E~0); 1493521#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1493522#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1517089#L1389-1 assume !(1 == ~T11_E~0); 1517088#L1394-1 assume !(1 == ~T12_E~0); 1517087#L1399-1 assume !(1 == ~E_M~0); 1517086#L1404-1 assume !(1 == ~E_1~0); 1517085#L1409-1 assume !(1 == ~E_2~0); 1517084#L1414-1 assume !(1 == ~E_3~0); 1517083#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1517082#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1517068#L1429-1 assume !(1 == ~E_6~0); 1517066#L1434-1 assume !(1 == ~E_7~0); 1517064#L1439-1 assume !(1 == ~E_8~0); 1517062#L1444-1 assume !(1 == ~E_9~0); 1517060#L1449-1 assume !(1 == ~E_10~0); 1517058#L1454-1 assume !(1 == ~E_11~0); 1516954#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 1516952#L1464-1 assume { :end_inline_reset_delta_events } true; 1516949#L1810-2 [2024-11-13 14:57:57,382 INFO L747 eck$LassoCheckResult]: Loop: 1516949#L1810-2 assume !false; 1516696#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1515165#L1176-1 assume !false; 1515164#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1514821#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1514810#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1514808#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1514805#L1003 assume !(0 != eval_~tmp~0#1); 1514806#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1519943#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1519941#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1519939#L1201-5 assume !(0 == ~T1_E~0); 1519937#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1519935#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1519933#L1216-3 assume !(0 == ~T4_E~0); 1519931#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1519929#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1519926#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1519924#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1519922#L1241-3 assume !(0 == ~T9_E~0); 1519920#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1519918#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1519916#L1256-3 assume !(0 == ~T12_E~0); 1519913#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1519911#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1519909#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1519907#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1519905#L1281-3 assume !(0 == ~E_4~0); 1519903#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1519900#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1519898#L1296-3 assume !(0 == ~E_7~0); 1519896#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1519894#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1519892#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1519890#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1519887#L1321-3 assume !(0 == ~E_12~0); 1519885#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1519883#L593-42 assume !(1 == ~m_pc~0); 1519881#L593-44 is_master_triggered_~__retres1~0#1 := 0; 1519879#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1519877#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1519874#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1519872#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1519870#L612-42 assume 1 == ~t1_pc~0; 1519868#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1519869#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1519954#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1519858#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1519856#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1519854#L631-42 assume !(1 == ~t2_pc~0); 1519853#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1519850#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1519846#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1519842#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1519837#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1519835#L650-42 assume !(1 == ~t3_pc~0); 1519833#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1519832#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1519831#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1519830#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1519829#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1519815#L669-42 assume !(1 == ~t4_pc~0); 1519813#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1519811#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1519808#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1519806#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1519804#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1519802#L688-42 assume !(1 == ~t5_pc~0); 1519799#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1519797#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1519795#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1519793#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1519791#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1519789#L707-42 assume !(1 == ~t6_pc~0); 1519787#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1519785#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1519783#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1519781#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 1519779#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1519777#L726-42 assume !(1 == ~t7_pc~0); 1519775#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1519631#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1519623#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1519614#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1519577#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1519315#L745-42 assume !(1 == ~t8_pc~0); 1519306#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 1519181#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1519178#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1519176#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1519174#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1519171#L764-42 assume !(1 == ~t9_pc~0); 1519169#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1519166#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1519164#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1519162#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1519161#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1519157#L783-42 assume 1 == ~t10_pc~0; 1519152#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1519149#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1519146#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1519144#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1519142#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1519140#L802-42 assume !(1 == ~t11_pc~0); 1519137#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1519134#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1519119#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1519108#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1519097#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1519091#L821-42 assume 1 == ~t12_pc~0; 1519085#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1519080#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1519076#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1519071#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1519065#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1519061#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1519056#L1339-5 assume !(1 == ~T1_E~0); 1517181#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1495216#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1517176#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1517173#L1359-3 assume !(1 == ~T5_E~0); 1517171#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1517169#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1517167#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1517165#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1517161#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1517159#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1517155#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1517154#L1399-3 assume !(1 == ~E_M~0); 1517152#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1517150#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1517148#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1517146#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1517142#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1517138#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1517136#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1517134#L1439-3 assume !(1 == ~E_8~0); 1517132#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1517130#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1517128#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1517126#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1517122#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1517107#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1517098#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1517094#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1517092#L1829 assume !(0 == start_simulation_~tmp~3#1); 1517090#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1517073#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1517067#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1517065#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1517063#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1517061#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1517059#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1516951#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 1516949#L1810-2 [2024-11-13 14:57:57,382 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:57,383 INFO L85 PathProgramCache]: Analyzing trace with hash -1572109753, now seen corresponding path program 1 times [2024-11-13 14:57:57,383 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:57,383 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1053755434] [2024-11-13 14:57:57,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:57,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:57,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:57,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:57,470 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:57,470 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1053755434] [2024-11-13 14:57:57,470 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1053755434] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:57,470 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:57,470 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:57:57,470 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1244038825] [2024-11-13 14:57:57,470 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:57,471 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:57:57,472 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:57:57,472 INFO L85 PathProgramCache]: Analyzing trace with hash 92346917, now seen corresponding path program 1 times [2024-11-13 14:57:57,472 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:57:57,472 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1444776620] [2024-11-13 14:57:57,472 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:57:57,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:57:57,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:57:57,524 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:57:57,524 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:57:57,524 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1444776620] [2024-11-13 14:57:57,525 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1444776620] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:57:57,525 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:57:57,525 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:57:57,526 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1120115012] [2024-11-13 14:57:57,526 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:57:57,526 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:57:57,526 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:57:57,526 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 14:57:57,526 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 14:57:57,527 INFO L87 Difference]: Start difference. First operand 489182 states and 694480 transitions. cyclomatic complexity: 205554 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:58:00,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:58:00,157 INFO L93 Difference]: Finished difference Result 502049 states and 707347 transitions. [2024-11-13 14:58:00,157 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 502049 states and 707347 transitions. [2024-11-13 14:58:02,632 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 500032