./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.01.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.01.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 13:20:51,957 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 13:20:52,086 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 13:20:52,099 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 13:20:52,100 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 13:20:52,147 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 13:20:52,149 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 13:20:52,149 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 13:20:52,150 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 13:20:52,150 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 13:20:52,152 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 13:20:52,153 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 13:20:52,153 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 13:20:52,153 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 13:20:52,153 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 13:20:52,153 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 13:20:52,155 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 13:20:52,155 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 13:20:52,155 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 13:20:52,155 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 13:20:52,155 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 13:20:52,156 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 13:20:52,156 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 13:20:52,156 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 13:20:52,156 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 13:20:52,156 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 13:20:52,156 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 13:20:52,156 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 13:20:52,157 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 13:20:52,157 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 13:20:52,157 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 13:20:52,157 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 13:20:52,157 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 13:20:52,157 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 13:20:52,157 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 13:20:52,158 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 13:20:52,158 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 13:20:52,158 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 13:20:52,158 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 13:20:52,158 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe [2024-11-13 13:20:52,532 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 13:20:52,544 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 13:20:52,546 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 13:20:52,548 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 13:20:52,549 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 13:20:52,550 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/transmitter.01.cil.c Unable to find full path for "g++" [2024-11-13 13:20:54,802 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 13:20:55,240 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 13:20:55,243 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/sv-benchmarks/c/systemc/transmitter.01.cil.c [2024-11-13 13:20:55,256 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/data/b0d42673b/cd62c8012ccf4c19b71488d2f68e31c8/FLAG6ee4e8158 [2024-11-13 13:20:55,280 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/data/b0d42673b/cd62c8012ccf4c19b71488d2f68e31c8 [2024-11-13 13:20:55,284 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 13:20:55,286 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 13:20:55,289 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 13:20:55,289 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 13:20:55,295 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 13:20:55,296 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 01:20:55" (1/1) ... [2024-11-13 13:20:55,298 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@38e74021 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:20:55, skipping insertion in model container [2024-11-13 13:20:55,302 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 01:20:55" (1/1) ... [2024-11-13 13:20:55,342 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 13:20:55,638 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 13:20:55,651 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 13:20:55,689 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 13:20:55,710 INFO L204 MainTranslator]: Completed translation [2024-11-13 13:20:55,711 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:20:55 WrapperNode [2024-11-13 13:20:55,711 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 13:20:55,713 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 13:20:55,713 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 13:20:55,713 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 13:20:55,722 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:20:55" (1/1) ... [2024-11-13 13:20:55,731 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:20:55" (1/1) ... [2024-11-13 13:20:55,778 INFO L138 Inliner]: procedures = 30, calls = 34, calls flagged for inlining = 29, calls inlined = 35, statements flattened = 356 [2024-11-13 13:20:55,778 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 13:20:55,783 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 13:20:55,783 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 13:20:55,783 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 13:20:55,795 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:20:55" (1/1) ... [2024-11-13 13:20:55,795 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:20:55" (1/1) ... [2024-11-13 13:20:55,798 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:20:55" (1/1) ... [2024-11-13 13:20:55,824 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 13:20:55,829 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:20:55" (1/1) ... [2024-11-13 13:20:55,829 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:20:55" (1/1) ... [2024-11-13 13:20:55,838 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:20:55" (1/1) ... [2024-11-13 13:20:55,850 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:20:55" (1/1) ... [2024-11-13 13:20:55,853 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:20:55" (1/1) ... [2024-11-13 13:20:55,856 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:20:55" (1/1) ... [2024-11-13 13:20:55,862 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 13:20:55,863 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 13:20:55,863 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 13:20:55,863 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 13:20:55,867 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:20:55" (1/1) ... [2024-11-13 13:20:55,877 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:20:55,895 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:20:55,910 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:20:55,918 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 13:20:55,944 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 13:20:55,944 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 13:20:55,945 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 13:20:55,945 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 13:20:56,022 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 13:20:56,024 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 13:20:56,563 INFO L? ?]: Removed 60 outVars from TransFormulas that were not future-live. [2024-11-13 13:20:56,563 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 13:20:56,580 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 13:20:56,580 INFO L316 CfgBuilder]: Removed 5 assume(true) statements. [2024-11-13 13:20:56,581 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:20:56 BoogieIcfgContainer [2024-11-13 13:20:56,581 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 13:20:56,582 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 13:20:56,582 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 13:20:56,589 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 13:20:56,590 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:20:56,590 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 01:20:55" (1/3) ... [2024-11-13 13:20:56,591 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1fa3ae86 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 01:20:56, skipping insertion in model container [2024-11-13 13:20:56,592 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:20:56,592 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:20:55" (2/3) ... [2024-11-13 13:20:56,592 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1fa3ae86 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 01:20:56, skipping insertion in model container [2024-11-13 13:20:56,592 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:20:56,593 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:20:56" (3/3) ... [2024-11-13 13:20:56,594 INFO L333 chiAutomizerObserver]: Analyzing ICFG transmitter.01.cil.c [2024-11-13 13:20:56,661 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 13:20:56,662 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 13:20:56,662 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 13:20:56,662 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 13:20:56,662 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 13:20:56,662 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 13:20:56,663 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 13:20:56,663 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 13:20:56,670 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 136 states, 135 states have (on average 1.511111111111111) internal successors, (204), 135 states have internal predecessors, (204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:20:56,695 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 103 [2024-11-13 13:20:56,695 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:20:56,695 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:20:56,704 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:20:56,704 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:20:56,704 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 13:20:56,705 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 136 states, 135 states have (on average 1.511111111111111) internal successors, (204), 135 states have internal predecessors, (204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:20:56,717 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 103 [2024-11-13 13:20:56,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:20:56,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:20:56,722 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:20:56,722 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:20:56,734 INFO L745 eck$LassoCheckResult]: Stem: 31#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 48#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 134#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13#L161true assume !(1 == ~m_i~0);~m_st~0 := 2; 5#L161-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 80#L166-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 89#L250true assume !(0 == ~M_E~0); 108#L250-2true assume !(0 == ~T1_E~0); 39#L255-1true assume !(0 == ~E_1~0); 81#L260-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55#L115true assume !(1 == ~m_pc~0); 59#L115-2true is_master_triggered_~__retres1~0#1 := 0; 69#L126true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8#is_master_triggered_returnLabel#1true activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 66#L300true assume !(0 != activate_threads_~tmp~1#1); 107#L300-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121#L134true assume 1 == ~t1_pc~0; 109#L135true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 57#L145true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10#L308true assume !(0 != activate_threads_~tmp___0~0#1); 62#L308-2true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60#L273true assume !(1 == ~M_E~0); 113#L273-2true assume !(1 == ~T1_E~0); 102#L278-1true assume !(1 == ~E_1~0); 72#L283-1true assume { :end_inline_reset_delta_events } true; 58#L404-2true [2024-11-13 13:20:56,737 INFO L747 eck$LassoCheckResult]: Loop: 58#L404-2true assume !false; 82#L405true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 96#L225-1true assume !true; 85#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 117#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 120#L250-3true assume 0 == ~M_E~0;~M_E~0 := 1; 98#L250-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 104#L255-3true assume 0 == ~E_1~0;~E_1~0 := 1; 6#L260-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49#L115-6true assume 1 == ~m_pc~0; 116#L116-2true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 135#L126-2true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54#is_master_triggered_returnLabel#3true activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 74#L300-6true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 118#L300-8true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 133#L134-6true assume !(1 == ~t1_pc~0); 32#L134-8true is_transmit1_triggered_~__retres1~1#1 := 0; 53#L145-2true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 125#is_transmit1_triggered_returnLabel#3true activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 50#L308-6true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7#L308-8true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 130#L273-3true assume 1 == ~M_E~0;~M_E~0 := 2; 45#L273-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 33#L278-3true assume !(1 == ~E_1~0); 95#L283-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 76#L179-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 114#L191-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 100#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 19#L423true assume !(0 == start_simulation_~tmp~3#1); 18#L423-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 22#L179-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 73#L191-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 37#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 16#L378true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 17#L385true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 136#stop_simulation_returnLabel#1true start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 44#L436true assume !(0 != start_simulation_~tmp___0~1#1); 58#L404-2true [2024-11-13 13:20:56,743 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:20:56,744 INFO L85 PathProgramCache]: Analyzing trace with hash 920294251, now seen corresponding path program 1 times [2024-11-13 13:20:56,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:20:56,755 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1303656721] [2024-11-13 13:20:56,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:20:56,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:20:56,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:20:57,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:20:57,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:20:57,022 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1303656721] [2024-11-13 13:20:57,023 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1303656721] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:20:57,027 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:20:57,027 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:20:57,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1972612481] [2024-11-13 13:20:57,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:20:57,036 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:20:57,037 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:20:57,037 INFO L85 PathProgramCache]: Analyzing trace with hash 1273781740, now seen corresponding path program 1 times [2024-11-13 13:20:57,038 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:20:57,038 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [265394880] [2024-11-13 13:20:57,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:20:57,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:20:57,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:20:57,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:20:57,106 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:20:57,107 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [265394880] [2024-11-13 13:20:57,107 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [265394880] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:20:57,107 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:20:57,107 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:20:57,107 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1830926542] [2024-11-13 13:20:57,107 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:20:57,108 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:20:57,112 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:20:57,157 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:20:57,157 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:20:57,162 INFO L87 Difference]: Start difference. First operand has 136 states, 135 states have (on average 1.511111111111111) internal successors, (204), 135 states have internal predecessors, (204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:20:57,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:20:57,207 INFO L93 Difference]: Finished difference Result 134 states and 190 transitions. [2024-11-13 13:20:57,208 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 134 states and 190 transitions. [2024-11-13 13:20:57,212 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 99 [2024-11-13 13:20:57,221 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 134 states to 128 states and 184 transitions. [2024-11-13 13:20:57,222 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128 [2024-11-13 13:20:57,223 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128 [2024-11-13 13:20:57,224 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128 states and 184 transitions. [2024-11-13 13:20:57,225 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:20:57,226 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128 states and 184 transitions. [2024-11-13 13:20:57,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states and 184 transitions. [2024-11-13 13:20:57,260 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 128. [2024-11-13 13:20:57,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 128 states, 128 states have (on average 1.4375) internal successors, (184), 127 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:20:57,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 184 transitions. [2024-11-13 13:20:57,265 INFO L240 hiAutomatonCegarLoop]: Abstraction has 128 states and 184 transitions. [2024-11-13 13:20:57,266 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:20:57,270 INFO L424 stractBuchiCegarLoop]: Abstraction has 128 states and 184 transitions. [2024-11-13 13:20:57,271 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 13:20:57,271 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 128 states and 184 transitions. [2024-11-13 13:20:57,273 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 99 [2024-11-13 13:20:57,273 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:20:57,273 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:20:57,275 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:20:57,275 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:20:57,276 INFO L745 eck$LassoCheckResult]: Stem: 329#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 330#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 352#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 348#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 298#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 283#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 284#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 381#L250 assume !(0 == ~M_E~0); 390#L250-2 assume !(0 == ~T1_E~0); 342#L255-1 assume !(0 == ~E_1~0); 343#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 359#L115 assume !(1 == ~m_pc~0); 325#L115-2 is_master_triggered_~__retres1~0#1 := 0; 326#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 289#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 290#L300 assume !(0 != activate_threads_~tmp~1#1); 368#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 400#L134 assume 1 == ~t1_pc~0; 401#L135 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 361#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 341#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 292#L308 assume !(0 != activate_threads_~tmp___0~0#1); 293#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 363#L273 assume !(1 == ~M_E~0); 364#L273-2 assume !(1 == ~T1_E~0); 398#L278-1 assume !(1 == ~E_1~0); 372#L283-1 assume { :end_inline_reset_delta_events } true; 347#L404-2 [2024-11-13 13:20:57,276 INFO L747 eck$LassoCheckResult]: Loop: 347#L404-2 assume !false; 362#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 380#L225-1 assume !false; 386#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 387#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 328#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 299#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 300#L206 assume !(0 != eval_~tmp~0#1); 338#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 383#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 405#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 395#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 396#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 285#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 286#L115-6 assume 1 == ~m_pc~0; 353#L116-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 404#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 357#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 358#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 373#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 406#L134-6 assume !(1 == ~t1_pc~0); 331#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 332#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 356#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 355#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 287#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 288#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 349#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 333#L278-3 assume !(1 == ~E_1~0); 334#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 375#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 376#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 397#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 309#L423 assume !(0 == start_simulation_~tmp~3#1); 307#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 308#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 313#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 340#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 301#L378 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 302#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 306#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 346#L436 assume !(0 != start_simulation_~tmp___0~1#1); 347#L404-2 [2024-11-13 13:20:57,277 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:20:57,277 INFO L85 PathProgramCache]: Analyzing trace with hash -1569234711, now seen corresponding path program 1 times [2024-11-13 13:20:57,278 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:20:57,278 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1597310099] [2024-11-13 13:20:57,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:20:57,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:20:57,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:20:57,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:20:57,466 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:20:57,466 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1597310099] [2024-11-13 13:20:57,466 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1597310099] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:20:57,466 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:20:57,466 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:20:57,467 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1750180165] [2024-11-13 13:20:57,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:20:57,467 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:20:57,467 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:20:57,468 INFO L85 PathProgramCache]: Analyzing trace with hash -1891941062, now seen corresponding path program 1 times [2024-11-13 13:20:57,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:20:57,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1395422165] [2024-11-13 13:20:57,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:20:57,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:20:57,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:20:57,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:20:57,599 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:20:57,599 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1395422165] [2024-11-13 13:20:57,599 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1395422165] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:20:57,599 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:20:57,600 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:20:57,600 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [813699141] [2024-11-13 13:20:57,600 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:20:57,601 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:20:57,601 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:20:57,602 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:20:57,602 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:20:57,603 INFO L87 Difference]: Start difference. First operand 128 states and 184 transitions. cyclomatic complexity: 57 Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 2 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:20:57,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:20:57,702 INFO L93 Difference]: Finished difference Result 222 states and 313 transitions. [2024-11-13 13:20:57,702 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 222 states and 313 transitions. [2024-11-13 13:20:57,706 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 192 [2024-11-13 13:20:57,716 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 222 states to 222 states and 313 transitions. [2024-11-13 13:20:57,716 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 222 [2024-11-13 13:20:57,717 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 222 [2024-11-13 13:20:57,717 INFO L73 IsDeterministic]: Start isDeterministic. Operand 222 states and 313 transitions. [2024-11-13 13:20:57,718 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:20:57,718 INFO L218 hiAutomatonCegarLoop]: Abstraction has 222 states and 313 transitions. [2024-11-13 13:20:57,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 222 states and 313 transitions. [2024-11-13 13:20:57,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 222 to 218. [2024-11-13 13:20:57,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 218 states, 218 states have (on average 1.4128440366972477) internal successors, (308), 217 states have internal predecessors, (308), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:20:57,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 218 states to 218 states and 308 transitions. [2024-11-13 13:20:57,747 INFO L240 hiAutomatonCegarLoop]: Abstraction has 218 states and 308 transitions. [2024-11-13 13:20:57,748 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:20:57,750 INFO L424 stractBuchiCegarLoop]: Abstraction has 218 states and 308 transitions. [2024-11-13 13:20:57,751 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 13:20:57,752 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 218 states and 308 transitions. [2024-11-13 13:20:57,754 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 190 [2024-11-13 13:20:57,757 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:20:57,758 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:20:57,759 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:20:57,759 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:20:57,760 INFO L745 eck$LassoCheckResult]: Stem: 688#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 689#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 713#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 708#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 655#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 640#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 641#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 745#L250 assume !(0 == ~M_E~0); 760#L250-2 assume !(0 == ~T1_E~0); 702#L255-1 assume !(0 == ~E_1~0); 703#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 722#L115 assume !(1 == ~m_pc~0); 683#L115-2 is_master_triggered_~__retres1~0#1 := 0; 684#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 646#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 647#L300 assume !(0 != activate_threads_~tmp~1#1); 732#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 767#L134 assume !(1 == ~t1_pc~0); 730#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 723#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 700#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 651#L308 assume !(0 != activate_threads_~tmp___0~0#1); 652#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 725#L273 assume !(1 == ~M_E~0); 726#L273-2 assume !(1 == ~T1_E~0); 765#L278-1 assume !(1 == ~E_1~0); 735#L283-1 assume { :end_inline_reset_delta_events } true; 736#L404-2 [2024-11-13 13:20:57,760 INFO L747 eck$LassoCheckResult]: Loop: 736#L404-2 assume !false; 813#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 812#L225-1 assume !false; 811#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 809#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 808#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 807#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 806#L206 assume !(0 != eval_~tmp~0#1); 804#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 801#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 799#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 797#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 795#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 792#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 790#L115-6 assume 1 == ~m_pc~0; 773#L116-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 774#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 719#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 720#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 737#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 781#L134-6 assume !(1 == ~t1_pc~0); 782#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 840#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 839#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 838#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 644#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 645#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 837#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 692#L278-3 assume !(1 == ~E_1~0); 693#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 739#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 740#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 764#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 666#L423 assume !(0 == start_simulation_~tmp~3#1); 668#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 846#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 845#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 844#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 843#L378 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 842#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 841#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 816#L436 assume !(0 != start_simulation_~tmp___0~1#1); 736#L404-2 [2024-11-13 13:20:57,760 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:20:57,761 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 1 times [2024-11-13 13:20:57,761 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:20:57,761 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1616679376] [2024-11-13 13:20:57,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:20:57,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:20:57,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:20:57,790 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:20:57,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:20:57,840 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:20:57,841 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:20:57,841 INFO L85 PathProgramCache]: Analyzing trace with hash -1891941062, now seen corresponding path program 2 times [2024-11-13 13:20:57,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:20:57,842 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [837931800] [2024-11-13 13:20:57,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:20:57,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:20:57,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:20:57,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:20:57,899 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:20:57,899 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [837931800] [2024-11-13 13:20:57,899 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [837931800] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:20:57,899 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:20:57,899 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:20:57,900 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1174827295] [2024-11-13 13:20:57,900 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:20:57,900 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:20:57,901 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:20:57,901 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:20:57,901 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:20:57,901 INFO L87 Difference]: Start difference. First operand 218 states and 308 transitions. cyclomatic complexity: 92 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:20:58,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:20:58,006 INFO L93 Difference]: Finished difference Result 277 states and 388 transitions. [2024-11-13 13:20:58,006 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 277 states and 388 transitions. [2024-11-13 13:20:58,013 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 232 [2024-11-13 13:20:58,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 277 states to 277 states and 388 transitions. [2024-11-13 13:20:58,020 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 277 [2024-11-13 13:20:58,021 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 277 [2024-11-13 13:20:58,021 INFO L73 IsDeterministic]: Start isDeterministic. Operand 277 states and 388 transitions. [2024-11-13 13:20:58,023 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:20:58,023 INFO L218 hiAutomatonCegarLoop]: Abstraction has 277 states and 388 transitions. [2024-11-13 13:20:58,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 277 states and 388 transitions. [2024-11-13 13:20:58,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 277 to 277. [2024-11-13 13:20:58,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 277 states, 277 states have (on average 1.4007220216606497) internal successors, (388), 276 states have internal predecessors, (388), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:20:58,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277 states to 277 states and 388 transitions. [2024-11-13 13:20:58,055 INFO L240 hiAutomatonCegarLoop]: Abstraction has 277 states and 388 transitions. [2024-11-13 13:20:58,059 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:20:58,060 INFO L424 stractBuchiCegarLoop]: Abstraction has 277 states and 388 transitions. [2024-11-13 13:20:58,060 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 13:20:58,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 277 states and 388 transitions. [2024-11-13 13:20:58,062 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 232 [2024-11-13 13:20:58,064 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:20:58,064 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:20:58,065 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:20:58,065 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:20:58,065 INFO L745 eck$LassoCheckResult]: Stem: 1189#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 1190#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 1214#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1209#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1156#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 1141#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1142#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1247#L250 assume !(0 == ~M_E~0); 1261#L250-2 assume !(0 == ~T1_E~0); 1202#L255-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1203#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1394#L115 assume !(1 == ~m_pc~0); 1391#L115-2 is_master_triggered_~__retres1~0#1 := 0; 1389#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1387#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1385#L300 assume !(0 != activate_threads_~tmp~1#1); 1383#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1381#L134 assume !(1 == ~t1_pc~0); 1231#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1224#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1201#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1150#L308 assume !(0 != activate_threads_~tmp___0~0#1); 1151#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1226#L273 assume !(1 == ~M_E~0); 1227#L273-2 assume !(1 == ~T1_E~0); 1267#L278-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1237#L283-1 assume { :end_inline_reset_delta_events } true; 1238#L404-2 [2024-11-13 13:20:58,066 INFO L747 eck$LassoCheckResult]: Loop: 1238#L404-2 assume !false; 1363#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1362#L225-1 assume !false; 1361#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1321#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1319#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1318#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1315#L206 assume !(0 != eval_~tmp~0#1); 1249#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1250#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1276#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1265#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1266#L255-3 assume !(0 == ~E_1~0); 1268#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1408#L115-6 assume 1 == ~m_pc~0; 1406#L116-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1405#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1404#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1403#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1402#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1401#L134-6 assume !(1 == ~t1_pc~0); 1191#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 1192#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1400#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1399#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1398#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1397#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1396#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1395#L278-3 assume !(1 == ~E_1~0); 1194#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1241#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1242#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1264#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 1166#L423 assume !(0 == start_simulation_~tmp~3#1); 1168#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1376#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1374#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1372#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 1370#L378 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1368#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1367#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 1365#L436 assume !(0 != start_simulation_~tmp___0~1#1); 1238#L404-2 [2024-11-13 13:20:58,066 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:20:58,066 INFO L85 PathProgramCache]: Analyzing trace with hash 1089490508, now seen corresponding path program 1 times [2024-11-13 13:20:58,066 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:20:58,066 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [133999422] [2024-11-13 13:20:58,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:20:58,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:20:58,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:20:58,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:20:58,122 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:20:58,122 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [133999422] [2024-11-13 13:20:58,122 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [133999422] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:20:58,122 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:20:58,123 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:20:58,123 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1053622369] [2024-11-13 13:20:58,123 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:20:58,123 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:20:58,123 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:20:58,124 INFO L85 PathProgramCache]: Analyzing trace with hash -1869308808, now seen corresponding path program 1 times [2024-11-13 13:20:58,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:20:58,124 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [222232935] [2024-11-13 13:20:58,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:20:58,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:20:58,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:20:58,210 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:20:58,210 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:20:58,210 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [222232935] [2024-11-13 13:20:58,210 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [222232935] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:20:58,211 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:20:58,211 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:20:58,211 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1225394829] [2024-11-13 13:20:58,211 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:20:58,211 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:20:58,211 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:20:58,212 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:20:58,212 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:20:58,212 INFO L87 Difference]: Start difference. First operand 277 states and 388 transitions. cyclomatic complexity: 113 Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 2 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:20:58,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:20:58,299 INFO L93 Difference]: Finished difference Result 218 states and 297 transitions. [2024-11-13 13:20:58,299 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 218 states and 297 transitions. [2024-11-13 13:20:58,301 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 190 [2024-11-13 13:20:58,303 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 218 states to 218 states and 297 transitions. [2024-11-13 13:20:58,304 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 218 [2024-11-13 13:20:58,304 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 218 [2024-11-13 13:20:58,304 INFO L73 IsDeterministic]: Start isDeterministic. Operand 218 states and 297 transitions. [2024-11-13 13:20:58,338 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:20:58,338 INFO L218 hiAutomatonCegarLoop]: Abstraction has 218 states and 297 transitions. [2024-11-13 13:20:58,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218 states and 297 transitions. [2024-11-13 13:20:58,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218 to 218. [2024-11-13 13:20:58,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 218 states, 218 states have (on average 1.3623853211009174) internal successors, (297), 217 states have internal predecessors, (297), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:20:58,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 218 states to 218 states and 297 transitions. [2024-11-13 13:20:58,358 INFO L240 hiAutomatonCegarLoop]: Abstraction has 218 states and 297 transitions. [2024-11-13 13:20:58,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:20:58,360 INFO L424 stractBuchiCegarLoop]: Abstraction has 218 states and 297 transitions. [2024-11-13 13:20:58,360 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 13:20:58,360 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 218 states and 297 transitions. [2024-11-13 13:20:58,362 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 190 [2024-11-13 13:20:58,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:20:58,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:20:58,367 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:20:58,367 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:20:58,367 INFO L745 eck$LassoCheckResult]: Stem: 1694#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 1695#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 1718#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1713#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1660#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 1645#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1646#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1749#L250 assume !(0 == ~M_E~0); 1761#L250-2 assume !(0 == ~T1_E~0); 1707#L255-1 assume !(0 == ~E_1~0); 1708#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1725#L115 assume !(1 == ~m_pc~0); 1688#L115-2 is_master_triggered_~__retres1~0#1 := 0; 1689#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1651#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1652#L300 assume !(0 != activate_threads_~tmp~1#1); 1736#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1769#L134 assume !(1 == ~t1_pc~0); 1733#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1727#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1706#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1654#L308 assume !(0 != activate_threads_~tmp___0~0#1); 1655#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1729#L273 assume !(1 == ~M_E~0); 1730#L273-2 assume !(1 == ~T1_E~0); 1766#L278-1 assume !(1 == ~E_1~0); 1739#L283-1 assume { :end_inline_reset_delta_events } true; 1740#L404-2 [2024-11-13 13:20:58,367 INFO L747 eck$LassoCheckResult]: Loop: 1740#L404-2 assume !false; 1816#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1813#L225-1 assume !false; 1810#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1806#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1803#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1801#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1798#L206 assume !(0 != eval_~tmp~0#1); 1799#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1858#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1857#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1856#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1767#L255-3 assume !(0 == ~E_1~0); 1647#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1648#L115-6 assume 1 == ~m_pc~0; 1719#L116-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1774#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1723#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1724#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1741#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1776#L134-6 assume !(1 == ~t1_pc~0); 1696#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 1697#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1722#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1721#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1649#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1650#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1714#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1698#L278-3 assume !(1 == ~E_1~0); 1699#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1743#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1744#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1763#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 1671#L423 assume !(0 == start_simulation_~tmp~3#1); 1669#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1670#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1675#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1705#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 1665#L378 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1666#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1837#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 1836#L436 assume !(0 != start_simulation_~tmp___0~1#1); 1740#L404-2 [2024-11-13 13:20:58,368 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:20:58,368 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 2 times [2024-11-13 13:20:58,368 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:20:58,368 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [743381206] [2024-11-13 13:20:58,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:20:58,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:20:58,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:20:58,397 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:20:58,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:20:58,418 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:20:58,422 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:20:58,423 INFO L85 PathProgramCache]: Analyzing trace with hash -1869308808, now seen corresponding path program 2 times [2024-11-13 13:20:58,423 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:20:58,423 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1594976067] [2024-11-13 13:20:58,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:20:58,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:20:58,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:20:58,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:20:58,570 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:20:58,570 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1594976067] [2024-11-13 13:20:58,570 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1594976067] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:20:58,571 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:20:58,571 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:20:58,571 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1331776499] [2024-11-13 13:20:58,571 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:20:58,571 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:20:58,575 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:20:58,575 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:20:58,576 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:20:58,576 INFO L87 Difference]: Start difference. First operand 218 states and 297 transitions. cyclomatic complexity: 81 Second operand has 5 states, 5 states have (on average 8.4) internal successors, (42), 5 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:20:58,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:20:58,676 INFO L93 Difference]: Finished difference Result 232 states and 311 transitions. [2024-11-13 13:20:58,676 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 232 states and 311 transitions. [2024-11-13 13:20:58,678 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 204 [2024-11-13 13:20:58,680 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 232 states to 232 states and 311 transitions. [2024-11-13 13:20:58,680 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 232 [2024-11-13 13:20:58,680 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 232 [2024-11-13 13:20:58,680 INFO L73 IsDeterministic]: Start isDeterministic. Operand 232 states and 311 transitions. [2024-11-13 13:20:58,681 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:20:58,681 INFO L218 hiAutomatonCegarLoop]: Abstraction has 232 states and 311 transitions. [2024-11-13 13:20:58,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 232 states and 311 transitions. [2024-11-13 13:20:58,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 232 to 224. [2024-11-13 13:20:58,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 224 states, 224 states have (on average 1.3526785714285714) internal successors, (303), 223 states have internal predecessors, (303), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:20:58,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224 states to 224 states and 303 transitions. [2024-11-13 13:20:58,688 INFO L240 hiAutomatonCegarLoop]: Abstraction has 224 states and 303 transitions. [2024-11-13 13:20:58,688 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:20:58,689 INFO L424 stractBuchiCegarLoop]: Abstraction has 224 states and 303 transitions. [2024-11-13 13:20:58,689 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 13:20:58,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 224 states and 303 transitions. [2024-11-13 13:20:58,691 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 196 [2024-11-13 13:20:58,691 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:20:58,691 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:20:58,692 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:20:58,692 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:20:58,692 INFO L745 eck$LassoCheckResult]: Stem: 2151#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 2152#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 2176#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2170#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2118#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 2103#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2104#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2209#L250 assume !(0 == ~M_E~0); 2223#L250-2 assume !(0 == ~T1_E~0); 2164#L255-1 assume !(0 == ~E_1~0); 2165#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2183#L115 assume !(1 == ~m_pc~0); 2144#L115-2 is_master_triggered_~__retres1~0#1 := 0; 2145#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2109#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2110#L300 assume !(0 != activate_threads_~tmp~1#1); 2193#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2232#L134 assume !(1 == ~t1_pc~0); 2191#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2185#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2163#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2112#L308 assume !(0 != activate_threads_~tmp___0~0#1); 2113#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2187#L273 assume !(1 == ~M_E~0); 2188#L273-2 assume !(1 == ~T1_E~0); 2230#L278-1 assume !(1 == ~E_1~0); 2198#L283-1 assume { :end_inline_reset_delta_events } true; 2199#L404-2 [2024-11-13 13:20:58,692 INFO L747 eck$LassoCheckResult]: Loop: 2199#L404-2 assume !false; 2284#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2283#L225-1 assume !false; 2215#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2216#L179 assume !(0 == ~m_st~0); 2146#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 2148#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2277#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2273#L206 assume !(0 != eval_~tmp~0#1); 2211#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2212#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2239#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2228#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2229#L255-3 assume !(0 == ~E_1~0); 2105#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2106#L115-6 assume 1 == ~m_pc~0; 2177#L116-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2238#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2181#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2182#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2200#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2240#L134-6 assume !(1 == ~t1_pc~0); 2153#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 2154#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2180#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2179#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2107#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2108#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2171#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2155#L278-3 assume !(1 == ~E_1~0); 2156#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2225#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2313#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2227#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 2128#L423 assume !(0 == start_simulation_~tmp~3#1); 2126#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2127#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2132#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2197#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 2290#L378 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2289#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2288#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 2287#L436 assume !(0 != start_simulation_~tmp___0~1#1); 2199#L404-2 [2024-11-13 13:20:58,693 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:20:58,693 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 3 times [2024-11-13 13:20:58,693 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:20:58,693 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1131105876] [2024-11-13 13:20:58,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:20:58,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:20:58,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:20:58,702 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:20:58,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:20:58,715 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:20:58,715 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:20:58,716 INFO L85 PathProgramCache]: Analyzing trace with hash 586356843, now seen corresponding path program 1 times [2024-11-13 13:20:58,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:20:58,716 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1682550156] [2024-11-13 13:20:58,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:20:58,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:20:58,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:20:58,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:20:58,781 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:20:58,782 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1682550156] [2024-11-13 13:20:58,782 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1682550156] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:20:58,782 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:20:58,782 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:20:58,782 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1805785728] [2024-11-13 13:20:58,782 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:20:58,783 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:20:58,783 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:20:58,783 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:20:58,783 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:20:58,783 INFO L87 Difference]: Start difference. First operand 224 states and 303 transitions. cyclomatic complexity: 81 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:20:58,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:20:58,874 INFO L93 Difference]: Finished difference Result 234 states and 313 transitions. [2024-11-13 13:20:58,874 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 234 states and 313 transitions. [2024-11-13 13:20:58,879 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 206 [2024-11-13 13:20:58,881 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 234 states to 234 states and 313 transitions. [2024-11-13 13:20:58,881 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 234 [2024-11-13 13:20:58,882 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 234 [2024-11-13 13:20:58,882 INFO L73 IsDeterministic]: Start isDeterministic. Operand 234 states and 313 transitions. [2024-11-13 13:20:58,883 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:20:58,883 INFO L218 hiAutomatonCegarLoop]: Abstraction has 234 states and 313 transitions. [2024-11-13 13:20:58,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 234 states and 313 transitions. [2024-11-13 13:20:58,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 234 to 230. [2024-11-13 13:20:58,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 230 states, 230 states have (on average 1.3434782608695652) internal successors, (309), 229 states have internal predecessors, (309), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:20:58,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 309 transitions. [2024-11-13 13:20:58,899 INFO L240 hiAutomatonCegarLoop]: Abstraction has 230 states and 309 transitions. [2024-11-13 13:20:58,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:20:58,903 INFO L424 stractBuchiCegarLoop]: Abstraction has 230 states and 309 transitions. [2024-11-13 13:20:58,903 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 13:20:58,903 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 230 states and 309 transitions. [2024-11-13 13:20:58,905 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 202 [2024-11-13 13:20:58,905 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:20:58,905 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:20:58,910 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:20:58,910 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:20:58,911 INFO L745 eck$LassoCheckResult]: Stem: 2617#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 2618#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 2642#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2636#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2584#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 2569#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2570#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2674#L250 assume !(0 == ~M_E~0); 2685#L250-2 assume !(0 == ~T1_E~0); 2630#L255-1 assume !(0 == ~E_1~0); 2631#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2649#L115 assume !(1 == ~m_pc~0); 2610#L115-2 is_master_triggered_~__retres1~0#1 := 0; 2611#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2575#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2576#L300 assume !(0 != activate_threads_~tmp~1#1); 2659#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2697#L134 assume !(1 == ~t1_pc~0); 2655#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2651#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2629#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2578#L308 assume !(0 != activate_threads_~tmp___0~0#1); 2579#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2653#L273 assume !(1 == ~M_E~0); 2654#L273-2 assume !(1 == ~T1_E~0); 2694#L278-1 assume !(1 == ~E_1~0); 2663#L283-1 assume { :end_inline_reset_delta_events } true; 2638#L404-2 [2024-11-13 13:20:58,911 INFO L747 eck$LassoCheckResult]: Loop: 2638#L404-2 assume !false; 2652#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2673#L225-1 assume !false; 2681#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2682#L179 assume !(0 == ~m_st~0); 2612#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 2614#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2585#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2586#L206 assume !(0 != eval_~tmp~0#1); 2677#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2678#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2702#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2691#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2692#L255-3 assume !(0 == ~E_1~0); 2571#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2572#L115-6 assume 1 == ~m_pc~0; 2643#L116-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2701#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2647#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2648#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2664#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2703#L134-6 assume !(1 == ~t1_pc~0); 2705#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 2762#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2761#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2759#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2758#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2757#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2756#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2755#L278-3 assume !(1 == ~E_1~0); 2754#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2666#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2667#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2693#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 2594#L423 assume !(0 == start_simulation_~tmp~3#1); 2592#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2593#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2598#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2628#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 2589#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2590#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2591#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 2637#L436 assume !(0 != start_simulation_~tmp___0~1#1); 2638#L404-2 [2024-11-13 13:20:58,911 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:20:58,911 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 4 times [2024-11-13 13:20:58,912 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:20:58,912 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [443682914] [2024-11-13 13:20:58,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:20:58,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:20:58,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:20:58,928 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:20:58,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:20:58,939 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:20:58,939 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:20:58,939 INFO L85 PathProgramCache]: Analyzing trace with hash 586297261, now seen corresponding path program 1 times [2024-11-13 13:20:58,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:20:58,940 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1335832160] [2024-11-13 13:20:58,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:20:58,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:20:58,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:20:59,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:20:59,102 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:20:59,102 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1335832160] [2024-11-13 13:20:59,102 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1335832160] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:20:59,102 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:20:59,102 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:20:59,102 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1418794104] [2024-11-13 13:20:59,102 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:20:59,103 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:20:59,103 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:20:59,103 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:20:59,103 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:20:59,104 INFO L87 Difference]: Start difference. First operand 230 states and 309 transitions. cyclomatic complexity: 81 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:20:59,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:20:59,221 INFO L93 Difference]: Finished difference Result 233 states and 306 transitions. [2024-11-13 13:20:59,221 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 233 states and 306 transitions. [2024-11-13 13:20:59,224 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 205 [2024-11-13 13:20:59,226 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 233 states to 233 states and 306 transitions. [2024-11-13 13:20:59,226 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 233 [2024-11-13 13:20:59,226 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 233 [2024-11-13 13:20:59,226 INFO L73 IsDeterministic]: Start isDeterministic. Operand 233 states and 306 transitions. [2024-11-13 13:20:59,227 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:20:59,227 INFO L218 hiAutomatonCegarLoop]: Abstraction has 233 states and 306 transitions. [2024-11-13 13:20:59,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 233 states and 306 transitions. [2024-11-13 13:20:59,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 233 to 233. [2024-11-13 13:20:59,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 233 states, 233 states have (on average 1.3133047210300428) internal successors, (306), 232 states have internal predecessors, (306), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:20:59,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 233 states to 233 states and 306 transitions. [2024-11-13 13:20:59,233 INFO L240 hiAutomatonCegarLoop]: Abstraction has 233 states and 306 transitions. [2024-11-13 13:20:59,234 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:20:59,235 INFO L424 stractBuchiCegarLoop]: Abstraction has 233 states and 306 transitions. [2024-11-13 13:20:59,235 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 13:20:59,235 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 233 states and 306 transitions. [2024-11-13 13:20:59,237 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 205 [2024-11-13 13:20:59,237 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:20:59,237 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:20:59,238 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:20:59,238 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:20:59,238 INFO L745 eck$LassoCheckResult]: Stem: 3088#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 3089#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 3113#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3106#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3055#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 3040#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3041#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3144#L250 assume !(0 == ~M_E~0); 3155#L250-2 assume !(0 == ~T1_E~0); 3100#L255-1 assume !(0 == ~E_1~0); 3101#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3120#L115 assume !(1 == ~m_pc~0); 3081#L115-2 is_master_triggered_~__retres1~0#1 := 0; 3082#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3046#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3047#L300 assume !(0 != activate_threads_~tmp~1#1); 3130#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3166#L134 assume !(1 == ~t1_pc~0); 3126#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3122#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3099#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3049#L308 assume !(0 != activate_threads_~tmp___0~0#1); 3050#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3124#L273 assume !(1 == ~M_E~0); 3125#L273-2 assume !(1 == ~T1_E~0); 3163#L278-1 assume !(1 == ~E_1~0); 3134#L283-1 assume { :end_inline_reset_delta_events } true; 3108#L404-2 [2024-11-13 13:20:59,239 INFO L747 eck$LassoCheckResult]: Loop: 3108#L404-2 assume !false; 3123#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3143#L225-1 assume !false; 3149#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3150#L179 assume !(0 == ~m_st~0); 3083#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 3085#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3264#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3263#L206 assume !(0 != eval_~tmp~0#1); 3147#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3148#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3171#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3160#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3161#L255-3 assume !(0 == ~E_1~0); 3042#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3043#L115-6 assume 1 == ~m_pc~0; 3114#L116-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3170#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3118#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3119#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3135#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3172#L134-6 assume !(1 == ~t1_pc~0); 3090#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 3091#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3117#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3116#L308-6 assume !(0 != activate_threads_~tmp___0~0#1); 3044#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3045#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3109#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3092#L278-3 assume !(1 == ~E_1~0); 3093#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3137#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3138#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3162#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 3065#L423 assume !(0 == start_simulation_~tmp~3#1); 3063#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3064#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3069#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3098#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 3060#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3061#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3062#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 3107#L436 assume !(0 != start_simulation_~tmp___0~1#1); 3108#L404-2 [2024-11-13 13:20:59,239 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:20:59,239 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 5 times [2024-11-13 13:20:59,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:20:59,239 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541160786] [2024-11-13 13:20:59,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:20:59,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:20:59,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:20:59,249 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:20:59,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:20:59,258 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:20:59,258 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:20:59,259 INFO L85 PathProgramCache]: Analyzing trace with hash -1407847445, now seen corresponding path program 1 times [2024-11-13 13:20:59,259 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:20:59,259 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1534894896] [2024-11-13 13:20:59,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:20:59,259 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:20:59,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:20:59,270 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:20:59,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:20:59,292 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:20:59,293 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:20:59,293 INFO L85 PathProgramCache]: Analyzing trace with hash 45124292, now seen corresponding path program 1 times [2024-11-13 13:20:59,293 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:20:59,295 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1032767468] [2024-11-13 13:20:59,296 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:20:59,296 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:20:59,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:20:59,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:20:59,369 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:20:59,369 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1032767468] [2024-11-13 13:20:59,369 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1032767468] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:20:59,369 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:20:59,370 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:20:59,370 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1672944192] [2024-11-13 13:20:59,370 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:20:59,982 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 13:20:59,983 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 13:20:59,983 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 13:20:59,983 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 13:20:59,984 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-13 13:20:59,984 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:20:59,984 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 13:20:59,985 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 13:20:59,985 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.01.cil.c_Iteration8_Loop [2024-11-13 13:20:59,985 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 13:20:59,986 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 13:21:00,008 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,017 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,021 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,025 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,030 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,035 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,039 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,042 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,048 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,058 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,067 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,072 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,076 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,080 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,084 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,088 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,091 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,095 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,099 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,102 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,107 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,111 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,115 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,121 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,127 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,130 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,140 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,143 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,147 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,151 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,160 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:00,525 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 13:21:00,526 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-13 13:21:00,528 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:00,530 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:00,535 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:00,542 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-13 13:21:00,543 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:21:00,543 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:21:00,571 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:21:00,572 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:21:00,597 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-11-13 13:21:00,597 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:00,598 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:00,604 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:00,611 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:21:00,611 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:21:00,613 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-13 13:21:00,638 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:21:00,638 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:21:00,660 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2024-11-13 13:21:00,661 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:00,661 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:00,664 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:00,665 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-13 13:21:00,667 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:21:00,667 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:21:00,683 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:21:00,683 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_master_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:21:00,698 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-11-13 13:21:00,698 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:00,699 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:00,701 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:00,702 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-13 13:21:00,703 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:21:00,704 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:21:00,722 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:21:00,722 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:21:00,735 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-11-13 13:21:00,735 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:00,735 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:00,737 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:00,738 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-13 13:21:00,739 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:21:00,739 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:21:00,754 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:21:00,754 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:21:00,771 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2024-11-13 13:21:00,772 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:00,772 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:00,774 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:00,775 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-13 13:21:00,776 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:21:00,776 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:21:00,798 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:21:00,798 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_~__retres1~2#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_~__retres1~2#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:21:00,821 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2024-11-13 13:21:00,821 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:00,821 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:00,823 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:00,826 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-13 13:21:00,827 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:21:00,827 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:21:00,848 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:21:00,849 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Honda state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:21:00,870 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-11-13 13:21:00,870 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:00,870 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:00,873 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:00,875 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-13 13:21:00,876 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:21:00,876 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:21:00,908 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:21:00,908 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=4} Honda state: {~t1_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:21:00,930 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2024-11-13 13:21:00,931 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:00,931 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:00,933 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:00,934 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-13 13:21:00,936 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:21:00,936 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:21:00,968 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:21:00,968 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_1~0=-1} Honda state: {~E_1~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:21:00,992 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2024-11-13 13:21:00,993 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:00,993 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:00,998 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:01,001 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-13 13:21:01,003 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:21:01,003 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:21:01,046 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2024-11-13 13:21:01,047 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:01,047 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:01,049 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:01,051 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-11-13 13:21:01,053 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-13 13:21:01,053 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:21:01,080 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-13 13:21:01,103 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2024-11-13 13:21:01,103 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 13:21:01,103 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 13:21:01,103 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 13:21:01,104 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 13:21:01,104 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-13 13:21:01,104 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:01,104 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 13:21:01,104 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 13:21:01,104 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.01.cil.c_Iteration8_Loop [2024-11-13 13:21:01,104 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 13:21:01,104 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 13:21:01,109 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,116 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,120 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,124 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,128 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,135 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,142 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,146 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,156 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,165 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,177 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,183 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,187 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,191 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,196 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,200 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,205 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,208 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,215 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,219 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,224 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,229 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,234 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,239 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,244 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,249 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,253 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,256 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,267 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,276 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,284 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:21:01,558 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 13:21:01,563 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-13 13:21:01,564 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:01,564 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:01,567 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:01,569 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-11-13 13:21:01,570 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:21:01,586 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:21:01,586 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:21:01,586 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:21:01,587 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:21:01,587 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:21:01,594 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:21:01,594 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:21:01,597 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:21:01,616 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2024-11-13 13:21:01,617 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:01,617 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:01,620 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:01,623 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-11-13 13:21:01,625 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:21:01,642 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:21:01,642 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:21:01,642 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:21:01,642 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:21:01,642 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:21:01,643 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:21:01,644 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:21:01,649 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:21:01,668 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2024-11-13 13:21:01,669 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:01,669 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:01,671 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:01,674 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-11-13 13:21:01,675 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:21:01,691 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:21:01,691 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:21:01,691 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:21:01,691 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:21:01,692 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:21:01,692 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:21:01,692 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:21:01,697 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:21:01,716 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2024-11-13 13:21:01,717 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:01,717 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:01,721 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:01,722 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-11-13 13:21:01,724 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:21:01,741 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:21:01,741 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:21:01,742 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:21:01,742 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:21:01,742 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:21:01,743 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:21:01,743 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:21:01,745 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:21:01,766 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2024-11-13 13:21:01,767 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:01,767 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:01,770 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:01,773 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-11-13 13:21:01,774 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:21:01,791 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:21:01,791 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:21:01,791 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:21:01,792 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:21:01,792 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:21:01,792 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:21:01,792 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:21:01,795 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:21:01,815 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2024-11-13 13:21:01,815 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:01,815 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:01,818 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:01,821 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-11-13 13:21:01,821 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:21:01,839 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:21:01,839 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:21:01,840 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:21:01,840 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:21:01,840 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:21:01,840 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:21:01,840 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:21:01,843 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:21:01,864 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2024-11-13 13:21:01,865 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:01,865 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:01,868 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:01,870 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-11-13 13:21:01,871 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:21:01,887 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:21:01,888 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:21:01,888 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:21:01,888 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:21:01,888 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:21:01,889 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:21:01,889 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:21:01,894 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:21:01,916 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2024-11-13 13:21:01,916 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:01,916 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:01,920 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:01,923 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2024-11-13 13:21:01,924 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:21:01,941 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:21:01,942 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:21:01,942 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:21:01,942 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 13:21:01,942 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:21:01,943 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 13:21:01,943 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:21:01,949 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:21:01,970 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2024-11-13 13:21:01,970 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:01,970 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:01,973 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:01,976 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2024-11-13 13:21:01,977 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:21:01,995 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:21:01,995 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:21:01,995 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:21:01,995 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 13:21:01,995 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:21:01,996 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 13:21:01,996 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:21:02,002 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:21:02,027 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2024-11-13 13:21:02,028 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:02,028 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:02,030 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:02,032 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2024-11-13 13:21:02,037 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:21:02,056 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:21:02,056 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:21:02,056 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:21:02,056 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:21:02,056 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:21:02,058 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:21:02,058 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:21:02,062 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-13 13:21:02,067 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-13 13:21:02,070 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-13 13:21:02,072 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:21:02,072 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:21:02,078 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:21:02,079 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2024-11-13 13:21:02,080 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-13 13:21:02,080 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-13 13:21:02,080 INFO L474 LassoAnalysis]: Proved termination. [2024-11-13 13:21:02,081 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~M_E~0) = -1*~M_E~0 + 1 Supporting invariants [] [2024-11-13 13:21:02,103 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2024-11-13 13:21:02,108 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-13 13:21:02,158 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:21:02,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:21:02,209 INFO L255 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-13 13:21:02,211 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:21:02,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:21:02,333 INFO L255 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-13 13:21:02,336 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:21:02,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:21:02,600 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-13 13:21:02,601 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 233 states and 306 transitions. cyclomatic complexity: 75 Second operand has 5 states, 5 states have (on average 14.0) internal successors, (70), 5 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:21:02,723 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 233 states and 306 transitions. cyclomatic complexity: 75. Second operand has 5 states, 5 states have (on average 14.0) internal successors, (70), 5 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 579 states and 767 transitions. Complement of second has 5 states. [2024-11-13 13:21:02,727 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-13 13:21:02,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 14.0) internal successors, (70), 5 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:21:02,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 149 transitions. [2024-11-13 13:21:02,736 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 149 transitions. Stem has 27 letters. Loop has 43 letters. [2024-11-13 13:21:02,741 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:21:02,742 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 149 transitions. Stem has 70 letters. Loop has 43 letters. [2024-11-13 13:21:02,743 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:21:02,746 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 149 transitions. Stem has 27 letters. Loop has 86 letters. [2024-11-13 13:21:02,767 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:21:02,768 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 579 states and 767 transitions. [2024-11-13 13:21:02,775 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 373 [2024-11-13 13:21:02,782 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 579 states to 579 states and 767 transitions. [2024-11-13 13:21:02,782 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 402 [2024-11-13 13:21:02,783 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 407 [2024-11-13 13:21:02,783 INFO L73 IsDeterministic]: Start isDeterministic. Operand 579 states and 767 transitions. [2024-11-13 13:21:02,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:21:02,784 INFO L218 hiAutomatonCegarLoop]: Abstraction has 579 states and 767 transitions. [2024-11-13 13:21:02,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 579 states and 767 transitions. [2024-11-13 13:21:02,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 579 to 574. [2024-11-13 13:21:02,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 574 states, 574 states have (on average 1.3275261324041812) internal successors, (762), 573 states have internal predecessors, (762), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:21:02,804 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Ended with exit code 0 [2024-11-13 13:21:02,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 574 states to 574 states and 762 transitions. [2024-11-13 13:21:02,809 INFO L240 hiAutomatonCegarLoop]: Abstraction has 574 states and 762 transitions. [2024-11-13 13:21:02,809 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:21:02,810 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:21:02,810 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:21:02,810 INFO L87 Difference]: Start difference. First operand 574 states and 762 transitions. Second operand has 3 states, 3 states have (on average 23.333333333333332) internal successors, (70), 3 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:21:02,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:21:02,871 INFO L93 Difference]: Finished difference Result 919 states and 1162 transitions. [2024-11-13 13:21:02,871 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 919 states and 1162 transitions. [2024-11-13 13:21:02,881 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 614 [2024-11-13 13:21:02,888 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 919 states to 919 states and 1162 transitions. [2024-11-13 13:21:02,888 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 643 [2024-11-13 13:21:02,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 643 [2024-11-13 13:21:02,891 INFO L73 IsDeterministic]: Start isDeterministic. Operand 919 states and 1162 transitions. [2024-11-13 13:21:02,891 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:21:02,891 INFO L218 hiAutomatonCegarLoop]: Abstraction has 919 states and 1162 transitions. [2024-11-13 13:21:02,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 919 states and 1162 transitions. [2024-11-13 13:21:02,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 919 to 847. [2024-11-13 13:21:02,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 847 states, 847 states have (on average 1.2798110979929163) internal successors, (1084), 846 states have internal predecessors, (1084), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:21:02,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 847 states to 847 states and 1084 transitions. [2024-11-13 13:21:02,928 INFO L240 hiAutomatonCegarLoop]: Abstraction has 847 states and 1084 transitions. [2024-11-13 13:21:02,928 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:21:02,929 INFO L424 stractBuchiCegarLoop]: Abstraction has 847 states and 1084 transitions. [2024-11-13 13:21:02,929 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 13:21:02,929 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 847 states and 1084 transitions. [2024-11-13 13:21:02,935 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 566 [2024-11-13 13:21:02,938 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:21:02,938 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:21:02,939 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:21:02,939 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:21:02,940 INFO L745 eck$LassoCheckResult]: Stem: 5657#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 5658#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 5706#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5694#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5603#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 5579#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5580#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5771#L250 assume !(0 == ~M_E~0); 5792#L250-2 assume !(0 == ~T1_E~0); 5680#L255-1 assume !(0 == ~E_1~0); 5681#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5723#L115 assume !(1 == ~m_pc~0); 5646#L115-2 is_master_triggered_~__retres1~0#1 := 0; 5647#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5589#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5590#L300 assume !(0 != activate_threads_~tmp~1#1); 5739#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5816#L134 assume !(1 == ~t1_pc~0); 5733#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5728#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5679#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5593#L308 assume !(0 != activate_threads_~tmp___0~0#1); 5594#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5731#L273 assume !(1 == ~M_E~0); 5732#L273-2 assume !(1 == ~T1_E~0); 5808#L278-1 assume !(1 == ~E_1~0); 5746#L283-1 assume { :end_inline_reset_delta_events } true; 5747#L404-2 assume !false; 5729#L405 [2024-11-13 13:21:02,940 INFO L747 eck$LassoCheckResult]: Loop: 5729#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5768#L225-1 assume !false; 5781#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5782#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5764#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5765#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5671#L206 assume 0 != eval_~tmp~0#1; 5672#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 5775#L214 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 5638#L41 assume !(0 == ~m_pc~0); 5640#L44 assume 1 == ~m_pc~0; 6074#$Ultimate##91 assume !false; 6071#L61 ~m_pc~0 := 1;~m_st~0 := 2; 6069#master_returnLabel#1 assume { :end_inline_master } true; 6053#L214-2 havoc eval_~tmp_ndt_1~0#1; 6049#L211-1 assume !(0 == ~t1_st~0); 6047#L225-1 assume !false; 6046#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6045#L179 assume !(0 == ~m_st~0); 6043#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6042#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6041#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6036#L206 assume !(0 != eval_~tmp~0#1); 6034#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6030#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5837#L250-3 assume !(0 == ~M_E~0); 5801#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5802#L255-3 assume !(0 == ~E_1~0); 5810#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5707#L115-6 assume 1 == ~m_pc~0; 5708#L116-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5850#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5851#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5752#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5753#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6317#L134-6 assume !(1 == ~t1_pc~0); 6315#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 6313#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6311#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6309#L308-6 assume !(0 != activate_threads_~tmp___0~0#1); 6308#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6307#L273-3 assume !(1 == ~M_E~0); 6295#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6291#L278-3 assume !(1 == ~E_1~0); 6289#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6243#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6078#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6205#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 6006#L423 assume !(0 == start_simulation_~tmp~3#1); 6008#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6287#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6067#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5677#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 5612#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5613#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5616#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 5695#L436 assume !(0 != start_simulation_~tmp___0~1#1); 5696#L404-2 assume !false; 5729#L405 [2024-11-13 13:21:02,940 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:21:02,941 INFO L85 PathProgramCache]: Analyzing trace with hash 2020492971, now seen corresponding path program 1 times [2024-11-13 13:21:02,941 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:21:02,941 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1832790487] [2024-11-13 13:21:02,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:21:02,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:21:02,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:21:02,961 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:21:02,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:21:02,978 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:21:02,979 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:21:02,980 INFO L85 PathProgramCache]: Analyzing trace with hash -570455392, now seen corresponding path program 1 times [2024-11-13 13:21:02,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:21:02,980 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2043612775] [2024-11-13 13:21:02,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:21:02,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:21:02,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:21:03,053 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-11-13 13:21:03,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:21:03,053 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2043612775] [2024-11-13 13:21:03,054 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2043612775] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:21:03,054 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:21:03,054 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:21:03,054 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1032606605] [2024-11-13 13:21:03,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:21:03,055 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:21:03,056 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:21:03,056 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:21:03,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:21:03,057 INFO L87 Difference]: Start difference. First operand 847 states and 1084 transitions. cyclomatic complexity: 243 Second operand has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:21:03,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:21:03,124 INFO L93 Difference]: Finished difference Result 1368 states and 1710 transitions. [2024-11-13 13:21:03,125 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1368 states and 1710 transitions. [2024-11-13 13:21:03,139 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 844 [2024-11-13 13:21:03,149 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1368 states to 1310 states and 1640 transitions. [2024-11-13 13:21:03,149 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 890 [2024-11-13 13:21:03,151 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 890 [2024-11-13 13:21:03,152 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1310 states and 1640 transitions. [2024-11-13 13:21:03,152 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:21:03,152 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1310 states and 1640 transitions. [2024-11-13 13:21:03,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1310 states and 1640 transitions. [2024-11-13 13:21:03,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1310 to 1302. [2024-11-13 13:21:03,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1302 states, 1302 states have (on average 1.251920122887865) internal successors, (1630), 1301 states have internal predecessors, (1630), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:21:03,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1302 states to 1302 states and 1630 transitions. [2024-11-13 13:21:03,191 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1302 states and 1630 transitions. [2024-11-13 13:21:03,192 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:21:03,193 INFO L424 stractBuchiCegarLoop]: Abstraction has 1302 states and 1630 transitions. [2024-11-13 13:21:03,193 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 13:21:03,193 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1302 states and 1630 transitions. [2024-11-13 13:21:03,203 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 838 [2024-11-13 13:21:03,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:21:03,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:21:03,204 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:21:03,204 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:21:03,205 INFO L745 eck$LassoCheckResult]: Stem: 7877#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 7878#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 7925#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7913#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7825#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 7800#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7801#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7987#L250 assume 0 == ~M_E~0;~M_E~0 := 1; 8008#L250-2 assume !(0 == ~T1_E~0); 8087#L255-1 assume !(0 == ~E_1~0); 8086#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7941#L115 assume !(1 == ~m_pc~0); 7942#L115-2 is_master_triggered_~__retres1~0#1 := 0; 7868#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7810#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 7811#L300 assume !(0 != activate_threads_~tmp~1#1); 8079#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8078#L134 assume !(1 == ~t1_pc~0); 8077#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8076#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8075#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 7815#L308 assume !(0 != activate_threads_~tmp___0~0#1); 7816#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7950#L273 assume 1 == ~M_E~0;~M_E~0 := 2; 7951#L273-2 assume !(1 == ~T1_E~0); 8029#L278-1 assume !(1 == ~E_1~0); 7967#L283-1 assume { :end_inline_reset_delta_events } true; 7968#L404-2 assume !false; 8653#L405 [2024-11-13 13:21:03,205 INFO L747 eck$LassoCheckResult]: Loop: 8653#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8650#L225-1 assume !false; 8648#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8646#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 8497#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8643#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8640#L206 assume 0 != eval_~tmp~0#1; 8638#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 8621#L214 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 8634#L41 assume !(0 == ~m_pc~0); 8631#L44 assume 1 == ~m_pc~0; 8630#$Ultimate##91 assume !false; 8628#L61 ~m_pc~0 := 1;~m_st~0 := 2; 8625#master_returnLabel#1 assume { :end_inline_master } true; 8620#L214-2 havoc eval_~tmp_ndt_1~0#1; 8615#L211-1 assume !(0 == ~t1_st~0); 8504#L225-1 assume !false; 8505#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8496#L179 assume !(0 == ~m_st~0); 8498#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 8488#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8489#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8481#L206 assume !(0 != eval_~tmp~0#1); 8483#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8474#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8475#L250-3 assume !(0 == ~M_E~0); 8468#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8469#L255-3 assume !(0 == ~E_1~0); 8460#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8461#L115-6 assume !(1 == ~m_pc~0); 8453#L115-8 is_master_triggered_~__retres1~0#1 := 0; 8454#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8446#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8447#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8582#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8689#L134-6 assume !(1 == ~t1_pc~0); 8688#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 8687#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8686#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8685#L308-6 assume !(0 != activate_threads_~tmp___0~0#1); 8684#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8683#L273-3 assume !(1 == ~M_E~0); 8682#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8681#L278-3 assume !(1 == ~E_1~0); 8679#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8676#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 8675#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8674#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 8672#L423 assume !(0 == start_simulation_~tmp~3#1); 8671#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8670#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 8544#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8669#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 8668#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8667#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8666#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 8665#L436 assume !(0 != start_simulation_~tmp___0~1#1); 8658#L404-2 assume !false; 8653#L405 [2024-11-13 13:21:03,206 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:21:03,206 INFO L85 PathProgramCache]: Analyzing trace with hash 1595944103, now seen corresponding path program 1 times [2024-11-13 13:21:03,206 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:21:03,206 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1285633213] [2024-11-13 13:21:03,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:21:03,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:21:03,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:21:03,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:21:03,269 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:21:03,270 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1285633213] [2024-11-13 13:21:03,270 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1285633213] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:21:03,270 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:21:03,270 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:21:03,270 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [924209005] [2024-11-13 13:21:03,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:21:03,270 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:21:03,271 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:21:03,271 INFO L85 PathProgramCache]: Analyzing trace with hash -1542130079, now seen corresponding path program 1 times [2024-11-13 13:21:03,271 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:21:03,271 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [458481284] [2024-11-13 13:21:03,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:21:03,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:21:03,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:21:03,320 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:21:03,320 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:21:03,320 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [458481284] [2024-11-13 13:21:03,320 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [458481284] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:21:03,320 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:21:03,320 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:21:03,321 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [65236657] [2024-11-13 13:21:03,321 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:21:03,321 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:21:03,321 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:21:03,321 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:21:03,322 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:21:03,322 INFO L87 Difference]: Start difference. First operand 1302 states and 1630 transitions. cyclomatic complexity: 336 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 2 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:21:03,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:21:03,359 INFO L93 Difference]: Finished difference Result 841 states and 1025 transitions. [2024-11-13 13:21:03,360 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 841 states and 1025 transitions. [2024-11-13 13:21:03,367 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 566 [2024-11-13 13:21:03,371 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 841 states to 595 states and 726 transitions. [2024-11-13 13:21:03,372 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 595 [2024-11-13 13:21:03,372 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 595 [2024-11-13 13:21:03,373 INFO L73 IsDeterministic]: Start isDeterministic. Operand 595 states and 726 transitions. [2024-11-13 13:21:03,374 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:21:03,374 INFO L218 hiAutomatonCegarLoop]: Abstraction has 595 states and 726 transitions. [2024-11-13 13:21:03,375 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 595 states and 726 transitions. [2024-11-13 13:21:03,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 595 to 348. [2024-11-13 13:21:03,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 348 states, 348 states have (on average 1.2155172413793103) internal successors, (423), 347 states have internal predecessors, (423), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:21:03,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 348 states to 348 states and 423 transitions. [2024-11-13 13:21:03,386 INFO L240 hiAutomatonCegarLoop]: Abstraction has 348 states and 423 transitions. [2024-11-13 13:21:03,387 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:21:03,387 INFO L424 stractBuchiCegarLoop]: Abstraction has 348 states and 423 transitions. [2024-11-13 13:21:03,387 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 13:21:03,388 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 348 states and 423 transitions. [2024-11-13 13:21:03,390 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 320 [2024-11-13 13:21:03,391 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:21:03,391 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:21:03,391 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:21:03,392 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:21:03,392 INFO L745 eck$LassoCheckResult]: Stem: 9994#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 9995#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 10022#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10017#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9965#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 9948#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9949#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10056#L250 assume !(0 == ~M_E~0); 10072#L250-2 assume !(0 == ~T1_E~0); 10008#L255-1 assume !(0 == ~E_1~0); 10009#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10031#L115 assume !(1 == ~m_pc~0); 9992#L115-2 is_master_triggered_~__retres1~0#1 := 0; 10035#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9954#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 9955#L300 assume !(0 != activate_threads_~tmp~1#1); 10043#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10081#L134 assume !(1 == ~t1_pc~0); 10040#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10032#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10006#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9959#L308 assume !(0 != activate_threads_~tmp___0~0#1); 9960#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10036#L273 assume !(1 == ~M_E~0); 10037#L273-2 assume !(1 == ~T1_E~0); 10078#L278-1 assume !(1 == ~E_1~0); 10047#L283-1 assume { :end_inline_reset_delta_events } true; 10016#L404-2 [2024-11-13 13:21:03,392 INFO L747 eck$LassoCheckResult]: Loop: 10016#L404-2 assume !false; 10251#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10249#L225-1 assume !false; 10248#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10247#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10118#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10246#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10002#L206 assume 0 != eval_~tmp~0#1; 10003#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 10059#L214 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 9984#L41 assume !(0 == ~m_pc~0); 9986#L44 assume 1 == ~m_pc~0; 10007#$Ultimate##91 assume !false; 10045#L61 ~m_pc~0 := 1;~m_st~0 := 2; 10046#master_returnLabel#1 assume { :end_inline_master } true; 10127#L214-2 havoc eval_~tmp_ndt_1~0#1; 10122#L211-1 assume !(0 == ~t1_st~0); 10120#L225-1 assume !false; 10119#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10117#L179 assume !(0 == ~m_st~0); 9988#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 9990#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10150#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10149#L206 assume !(0 != eval_~tmp~0#1); 10060#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10061#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10086#L250-3 assume !(0 == ~M_E~0); 10075#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10076#L255-3 assume !(0 == ~E_1~0); 9950#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9951#L115-6 assume !(1 == ~m_pc~0); 10024#L115-8 is_master_triggered_~__retres1~0#1 := 0; 10091#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10027#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10028#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10049#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10087#L134-6 assume !(1 == ~t1_pc~0); 9996#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 9997#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10026#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10025#L308-6 assume !(0 != activate_threads_~tmp___0~0#1); 9952#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9953#L273-3 assume !(1 == ~M_E~0); 10018#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9998#L278-3 assume !(1 == ~E_1~0); 9999#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10051#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10052#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10077#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 9973#L423 assume !(0 == start_simulation_~tmp~3#1); 9971#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9972#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 9977#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10005#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 9968#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9969#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9970#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 10015#L436 assume !(0 != start_simulation_~tmp___0~1#1); 10016#L404-2 [2024-11-13 13:21:03,393 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:21:03,393 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 6 times [2024-11-13 13:21:03,393 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:21:03,393 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1276246566] [2024-11-13 13:21:03,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:21:03,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:21:03,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:21:03,401 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:21:03,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:21:03,411 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:21:03,412 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:21:03,412 INFO L85 PathProgramCache]: Analyzing trace with hash 568831201, now seen corresponding path program 2 times [2024-11-13 13:21:03,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:21:03,412 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1528622783] [2024-11-13 13:21:03,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:21:03,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:21:03,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:21:03,459 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:21:03,459 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:21:03,459 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1528622783] [2024-11-13 13:21:03,460 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1528622783] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:21:03,460 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:21:03,460 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:21:03,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1832795898] [2024-11-13 13:21:03,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:21:03,460 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:21:03,460 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:21:03,461 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:21:03,461 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:21:03,461 INFO L87 Difference]: Start difference. First operand 348 states and 423 transitions. cyclomatic complexity: 77 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 3 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:21:03,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:21:03,490 INFO L93 Difference]: Finished difference Result 426 states and 508 transitions. [2024-11-13 13:21:03,490 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 426 states and 508 transitions. [2024-11-13 13:21:03,494 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 309 [2024-11-13 13:21:03,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 426 states to 426 states and 508 transitions. [2024-11-13 13:21:03,497 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 426 [2024-11-13 13:21:03,497 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 426 [2024-11-13 13:21:03,498 INFO L73 IsDeterministic]: Start isDeterministic. Operand 426 states and 508 transitions. [2024-11-13 13:21:03,498 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:21:03,499 INFO L218 hiAutomatonCegarLoop]: Abstraction has 426 states and 508 transitions. [2024-11-13 13:21:03,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 426 states and 508 transitions. [2024-11-13 13:21:03,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 426 to 394. [2024-11-13 13:21:03,506 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 394 states, 394 states have (on average 1.1979695431472082) internal successors, (472), 393 states have internal predecessors, (472), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:21:03,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 394 states to 394 states and 472 transitions. [2024-11-13 13:21:03,508 INFO L240 hiAutomatonCegarLoop]: Abstraction has 394 states and 472 transitions. [2024-11-13 13:21:03,509 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:21:03,509 INFO L424 stractBuchiCegarLoop]: Abstraction has 394 states and 472 transitions. [2024-11-13 13:21:03,510 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 13:21:03,510 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 394 states and 472 transitions. [2024-11-13 13:21:03,513 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 309 [2024-11-13 13:21:03,513 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:21:03,513 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:21:03,514 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:21:03,514 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:21:03,514 INFO L745 eck$LassoCheckResult]: Stem: 10773#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 10774#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 10803#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10795#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10743#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 10728#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10729#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10842#L250 assume !(0 == ~M_E~0); 10853#L250-2 assume !(0 == ~T1_E~0); 10787#L255-1 assume !(0 == ~E_1~0); 10788#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10809#L115 assume 1 == ~m_pc~0; 10767#L116 assume !(1 == ~M_E~0); 10768#L115-2 is_master_triggered_~__retres1~0#1 := 0; 11055#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10734#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10735#L300 assume !(0 != activate_threads_~tmp~1#1); 10825#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10882#L134 assume !(1 == ~t1_pc~0); 10819#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10820#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10785#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10786#L308 assume !(0 != activate_threads_~tmp___0~0#1); 11052#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11051#L273 assume !(1 == ~M_E~0); 10872#L273-2 assume !(1 == ~T1_E~0); 10873#L278-1 assume !(1 == ~E_1~0); 10830#L283-1 assume { :end_inline_reset_delta_events } true; 10831#L404-2 [2024-11-13 13:21:03,514 INFO L747 eck$LassoCheckResult]: Loop: 10831#L404-2 assume !false; 11066#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11064#L225-1 assume !false; 10847#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10848#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10920#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 11063#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10781#L206 assume 0 != eval_~tmp~0#1; 10782#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 10844#L214 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 10765#L41 assume !(0 == ~m_pc~0); 10766#L44 assume 1 == ~m_pc~0; 10992#$Ultimate##91 assume !false; 10950#L61 ~m_pc~0 := 1;~m_st~0 := 2; 10948#master_returnLabel#1 assume { :end_inline_master } true; 10930#L214-2 havoc eval_~tmp_ndt_1~0#1; 10924#L211-1 assume !(0 == ~t1_st~0); 10922#L225-1 assume !false; 10921#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10919#L179 assume !(0 == ~m_st~0); 10769#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 10771#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10894#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10895#L206 assume !(0 != eval_~tmp~0#1); 10916#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10913#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10912#L250-3 assume !(0 == ~M_E~0); 10911#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10910#L255-3 assume !(0 == ~E_1~0); 10730#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10731#L115-6 assume 1 == ~m_pc~0; 10804#L116-2 assume !(1 == ~M_E~0); 10908#L115-8 is_master_triggered_~__retres1~0#1 := 0; 10907#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10906#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10833#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10834#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10880#L134-6 assume !(1 == ~t1_pc~0); 10775#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 10776#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10806#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10805#L308-6 assume !(0 != activate_threads_~tmp___0~0#1); 10732#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10733#L273-3 assume !(1 == ~M_E~0); 10798#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10799#L278-3 assume !(1 == ~E_1~0); 11083#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11082#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10899#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 11081#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 11079#L423 assume !(0 == start_simulation_~tmp~3#1); 11076#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11074#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10943#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 11071#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 11070#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10750#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10751#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 10889#L436 assume !(0 != start_simulation_~tmp___0~1#1); 10831#L404-2 [2024-11-13 13:21:03,515 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:21:03,515 INFO L85 PathProgramCache]: Analyzing trace with hash -831988783, now seen corresponding path program 1 times [2024-11-13 13:21:03,515 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:21:03,515 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1629201911] [2024-11-13 13:21:03,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:21:03,515 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:21:03,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:21:03,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:21:03,543 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:21:03,544 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1629201911] [2024-11-13 13:21:03,544 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1629201911] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:21:03,544 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:21:03,544 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:21:03,544 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1903869264] [2024-11-13 13:21:03,544 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:21:03,544 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:21:03,545 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:21:03,545 INFO L85 PathProgramCache]: Analyzing trace with hash 1887456595, now seen corresponding path program 1 times [2024-11-13 13:21:03,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:21:03,545 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [669486982] [2024-11-13 13:21:03,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:21:03,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:21:03,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:21:03,695 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-11-13 13:21:03,695 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:21:03,695 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [669486982] [2024-11-13 13:21:03,696 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [669486982] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:21:03,696 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:21:03,696 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:21:03,696 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1767422909] [2024-11-13 13:21:03,696 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:21:03,697 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:21:03,697 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:21:03,697 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:21:03,697 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:21:03,697 INFO L87 Difference]: Start difference. First operand 394 states and 472 transitions. cyclomatic complexity: 82 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 2 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:21:03,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:21:03,722 INFO L93 Difference]: Finished difference Result 380 states and 451 transitions. [2024-11-13 13:21:03,722 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 380 states and 451 transitions. [2024-11-13 13:21:03,726 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 309 [2024-11-13 13:21:03,728 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 380 states to 380 states and 451 transitions. [2024-11-13 13:21:03,728 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 380 [2024-11-13 13:21:03,729 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 380 [2024-11-13 13:21:03,729 INFO L73 IsDeterministic]: Start isDeterministic. Operand 380 states and 451 transitions. [2024-11-13 13:21:03,730 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:21:03,730 INFO L218 hiAutomatonCegarLoop]: Abstraction has 380 states and 451 transitions. [2024-11-13 13:21:03,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 380 states and 451 transitions. [2024-11-13 13:21:03,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 380 to 376. [2024-11-13 13:21:03,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 376 states, 376 states have (on average 1.1888297872340425) internal successors, (447), 375 states have internal predecessors, (447), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:21:03,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 376 states to 376 states and 447 transitions. [2024-11-13 13:21:03,739 INFO L240 hiAutomatonCegarLoop]: Abstraction has 376 states and 447 transitions. [2024-11-13 13:21:03,740 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:21:03,741 INFO L424 stractBuchiCegarLoop]: Abstraction has 376 states and 447 transitions. [2024-11-13 13:21:03,741 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 13:21:03,741 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 376 states and 447 transitions. [2024-11-13 13:21:03,744 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 309 [2024-11-13 13:21:03,744 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:21:03,744 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:21:03,745 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:21:03,745 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:21:03,745 INFO L745 eck$LassoCheckResult]: Stem: 11553#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 11554#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 11581#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11577#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11528#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 11511#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11512#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11621#L250 assume !(0 == ~M_E~0); 11637#L250-2 assume !(0 == ~T1_E~0); 11568#L255-1 assume !(0 == ~E_1~0); 11569#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11591#L115 assume !(1 == ~m_pc~0); 11592#L115-2 is_master_triggered_~__retres1~0#1 := 0; 11596#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11517#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 11518#L300 assume !(0 != activate_threads_~tmp~1#1); 11603#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11647#L134 assume !(1 == ~t1_pc~0); 11601#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11594#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11565#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11522#L308 assume !(0 != activate_threads_~tmp___0~0#1); 11523#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11597#L273 assume !(1 == ~M_E~0); 11598#L273-2 assume !(1 == ~T1_E~0); 11643#L278-1 assume !(1 == ~E_1~0); 11608#L283-1 assume { :end_inline_reset_delta_events } true; 11609#L404-2 assume !false; 11703#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11701#L225-1 [2024-11-13 13:21:03,745 INFO L747 eck$LassoCheckResult]: Loop: 11701#L225-1 assume !false; 11700#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11699#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 11698#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 11697#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11696#L206 assume 0 != eval_~tmp~0#1; 11695#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 11693#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 11694#L214-2 havoc eval_~tmp_ndt_1~0#1; 11704#L211-1 assume !(0 == ~t1_st~0); 11701#L225-1 [2024-11-13 13:21:03,746 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:21:03,746 INFO L85 PathProgramCache]: Analyzing trace with hash -1789227222, now seen corresponding path program 1 times [2024-11-13 13:21:03,746 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:21:03,746 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1823780610] [2024-11-13 13:21:03,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:21:03,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:21:03,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:21:03,756 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:21:03,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:21:03,765 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:21:03,765 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:21:03,766 INFO L85 PathProgramCache]: Analyzing trace with hash -589341508, now seen corresponding path program 1 times [2024-11-13 13:21:03,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:21:03,766 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [863876651] [2024-11-13 13:21:03,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:21:03,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:21:03,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:21:03,771 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:21:03,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:21:03,774 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:21:03,775 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:21:03,775 INFO L85 PathProgramCache]: Analyzing trace with hash -1573663579, now seen corresponding path program 1 times [2024-11-13 13:21:03,775 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:21:03,775 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1456543469] [2024-11-13 13:21:03,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:21:03,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:21:03,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:21:03,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:21:03,830 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:21:03,830 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1456543469] [2024-11-13 13:21:03,830 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1456543469] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:21:03,830 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:21:03,830 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:21:03,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1470802783] [2024-11-13 13:21:03,831 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:21:03,879 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:21:03,880 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:21:03,880 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:21:03,880 INFO L87 Difference]: Start difference. First operand 376 states and 447 transitions. cyclomatic complexity: 75 Second operand has 3 states, 2 states have (on average 19.5) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:21:03,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:21:03,929 INFO L93 Difference]: Finished difference Result 604 states and 704 transitions. [2024-11-13 13:21:03,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 604 states and 704 transitions. [2024-11-13 13:21:03,937 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 424 [2024-11-13 13:21:03,941 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 604 states to 604 states and 704 transitions. [2024-11-13 13:21:03,941 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 604 [2024-11-13 13:21:03,942 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 604 [2024-11-13 13:21:03,942 INFO L73 IsDeterministic]: Start isDeterministic. Operand 604 states and 704 transitions. [2024-11-13 13:21:03,944 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:21:03,944 INFO L218 hiAutomatonCegarLoop]: Abstraction has 604 states and 704 transitions. [2024-11-13 13:21:03,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 604 states and 704 transitions. [2024-11-13 13:21:03,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 604 to 530. [2024-11-13 13:21:03,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 530 states, 530 states have (on average 1.1735849056603773) internal successors, (622), 529 states have internal predecessors, (622), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:21:03,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 530 states to 530 states and 622 transitions. [2024-11-13 13:21:03,960 INFO L240 hiAutomatonCegarLoop]: Abstraction has 530 states and 622 transitions. [2024-11-13 13:21:03,961 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:21:03,962 INFO L424 stractBuchiCegarLoop]: Abstraction has 530 states and 622 transitions. [2024-11-13 13:21:03,962 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 13:21:03,962 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 530 states and 622 transitions. [2024-11-13 13:21:03,967 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 395 [2024-11-13 13:21:03,967 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:21:03,968 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:21:03,970 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:21:03,970 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:21:03,970 INFO L745 eck$LassoCheckResult]: Stem: 12543#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 12544#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 12569#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12564#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12515#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 12499#L161-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 12500#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12841#L250 assume !(0 == ~M_E~0); 12840#L250-2 assume !(0 == ~T1_E~0); 12839#L255-1 assume !(0 == ~E_1~0); 12838#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12578#L115 assume !(1 == ~m_pc~0); 12579#L115-2 is_master_triggered_~__retres1~0#1 := 0; 12585#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12506#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 12507#L300 assume !(0 != activate_threads_~tmp~1#1); 12594#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12644#L134 assume !(1 == ~t1_pc~0); 12822#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12821#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12554#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 12555#L308 assume !(0 != activate_threads_~tmp___0~0#1); 12588#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12589#L273 assume !(1 == ~M_E~0); 12647#L273-2 assume !(1 == ~T1_E~0); 12635#L278-1 assume !(1 == ~E_1~0); 12636#L283-1 assume { :end_inline_reset_delta_events } true; 12819#L404-2 assume !false; 12818#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12811#L225-1 [2024-11-13 13:21:03,973 INFO L747 eck$LassoCheckResult]: Loop: 12811#L225-1 assume !false; 12812#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 12803#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 12804#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 12796#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12797#L206 assume 0 != eval_~tmp~0#1; 12790#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 12791#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 12785#L214-2 havoc eval_~tmp_ndt_1~0#1; 12786#L211-1 assume !(0 == ~t1_st~0); 12811#L225-1 [2024-11-13 13:21:03,974 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:21:03,974 INFO L85 PathProgramCache]: Analyzing trace with hash -1923240728, now seen corresponding path program 1 times [2024-11-13 13:21:03,974 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:21:03,974 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [415353828] [2024-11-13 13:21:03,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:21:03,975 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:21:03,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:21:04,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:21:04,013 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:21:04,013 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [415353828] [2024-11-13 13:21:04,013 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [415353828] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:21:04,013 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:21:04,013 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:21:04,013 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [526292578] [2024-11-13 13:21:04,014 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:21:04,014 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:21:04,014 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:21:04,014 INFO L85 PathProgramCache]: Analyzing trace with hash -589341508, now seen corresponding path program 2 times [2024-11-13 13:21:04,015 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:21:04,015 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [969705934] [2024-11-13 13:21:04,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:21:04,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:21:04,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:21:04,022 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:21:04,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:21:04,029 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:21:04,070 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:21:04,070 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:21:04,071 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:21:04,071 INFO L87 Difference]: Start difference. First operand 530 states and 622 transitions. cyclomatic complexity: 97 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:21:04,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:21:04,081 INFO L93 Difference]: Finished difference Result 344 states and 404 transitions. [2024-11-13 13:21:04,081 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 344 states and 404 transitions. [2024-11-13 13:21:04,084 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 262 [2024-11-13 13:21:04,087 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 344 states to 344 states and 404 transitions. [2024-11-13 13:21:04,087 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 344 [2024-11-13 13:21:04,088 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 344 [2024-11-13 13:21:04,088 INFO L73 IsDeterministic]: Start isDeterministic. Operand 344 states and 404 transitions. [2024-11-13 13:21:04,089 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:21:04,089 INFO L218 hiAutomatonCegarLoop]: Abstraction has 344 states and 404 transitions. [2024-11-13 13:21:04,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 344 states and 404 transitions. [2024-11-13 13:21:04,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 344 to 344. [2024-11-13 13:21:04,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 344 states, 344 states have (on average 1.1744186046511629) internal successors, (404), 343 states have internal predecessors, (404), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:21:04,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 344 states to 344 states and 404 transitions. [2024-11-13 13:21:04,098 INFO L240 hiAutomatonCegarLoop]: Abstraction has 344 states and 404 transitions. [2024-11-13 13:21:04,099 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:21:04,099 INFO L424 stractBuchiCegarLoop]: Abstraction has 344 states and 404 transitions. [2024-11-13 13:21:04,100 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 13:21:04,100 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 344 states and 404 transitions. [2024-11-13 13:21:04,103 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 262 [2024-11-13 13:21:04,103 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:21:04,103 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:21:04,103 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:21:04,104 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:21:04,104 INFO L745 eck$LassoCheckResult]: Stem: 13423#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 13424#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 13449#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13444#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13395#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 13379#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13380#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13486#L250 assume !(0 == ~M_E~0); 13499#L250-2 assume !(0 == ~T1_E~0); 13436#L255-1 assume !(0 == ~E_1~0); 13437#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13457#L115 assume !(1 == ~m_pc~0); 13458#L115-2 is_master_triggered_~__retres1~0#1 := 0; 13461#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13385#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 13386#L300 assume !(0 != activate_threads_~tmp~1#1); 13469#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13513#L134 assume !(1 == ~t1_pc~0); 13466#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13459#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13435#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 13389#L308 assume !(0 != activate_threads_~tmp___0~0#1); 13390#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13462#L273 assume !(1 == ~M_E~0); 13463#L273-2 assume !(1 == ~T1_E~0); 13510#L278-1 assume !(1 == ~E_1~0); 13474#L283-1 assume { :end_inline_reset_delta_events } true; 13475#L404-2 assume !false; 13487#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13488#L225-1 [2024-11-13 13:21:04,104 INFO L747 eck$LassoCheckResult]: Loop: 13488#L225-1 assume !false; 13715#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 13524#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 13525#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 13714#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13431#L206 assume 0 != eval_~tmp~0#1; 13432#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 13490#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 13527#L214-2 havoc eval_~tmp_ndt_1~0#1; 13718#L211-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 13717#L228 assume !(0 != eval_~tmp_ndt_2~0#1); 13716#L228-2 havoc eval_~tmp_ndt_2~0#1; 13488#L225-1 [2024-11-13 13:21:04,105 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:21:04,105 INFO L85 PathProgramCache]: Analyzing trace with hash -1789227222, now seen corresponding path program 2 times [2024-11-13 13:21:04,105 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:21:04,105 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815154569] [2024-11-13 13:21:04,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:21:04,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:21:04,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:21:04,117 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:21:04,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:21:04,129 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:21:04,129 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:21:04,130 INFO L85 PathProgramCache]: Analyzing trace with hash 578462772, now seen corresponding path program 1 times [2024-11-13 13:21:04,130 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:21:04,130 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1525154362] [2024-11-13 13:21:04,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:21:04,130 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:21:04,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:21:04,135 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:21:04,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:21:04,142 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:21:04,146 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:21:04,146 INFO L85 PathProgramCache]: Analyzing trace with hash -462242339, now seen corresponding path program 1 times [2024-11-13 13:21:04,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:21:04,146 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2128633808] [2024-11-13 13:21:04,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:21:04,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:21:04,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:21:04,164 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:21:04,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:21:04,175 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:21:04,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:21:04,705 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:21:04,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:21:04,828 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.11 01:21:04 BoogieIcfgContainer [2024-11-13 13:21:04,828 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-13 13:21:04,830 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-13 13:21:04,830 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-13 13:21:04,831 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-13 13:21:04,832 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:20:56" (3/4) ... [2024-11-13 13:21:04,835 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-13 13:21:04,918 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/witness.graphml [2024-11-13 13:21:04,919 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-13 13:21:04,920 INFO L158 Benchmark]: Toolchain (without parser) took 9634.01ms. Allocated memory was 117.4MB in the beginning and 285.2MB in the end (delta: 167.8MB). Free memory was 85.2MB in the beginning and 221.6MB in the end (delta: -136.4MB). Peak memory consumption was 29.1MB. Max. memory is 16.1GB. [2024-11-13 13:21:04,920 INFO L158 Benchmark]: CDTParser took 2.24ms. Allocated memory is still 167.8MB. Free memory is still 104.6MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 13:21:04,920 INFO L158 Benchmark]: CACSL2BoogieTranslator took 423.24ms. Allocated memory is still 117.4MB. Free memory was 85.2MB in the beginning and 72.5MB in the end (delta: 12.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 13:21:04,921 INFO L158 Benchmark]: Boogie Procedure Inliner took 65.46ms. Allocated memory is still 117.4MB. Free memory was 72.5MB in the beginning and 70.4MB in the end (delta: 2.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 13:21:04,923 INFO L158 Benchmark]: Boogie Preprocessor took 79.41ms. Allocated memory is still 117.4MB. Free memory was 70.4MB in the beginning and 68.5MB in the end (delta: 1.9MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 13:21:04,924 INFO L158 Benchmark]: RCFGBuilder took 718.11ms. Allocated memory is still 117.4MB. Free memory was 68.1MB in the beginning and 47.2MB in the end (delta: 21.0MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-13 13:21:04,925 INFO L158 Benchmark]: BuchiAutomizer took 8246.07ms. Allocated memory was 117.4MB in the beginning and 285.2MB in the end (delta: 167.8MB). Free memory was 47.2MB in the beginning and 224.4MB in the end (delta: -177.2MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 13:21:04,926 INFO L158 Benchmark]: Witness Printer took 88.62ms. Allocated memory is still 285.2MB. Free memory was 224.4MB in the beginning and 221.6MB in the end (delta: 2.7MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 13:21:04,930 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 2.24ms. Allocated memory is still 167.8MB. Free memory is still 104.6MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 423.24ms. Allocated memory is still 117.4MB. Free memory was 85.2MB in the beginning and 72.5MB in the end (delta: 12.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 65.46ms. Allocated memory is still 117.4MB. Free memory was 72.5MB in the beginning and 70.4MB in the end (delta: 2.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 79.41ms. Allocated memory is still 117.4MB. Free memory was 70.4MB in the beginning and 68.5MB in the end (delta: 1.9MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 718.11ms. Allocated memory is still 117.4MB. Free memory was 68.1MB in the beginning and 47.2MB in the end (delta: 21.0MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 8246.07ms. Allocated memory was 117.4MB in the beginning and 285.2MB in the end (delta: 167.8MB). Free memory was 47.2MB in the beginning and 224.4MB in the end (delta: -177.2MB). There was no memory consumed. Max. memory is 16.1GB. * Witness Printer took 88.62ms. Allocated memory is still 285.2MB. Free memory was 224.4MB in the beginning and 221.6MB in the end (delta: 2.7MB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 15 terminating modules (14 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -1 * M_E) + 1) and consists of 3 locations. 14 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 344 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 8.1s and 15 iterations. TraceHistogramMax:2. Analysis of lassos took 5.7s. Construction of modules took 0.5s. Büchi inclusion checks took 1.6s. Highest rank in rank-based complementation 3. Minimization of det autom 12. Minimization of nondet autom 3. Automata minimization 0.3s AutomataMinimizationTime, 15 MinimizatonAttempts, 458 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1418 SdHoareTripleChecker+Valid, 0.7s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1417 mSDsluCounter, 5115 SdHoareTripleChecker+Invalid, 0.5s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2480 mSDsCounter, 95 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 278 IncrementalHoareTripleChecker+Invalid, 373 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 95 mSolverCounterUnsat, 2635 mSDtfsCounter, 278 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI6 SFLT0 conc1 concLT1 SILN1 SILU0 SILI5 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital40 mio100 ax100 hnf100 lsp25 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq179 hnf100 smp100 dnf166 smp73 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 32ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 9 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.3s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 201]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int E_1 = 2; VAL [E_1=2, M_E=2, T1_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0] [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L255] COND FALSE !(T1_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L260] COND FALSE !(E_1 == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L115] COND FALSE !(m_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L125] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L127] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L134] COND FALSE !(t1_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L144] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L146] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L278] COND FALSE !(T1_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L283] COND FALSE !(E_1 == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L401] RET reset_delta_events() [L404] COND TRUE 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] Loop: [L201] COND TRUE 1 [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE !(\read(tmp_ndt_1)) [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 201]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int E_1 = 2; VAL [E_1=2, M_E=2, T1_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0] [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L255] COND FALSE !(T1_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L260] COND FALSE !(E_1 == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L115] COND FALSE !(m_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L125] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L127] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L134] COND FALSE !(t1_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L144] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L146] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L278] COND FALSE !(T1_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L283] COND FALSE !(E_1 == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L401] RET reset_delta_events() [L404] COND TRUE 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] Loop: [L201] COND TRUE 1 [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE !(\read(tmp_ndt_1)) [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-13 13:21:04,973 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892385de-49c2-45bf-b1d6-d709c15c8e7b/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)