./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.02.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.02.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 15:32:36,317 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 15:32:36,408 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 15:32:36,414 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 15:32:36,414 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 15:32:36,442 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 15:32:36,443 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 15:32:36,443 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 15:32:36,443 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 15:32:36,443 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 15:32:36,444 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 15:32:36,444 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 15:32:36,444 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 15:32:36,444 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 15:32:36,444 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 15:32:36,445 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 15:32:36,445 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 15:32:36,445 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 15:32:36,445 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 15:32:36,445 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 15:32:36,445 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 15:32:36,445 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 15:32:36,448 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 15:32:36,448 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 15:32:36,448 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 15:32:36,448 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 15:32:36,448 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 15:32:36,449 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 15:32:36,449 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 15:32:36,449 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 15:32:36,449 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 15:32:36,449 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 15:32:36,449 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 15:32:36,449 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 15:32:36,449 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 15:32:36,450 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 15:32:36,450 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 15:32:36,450 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 15:32:36,450 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 15:32:36,450 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c [2024-11-13 15:32:36,872 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 15:32:36,888 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 15:32:36,891 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 15:32:36,894 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 15:32:36,895 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 15:32:36,896 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/transmitter.02.cil.c Unable to find full path for "g++" [2024-11-13 15:32:39,082 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 15:32:39,410 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 15:32:39,411 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/sv-benchmarks/c/systemc/transmitter.02.cil.c [2024-11-13 15:32:39,422 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/data/017b2a19e/6d405b3c561d48878eeda03f952cdda7/FLAGd07262bfa [2024-11-13 15:32:39,438 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/data/017b2a19e/6d405b3c561d48878eeda03f952cdda7 [2024-11-13 15:32:39,441 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 15:32:39,443 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 15:32:39,444 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 15:32:39,445 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 15:32:39,450 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 15:32:39,451 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:32:39" (1/1) ... [2024-11-13 15:32:39,452 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@38e74021 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:32:39, skipping insertion in model container [2024-11-13 15:32:39,452 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:32:39" (1/1) ... [2024-11-13 15:32:39,480 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 15:32:39,744 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:32:39,764 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 15:32:39,810 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:32:39,828 INFO L204 MainTranslator]: Completed translation [2024-11-13 15:32:39,829 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:32:39 WrapperNode [2024-11-13 15:32:39,829 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 15:32:39,830 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 15:32:39,831 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 15:32:39,831 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 15:32:39,839 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:32:39" (1/1) ... [2024-11-13 15:32:39,850 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:32:39" (1/1) ... [2024-11-13 15:32:39,904 INFO L138 Inliner]: procedures = 32, calls = 37, calls flagged for inlining = 32, calls inlined = 45, statements flattened = 530 [2024-11-13 15:32:39,904 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 15:32:39,905 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 15:32:39,905 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 15:32:39,905 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 15:32:39,922 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:32:39" (1/1) ... [2024-11-13 15:32:39,922 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:32:39" (1/1) ... [2024-11-13 15:32:39,925 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:32:39" (1/1) ... [2024-11-13 15:32:39,944 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 15:32:39,944 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:32:39" (1/1) ... [2024-11-13 15:32:39,944 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:32:39" (1/1) ... [2024-11-13 15:32:39,962 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:32:39" (1/1) ... [2024-11-13 15:32:39,982 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:32:39" (1/1) ... [2024-11-13 15:32:39,983 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:32:39" (1/1) ... [2024-11-13 15:32:39,989 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:32:39" (1/1) ... [2024-11-13 15:32:39,997 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 15:32:39,998 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 15:32:39,998 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 15:32:39,998 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 15:32:40,003 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:32:39" (1/1) ... [2024-11-13 15:32:40,017 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:40,053 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:40,071 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:40,075 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 15:32:40,111 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 15:32:40,112 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 15:32:40,112 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 15:32:40,112 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 15:32:40,201 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 15:32:40,203 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 15:32:40,975 INFO L? ?]: Removed 90 outVars from TransFormulas that were not future-live. [2024-11-13 15:32:40,975 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 15:32:40,994 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 15:32:40,994 INFO L316 CfgBuilder]: Removed 6 assume(true) statements. [2024-11-13 15:32:40,995 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:32:40 BoogieIcfgContainer [2024-11-13 15:32:40,995 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 15:32:40,996 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 15:32:40,996 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 15:32:41,008 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 15:32:41,009 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:32:41,009 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 03:32:39" (1/3) ... [2024-11-13 15:32:41,010 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7de9eca3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:32:41, skipping insertion in model container [2024-11-13 15:32:41,010 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:32:41,011 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:32:39" (2/3) ... [2024-11-13 15:32:41,011 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7de9eca3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:32:41, skipping insertion in model container [2024-11-13 15:32:41,012 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:32:41,012 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:32:40" (3/3) ... [2024-11-13 15:32:41,014 INFO L333 chiAutomizerObserver]: Analyzing ICFG transmitter.02.cil.c [2024-11-13 15:32:41,094 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 15:32:41,095 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 15:32:41,095 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 15:32:41,095 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 15:32:41,096 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 15:32:41,096 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 15:32:41,097 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 15:32:41,097 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 15:32:41,105 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 209 states, 208 states have (on average 1.5288461538461537) internal successors, (318), 208 states have internal predecessors, (318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:41,146 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 164 [2024-11-13 15:32:41,148 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:41,148 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:41,161 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:41,162 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:41,162 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 15:32:41,163 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 209 states, 208 states have (on average 1.5288461538461537) internal successors, (318), 208 states have internal predecessors, (318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:41,182 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 164 [2024-11-13 15:32:41,182 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:41,186 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:41,188 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:41,188 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:41,203 INFO L745 eck$LassoCheckResult]: Stem: 147#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 158#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 205#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 155#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 182#L221true assume !(1 == ~m_i~0);~m_st~0 := 2; 60#L221-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 42#L226-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 162#L231-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33#L334true assume !(0 == ~M_E~0); 169#L334-2true assume !(0 == ~T1_E~0); 113#L339-1true assume !(0 == ~T2_E~0); 108#L344-1true assume 0 == ~E_1~0;~E_1~0 := 1; 143#L349-1true assume !(0 == ~E_2~0); 41#L354-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117#L156true assume !(1 == ~m_pc~0); 154#L156-2true is_master_triggered_~__retres1~0#1 := 0; 136#L167true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 128#is_master_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 78#L405true assume !(0 != activate_threads_~tmp~1#1); 63#L405-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126#L175true assume 1 == ~t1_pc~0; 161#L176true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 64#L186true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 115#L413true assume !(0 != activate_threads_~tmp___0~0#1); 185#L413-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 187#L194true assume !(1 == ~t2_pc~0); 203#L194-2true is_transmit2_triggered_~__retres1~2#1 := 0; 70#L205true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 209#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 27#L421true assume !(0 != activate_threads_~tmp___1~0#1); 85#L421-2true havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12#L367true assume !(1 == ~M_E~0); 186#L367-2true assume !(1 == ~T1_E~0); 130#L372-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 132#L377-1true assume !(1 == ~E_1~0); 25#L382-1true assume !(1 == ~E_2~0); 80#L387-1true assume { :end_inline_reset_delta_events } true; 107#L528-2true [2024-11-13 15:32:41,205 INFO L747 eck$LassoCheckResult]: Loop: 107#L528-2true assume !false; 88#L529true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17#L309-1true assume false; 82#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 112#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 207#L334-3true assume 0 == ~M_E~0;~M_E~0 := 1; 159#L334-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 116#L339-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 183#L344-3true assume 0 == ~E_1~0;~E_1~0 := 1; 76#L349-3true assume 0 == ~E_2~0;~E_2~0 := 1; 32#L354-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101#L156-9true assume !(1 == ~m_pc~0); 4#L156-11true is_master_triggered_~__retres1~0#1 := 0; 57#L167-3true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 135#is_master_triggered_returnLabel#4true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 118#L405-9true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21#L405-11true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 192#L175-9true assume !(1 == ~t1_pc~0); 141#L175-11true is_transmit1_triggered_~__retres1~1#1 := 0; 14#L186-3true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 201#is_transmit1_triggered_returnLabel#4true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 153#L413-9true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 146#L413-11true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 190#L194-9true assume !(1 == ~t2_pc~0); 28#L194-11true is_transmit2_triggered_~__retres1~2#1 := 0; 196#L205-3true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5#is_transmit2_triggered_returnLabel#4true activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 110#L421-9true assume !(0 != activate_threads_~tmp___1~0#1); 144#L421-11true havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54#L367-3true assume 1 == ~M_E~0;~M_E~0 := 2; 7#L367-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 34#L372-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 18#L377-3true assume 1 == ~E_1~0;~E_1~0 := 2; 30#L382-3true assume !(1 == ~E_2~0); 111#L387-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 145#L244-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 180#L261-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 188#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 152#L547true assume !(0 == start_simulation_~tmp~3#1); 166#L547-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 149#L244-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 52#L261-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 37#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 40#L502true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49#L509true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 122#stop_simulation_returnLabel#1true start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 20#L560true assume !(0 != start_simulation_~tmp___0~1#1); 107#L528-2true [2024-11-13 15:32:41,215 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:41,216 INFO L85 PathProgramCache]: Analyzing trace with hash -886407522, now seen corresponding path program 1 times [2024-11-13 15:32:41,226 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:41,227 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [407709007] [2024-11-13 15:32:41,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:41,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:41,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:41,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:41,533 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:41,534 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [407709007] [2024-11-13 15:32:41,535 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [407709007] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:41,535 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:41,536 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:32:41,539 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [213721554] [2024-11-13 15:32:41,540 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:41,546 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:32:41,548 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:41,548 INFO L85 PathProgramCache]: Analyzing trace with hash -1217211153, now seen corresponding path program 1 times [2024-11-13 15:32:41,548 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:41,549 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574701541] [2024-11-13 15:32:41,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:41,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:41,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:41,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:41,597 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:41,597 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [574701541] [2024-11-13 15:32:41,597 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [574701541] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:41,597 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:41,597 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:32:41,598 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2121744923] [2024-11-13 15:32:41,598 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:41,601 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:32:41,602 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:32:41,633 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:32:41,634 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:32:41,637 INFO L87 Difference]: Start difference. First operand has 209 states, 208 states have (on average 1.5288461538461537) internal successors, (318), 208 states have internal predecessors, (318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:41,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:32:41,710 INFO L93 Difference]: Finished difference Result 207 states and 302 transitions. [2024-11-13 15:32:41,711 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 207 states and 302 transitions. [2024-11-13 15:32:41,753 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2024-11-13 15:32:41,765 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 207 states to 201 states and 296 transitions. [2024-11-13 15:32:41,766 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 201 [2024-11-13 15:32:41,768 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 201 [2024-11-13 15:32:41,769 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201 states and 296 transitions. [2024-11-13 15:32:41,770 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:32:41,770 INFO L218 hiAutomatonCegarLoop]: Abstraction has 201 states and 296 transitions. [2024-11-13 15:32:41,786 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states and 296 transitions. [2024-11-13 15:32:41,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 201. [2024-11-13 15:32:41,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 201 states, 201 states have (on average 1.472636815920398) internal successors, (296), 200 states have internal predecessors, (296), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:41,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 296 transitions. [2024-11-13 15:32:41,807 INFO L240 hiAutomatonCegarLoop]: Abstraction has 201 states and 296 transitions. [2024-11-13 15:32:41,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:32:41,812 INFO L424 stractBuchiCegarLoop]: Abstraction has 201 states and 296 transitions. [2024-11-13 15:32:41,812 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 15:32:41,812 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 201 states and 296 transitions. [2024-11-13 15:32:41,815 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2024-11-13 15:32:41,815 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:41,815 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:41,819 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:41,819 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:41,820 INFO L745 eck$LassoCheckResult]: Stem: 608#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 609#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 617#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 615#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 616#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 530#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 505#L226-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 506#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 489#L334 assume !(0 == ~M_E~0); 490#L334-2 assume !(0 == ~T1_E~0); 585#L339-1 assume !(0 == ~T2_E~0); 579#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 580#L349-1 assume !(0 == ~E_2~0); 503#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 504#L156 assume !(1 == ~m_pc~0); 436#L156-2 is_master_triggered_~__retres1~0#1 := 0; 435#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 597#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 552#L405 assume !(0 != activate_threads_~tmp~1#1); 534#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 535#L175 assume 1 == ~t1_pc~0; 594#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 536#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 500#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 501#L413 assume !(0 != activate_threads_~tmp___0~0#1); 587#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 624#L194 assume !(1 == ~t2_pc~0); 578#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 546#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 547#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 478#L421 assume !(0 != activate_threads_~tmp___1~0#1); 479#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 448#L367 assume !(1 == ~M_E~0); 449#L367-2 assume !(1 == ~T1_E~0); 598#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 599#L377-1 assume !(1 == ~E_1~0); 475#L382-1 assume !(1 == ~E_2~0); 476#L387-1 assume { :end_inline_reset_delta_events } true; 465#L528-2 [2024-11-13 15:32:41,820 INFO L747 eck$LassoCheckResult]: Loop: 465#L528-2 assume !false; 559#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 458#L309-1 assume !false; 459#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 439#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 440#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 447#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 425#L276 assume !(0 != eval_~tmp~0#1); 427#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 555#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 584#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 618#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 588#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 589#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 551#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 487#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 488#L156-9 assume 1 == ~m_pc~0; 573#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 431#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 527#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 590#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 466#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 467#L175-9 assume 1 == ~t1_pc~0; 512#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 452#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 453#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 614#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 606#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 607#L194-9 assume !(1 == ~t2_pc~0); 480#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 481#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 432#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 433#L421-9 assume !(0 != activate_threads_~tmp___1~0#1); 582#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 523#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 437#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 438#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 460#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 461#L382-3 assume !(1 == ~E_2~0); 484#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 583#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 492#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 623#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 613#L547 assume !(0 == start_simulation_~tmp~3#1); 600#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 610#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 521#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 495#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 496#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 502#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 517#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 464#L560 assume !(0 != start_simulation_~tmp___0~1#1); 465#L528-2 [2024-11-13 15:32:41,821 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:41,821 INFO L85 PathProgramCache]: Analyzing trace with hash 1357575776, now seen corresponding path program 1 times [2024-11-13 15:32:41,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:41,821 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [259390701] [2024-11-13 15:32:41,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:41,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:41,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:41,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:41,939 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:41,940 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [259390701] [2024-11-13 15:32:41,940 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [259390701] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:41,940 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:41,940 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:32:41,941 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1683178177] [2024-11-13 15:32:41,941 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:41,941 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:32:41,942 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:41,942 INFO L85 PathProgramCache]: Analyzing trace with hash -1484192068, now seen corresponding path program 1 times [2024-11-13 15:32:41,942 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:41,942 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1845644934] [2024-11-13 15:32:41,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:41,942 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:41,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:42,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:42,039 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:42,040 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1845644934] [2024-11-13 15:32:42,040 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1845644934] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:42,040 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:42,040 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:32:42,041 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [562005770] [2024-11-13 15:32:42,041 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:42,041 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:32:42,041 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:32:42,042 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:32:42,044 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:32:42,044 INFO L87 Difference]: Start difference. First operand 201 states and 296 transitions. cyclomatic complexity: 96 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:42,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:32:42,081 INFO L93 Difference]: Finished difference Result 201 states and 295 transitions. [2024-11-13 15:32:42,081 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 201 states and 295 transitions. [2024-11-13 15:32:42,084 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2024-11-13 15:32:42,086 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 201 states to 201 states and 295 transitions. [2024-11-13 15:32:42,089 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 201 [2024-11-13 15:32:42,089 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 201 [2024-11-13 15:32:42,090 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201 states and 295 transitions. [2024-11-13 15:32:42,091 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:32:42,094 INFO L218 hiAutomatonCegarLoop]: Abstraction has 201 states and 295 transitions. [2024-11-13 15:32:42,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states and 295 transitions. [2024-11-13 15:32:42,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 201. [2024-11-13 15:32:42,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 201 states, 201 states have (on average 1.4676616915422886) internal successors, (295), 200 states have internal predecessors, (295), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:42,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 295 transitions. [2024-11-13 15:32:42,109 INFO L240 hiAutomatonCegarLoop]: Abstraction has 201 states and 295 transitions. [2024-11-13 15:32:42,110 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:32:42,111 INFO L424 stractBuchiCegarLoop]: Abstraction has 201 states and 295 transitions. [2024-11-13 15:32:42,111 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 15:32:42,111 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 201 states and 295 transitions. [2024-11-13 15:32:42,113 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2024-11-13 15:32:42,113 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:42,113 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:42,115 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:42,115 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:42,115 INFO L745 eck$LassoCheckResult]: Stem: 1017#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1018#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1026#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1024#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1025#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 939#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 914#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 915#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 898#L334 assume !(0 == ~M_E~0); 899#L334-2 assume !(0 == ~T1_E~0); 994#L339-1 assume !(0 == ~T2_E~0); 988#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 989#L349-1 assume !(0 == ~E_2~0); 912#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 913#L156 assume !(1 == ~m_pc~0); 845#L156-2 is_master_triggered_~__retres1~0#1 := 0; 844#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1006#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 961#L405 assume !(0 != activate_threads_~tmp~1#1); 943#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 944#L175 assume 1 == ~t1_pc~0; 1003#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 945#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 909#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 910#L413 assume !(0 != activate_threads_~tmp___0~0#1); 996#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1033#L194 assume !(1 == ~t2_pc~0); 987#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 955#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 956#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 887#L421 assume !(0 != activate_threads_~tmp___1~0#1); 888#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 857#L367 assume !(1 == ~M_E~0); 858#L367-2 assume !(1 == ~T1_E~0); 1007#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1008#L377-1 assume !(1 == ~E_1~0); 884#L382-1 assume !(1 == ~E_2~0); 885#L387-1 assume { :end_inline_reset_delta_events } true; 874#L528-2 [2024-11-13 15:32:42,115 INFO L747 eck$LassoCheckResult]: Loop: 874#L528-2 assume !false; 968#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 867#L309-1 assume !false; 868#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 848#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 849#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 856#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 834#L276 assume !(0 != eval_~tmp~0#1); 836#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 964#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 993#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1027#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 997#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 998#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 960#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 896#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 897#L156-9 assume 1 == ~m_pc~0; 982#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 840#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 936#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 999#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 875#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 876#L175-9 assume 1 == ~t1_pc~0; 921#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 861#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 862#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1023#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1015#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1016#L194-9 assume 1 == ~t2_pc~0; 963#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 890#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 841#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 842#L421-9 assume !(0 != activate_threads_~tmp___1~0#1); 991#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 932#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 846#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 847#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 869#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 870#L382-3 assume !(1 == ~E_2~0); 893#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 992#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 901#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1032#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1022#L547 assume !(0 == start_simulation_~tmp~3#1); 1009#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1019#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 930#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 904#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 905#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 911#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 926#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 873#L560 assume !(0 != start_simulation_~tmp___0~1#1); 874#L528-2 [2024-11-13 15:32:42,116 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:42,116 INFO L85 PathProgramCache]: Analyzing trace with hash 1082816162, now seen corresponding path program 1 times [2024-11-13 15:32:42,116 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:42,116 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1255631002] [2024-11-13 15:32:42,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:42,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:42,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:42,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:42,256 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:42,256 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1255631002] [2024-11-13 15:32:42,256 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1255631002] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:42,256 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:42,256 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:32:42,256 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [578453287] [2024-11-13 15:32:42,256 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:42,257 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:32:42,257 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:42,257 INFO L85 PathProgramCache]: Analyzing trace with hash 106202909, now seen corresponding path program 1 times [2024-11-13 15:32:42,257 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:42,258 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [703511838] [2024-11-13 15:32:42,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:42,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:42,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:42,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:42,352 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:42,352 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [703511838] [2024-11-13 15:32:42,352 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [703511838] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:42,352 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:42,352 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:32:42,352 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2041260578] [2024-11-13 15:32:42,352 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:42,353 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:32:42,353 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:32:42,353 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:32:42,353 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:32:42,354 INFO L87 Difference]: Start difference. First operand 201 states and 295 transitions. cyclomatic complexity: 95 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:42,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:32:42,546 INFO L93 Difference]: Finished difference Result 342 states and 498 transitions. [2024-11-13 15:32:42,546 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 342 states and 498 transitions. [2024-11-13 15:32:42,549 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 296 [2024-11-13 15:32:42,556 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 342 states to 342 states and 498 transitions. [2024-11-13 15:32:42,556 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 342 [2024-11-13 15:32:42,557 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 342 [2024-11-13 15:32:42,557 INFO L73 IsDeterministic]: Start isDeterministic. Operand 342 states and 498 transitions. [2024-11-13 15:32:42,558 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:32:42,558 INFO L218 hiAutomatonCegarLoop]: Abstraction has 342 states and 498 transitions. [2024-11-13 15:32:42,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 342 states and 498 transitions. [2024-11-13 15:32:42,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 342 to 340. [2024-11-13 15:32:42,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 340 states, 340 states have (on average 1.4588235294117646) internal successors, (496), 339 states have internal predecessors, (496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:42,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340 states to 340 states and 496 transitions. [2024-11-13 15:32:42,590 INFO L240 hiAutomatonCegarLoop]: Abstraction has 340 states and 496 transitions. [2024-11-13 15:32:42,590 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:32:42,592 INFO L424 stractBuchiCegarLoop]: Abstraction has 340 states and 496 transitions. [2024-11-13 15:32:42,592 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 15:32:42,592 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 340 states and 496 transitions. [2024-11-13 15:32:42,595 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 296 [2024-11-13 15:32:42,595 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:42,595 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:42,599 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:42,599 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:42,599 INFO L745 eck$LassoCheckResult]: Stem: 1588#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1589#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1599#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1596#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1597#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 1495#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1468#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1469#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1452#L334 assume !(0 == ~M_E~0); 1453#L334-2 assume !(0 == ~T1_E~0); 1557#L339-1 assume !(0 == ~T2_E~0); 1550#L344-1 assume !(0 == ~E_1~0); 1551#L349-1 assume !(0 == ~E_2~0); 1466#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1467#L156 assume !(1 == ~m_pc~0); 1398#L156-2 is_master_triggered_~__retres1~0#1 := 0; 1397#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1573#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1519#L405 assume !(0 != activate_threads_~tmp~1#1); 1499#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1500#L175 assume 1 == ~t1_pc~0; 1570#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1501#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1463#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1464#L413 assume !(0 != activate_threads_~tmp___0~0#1); 1559#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1608#L194 assume !(1 == ~t2_pc~0); 1549#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1511#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1512#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1441#L421 assume !(0 != activate_threads_~tmp___1~0#1); 1442#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1411#L367 assume !(1 == ~M_E~0); 1412#L367-2 assume !(1 == ~T1_E~0); 1574#L372-1 assume !(1 == ~T2_E~0); 1575#L377-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1578#L382-1 assume !(1 == ~E_2~0); 1621#L387-1 assume { :end_inline_reset_delta_events } true; 1620#L528-2 [2024-11-13 15:32:42,600 INFO L747 eck$LassoCheckResult]: Loop: 1620#L528-2 assume !false; 1619#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1421#L309-1 assume !false; 1422#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1401#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1402#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1409#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1410#L276 assume !(0 != eval_~tmp~0#1); 1522#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1523#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1614#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1600#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1601#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1607#L344-3 assume !(0 == ~E_1~0); 1518#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1450#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1451#L156-9 assume !(1 == ~m_pc~0); 1392#L156-11 is_master_triggered_~__retres1~0#1 := 0; 1393#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1492#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1562#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1429#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1430#L175-9 assume 1 == ~t1_pc~0; 1611#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1658#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1657#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1656#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1655#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1654#L194-9 assume 1 == ~t2_pc~0; 1521#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1444#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1394#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1395#L421-9 assume !(0 != activate_threads_~tmp___1~0#1); 1553#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1488#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1399#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1400#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1423#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1424#L382-3 assume !(1 == ~E_2~0); 1447#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1554#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1455#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1606#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1594#L547 assume !(0 == start_simulation_~tmp~3#1); 1577#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1591#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1486#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1458#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 1459#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1465#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1482#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1566#L560 assume !(0 != start_simulation_~tmp___0~1#1); 1620#L528-2 [2024-11-13 15:32:42,602 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:42,602 INFO L85 PathProgramCache]: Analyzing trace with hash -1288865440, now seen corresponding path program 1 times [2024-11-13 15:32:42,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:42,602 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1153757953] [2024-11-13 15:32:42,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:42,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:42,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:42,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:42,657 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:42,657 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1153757953] [2024-11-13 15:32:42,657 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1153757953] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:42,657 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:42,657 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:32:42,658 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1501299497] [2024-11-13 15:32:42,658 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:42,658 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:32:42,658 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:42,658 INFO L85 PathProgramCache]: Analyzing trace with hash 790986430, now seen corresponding path program 1 times [2024-11-13 15:32:42,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:42,659 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1199107602] [2024-11-13 15:32:42,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:42,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:42,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:42,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:42,718 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:42,718 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1199107602] [2024-11-13 15:32:42,718 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1199107602] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:42,718 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:42,718 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:32:42,718 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [735941014] [2024-11-13 15:32:42,719 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:42,719 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:32:42,719 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:32:42,719 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:32:42,719 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:32:42,720 INFO L87 Difference]: Start difference. First operand 340 states and 496 transitions. cyclomatic complexity: 158 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 2 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:42,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:32:42,783 INFO L93 Difference]: Finished difference Result 582 states and 842 transitions. [2024-11-13 15:32:42,783 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 582 states and 842 transitions. [2024-11-13 15:32:42,791 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 535 [2024-11-13 15:32:42,796 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 582 states to 582 states and 842 transitions. [2024-11-13 15:32:42,797 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 582 [2024-11-13 15:32:42,798 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 582 [2024-11-13 15:32:42,799 INFO L73 IsDeterministic]: Start isDeterministic. Operand 582 states and 842 transitions. [2024-11-13 15:32:42,800 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:32:42,801 INFO L218 hiAutomatonCegarLoop]: Abstraction has 582 states and 842 transitions. [2024-11-13 15:32:42,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 582 states and 842 transitions. [2024-11-13 15:32:42,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 582 to 578. [2024-11-13 15:32:42,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 578 states, 578 states have (on average 1.4498269896193772) internal successors, (838), 577 states have internal predecessors, (838), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:42,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 578 states to 578 states and 838 transitions. [2024-11-13 15:32:42,838 INFO L240 hiAutomatonCegarLoop]: Abstraction has 578 states and 838 transitions. [2024-11-13 15:32:42,838 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:32:42,839 INFO L424 stractBuchiCegarLoop]: Abstraction has 578 states and 838 transitions. [2024-11-13 15:32:42,839 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 15:32:42,840 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 578 states and 838 transitions. [2024-11-13 15:32:42,844 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 531 [2024-11-13 15:32:42,844 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:42,844 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:42,872 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:42,872 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:42,872 INFO L745 eck$LassoCheckResult]: Stem: 2525#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2526#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2541#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2536#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2537#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 2429#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2398#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2399#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2381#L334 assume !(0 == ~M_E~0); 2382#L334-2 assume !(0 == ~T1_E~0); 2493#L339-1 assume !(0 == ~T2_E~0); 2487#L344-1 assume !(0 == ~E_1~0); 2488#L349-1 assume !(0 == ~E_2~0); 2396#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2397#L156 assume !(1 == ~m_pc~0); 2329#L156-2 is_master_triggered_~__retres1~0#1 := 0; 2328#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2507#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2452#L405 assume !(0 != activate_threads_~tmp~1#1); 2437#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2438#L175 assume !(1 == ~t1_pc~0); 2442#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2439#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2393#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2394#L413 assume !(0 != activate_threads_~tmp___0~0#1); 2495#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2555#L194 assume !(1 == ~t2_pc~0); 2484#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2447#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2448#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2370#L421 assume !(0 != activate_threads_~tmp___1~0#1); 2371#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2339#L367 assume !(1 == ~M_E~0); 2340#L367-2 assume !(1 == ~T1_E~0); 2508#L372-1 assume !(1 == ~T2_E~0); 2509#L377-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2367#L382-1 assume !(1 == ~E_2~0); 2368#L387-1 assume { :end_inline_reset_delta_events } true; 2485#L528-2 [2024-11-13 15:32:42,873 INFO L747 eck$LassoCheckResult]: Loop: 2485#L528-2 assume !false; 2486#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2795#L309-1 assume !false; 2405#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2406#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2503#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2504#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2316#L276 assume !(0 != eval_~tmp~0#1); 2318#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2458#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2492#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2542#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2496#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2497#L344-3 assume !(0 == ~E_1~0); 2451#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2379#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2380#L156-9 assume !(1 == ~m_pc~0); 2321#L156-11 is_master_triggered_~__retres1~0#1 := 0; 2322#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2426#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2499#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2358#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2359#L175-9 assume !(1 == ~t1_pc~0); 2557#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 2702#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2701#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2700#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2699#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2698#L194-9 assume 1 == ~t2_pc~0; 2696#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2694#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2692#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2690#L421-9 assume !(0 != activate_threads_~tmp___1~0#1); 2688#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2684#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2681#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2678#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2675#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2672#L382-3 assume !(1 == ~E_2~0); 2669#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2663#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2659#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2556#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 2533#L547 assume !(0 == start_simulation_~tmp~3#1); 2511#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2530#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2415#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2388#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 2389#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2395#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2635#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2636#L560 assume !(0 != start_simulation_~tmp___0~1#1); 2485#L528-2 [2024-11-13 15:32:42,873 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:42,873 INFO L85 PathProgramCache]: Analyzing trace with hash -148513729, now seen corresponding path program 1 times [2024-11-13 15:32:42,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:42,873 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529355665] [2024-11-13 15:32:42,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:42,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:42,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:42,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:42,969 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:42,969 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1529355665] [2024-11-13 15:32:42,970 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1529355665] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:42,970 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:42,970 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:32:42,970 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1593785696] [2024-11-13 15:32:42,970 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:42,970 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:32:42,971 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:42,971 INFO L85 PathProgramCache]: Analyzing trace with hash 733842205, now seen corresponding path program 1 times [2024-11-13 15:32:42,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:42,971 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [776248242] [2024-11-13 15:32:42,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:42,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:42,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:43,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:43,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:43,032 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [776248242] [2024-11-13 15:32:43,033 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [776248242] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:43,033 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:43,033 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:32:43,033 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [211061895] [2024-11-13 15:32:43,033 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:43,033 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:32:43,033 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:32:43,034 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:32:43,034 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:32:43,034 INFO L87 Difference]: Start difference. First operand 578 states and 838 transitions. cyclomatic complexity: 264 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:43,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:32:43,160 INFO L93 Difference]: Finished difference Result 592 states and 834 transitions. [2024-11-13 15:32:43,160 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 592 states and 834 transitions. [2024-11-13 15:32:43,165 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 544 [2024-11-13 15:32:43,171 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 592 states to 592 states and 834 transitions. [2024-11-13 15:32:43,171 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 592 [2024-11-13 15:32:43,172 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 592 [2024-11-13 15:32:43,172 INFO L73 IsDeterministic]: Start isDeterministic. Operand 592 states and 834 transitions. [2024-11-13 15:32:43,174 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:32:43,175 INFO L218 hiAutomatonCegarLoop]: Abstraction has 592 states and 834 transitions. [2024-11-13 15:32:43,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 592 states and 834 transitions. [2024-11-13 15:32:43,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 592 to 575. [2024-11-13 15:32:43,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 575 states, 575 states have (on average 1.413913043478261) internal successors, (813), 574 states have internal predecessors, (813), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:43,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 575 states to 575 states and 813 transitions. [2024-11-13 15:32:43,198 INFO L240 hiAutomatonCegarLoop]: Abstraction has 575 states and 813 transitions. [2024-11-13 15:32:43,199 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:32:43,201 INFO L424 stractBuchiCegarLoop]: Abstraction has 575 states and 813 transitions. [2024-11-13 15:32:43,202 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 15:32:43,202 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 575 states and 813 transitions. [2024-11-13 15:32:43,206 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 531 [2024-11-13 15:32:43,206 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:43,206 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:43,210 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:43,210 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:43,210 INFO L745 eck$LassoCheckResult]: Stem: 3701#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 3702#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 3713#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3709#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3710#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 3602#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3576#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3577#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3559#L334 assume !(0 == ~M_E~0); 3560#L334-2 assume !(0 == ~T1_E~0); 3670#L339-1 assume !(0 == ~T2_E~0); 3662#L344-1 assume !(0 == ~E_1~0); 3663#L349-1 assume !(0 == ~E_2~0); 3574#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3575#L156 assume !(1 == ~m_pc~0); 3509#L156-2 is_master_triggered_~__retres1~0#1 := 0; 3508#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3684#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3628#L405 assume !(0 != activate_threads_~tmp~1#1); 3610#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3611#L175 assume !(1 == ~t1_pc~0); 3615#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3612#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3570#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3571#L413 assume !(0 != activate_threads_~tmp___0~0#1); 3674#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3727#L194 assume !(1 == ~t2_pc~0); 3659#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3622#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3623#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3548#L421 assume !(0 != activate_threads_~tmp___1~0#1); 3549#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3520#L367 assume !(1 == ~M_E~0); 3521#L367-2 assume !(1 == ~T1_E~0); 3685#L372-1 assume !(1 == ~T2_E~0); 3686#L377-1 assume !(1 == ~E_1~0); 3545#L382-1 assume !(1 == ~E_2~0); 3546#L387-1 assume { :end_inline_reset_delta_events } true; 3535#L528-2 [2024-11-13 15:32:43,211 INFO L747 eck$LassoCheckResult]: Loop: 3535#L528-2 assume !false; 3812#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3805#L309-1 assume !false; 3784#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3785#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3681#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3517#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3496#L276 assume !(0 != eval_~tmp~0#1); 3498#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3798#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3796#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3794#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3792#L339-3 assume !(0 == ~T2_E~0); 3786#L344-3 assume !(0 == ~E_1~0); 3787#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3557#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3558#L156-9 assume 1 == ~m_pc~0; 3652#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3865#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3690#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3675#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3676#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3728#L175-9 assume !(1 == ~t1_pc~0); 3729#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 4070#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3741#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3708#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3696#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3697#L194-9 assume !(1 == ~t2_pc~0); 3550#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 3551#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3503#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3504#L421-9 assume !(0 != activate_threads_~tmp___1~0#1); 4062#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3595#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3505#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3506#L372-3 assume !(1 == ~T2_E~0); 3530#L377-3 assume !(1 == ~E_1~0); 3531#L382-3 assume !(1 == ~E_2~0); 3554#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3668#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3562#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3725#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 3706#L547 assume !(0 == start_simulation_~tmp~3#1); 3707#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3908#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3904#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3900#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 3572#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3573#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3589#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3534#L560 assume !(0 != start_simulation_~tmp___0~1#1); 3535#L528-2 [2024-11-13 15:32:43,214 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:43,214 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 1 times [2024-11-13 15:32:43,214 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:43,214 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2061879991] [2024-11-13 15:32:43,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:43,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:43,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:43,230 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:32:43,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:43,271 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:32:43,272 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:43,272 INFO L85 PathProgramCache]: Analyzing trace with hash 1530491803, now seen corresponding path program 1 times [2024-11-13 15:32:43,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:43,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2005426472] [2024-11-13 15:32:43,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:43,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:43,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:43,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:43,334 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:43,334 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2005426472] [2024-11-13 15:32:43,334 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2005426472] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:43,334 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:43,334 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:32:43,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1282234003] [2024-11-13 15:32:43,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:43,335 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:32:43,336 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:32:43,337 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:32:43,337 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:32:43,337 INFO L87 Difference]: Start difference. First operand 575 states and 813 transitions. cyclomatic complexity: 242 Second operand has 3 states, 3 states have (on average 17.333333333333332) internal successors, (52), 3 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:43,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:32:43,411 INFO L93 Difference]: Finished difference Result 866 states and 1209 transitions. [2024-11-13 15:32:43,411 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 866 states and 1209 transitions. [2024-11-13 15:32:43,418 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 794 [2024-11-13 15:32:43,424 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 866 states to 866 states and 1209 transitions. [2024-11-13 15:32:43,424 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 866 [2024-11-13 15:32:43,427 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 866 [2024-11-13 15:32:43,427 INFO L73 IsDeterministic]: Start isDeterministic. Operand 866 states and 1209 transitions. [2024-11-13 15:32:43,430 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:32:43,430 INFO L218 hiAutomatonCegarLoop]: Abstraction has 866 states and 1209 transitions. [2024-11-13 15:32:43,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 866 states and 1209 transitions. [2024-11-13 15:32:43,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 866 to 865. [2024-11-13 15:32:43,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 865 states, 865 states have (on average 1.3965317919075144) internal successors, (1208), 864 states have internal predecessors, (1208), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:43,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 865 states to 865 states and 1208 transitions. [2024-11-13 15:32:43,451 INFO L240 hiAutomatonCegarLoop]: Abstraction has 865 states and 1208 transitions. [2024-11-13 15:32:43,452 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:32:43,452 INFO L424 stractBuchiCegarLoop]: Abstraction has 865 states and 1208 transitions. [2024-11-13 15:32:43,452 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 15:32:43,453 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 865 states and 1208 transitions. [2024-11-13 15:32:43,458 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 793 [2024-11-13 15:32:43,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:43,459 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:43,460 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:43,460 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:43,460 INFO L745 eck$LassoCheckResult]: Stem: 5152#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 5153#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 5163#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5160#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5161#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 5053#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5023#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5024#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5006#L334 assume !(0 == ~M_E~0); 5007#L334-2 assume !(0 == ~T1_E~0); 5117#L339-1 assume !(0 == ~T2_E~0); 5111#L344-1 assume !(0 == ~E_1~0); 5112#L349-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5145#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5204#L156 assume !(1 == ~m_pc~0); 4954#L156-2 is_master_triggered_~__retres1~0#1 := 0; 4953#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5202#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5079#L405 assume !(0 != activate_threads_~tmp~1#1); 5058#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5059#L175 assume !(1 == ~t1_pc~0); 5067#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5060#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5061#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5197#L413 assume !(0 != activate_threads_~tmp___0~0#1); 5174#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5175#L194 assume !(1 == ~t2_pc~0); 5176#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5070#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5071#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4995#L421 assume !(0 != activate_threads_~tmp___1~0#1); 4996#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4965#L367 assume !(1 == ~M_E~0); 4966#L367-2 assume !(1 == ~T1_E~0); 5134#L372-1 assume !(1 == ~T2_E~0); 5135#L377-1 assume !(1 == ~E_1~0); 4992#L382-1 assume 1 == ~E_2~0;~E_2~0 := 2; 4993#L387-1 assume { :end_inline_reset_delta_events } true; 5082#L528-2 [2024-11-13 15:32:43,461 INFO L747 eck$LassoCheckResult]: Loop: 5082#L528-2 assume !false; 5565#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5556#L309-1 assume !false; 5254#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5255#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5544#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5543#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5541#L276 assume !(0 != eval_~tmp~0#1); 5542#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5667#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5665#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5664#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5663#L339-3 assume !(0 == ~T2_E~0); 5662#L344-3 assume !(0 == ~E_1~0); 5660#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5659#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5658#L156-9 assume 1 == ~m_pc~0; 5656#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5655#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5654#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5653#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5651#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5648#L175-9 assume !(1 == ~t1_pc~0); 5646#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 5644#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5642#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5640#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5638#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5636#L194-9 assume 1 == ~t2_pc~0; 5633#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5631#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5629#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5627#L421-9 assume !(0 != activate_threads_~tmp___1~0#1); 5623#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5621#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5619#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5617#L372-3 assume !(1 == ~T2_E~0); 5615#L377-3 assume !(1 == ~E_1~0); 5613#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5610#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5606#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5603#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5600#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 5598#L547 assume !(0 == start_simulation_~tmp~3#1); 5596#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5594#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5592#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5590#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 5589#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5588#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5586#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5584#L560 assume !(0 != start_simulation_~tmp___0~1#1); 5082#L528-2 [2024-11-13 15:32:43,461 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:43,461 INFO L85 PathProgramCache]: Analyzing trace with hash -210551483, now seen corresponding path program 1 times [2024-11-13 15:32:43,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:43,462 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [755533521] [2024-11-13 15:32:43,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:43,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:43,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:43,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:43,507 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:43,507 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [755533521] [2024-11-13 15:32:43,508 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [755533521] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:43,508 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:43,508 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:32:43,508 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [691405856] [2024-11-13 15:32:43,508 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:43,509 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:32:43,509 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:43,509 INFO L85 PathProgramCache]: Analyzing trace with hash -162963266, now seen corresponding path program 1 times [2024-11-13 15:32:43,509 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:43,509 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [337620359] [2024-11-13 15:32:43,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:43,510 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:43,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:43,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:43,589 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:43,589 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [337620359] [2024-11-13 15:32:43,589 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [337620359] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:43,589 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:43,589 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:32:43,589 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1762292478] [2024-11-13 15:32:43,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:43,590 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:32:43,590 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:32:43,590 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:32:43,591 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:32:43,591 INFO L87 Difference]: Start difference. First operand 865 states and 1208 transitions. cyclomatic complexity: 347 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 2 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:43,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:32:43,654 INFO L93 Difference]: Finished difference Result 575 states and 786 transitions. [2024-11-13 15:32:43,654 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 575 states and 786 transitions. [2024-11-13 15:32:43,659 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 531 [2024-11-13 15:32:43,662 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 575 states to 575 states and 786 transitions. [2024-11-13 15:32:43,662 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 575 [2024-11-13 15:32:43,663 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 575 [2024-11-13 15:32:43,663 INFO L73 IsDeterministic]: Start isDeterministic. Operand 575 states and 786 transitions. [2024-11-13 15:32:43,664 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:32:43,664 INFO L218 hiAutomatonCegarLoop]: Abstraction has 575 states and 786 transitions. [2024-11-13 15:32:43,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 575 states and 786 transitions. [2024-11-13 15:32:43,677 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 575 to 575. [2024-11-13 15:32:43,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 575 states, 575 states have (on average 1.3669565217391304) internal successors, (786), 574 states have internal predecessors, (786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:43,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 575 states to 575 states and 786 transitions. [2024-11-13 15:32:43,681 INFO L240 hiAutomatonCegarLoop]: Abstraction has 575 states and 786 transitions. [2024-11-13 15:32:43,681 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:32:43,682 INFO L424 stractBuchiCegarLoop]: Abstraction has 575 states and 786 transitions. [2024-11-13 15:32:43,682 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 15:32:43,682 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 575 states and 786 transitions. [2024-11-13 15:32:43,686 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 531 [2024-11-13 15:32:43,686 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:43,687 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:43,688 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:43,688 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:43,688 INFO L745 eck$LassoCheckResult]: Stem: 6598#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 6599#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6610#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6605#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6606#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 6499#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6473#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6474#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6456#L334 assume !(0 == ~M_E~0); 6457#L334-2 assume !(0 == ~T1_E~0); 6567#L339-1 assume !(0 == ~T2_E~0); 6560#L344-1 assume !(0 == ~E_1~0); 6561#L349-1 assume !(0 == ~E_2~0); 6471#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6472#L156 assume !(1 == ~m_pc~0); 6405#L156-2 is_master_triggered_~__retres1~0#1 := 0; 6404#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6580#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6525#L405 assume !(0 != activate_threads_~tmp~1#1); 6507#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6508#L175 assume !(1 == ~t1_pc~0); 6512#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6509#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6467#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6468#L413 assume !(0 != activate_threads_~tmp___0~0#1); 6571#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6623#L194 assume !(1 == ~t2_pc~0); 6558#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6516#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6517#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6445#L421 assume !(0 != activate_threads_~tmp___1~0#1); 6446#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6415#L367 assume !(1 == ~M_E~0); 6416#L367-2 assume !(1 == ~T1_E~0); 6581#L372-1 assume !(1 == ~T2_E~0); 6582#L377-1 assume !(1 == ~E_1~0); 6442#L382-1 assume !(1 == ~E_2~0); 6443#L387-1 assume { :end_inline_reset_delta_events } true; 6527#L528-2 [2024-11-13 15:32:43,688 INFO L747 eck$LassoCheckResult]: Loop: 6527#L528-2 assume !false; 6784#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6780#L309-1 assume !false; 6663#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6664#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6655#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6656#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6651#L276 assume !(0 != eval_~tmp~0#1); 6652#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6692#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6690#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6688#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6686#L339-3 assume !(0 == ~T2_E~0); 6682#L344-3 assume !(0 == ~E_1~0); 6683#L349-3 assume !(0 == ~E_2~0); 6678#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6679#L156-9 assume 1 == ~m_pc~0; 6672#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6673#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6668#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6669#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6433#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6434#L175-9 assume !(1 == ~t1_pc~0); 6625#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 6849#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6848#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6847#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6846#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6844#L194-9 assume !(1 == ~t2_pc~0); 6841#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 6839#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6837#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6834#L421-9 assume !(0 != activate_threads_~tmp___1~0#1); 6832#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6830#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6828#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6826#L372-3 assume !(1 == ~T2_E~0); 6824#L377-3 assume !(1 == ~E_1~0); 6822#L382-3 assume !(1 == ~E_2~0); 6820#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6815#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6812#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6811#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 6806#L547 assume !(0 == start_simulation_~tmp~3#1); 6807#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6809#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6805#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6803#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 6801#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6798#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6795#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6792#L560 assume !(0 != start_simulation_~tmp___0~1#1); 6527#L528-2 [2024-11-13 15:32:43,689 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:43,689 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 2 times [2024-11-13 15:32:43,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:43,689 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1909758781] [2024-11-13 15:32:43,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:43,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:43,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:43,704 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:32:43,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:43,726 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:32:43,727 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:43,727 INFO L85 PathProgramCache]: Analyzing trace with hash 501132505, now seen corresponding path program 1 times [2024-11-13 15:32:43,727 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:43,728 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192816263] [2024-11-13 15:32:43,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:43,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:43,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:43,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:43,847 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:43,847 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1192816263] [2024-11-13 15:32:43,848 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1192816263] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:43,848 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:43,848 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:32:43,848 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [222860079] [2024-11-13 15:32:43,848 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:43,848 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:32:43,848 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:32:43,849 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:32:43,849 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:32:43,849 INFO L87 Difference]: Start difference. First operand 575 states and 786 transitions. cyclomatic complexity: 215 Second operand has 5 states, 5 states have (on average 10.4) internal successors, (52), 5 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:43,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:32:43,933 INFO L93 Difference]: Finished difference Result 603 states and 814 transitions. [2024-11-13 15:32:43,933 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 603 states and 814 transitions. [2024-11-13 15:32:43,939 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 559 [2024-11-13 15:32:43,943 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 603 states to 603 states and 814 transitions. [2024-11-13 15:32:43,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 603 [2024-11-13 15:32:43,944 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 603 [2024-11-13 15:32:43,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 603 states and 814 transitions. [2024-11-13 15:32:43,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:32:43,946 INFO L218 hiAutomatonCegarLoop]: Abstraction has 603 states and 814 transitions. [2024-11-13 15:32:43,948 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 603 states and 814 transitions. [2024-11-13 15:32:43,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 603 to 587. [2024-11-13 15:32:43,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 587 states, 587 states have (on average 1.3594548551959114) internal successors, (798), 586 states have internal predecessors, (798), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:43,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 587 states and 798 transitions. [2024-11-13 15:32:43,966 INFO L240 hiAutomatonCegarLoop]: Abstraction has 587 states and 798 transitions. [2024-11-13 15:32:43,966 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:32:43,969 INFO L424 stractBuchiCegarLoop]: Abstraction has 587 states and 798 transitions. [2024-11-13 15:32:43,969 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 15:32:43,970 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 587 states and 798 transitions. [2024-11-13 15:32:43,975 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 543 [2024-11-13 15:32:43,976 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:43,976 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:43,979 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:43,979 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:43,979 INFO L745 eck$LassoCheckResult]: Stem: 7790#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 7791#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 7803#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7800#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7801#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 7686#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7658#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7659#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7641#L334 assume !(0 == ~M_E~0); 7642#L334-2 assume !(0 == ~T1_E~0); 7758#L339-1 assume !(0 == ~T2_E~0); 7751#L344-1 assume !(0 == ~E_1~0); 7752#L349-1 assume !(0 == ~E_2~0); 7656#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7657#L156 assume !(1 == ~m_pc~0); 7590#L156-2 is_master_triggered_~__retres1~0#1 := 0; 7589#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7772#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 7714#L405 assume !(0 != activate_threads_~tmp~1#1); 7694#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7695#L175 assume !(1 == ~t1_pc~0); 7699#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7696#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7652#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7653#L413 assume !(0 != activate_threads_~tmp___0~0#1); 7762#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7820#L194 assume !(1 == ~t2_pc~0); 7750#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7704#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7705#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7630#L421 assume !(0 != activate_threads_~tmp___1~0#1); 7631#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7602#L367 assume !(1 == ~M_E~0); 7603#L367-2 assume !(1 == ~T1_E~0); 7773#L372-1 assume !(1 == ~T2_E~0); 7774#L377-1 assume !(1 == ~E_1~0); 7627#L382-1 assume !(1 == ~E_2~0); 7628#L387-1 assume { :end_inline_reset_delta_events } true; 7617#L528-2 [2024-11-13 15:32:43,979 INFO L747 eck$LassoCheckResult]: Loop: 7617#L528-2 assume !false; 7725#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7710#L309-1 assume !false; 7662#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7591#L244 assume !(0 == ~m_st~0); 7593#L248 assume !(0 == ~t1_st~0); 7768#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 7810#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8004#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8003#L276 assume !(0 != eval_~tmp~0#1); 7988#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7986#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7984#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7889#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7886#L339-3 assume !(0 == ~T2_E~0); 7882#L344-3 assume !(0 == ~E_1~0); 7883#L349-3 assume !(0 == ~E_2~0); 7876#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7877#L156-9 assume !(1 == ~m_pc~0); 8128#L156-11 is_master_triggered_~__retres1~0#1 := 0; 8126#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8125#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8124#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8123#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7825#L175-9 assume !(1 == ~t1_pc~0); 7785#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 7604#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7605#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7799#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7788#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7789#L194-9 assume !(1 == ~t2_pc~0); 8087#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 8085#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8083#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8081#L421-9 assume !(0 != activate_threads_~tmp___1~0#1); 8079#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8078#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8077#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8076#L372-3 assume !(1 == ~T2_E~0); 8075#L377-3 assume !(1 == ~E_1~0); 8062#L382-3 assume !(1 == ~E_2~0); 8061#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8059#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 8057#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7821#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 7822#L547 assume !(0 == start_simulation_~tmp~3#1); 8010#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8008#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 8005#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8002#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 7654#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7655#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8000#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 7616#L560 assume !(0 != start_simulation_~tmp___0~1#1); 7617#L528-2 [2024-11-13 15:32:43,980 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:43,980 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 3 times [2024-11-13 15:32:43,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:43,980 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1037129076] [2024-11-13 15:32:43,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:43,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:44,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:44,002 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:32:44,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:44,024 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:32:44,024 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:44,025 INFO L85 PathProgramCache]: Analyzing trace with hash -164321199, now seen corresponding path program 1 times [2024-11-13 15:32:44,025 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:44,025 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [936757210] [2024-11-13 15:32:44,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:44,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:44,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:44,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:44,141 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:44,141 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [936757210] [2024-11-13 15:32:44,141 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [936757210] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:44,142 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:44,142 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:32:44,142 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [937159537] [2024-11-13 15:32:44,142 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:44,142 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:32:44,142 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:32:44,143 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:32:44,143 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:32:44,143 INFO L87 Difference]: Start difference. First operand 587 states and 798 transitions. cyclomatic complexity: 215 Second operand has 5 states, 5 states have (on average 10.8) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:44,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:32:44,282 INFO L93 Difference]: Finished difference Result 626 states and 837 transitions. [2024-11-13 15:32:44,282 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 837 transitions. [2024-11-13 15:32:44,287 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 579 [2024-11-13 15:32:44,291 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 837 transitions. [2024-11-13 15:32:44,291 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2024-11-13 15:32:44,292 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2024-11-13 15:32:44,292 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 837 transitions. [2024-11-13 15:32:44,293 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:32:44,293 INFO L218 hiAutomatonCegarLoop]: Abstraction has 626 states and 837 transitions. [2024-11-13 15:32:44,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 837 transitions. [2024-11-13 15:32:44,306 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2024-11-13 15:32:44,307 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.3370607028753994) internal successors, (837), 625 states have internal predecessors, (837), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:44,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 837 transitions. [2024-11-13 15:32:44,311 INFO L240 hiAutomatonCegarLoop]: Abstraction has 626 states and 837 transitions. [2024-11-13 15:32:44,311 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:32:44,312 INFO L424 stractBuchiCegarLoop]: Abstraction has 626 states and 837 transitions. [2024-11-13 15:32:44,313 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 15:32:44,313 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 837 transitions. [2024-11-13 15:32:44,318 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 579 [2024-11-13 15:32:44,318 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:44,318 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:44,319 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:44,319 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:44,319 INFO L745 eck$LassoCheckResult]: Stem: 9005#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 9006#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 9017#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9013#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9014#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 8908#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8880#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8881#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8862#L334 assume !(0 == ~M_E~0); 8863#L334-2 assume !(0 == ~T1_E~0); 8974#L339-1 assume !(0 == ~T2_E~0); 8968#L344-1 assume !(0 == ~E_1~0); 8969#L349-1 assume !(0 == ~E_2~0); 8878#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8879#L156 assume !(1 == ~m_pc~0); 8811#L156-2 is_master_triggered_~__retres1~0#1 := 0; 8995#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8987#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8934#L405 assume !(0 != activate_threads_~tmp~1#1); 8913#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8914#L175 assume !(1 == ~t1_pc~0); 8921#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8915#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8875#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8876#L413 assume !(0 != activate_threads_~tmp___0~0#1); 8976#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9032#L194 assume !(1 == ~t2_pc~0); 8966#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8924#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8925#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8851#L421 assume !(0 != activate_threads_~tmp___1~0#1); 8852#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8820#L367 assume !(1 == ~M_E~0); 8821#L367-2 assume !(1 == ~T1_E~0); 8988#L372-1 assume !(1 == ~T2_E~0); 8989#L377-1 assume !(1 == ~E_1~0); 8848#L382-1 assume !(1 == ~E_2~0); 8849#L387-1 assume { :end_inline_reset_delta_events } true; 8838#L528-2 [2024-11-13 15:32:44,323 INFO L747 eck$LassoCheckResult]: Loop: 8838#L528-2 assume !false; 8967#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9405#L309-1 assume !false; 9404#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8812#L244 assume !(0 == ~m_st~0); 8814#L248 assume !(0 == ~t1_st~0); 8984#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 9023#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 9381#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9365#L276 assume !(0 != eval_~tmp~0#1); 8937#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8938#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8973#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9018#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8977#L339-3 assume !(0 == ~T2_E~0); 8978#L344-3 assume !(0 == ~E_1~0); 8931#L349-3 assume !(0 == ~E_2~0); 8860#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8861#L156-9 assume !(1 == ~m_pc~0); 8803#L156-11 is_master_triggered_~__retres1~0#1 := 0; 8804#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8904#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8979#L405-9 assume !(0 != activate_threads_~tmp~1#1); 8839#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8840#L175-9 assume !(1 == ~t1_pc~0); 8998#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 8824#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8825#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 9012#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9002#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9003#L194-9 assume !(1 == ~t2_pc~0); 8853#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 8854#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8805#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8806#L421-9 assume !(0 != activate_threads_~tmp___1~0#1); 8971#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8899#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8900#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8864#L372-3 assume !(1 == ~T2_E~0); 8865#L377-3 assume !(1 == ~E_1~0); 9358#L382-3 assume !(1 == ~E_2~0); 9357#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 9000#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 8867#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 9030#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 9011#L547 assume !(0 == start_simulation_~tmp~3#1); 8990#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 9007#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 8898#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8870#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 8871#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8877#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8893#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 8837#L560 assume !(0 != start_simulation_~tmp___0~1#1); 8838#L528-2 [2024-11-13 15:32:44,324 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:44,324 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 4 times [2024-11-13 15:32:44,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:44,324 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [115228951] [2024-11-13 15:32:44,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:44,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:44,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:44,337 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:32:44,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:44,354 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:32:44,355 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:44,355 INFO L85 PathProgramCache]: Analyzing trace with hash 110438415, now seen corresponding path program 1 times [2024-11-13 15:32:44,356 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:44,356 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [440001824] [2024-11-13 15:32:44,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:44,356 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:44,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:44,405 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:44,405 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:44,405 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [440001824] [2024-11-13 15:32:44,405 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [440001824] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:44,405 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:44,406 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:32:44,406 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1883017296] [2024-11-13 15:32:44,406 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:44,406 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:32:44,406 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:32:44,406 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:32:44,407 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:32:44,407 INFO L87 Difference]: Start difference. First operand 626 states and 837 transitions. cyclomatic complexity: 215 Second operand has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:44,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:32:44,466 INFO L93 Difference]: Finished difference Result 1063 states and 1390 transitions. [2024-11-13 15:32:44,466 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1063 states and 1390 transitions. [2024-11-13 15:32:44,475 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1012 [2024-11-13 15:32:44,481 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1063 states to 1063 states and 1390 transitions. [2024-11-13 15:32:44,482 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1063 [2024-11-13 15:32:44,483 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1063 [2024-11-13 15:32:44,483 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1063 states and 1390 transitions. [2024-11-13 15:32:44,486 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:32:44,486 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1063 states and 1390 transitions. [2024-11-13 15:32:44,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1063 states and 1390 transitions. [2024-11-13 15:32:44,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1063 to 1028. [2024-11-13 15:32:44,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1028 states, 1028 states have (on average 1.3103112840466926) internal successors, (1347), 1027 states have internal predecessors, (1347), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:44,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1028 states to 1028 states and 1347 transitions. [2024-11-13 15:32:44,514 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1028 states and 1347 transitions. [2024-11-13 15:32:44,514 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:32:44,515 INFO L424 stractBuchiCegarLoop]: Abstraction has 1028 states and 1347 transitions. [2024-11-13 15:32:44,515 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 15:32:44,515 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1028 states and 1347 transitions. [2024-11-13 15:32:44,523 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 977 [2024-11-13 15:32:44,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:44,523 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:44,524 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:44,524 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:44,524 INFO L745 eck$LassoCheckResult]: Stem: 10695#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 10696#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 10705#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10703#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10704#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 10597#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10571#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10572#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10555#L334 assume !(0 == ~M_E~0); 10556#L334-2 assume !(0 == ~T1_E~0); 10663#L339-1 assume !(0 == ~T2_E~0); 10657#L344-1 assume !(0 == ~E_1~0); 10658#L349-1 assume !(0 == ~E_2~0); 10569#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10570#L156 assume !(1 == ~m_pc~0); 10504#L156-2 is_master_triggered_~__retres1~0#1 := 0; 10686#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10677#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10624#L405 assume !(0 != activate_threads_~tmp~1#1); 10602#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10603#L175 assume !(1 == ~t1_pc~0); 10610#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10604#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10566#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10567#L413 assume !(0 != activate_threads_~tmp___0~0#1); 10665#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10720#L194 assume !(1 == ~t2_pc~0); 10656#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10615#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10616#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10544#L421 assume !(0 != activate_threads_~tmp___1~0#1); 10545#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10516#L367 assume !(1 == ~M_E~0); 10517#L367-2 assume !(1 == ~T1_E~0); 10679#L372-1 assume !(1 == ~T2_E~0); 10680#L377-1 assume !(1 == ~E_1~0); 10541#L382-1 assume !(1 == ~E_2~0); 10542#L387-1 assume { :end_inline_reset_delta_events } true; 10627#L528-2 [2024-11-13 15:32:44,525 INFO L747 eck$LassoCheckResult]: Loop: 10627#L528-2 assume !false; 11255#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11250#L309-1 assume !false; 11246#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11243#L244 assume !(0 == ~m_st~0); 10508#L248 assume !(0 == ~t1_st~0); 10673#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 10711#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11231#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11219#L276 assume !(0 != eval_~tmp~0#1); 10629#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10630#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10662#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10706#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10666#L339-3 assume !(0 == ~T2_E~0); 10667#L344-3 assume !(0 == ~E_1~0); 10621#L349-3 assume !(0 == ~E_2~0); 10553#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10554#L156-9 assume 1 == ~m_pc~0; 10650#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10671#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10684#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10685#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11506#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11511#L175-9 assume !(1 == ~t1_pc~0); 11510#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 11507#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10729#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10730#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11469#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11439#L194-9 assume !(1 == ~t2_pc~0); 11435#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 11433#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11431#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11429#L421-9 assume !(0 != activate_threads_~tmp___1~0#1); 11427#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11425#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11417#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11413#L372-3 assume !(1 == ~T2_E~0); 11351#L377-3 assume !(1 == ~E_1~0); 11345#L382-3 assume !(1 == ~E_2~0); 11339#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11330#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11324#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11317#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 11284#L547 assume !(0 == start_simulation_~tmp~3#1); 11280#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11276#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11274#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11271#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 11269#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11267#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11265#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 11263#L560 assume !(0 != start_simulation_~tmp___0~1#1); 10627#L528-2 [2024-11-13 15:32:44,525 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:44,525 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 5 times [2024-11-13 15:32:44,526 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:44,526 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1870030778] [2024-11-13 15:32:44,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:44,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:44,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:44,538 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:32:44,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:44,550 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:32:44,551 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:44,551 INFO L85 PathProgramCache]: Analyzing trace with hash 1600495410, now seen corresponding path program 1 times [2024-11-13 15:32:44,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:44,551 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364408683] [2024-11-13 15:32:44,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:44,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:44,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:44,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:44,646 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:44,646 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364408683] [2024-11-13 15:32:44,646 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [364408683] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:44,646 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:44,646 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:32:44,647 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1272724674] [2024-11-13 15:32:44,647 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:44,647 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:32:44,647 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:32:44,648 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:32:44,648 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:32:44,648 INFO L87 Difference]: Start difference. First operand 1028 states and 1347 transitions. cyclomatic complexity: 323 Second operand has 5 states, 5 states have (on average 10.8) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:44,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:32:44,761 INFO L93 Difference]: Finished difference Result 1031 states and 1328 transitions. [2024-11-13 15:32:44,761 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1031 states and 1328 transitions. [2024-11-13 15:32:44,769 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 980 [2024-11-13 15:32:44,776 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1031 states to 1031 states and 1328 transitions. [2024-11-13 15:32:44,776 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1031 [2024-11-13 15:32:44,777 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1031 [2024-11-13 15:32:44,777 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1031 states and 1328 transitions. [2024-11-13 15:32:44,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:32:44,780 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1031 states and 1328 transitions. [2024-11-13 15:32:44,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1031 states and 1328 transitions. [2024-11-13 15:32:44,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1031 to 1031. [2024-11-13 15:32:44,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1031 states, 1031 states have (on average 1.2880698351115423) internal successors, (1328), 1030 states have internal predecessors, (1328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:44,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1031 states to 1031 states and 1328 transitions. [2024-11-13 15:32:44,806 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1031 states and 1328 transitions. [2024-11-13 15:32:44,806 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:32:44,807 INFO L424 stractBuchiCegarLoop]: Abstraction has 1031 states and 1328 transitions. [2024-11-13 15:32:44,807 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 15:32:44,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1031 states and 1328 transitions. [2024-11-13 15:32:44,813 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 980 [2024-11-13 15:32:44,814 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:44,814 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:44,815 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:44,815 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:44,815 INFO L745 eck$LassoCheckResult]: Stem: 12773#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 12774#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 12784#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12781#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12782#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 12669#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12641#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12642#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12625#L334 assume !(0 == ~M_E~0); 12626#L334-2 assume !(0 == ~T1_E~0); 12738#L339-1 assume !(0 == ~T2_E~0); 12731#L344-1 assume !(0 == ~E_1~0); 12732#L349-1 assume !(0 == ~E_2~0); 12639#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12640#L156 assume !(1 == ~m_pc~0); 12573#L156-2 is_master_triggered_~__retres1~0#1 := 0; 12761#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12752#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 12696#L405 assume !(0 != activate_threads_~tmp~1#1); 12674#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12675#L175 assume !(1 == ~t1_pc~0); 12683#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12676#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12636#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 12637#L413 assume !(0 != activate_threads_~tmp___0~0#1); 12740#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12801#L194 assume !(1 == ~t2_pc~0); 12729#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12687#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12688#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12613#L421 assume !(0 != activate_threads_~tmp___1~0#1); 12614#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12585#L367 assume !(1 == ~M_E~0); 12586#L367-2 assume !(1 == ~T1_E~0); 12754#L372-1 assume !(1 == ~T2_E~0); 12755#L377-1 assume !(1 == ~E_1~0); 12610#L382-1 assume !(1 == ~E_2~0); 12611#L387-1 assume { :end_inline_reset_delta_events } true; 12699#L528-2 [2024-11-13 15:32:44,815 INFO L747 eck$LassoCheckResult]: Loop: 12699#L528-2 assume !false; 12851#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12848#L309-1 assume !false; 12843#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 12844#L244 assume !(0 == ~m_st~0); 13107#L248 assume !(0 == ~t1_st~0); 13103#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 13101#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13099#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13095#L276 assume !(0 != eval_~tmp~0#1); 13093#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13091#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13089#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13087#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13085#L339-3 assume !(0 == ~T2_E~0); 13083#L344-3 assume !(0 == ~E_1~0); 13081#L349-3 assume !(0 == ~E_2~0); 13079#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13075#L156-9 assume 1 == ~m_pc~0; 13069#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13065#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13063#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 13057#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13053#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13049#L175-9 assume !(1 == ~t1_pc~0); 13045#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 13041#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13037#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 13033#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 13029#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13024#L194-9 assume !(1 == ~t2_pc~0); 13019#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 13015#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13011#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13007#L421-9 assume !(0 != activate_threads_~tmp___1~0#1); 13003#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12999#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12995#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12991#L372-3 assume !(1 == ~T2_E~0); 12987#L377-3 assume !(1 == ~E_1~0); 12983#L382-3 assume !(1 == ~E_2~0); 12979#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 12975#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 12891#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 12892#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 12885#L547 assume !(0 == start_simulation_~tmp~3#1); 12882#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 12883#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 13141#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 12876#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 12877#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12872#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12873#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 12865#L560 assume !(0 != start_simulation_~tmp___0~1#1); 12699#L528-2 [2024-11-13 15:32:44,816 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:44,816 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 6 times [2024-11-13 15:32:44,816 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:44,816 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1986157504] [2024-11-13 15:32:44,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:44,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:44,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:44,827 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:32:44,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:44,837 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:32:44,838 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:44,838 INFO L85 PathProgramCache]: Analyzing trace with hash 1662535024, now seen corresponding path program 1 times [2024-11-13 15:32:44,838 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:44,838 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1388495996] [2024-11-13 15:32:44,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:44,838 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:44,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:44,850 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:32:44,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:44,862 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:32:44,863 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:44,863 INFO L85 PathProgramCache]: Analyzing trace with hash 861264176, now seen corresponding path program 1 times [2024-11-13 15:32:44,863 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:44,863 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [478814299] [2024-11-13 15:32:44,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:44,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:44,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:44,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:44,919 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:44,919 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [478814299] [2024-11-13 15:32:44,919 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [478814299] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:44,919 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:44,919 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:32:44,920 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1673443706] [2024-11-13 15:32:44,920 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:45,616 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 15:32:45,617 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 15:32:45,617 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 15:32:45,617 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 15:32:45,617 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-13 15:32:45,617 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:45,618 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 15:32:45,618 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 15:32:45,619 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.02.cil.c_Iteration12_Loop [2024-11-13 15:32:45,619 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 15:32:45,619 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 15:32:45,644 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,653 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,660 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,664 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,667 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,671 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,674 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,678 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,681 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,684 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,688 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,692 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,695 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,698 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,705 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,713 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,716 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,719 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,723 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,726 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,730 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,733 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,736 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,740 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,743 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,750 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,753 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,756 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,760 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,762 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,765 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,768 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,771 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,774 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,777 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,784 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,787 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,791 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,794 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,797 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:45,801 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,156 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 15:32:46,157 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-13 15:32:46,159 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:46,160 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:46,163 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:46,165 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-13 15:32:46,166 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:32:46,166 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:32:46,192 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:32:46,192 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:32:46,219 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2024-11-13 15:32:46,219 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:46,220 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:46,222 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:46,224 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-13 15:32:46,225 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:32:46,226 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:32:46,254 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:32:46,255 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_2~0=-8} Honda state: {~E_2~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:32:46,274 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-11-13 15:32:46,274 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:46,274 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:46,276 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:46,279 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-13 15:32:46,280 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:32:46,280 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:32:46,301 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:32:46,302 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret13#1=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret13#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:32:46,323 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-11-13 15:32:46,323 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:46,324 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:46,326 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:46,330 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-13 15:32:46,331 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:32:46,331 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:32:46,352 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:32:46,353 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:32:46,373 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2024-11-13 15:32:46,374 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:46,374 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:46,376 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:46,379 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-13 15:32:46,380 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:32:46,381 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:32:46,401 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:32:46,402 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_master_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:32:46,420 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2024-11-13 15:32:46,420 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:46,421 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:46,424 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:46,426 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-13 15:32:46,429 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:32:46,429 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:32:46,447 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:32:46,448 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:32:46,468 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2024-11-13 15:32:46,468 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:46,468 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:46,470 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:46,475 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-13 15:32:46,475 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:32:46,475 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:32:46,493 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:32:46,493 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:32:46,505 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-11-13 15:32:46,506 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:46,506 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:46,507 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:46,509 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-13 15:32:46,509 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:32:46,509 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:32:46,522 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:32:46,522 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:32:46,535 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2024-11-13 15:32:46,536 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:46,536 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:46,538 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:46,564 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-13 15:32:46,565 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:32:46,565 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:32:46,583 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:32:46,583 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Honda state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:32:46,602 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2024-11-13 15:32:46,603 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:46,603 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:46,606 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:46,608 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-13 15:32:46,610 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:32:46,610 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:32:46,636 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:32:46,636 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=4} Honda state: {~t1_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:32:46,655 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2024-11-13 15:32:46,656 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:46,656 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:46,659 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:46,661 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-11-13 15:32:46,663 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:32:46,663 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:32:46,688 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:32:46,689 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t2_st~0=4} Honda state: {~t2_st~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:32:46,703 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2024-11-13 15:32:46,703 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:46,703 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:46,705 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:46,706 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-11-13 15:32:46,706 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:32:46,706 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:32:46,718 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:32:46,718 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:32:46,730 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2024-11-13 15:32:46,731 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:46,731 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:46,733 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:46,734 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-11-13 15:32:46,734 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:32:46,734 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:32:46,747 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:32:46,747 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret8#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret8#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:32:46,760 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2024-11-13 15:32:46,760 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:46,760 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:46,762 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:46,763 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-11-13 15:32:46,764 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:32:46,764 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:32:46,784 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:32:46,784 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_1~0=-1} Honda state: {~E_1~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:32:46,799 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2024-11-13 15:32:46,800 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:46,800 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:46,803 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:46,804 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-11-13 15:32:46,805 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:32:46,805 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:32:46,832 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2024-11-13 15:32:46,832 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:46,832 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:46,834 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:46,835 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-11-13 15:32:46,836 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-13 15:32:46,836 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:32:46,859 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-13 15:32:46,877 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2024-11-13 15:32:46,878 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 15:32:46,878 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 15:32:46,878 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 15:32:46,878 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 15:32:46,878 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-13 15:32:46,878 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:46,878 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 15:32:46,878 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 15:32:46,878 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.02.cil.c_Iteration12_Loop [2024-11-13 15:32:46,878 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 15:32:46,878 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 15:32:46,880 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,885 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,892 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,895 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,897 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,901 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,904 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,907 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,913 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,915 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,918 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,922 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,925 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,928 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,935 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,942 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,944 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,947 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,949 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,952 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,955 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,957 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,961 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,966 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,974 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,980 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,983 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,985 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,988 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,991 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,994 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,997 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:46,999 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:47,002 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:47,005 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:47,008 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:47,013 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:47,016 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:47,019 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:47,022 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:47,025 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:32:47,338 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 15:32:47,342 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-13 15:32:47,343 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:47,343 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:47,345 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:47,349 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-11-13 15:32:47,351 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:32:47,367 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:32:47,367 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:32:47,367 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:32:47,367 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:32:47,368 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:32:47,376 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:32:47,376 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:32:47,379 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:32:47,397 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2024-11-13 15:32:47,397 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:47,397 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:47,399 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:47,403 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-11-13 15:32:47,403 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:32:47,418 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:32:47,418 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:32:47,418 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:32:47,418 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 15:32:47,418 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:32:47,419 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 15:32:47,419 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:32:47,422 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:32:47,440 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2024-11-13 15:32:47,440 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:47,441 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:47,443 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:47,446 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2024-11-13 15:32:47,447 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:32:47,462 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:32:47,462 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:32:47,462 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:32:47,462 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:32:47,462 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:32:47,463 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:32:47,463 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:32:47,467 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:32:47,486 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2024-11-13 15:32:47,486 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:47,486 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:47,490 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:47,494 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2024-11-13 15:32:47,495 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:32:47,511 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:32:47,511 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:32:47,511 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:32:47,511 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:32:47,511 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:32:47,512 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:32:47,512 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:32:47,513 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:32:47,533 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2024-11-13 15:32:47,534 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:47,534 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:47,536 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:47,539 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2024-11-13 15:32:47,540 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:32:47,555 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:32:47,556 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:32:47,556 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:32:47,556 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:32:47,556 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:32:47,556 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:32:47,556 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:32:47,558 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:32:47,577 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Ended with exit code 0 [2024-11-13 15:32:47,577 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:47,577 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:47,579 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:47,581 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2024-11-13 15:32:47,582 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:32:47,596 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:32:47,596 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:32:47,596 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:32:47,596 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:32:47,596 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:32:47,597 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:32:47,597 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:32:47,602 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:32:47,620 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Ended with exit code 0 [2024-11-13 15:32:47,621 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:47,621 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:47,623 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:47,625 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2024-11-13 15:32:47,626 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:32:47,641 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:32:47,641 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:32:47,641 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:32:47,642 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:32:47,642 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:32:47,642 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:32:47,643 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:32:47,645 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:32:47,659 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2024-11-13 15:32:47,659 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:47,659 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:47,661 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:47,662 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2024-11-13 15:32:47,663 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:32:47,674 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:32:47,674 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:32:47,674 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:32:47,674 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:32:47,674 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:32:47,675 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:32:47,675 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:32:47,677 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:32:47,694 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Ended with exit code 0 [2024-11-13 15:32:47,694 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:47,694 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:47,696 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:47,697 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2024-11-13 15:32:47,697 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:32:47,708 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:32:47,708 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:32:47,708 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:32:47,708 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:32:47,708 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:32:47,709 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:32:47,709 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:32:47,713 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:32:47,732 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Ended with exit code 0 [2024-11-13 15:32:47,732 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:47,732 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:47,734 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:47,736 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2024-11-13 15:32:47,738 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:32:47,753 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:32:47,753 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:32:47,753 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:32:47,754 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:32:47,754 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:32:47,754 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:32:47,754 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:32:47,758 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:32:47,772 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Ended with exit code 0 [2024-11-13 15:32:47,772 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:47,772 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:47,774 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:47,776 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2024-11-13 15:32:47,777 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:32:47,790 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:32:47,790 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:32:47,790 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:32:47,790 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 15:32:47,790 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:32:47,791 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 15:32:47,791 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:32:47,794 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:32:47,814 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Ended with exit code 0 [2024-11-13 15:32:47,814 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:47,814 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:47,816 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:47,818 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2024-11-13 15:32:47,819 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:32:47,836 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:32:47,837 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:32:47,837 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:32:47,837 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 15:32:47,837 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:32:47,838 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 15:32:47,838 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:32:47,843 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:32:47,856 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2024-11-13 15:32:47,856 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:47,856 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:47,858 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:47,860 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:32:47,860 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2024-11-13 15:32:47,871 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:32:47,871 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:32:47,871 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:32:47,871 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:32:47,871 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:32:47,872 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:32:47,872 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:32:47,874 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:32:47,886 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Ended with exit code 0 [2024-11-13 15:32:47,886 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:47,886 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:47,888 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:47,889 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2024-11-13 15:32:47,890 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:32:47,901 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:32:47,901 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:32:47,901 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:32:47,901 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 15:32:47,902 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:32:47,902 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 15:32:47,902 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:32:47,905 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:32:47,917 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2024-11-13 15:32:47,918 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:47,918 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:47,919 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:47,921 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2024-11-13 15:32:47,921 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:32:47,933 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:32:47,933 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:32:47,933 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:32:47,933 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:32:47,933 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:32:47,935 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:32:47,935 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:32:47,938 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-13 15:32:47,942 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-13 15:32:47,945 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-13 15:32:47,946 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:32:47,946 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:32:47,949 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:32:47,951 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2024-11-13 15:32:47,952 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-13 15:32:47,952 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-13 15:32:47,952 INFO L474 LassoAnalysis]: Proved termination. [2024-11-13 15:32:47,953 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~M_E~0) = -1*~M_E~0 + 1 Supporting invariants [] [2024-11-13 15:32:47,972 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Ended with exit code 0 [2024-11-13 15:32:47,975 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-13 15:32:48,013 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:48,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:48,064 INFO L255 TraceCheckSpWp]: Trace formula consists of 113 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-13 15:32:48,066 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 15:32:48,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:48,201 INFO L255 TraceCheckSpWp]: Trace formula consists of 107 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-13 15:32:48,203 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 15:32:48,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:48,444 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-13 15:32:48,446 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 1031 states and 1328 transitions. cyclomatic complexity: 301 Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:48,608 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 1031 states and 1328 transitions. cyclomatic complexity: 301. Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 2545 states and 3311 transitions. Complement of second has 5 states. [2024-11-13 15:32:48,611 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-13 15:32:48,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:48,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 235 transitions. [2024-11-13 15:32:48,625 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 235 transitions. Stem has 38 letters. Loop has 54 letters. [2024-11-13 15:32:48,627 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 15:32:48,627 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 235 transitions. Stem has 92 letters. Loop has 54 letters. [2024-11-13 15:32:48,628 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 15:32:48,628 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 235 transitions. Stem has 38 letters. Loop has 108 letters. [2024-11-13 15:32:48,635 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 15:32:48,635 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2545 states and 3311 transitions. [2024-11-13 15:32:48,659 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1716 [2024-11-13 15:32:48,676 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2545 states to 2545 states and 3311 transitions. [2024-11-13 15:32:48,676 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1776 [2024-11-13 15:32:48,679 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1789 [2024-11-13 15:32:48,679 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2545 states and 3311 transitions. [2024-11-13 15:32:48,679 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:32:48,679 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2545 states and 3311 transitions. [2024-11-13 15:32:48,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2545 states and 3311 transitions. [2024-11-13 15:32:48,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2545 to 2532. [2024-11-13 15:32:48,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2532 states, 2532 states have (on average 1.3001579778830963) internal successors, (3292), 2531 states have internal predecessors, (3292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:48,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2532 states to 2532 states and 3292 transitions. [2024-11-13 15:32:48,741 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2532 states and 3292 transitions. [2024-11-13 15:32:48,741 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:32:48,741 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:32:48,741 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:32:48,741 INFO L87 Difference]: Start difference. First operand 2532 states and 3292 transitions. Second operand has 3 states, 3 states have (on average 30.666666666666668) internal successors, (92), 3 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:48,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:32:48,797 INFO L93 Difference]: Finished difference Result 2646 states and 3379 transitions. [2024-11-13 15:32:48,797 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2646 states and 3379 transitions. [2024-11-13 15:32:48,818 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1792 [2024-11-13 15:32:48,834 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2646 states to 2646 states and 3379 transitions. [2024-11-13 15:32:48,834 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1852 [2024-11-13 15:32:48,837 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1852 [2024-11-13 15:32:48,837 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2646 states and 3379 transitions. [2024-11-13 15:32:48,839 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:32:48,840 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2646 states and 3379 transitions. [2024-11-13 15:32:48,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2646 states and 3379 transitions. [2024-11-13 15:32:48,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2646 to 2532. [2024-11-13 15:32:48,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2532 states, 2532 states have (on average 1.2812006319115323) internal successors, (3244), 2531 states have internal predecessors, (3244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:48,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2532 states to 2532 states and 3244 transitions. [2024-11-13 15:32:48,901 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2532 states and 3244 transitions. [2024-11-13 15:32:48,901 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:32:48,902 INFO L424 stractBuchiCegarLoop]: Abstraction has 2532 states and 3244 transitions. [2024-11-13 15:32:48,902 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 15:32:48,903 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2532 states and 3244 transitions. [2024-11-13 15:32:48,915 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1716 [2024-11-13 15:32:48,915 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:48,916 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:48,916 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:48,917 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:48,917 INFO L745 eck$LassoCheckResult]: Stem: 21967#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 21968#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 21989#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21985#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21986#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 21800#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21746#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21747#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21718#L334 assume !(0 == ~M_E~0); 21719#L334-2 assume !(0 == ~T1_E~0); 21909#L339-1 assume !(0 == ~T2_E~0); 21899#L344-1 assume !(0 == ~E_1~0); 21900#L349-1 assume !(0 == ~E_2~0); 21744#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21745#L156 assume !(1 == ~m_pc~0); 21633#L156-2 is_master_triggered_~__retres1~0#1 := 0; 21984#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22047#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 21841#L405 assume !(0 != activate_threads_~tmp~1#1); 21814#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21815#L175 assume !(1 == ~t1_pc~0); 21819#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21816#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21738#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 21739#L413 assume !(0 != activate_threads_~tmp___0~0#1); 21916#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22023#L194 assume !(1 == ~t2_pc~0); 21898#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21825#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21826#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 21700#L421 assume !(0 != activate_threads_~tmp___1~0#1); 21701#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21649#L367 assume !(1 == ~M_E~0); 21650#L367-2 assume !(1 == ~T1_E~0); 21938#L372-1 assume !(1 == ~T2_E~0); 21939#L377-1 assume !(1 == ~E_1~0); 21696#L382-1 assume !(1 == ~E_2~0); 21697#L387-1 assume { :end_inline_reset_delta_events } true; 21846#L528-2 assume !false; 22177#L529 [2024-11-13 15:32:48,917 INFO L747 eck$LassoCheckResult]: Loop: 22177#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23588#L309-1 assume !false; 23576#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 23569#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 23564#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 23559#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23554#L276 assume 0 != eval_~tmp~0#1; 23549#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 23543#L284 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 23538#L47 assume !(0 == ~m_pc~0); 23535#L50 assume 1 == ~m_pc~0; 23531#$Ultimate##124 assume !false; 23530#L67 ~m_pc~0 := 1;~m_st~0 := 2; 23528#master_returnLabel#1 assume { :end_inline_master } true; 23519#L284-2 havoc eval_~tmp_ndt_1~0#1; 23516#L281-1 assume !(0 == ~t1_st~0); 23498#L295-1 assume !(0 == ~t2_st~0); 23495#L309-1 assume !false; 23493#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 23469#L244 assume !(0 == ~m_st~0); 23465#L248 assume !(0 == ~t1_st~0); 23459#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 23453#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 23447#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23433#L276 assume !(0 != eval_~tmp~0#1); 23431#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23429#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23428#L334-3 assume !(0 == ~M_E~0); 23427#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23426#L339-3 assume !(0 == ~T2_E~0); 23425#L344-3 assume !(0 == ~E_1~0); 23424#L349-3 assume !(0 == ~E_2~0); 23423#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23311#L156-9 assume 1 == ~m_pc~0; 23305#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23306#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23422#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 23420#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23418#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23416#L175-9 assume !(1 == ~t1_pc~0); 23414#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 23412#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23410#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 23408#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 23407#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23289#L194-9 assume !(1 == ~t2_pc~0); 23285#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 23282#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23278#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 23275#L421-9 assume !(0 != activate_threads_~tmp___1~0#1); 23272#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23269#L367-3 assume !(1 == ~M_E~0); 23266#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23264#L372-3 assume !(1 == ~T2_E~0); 23263#L377-3 assume !(1 == ~E_1~0); 23260#L382-3 assume !(1 == ~E_2~0); 23257#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 23252#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 23251#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 23250#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 23249#L547 assume !(0 == start_simulation_~tmp~3#1); 22000#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 21969#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 21970#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 24041#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 21740#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21741#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23719#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 23717#L560 assume !(0 != start_simulation_~tmp___0~1#1); 23715#L528-2 assume !false; 22177#L529 [2024-11-13 15:32:48,918 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:48,918 INFO L85 PathProgramCache]: Analyzing trace with hash -308898553, now seen corresponding path program 1 times [2024-11-13 15:32:48,918 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:48,918 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1841581365] [2024-11-13 15:32:48,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:48,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:48,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:48,934 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:32:48,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:48,945 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:32:48,945 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:48,947 INFO L85 PathProgramCache]: Analyzing trace with hash -448268247, now seen corresponding path program 1 times [2024-11-13 15:32:48,947 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:48,947 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [17611567] [2024-11-13 15:32:48,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:48,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:48,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:49,007 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-11-13 15:32:49,007 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:49,007 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [17611567] [2024-11-13 15:32:49,007 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [17611567] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:49,007 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:49,007 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:32:49,007 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [961626844] [2024-11-13 15:32:49,007 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:49,008 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:32:49,008 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:32:49,008 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:32:49,008 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:32:49,008 INFO L87 Difference]: Start difference. First operand 2532 states and 3244 transitions. cyclomatic complexity: 724 Second operand has 3 states, 3 states have (on average 22.0) internal successors, (66), 3 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:49,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:32:49,091 INFO L93 Difference]: Finished difference Result 3736 states and 4689 transitions. [2024-11-13 15:32:49,091 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3736 states and 4689 transitions. [2024-11-13 15:32:49,114 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 2143 [2024-11-13 15:32:49,139 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3736 states to 3548 states and 4461 transitions. [2024-11-13 15:32:49,139 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2401 [2024-11-13 15:32:49,143 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2401 [2024-11-13 15:32:49,143 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3548 states and 4461 transitions. [2024-11-13 15:32:49,144 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:32:49,144 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3548 states and 4461 transitions. [2024-11-13 15:32:49,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3548 states and 4461 transitions. [2024-11-13 15:32:49,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3548 to 3428. [2024-11-13 15:32:49,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3428 states, 3428 states have (on average 1.2570011668611436) internal successors, (4309), 3427 states have internal predecessors, (4309), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:49,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3428 states to 3428 states and 4309 transitions. [2024-11-13 15:32:49,241 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3428 states and 4309 transitions. [2024-11-13 15:32:49,245 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:32:49,246 INFO L424 stractBuchiCegarLoop]: Abstraction has 3428 states and 4309 transitions. [2024-11-13 15:32:49,246 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 15:32:49,246 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3428 states and 4309 transitions. [2024-11-13 15:32:49,268 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 2026 [2024-11-13 15:32:49,269 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:49,269 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:49,269 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:49,269 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:49,270 INFO L745 eck$LassoCheckResult]: Stem: 28236#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 28237#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 28259#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28254#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28255#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 28066#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28019#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28020#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27992#L334 assume 0 == ~M_E~0;~M_E~0 := 1; 27993#L334-2 assume !(0 == ~T1_E~0); 28178#L339-1 assume !(0 == ~T2_E~0); 28179#L344-1 assume !(0 == ~E_1~0); 28226#L349-1 assume !(0 == ~E_2~0); 28227#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28187#L156 assume !(1 == ~m_pc~0); 28188#L156-2 is_master_triggered_~__retres1~0#1 := 0; 28220#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28221#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 28112#L405 assume !(0 != activate_threads_~tmp~1#1); 28082#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28083#L175 assume !(1 == ~t1_pc~0); 28088#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28084#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28085#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28316#L413 assume !(0 != activate_threads_~tmp___0~0#1); 28291#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28292#L194 assume !(1 == ~t2_pc~0); 28314#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28313#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28311#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28310#L421 assume !(0 != activate_threads_~tmp___1~0#1); 28309#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27922#L367 assume 1 == ~M_E~0;~M_E~0 := 2; 27923#L367-2 assume !(1 == ~T1_E~0); 28212#L372-1 assume !(1 == ~T2_E~0); 28213#L377-1 assume !(1 == ~E_1~0); 27968#L382-1 assume !(1 == ~E_2~0); 27969#L387-1 assume { :end_inline_reset_delta_events } true; 28117#L528-2 assume !false; 28132#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28133#L309-1 [2024-11-13 15:32:49,270 INFO L747 eck$LassoCheckResult]: Loop: 28133#L309-1 assume !false; 30798#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 30796#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 30794#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 30793#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30790#L276 assume 0 != eval_~tmp~0#1; 30789#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 28067#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 28069#L284-2 havoc eval_~tmp_ndt_1~0#1; 30804#L281-1 assume !(0 == ~t1_st~0); 30801#L295-1 assume !(0 == ~t2_st~0); 28133#L309-1 [2024-11-13 15:32:49,270 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:49,270 INFO L85 PathProgramCache]: Analyzing trace with hash -451333369, now seen corresponding path program 1 times [2024-11-13 15:32:49,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:49,270 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1954116478] [2024-11-13 15:32:49,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:49,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:49,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:49,383 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Ended with exit code 0 [2024-11-13 15:32:49,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:49,399 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:49,399 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1954116478] [2024-11-13 15:32:49,399 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1954116478] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:49,399 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:49,399 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:32:49,400 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1296242969] [2024-11-13 15:32:49,400 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:49,400 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:32:49,400 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:49,400 INFO L85 PathProgramCache]: Analyzing trace with hash -1019037780, now seen corresponding path program 1 times [2024-11-13 15:32:49,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:49,400 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [877359707] [2024-11-13 15:32:49,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:49,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:49,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:49,408 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:32:49,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:49,412 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:32:49,461 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:32:49,462 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:32:49,462 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:32:49,462 INFO L87 Difference]: Start difference. First operand 3428 states and 4309 transitions. cyclomatic complexity: 899 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:49,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:32:49,503 INFO L93 Difference]: Finished difference Result 1867 states and 2321 transitions. [2024-11-13 15:32:49,503 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1867 states and 2321 transitions. [2024-11-13 15:32:49,514 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 1238 [2024-11-13 15:32:49,521 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1867 states to 1364 states and 1693 transitions. [2024-11-13 15:32:49,521 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1364 [2024-11-13 15:32:49,523 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1364 [2024-11-13 15:32:49,523 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1364 states and 1693 transitions. [2024-11-13 15:32:49,525 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:32:49,525 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1364 states and 1693 transitions. [2024-11-13 15:32:49,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1364 states and 1693 transitions. [2024-11-13 15:32:49,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1364 to 860. [2024-11-13 15:32:49,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 860 states, 860 states have (on average 1.2337209302325582) internal successors, (1061), 859 states have internal predecessors, (1061), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:49,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 860 states to 860 states and 1061 transitions. [2024-11-13 15:32:49,546 INFO L240 hiAutomatonCegarLoop]: Abstraction has 860 states and 1061 transitions. [2024-11-13 15:32:49,547 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:32:49,547 INFO L424 stractBuchiCegarLoop]: Abstraction has 860 states and 1061 transitions. [2024-11-13 15:32:49,547 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 15:32:49,547 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 860 states and 1061 transitions. [2024-11-13 15:32:49,551 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 812 [2024-11-13 15:32:49,551 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:49,552 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:49,552 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:49,552 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:49,553 INFO L745 eck$LassoCheckResult]: Stem: 33386#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 33387#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 33396#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33393#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33394#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 33289#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33264#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33265#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33248#L334 assume !(0 == ~M_E~0); 33249#L334-2 assume !(0 == ~T1_E~0); 33354#L339-1 assume !(0 == ~T2_E~0); 33348#L344-1 assume !(0 == ~E_1~0); 33349#L349-1 assume !(0 == ~E_2~0); 33262#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33263#L156 assume !(1 == ~m_pc~0); 33199#L156-2 is_master_triggered_~__retres1~0#1 := 0; 33378#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33366#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 33317#L405 assume !(0 != activate_threads_~tmp~1#1); 33298#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33299#L175 assume !(1 == ~t1_pc~0); 33303#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33300#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33259#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 33260#L413 assume !(0 != activate_threads_~tmp___0~0#1); 33358#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33411#L194 assume !(1 == ~t2_pc~0); 33347#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33306#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33307#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 33237#L421 assume !(0 != activate_threads_~tmp___1~0#1); 33238#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33209#L367 assume !(1 == ~M_E~0); 33210#L367-2 assume !(1 == ~T1_E~0); 33367#L372-1 assume !(1 == ~T2_E~0); 33368#L377-1 assume !(1 == ~E_1~0); 33234#L382-1 assume !(1 == ~E_2~0); 33235#L387-1 assume { :end_inline_reset_delta_events } true; 33320#L528-2 [2024-11-13 15:32:49,553 INFO L747 eck$LassoCheckResult]: Loop: 33320#L528-2 assume !false; 33599#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33450#L309-1 assume !false; 33448#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 33446#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 33444#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 33442#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33440#L276 assume 0 != eval_~tmp~0#1; 33438#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 33290#L284 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 33291#L47 assume !(0 == ~m_pc~0); 33429#L50 assume 1 == ~m_pc~0; 34021#$Ultimate##124 assume !false; 34020#L67 ~m_pc~0 := 1;~m_st~0 := 2; 34019#master_returnLabel#1 assume { :end_inline_master } true; 34014#L284-2 havoc eval_~tmp_ndt_1~0#1; 34010#L281-1 assume !(0 == ~t1_st~0); 33994#L295-1 assume !(0 == ~t2_st~0); 33991#L309-1 assume !false; 33989#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 33987#L244 assume !(0 == ~m_st~0); 33985#L248 assume !(0 == ~t1_st~0); 33981#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 33979#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 33977#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33974#L276 assume !(0 != eval_~tmp~0#1); 33972#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33970#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33968#L334-3 assume !(0 == ~M_E~0); 33965#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33963#L339-3 assume !(0 == ~T2_E~0); 33961#L344-3 assume !(0 == ~E_1~0); 33960#L349-3 assume !(0 == ~E_2~0); 33959#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33958#L156-9 assume !(1 == ~m_pc~0); 33956#L156-11 is_master_triggered_~__retres1~0#1 := 0; 33285#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33286#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 33359#L405-9 assume !(0 != activate_threads_~tmp~1#1); 33225#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33226#L175-9 assume !(1 == ~t1_pc~0); 33380#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 33211#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33212#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 33392#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 33383#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33384#L194-9 assume !(1 == ~t2_pc~0); 33239#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 33240#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33829#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 33828#L421-9 assume !(0 != activate_threads_~tmp___1~0#1); 33827#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33826#L367-3 assume !(1 == ~M_E~0); 33825#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33824#L372-3 assume !(1 == ~T2_E~0); 33823#L377-3 assume !(1 == ~E_1~0); 33822#L382-3 assume !(1 == ~E_2~0); 33821#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 33820#L244-1 assume !(0 == ~m_st~0); 33819#L248-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 33817#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 33816#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 33814#L547 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 33813#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33812#L156-12 assume 1 == ~m_pc~0; 33413#L157-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 33414#L167-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33860#is_master_triggered_returnLabel#5 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 33858#L405-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33857#L405-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33856#L175-12 assume !(1 == ~t1_pc~0); 33855#L175-14 is_transmit1_triggered_~__retres1~1#1 := 0; 33854#L186-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33853#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 33852#L413-12 assume !(0 != activate_threads_~tmp___0~0#1); 33851#L413-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33850#L194-12 assume !(1 == ~t2_pc~0); 33848#L194-14 is_transmit2_triggered_~__retres1~2#1 := 0; 33847#L205-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33846#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 33845#L421-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33844#L421-14 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 33843#L454 assume 1 == ~M_E~0;~M_E~0 := 2; 33842#L454-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33841#L459-1 assume !(1 == ~T2_E~0); 33840#L464-1 assume !(1 == ~E_1~0); 33839#L469-1 assume !(1 == ~E_2~0); 33838#L474-1 assume { :end_inline_reset_time_events } true; 33837#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 33836#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 33835#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 33834#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 33833#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33832#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33831#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 33830#L560 assume !(0 != start_simulation_~tmp___0~1#1); 33320#L528-2 [2024-11-13 15:32:49,553 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:49,554 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 7 times [2024-11-13 15:32:49,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:49,554 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1154476878] [2024-11-13 15:32:49,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:49,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:49,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:49,564 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:32:49,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:49,575 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:32:49,575 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:49,575 INFO L85 PathProgramCache]: Analyzing trace with hash -1050013015, now seen corresponding path program 1 times [2024-11-13 15:32:49,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:49,576 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807213246] [2024-11-13 15:32:49,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:49,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:49,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:49,654 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:49,654 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:49,654 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1807213246] [2024-11-13 15:32:49,654 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1807213246] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:49,654 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:49,654 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:32:49,654 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320877465] [2024-11-13 15:32:49,655 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:49,655 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:32:49,655 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:32:49,655 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:32:49,655 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:32:49,655 INFO L87 Difference]: Start difference. First operand 860 states and 1061 transitions. cyclomatic complexity: 205 Second operand has 3 states, 3 states have (on average 32.0) internal successors, (96), 3 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:49,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:32:49,693 INFO L93 Difference]: Finished difference Result 989 states and 1203 transitions. [2024-11-13 15:32:49,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 989 states and 1203 transitions. [2024-11-13 15:32:49,699 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 813 [2024-11-13 15:32:49,704 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 989 states to 989 states and 1203 transitions. [2024-11-13 15:32:49,704 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 989 [2024-11-13 15:32:49,705 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 989 [2024-11-13 15:32:49,705 INFO L73 IsDeterministic]: Start isDeterministic. Operand 989 states and 1203 transitions. [2024-11-13 15:32:49,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:32:49,707 INFO L218 hiAutomatonCegarLoop]: Abstraction has 989 states and 1203 transitions. [2024-11-13 15:32:49,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 989 states and 1203 transitions. [2024-11-13 15:32:49,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 989 to 943. [2024-11-13 15:32:49,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 943 states, 943 states have (on average 1.2195121951219512) internal successors, (1150), 942 states have internal predecessors, (1150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:49,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 943 states to 943 states and 1150 transitions. [2024-11-13 15:32:49,727 INFO L240 hiAutomatonCegarLoop]: Abstraction has 943 states and 1150 transitions. [2024-11-13 15:32:49,727 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:32:49,728 INFO L424 stractBuchiCegarLoop]: Abstraction has 943 states and 1150 transitions. [2024-11-13 15:32:49,728 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 15:32:49,728 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 943 states and 1150 transitions. [2024-11-13 15:32:49,733 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 813 [2024-11-13 15:32:49,733 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:49,733 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:49,734 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:49,734 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:49,734 INFO L745 eck$LassoCheckResult]: Stem: 35253#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 35254#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 35267#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35264#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35265#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 35143#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35118#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35119#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35101#L334 assume !(0 == ~M_E~0); 35102#L334-2 assume !(0 == ~T1_E~0); 35216#L339-1 assume !(0 == ~T2_E~0); 35210#L344-1 assume !(0 == ~E_1~0); 35211#L349-1 assume !(0 == ~E_2~0); 35116#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35117#L156 assume 1 == ~m_pc~0; 35051#L157 assume !(1 == ~M_E~0); 35052#L156-2 is_master_triggered_~__retres1~0#1 := 0; 35242#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35232#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 35233#L405 assume !(0 != activate_threads_~tmp~1#1); 35388#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35386#L175 assume !(1 == ~t1_pc~0); 35157#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35158#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35113#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 35114#L413 assume !(0 != activate_threads_~tmp___0~0#1); 35218#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35281#L194 assume !(1 == ~t2_pc~0); 35209#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 35290#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35371#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 35369#L421 assume !(0 != activate_threads_~tmp___1~0#1); 35184#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35185#L367 assume !(1 == ~M_E~0); 35280#L367-2 assume !(1 == ~T1_E~0); 35234#L372-1 assume !(1 == ~T2_E~0); 35235#L377-1 assume !(1 == ~E_1~0); 35237#L382-1 assume !(1 == ~E_2~0); 35175#L387-1 assume { :end_inline_reset_delta_events } true; 35176#L528-2 [2024-11-13 15:32:49,735 INFO L747 eck$LassoCheckResult]: Loop: 35176#L528-2 assume !false; 35593#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35585#L309-1 assume !false; 35579#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 35573#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 35567#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 35562#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 35556#L276 assume 0 != eval_~tmp~0#1; 35549#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 35542#L284 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 35520#L47 assume !(0 == ~m_pc~0); 35518#L50 assume 1 == ~m_pc~0; 35298#$Ultimate##124 assume !false; 35514#L67 ~m_pc~0 := 1;~m_st~0 := 2; 35512#master_returnLabel#1 assume { :end_inline_master } true; 35504#L284-2 havoc eval_~tmp_ndt_1~0#1; 35501#L281-1 assume !(0 == ~t1_st~0); 35475#L295-1 assume !(0 == ~t2_st~0); 35469#L309-1 assume !false; 35467#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 35465#L244 assume !(0 == ~m_st~0); 35463#L248 assume !(0 == ~t1_st~0); 35460#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 35457#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 35455#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 35452#L276 assume !(0 != eval_~tmp~0#1); 35449#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35447#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35445#L334-3 assume !(0 == ~M_E~0); 35443#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35441#L339-3 assume !(0 == ~T2_E~0); 35439#L344-3 assume !(0 == ~E_1~0); 35437#L349-3 assume !(0 == ~E_2~0); 35435#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35433#L156-9 assume 1 == ~m_pc~0; 35431#L157-3 assume !(1 == ~M_E~0); 35429#L156-11 is_master_triggered_~__retres1~0#1 := 0; 35427#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35240#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 35241#L405-9 assume !(0 != activate_threads_~tmp~1#1); 35425#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35283#L175-9 assume !(1 == ~t1_pc~0); 35284#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 35622#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35621#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 35619#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 35617#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35615#L194-9 assume !(1 == ~t2_pc~0); 35611#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 35609#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35607#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 35605#L421-9 assume !(0 != activate_threads_~tmp___1~0#1); 35247#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35136#L367-3 assume !(1 == ~M_E~0); 35053#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35054#L372-3 assume !(1 == ~T2_E~0); 35582#L377-3 assume !(1 == ~E_1~0); 35576#L382-3 assume !(1 == ~E_2~0); 35569#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 35564#L244-1 assume !(0 == ~m_st~0); 35559#L248-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 35551#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 35545#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 35522#L547 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 35155#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35156#L156-12 assume 1 == ~m_pc~0; 35620#L157-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35618#L167-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35616#is_master_triggered_returnLabel#5 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 35612#L405-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35613#L405-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35703#L175-12 assume !(1 == ~t1_pc~0); 35702#L175-14 is_transmit1_triggered_~__retres1~1#1 := 0; 35701#L186-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35700#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 35699#L413-12 assume !(0 != activate_threads_~tmp___0~0#1); 35698#L413-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35697#L194-12 assume !(1 == ~t2_pc~0); 35695#L194-14 is_transmit2_triggered_~__retres1~2#1 := 0; 35694#L205-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35693#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 35692#L421-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35689#L421-14 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 35688#L454 assume 1 == ~M_E~0;~M_E~0 := 2; 35687#L454-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35686#L459-1 assume !(1 == ~T2_E~0); 35684#L464-1 assume !(1 == ~E_1~0); 35682#L469-1 assume !(1 == ~E_2~0); 35681#L474-1 assume { :end_inline_reset_time_events } true; 35680#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 35678#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 35677#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 35675#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 35672#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35669#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35666#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 35663#L560 assume !(0 != start_simulation_~tmp___0~1#1); 35176#L528-2 [2024-11-13 15:32:49,736 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:49,736 INFO L85 PathProgramCache]: Analyzing trace with hash -1839445214, now seen corresponding path program 1 times [2024-11-13 15:32:49,736 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:49,736 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [846815676] [2024-11-13 15:32:49,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:49,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:49,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:49,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:49,772 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:49,772 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [846815676] [2024-11-13 15:32:49,772 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [846815676] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:49,772 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:49,773 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:32:49,773 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [803485672] [2024-11-13 15:32:49,773 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:49,773 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:32:49,773 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:49,773 INFO L85 PathProgramCache]: Analyzing trace with hash -1793884478, now seen corresponding path program 1 times [2024-11-13 15:32:49,773 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:49,774 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702325471] [2024-11-13 15:32:49,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:49,774 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:49,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:49,823 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:49,823 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:49,823 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [702325471] [2024-11-13 15:32:49,823 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [702325471] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:49,823 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:49,823 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:32:49,824 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [270228039] [2024-11-13 15:32:49,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:49,824 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:32:49,824 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:32:49,824 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:32:49,824 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:32:49,824 INFO L87 Difference]: Start difference. First operand 943 states and 1150 transitions. cyclomatic complexity: 213 Second operand has 3 states, 3 states have (on average 13.0) internal successors, (39), 2 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:49,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:32:49,853 INFO L93 Difference]: Finished difference Result 543 states and 662 transitions. [2024-11-13 15:32:49,853 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 543 states and 662 transitions. [2024-11-13 15:32:49,857 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 440 [2024-11-13 15:32:49,860 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 543 states to 543 states and 662 transitions. [2024-11-13 15:32:49,860 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 543 [2024-11-13 15:32:49,860 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 543 [2024-11-13 15:32:49,860 INFO L73 IsDeterministic]: Start isDeterministic. Operand 543 states and 662 transitions. [2024-11-13 15:32:49,861 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:32:49,862 INFO L218 hiAutomatonCegarLoop]: Abstraction has 543 states and 662 transitions. [2024-11-13 15:32:49,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 543 states and 662 transitions. [2024-11-13 15:32:49,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 543 to 539. [2024-11-13 15:32:49,871 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 539 states, 539 states have (on average 1.2207792207792207) internal successors, (658), 538 states have internal predecessors, (658), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:49,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 539 states to 539 states and 658 transitions. [2024-11-13 15:32:49,873 INFO L240 hiAutomatonCegarLoop]: Abstraction has 539 states and 658 transitions. [2024-11-13 15:32:49,873 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:32:49,874 INFO L424 stractBuchiCegarLoop]: Abstraction has 539 states and 658 transitions. [2024-11-13 15:32:49,874 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 15:32:49,874 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 539 states and 658 transitions. [2024-11-13 15:32:49,876 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 440 [2024-11-13 15:32:49,877 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:49,877 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:49,878 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:49,878 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:49,879 INFO L745 eck$LassoCheckResult]: Stem: 36732#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 36733#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 36747#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36744#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36745#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 36629#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36604#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36605#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36589#L334 assume !(0 == ~M_E~0); 36590#L334-2 assume !(0 == ~T1_E~0); 36698#L339-1 assume !(0 == ~T2_E~0); 36692#L344-1 assume !(0 == ~E_1~0); 36693#L349-1 assume !(0 == ~E_2~0); 36602#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36603#L156 assume !(1 == ~m_pc~0); 36703#L156-2 is_master_triggered_~__retres1~0#1 := 0; 36720#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36714#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 36657#L405 assume !(0 != activate_threads_~tmp~1#1); 36634#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36635#L175 assume !(1 == ~t1_pc~0); 36642#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36636#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36599#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 36600#L413 assume !(0 != activate_threads_~tmp___0~0#1); 36700#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36758#L194 assume !(1 == ~t2_pc~0); 36691#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 36645#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36646#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 36578#L421 assume !(0 != activate_threads_~tmp___1~0#1); 36579#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36551#L367 assume !(1 == ~M_E~0); 36552#L367-2 assume !(1 == ~T1_E~0); 36715#L372-1 assume !(1 == ~T2_E~0); 36716#L377-1 assume !(1 == ~E_1~0); 36575#L382-1 assume !(1 == ~E_2~0); 36576#L387-1 assume { :end_inline_reset_delta_events } true; 36660#L528-2 assume !false; 36813#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36814#L309-1 [2024-11-13 15:32:49,879 INFO L747 eck$LassoCheckResult]: Loop: 36814#L309-1 assume !false; 36968#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 36967#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 36966#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 36965#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 36964#L276 assume 0 != eval_~tmp~0#1; 36963#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 36961#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 36962#L284-2 havoc eval_~tmp_ndt_1~0#1; 36973#L281-1 assume !(0 == ~t1_st~0); 36970#L295-1 assume !(0 == ~t2_st~0); 36814#L309-1 [2024-11-13 15:32:49,879 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:49,879 INFO L85 PathProgramCache]: Analyzing trace with hash -985920381, now seen corresponding path program 1 times [2024-11-13 15:32:49,879 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:49,879 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [917567602] [2024-11-13 15:32:49,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:49,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:49,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:49,889 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:32:49,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:49,902 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:32:49,903 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:49,903 INFO L85 PathProgramCache]: Analyzing trace with hash -1019037780, now seen corresponding path program 2 times [2024-11-13 15:32:49,904 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:49,904 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1313711479] [2024-11-13 15:32:49,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:49,904 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:49,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:49,907 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:32:49,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:49,911 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:32:49,911 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:49,911 INFO L85 PathProgramCache]: Analyzing trace with hash -595778070, now seen corresponding path program 1 times [2024-11-13 15:32:49,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:49,911 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [898370568] [2024-11-13 15:32:49,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:49,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:49,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:49,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:49,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:49,950 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [898370568] [2024-11-13 15:32:49,951 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [898370568] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:49,951 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:49,951 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:32:49,951 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [223036902] [2024-11-13 15:32:49,951 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:49,999 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:32:49,999 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:32:49,999 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:32:49,999 INFO L87 Difference]: Start difference. First operand 539 states and 658 transitions. cyclomatic complexity: 123 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:50,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:32:50,037 INFO L93 Difference]: Finished difference Result 889 states and 1069 transitions. [2024-11-13 15:32:50,037 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 889 states and 1069 transitions. [2024-11-13 15:32:50,043 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 627 [2024-11-13 15:32:50,048 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 889 states to 889 states and 1069 transitions. [2024-11-13 15:32:50,048 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 889 [2024-11-13 15:32:50,049 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 889 [2024-11-13 15:32:50,049 INFO L73 IsDeterministic]: Start isDeterministic. Operand 889 states and 1069 transitions. [2024-11-13 15:32:50,051 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:32:50,051 INFO L218 hiAutomatonCegarLoop]: Abstraction has 889 states and 1069 transitions. [2024-11-13 15:32:50,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 889 states and 1069 transitions. [2024-11-13 15:32:50,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 889 to 889. [2024-11-13 15:32:50,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 889 states, 889 states have (on average 1.202474690663667) internal successors, (1069), 888 states have internal predecessors, (1069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:50,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 889 states to 889 states and 1069 transitions. [2024-11-13 15:32:50,071 INFO L240 hiAutomatonCegarLoop]: Abstraction has 889 states and 1069 transitions. [2024-11-13 15:32:50,072 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:32:50,072 INFO L424 stractBuchiCegarLoop]: Abstraction has 889 states and 1069 transitions. [2024-11-13 15:32:50,072 INFO L331 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-13 15:32:50,073 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 889 states and 1069 transitions. [2024-11-13 15:32:50,079 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 627 [2024-11-13 15:32:50,079 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:50,079 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:50,080 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:50,080 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:50,080 INFO L745 eck$LassoCheckResult]: Stem: 38173#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 38174#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 38187#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38185#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38186#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 38066#L221-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 38041#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38042#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38505#L334 assume !(0 == ~M_E~0); 38197#L334-2 assume !(0 == ~T1_E~0); 38138#L339-1 assume !(0 == ~T2_E~0); 38131#L344-1 assume !(0 == ~E_1~0); 38132#L349-1 assume !(0 == ~E_2~0); 38039#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38040#L156 assume !(1 == ~m_pc~0); 38143#L156-2 is_master_triggered_~__retres1~0#1 := 0; 38489#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38487#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 38095#L405 assume !(0 != activate_threads_~tmp~1#1); 38072#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38073#L175 assume !(1 == ~t1_pc~0); 38149#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 38479#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38036#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 38037#L413 assume !(0 != activate_threads_~tmp___0~0#1); 38140#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38208#L194 assume !(1 == ~t2_pc~0); 38130#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38084#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38085#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 38219#L421 assume !(0 != activate_threads_~tmp___1~0#1); 38453#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38451#L367 assume !(1 == ~M_E~0); 38449#L367-2 assume !(1 == ~T1_E~0); 38447#L372-1 assume !(1 == ~T2_E~0); 38445#L377-1 assume !(1 == ~E_1~0); 38012#L382-1 assume !(1 == ~E_2~0); 38013#L387-1 assume { :end_inline_reset_delta_events } true; 38435#L528-2 assume !false; 38428#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38422#L309-1 [2024-11-13 15:32:50,080 INFO L747 eck$LassoCheckResult]: Loop: 38422#L309-1 assume !false; 38418#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 38412#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 38407#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 38402#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38397#L276 assume 0 != eval_~tmp~0#1; 38392#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 38383#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 38384#L284-2 havoc eval_~tmp_ndt_1~0#1; 38433#L281-1 assume !(0 == ~t1_st~0); 38426#L295-1 assume !(0 == ~t2_st~0); 38422#L309-1 [2024-11-13 15:32:50,081 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:50,081 INFO L85 PathProgramCache]: Analyzing trace with hash -1829925883, now seen corresponding path program 1 times [2024-11-13 15:32:50,081 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:50,081 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [684661023] [2024-11-13 15:32:50,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:50,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:50,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:50,111 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:50,111 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:50,111 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [684661023] [2024-11-13 15:32:50,111 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [684661023] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:50,111 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:50,111 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:32:50,111 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1615219570] [2024-11-13 15:32:50,111 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:50,112 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:32:50,112 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:50,112 INFO L85 PathProgramCache]: Analyzing trace with hash -1019037780, now seen corresponding path program 3 times [2024-11-13 15:32:50,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:50,112 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [411739671] [2024-11-13 15:32:50,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:50,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:50,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:50,116 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:32:50,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:50,120 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:32:50,170 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:32:50,170 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:32:50,171 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:32:50,171 INFO L87 Difference]: Start difference. First operand 889 states and 1069 transitions. cyclomatic complexity: 187 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:50,179 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:32:50,179 INFO L93 Difference]: Finished difference Result 565 states and 680 transitions. [2024-11-13 15:32:50,180 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 565 states and 680 transitions. [2024-11-13 15:32:50,183 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 436 [2024-11-13 15:32:50,185 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 565 states to 565 states and 680 transitions. [2024-11-13 15:32:50,186 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 565 [2024-11-13 15:32:50,186 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 565 [2024-11-13 15:32:50,187 INFO L73 IsDeterministic]: Start isDeterministic. Operand 565 states and 680 transitions. [2024-11-13 15:32:50,188 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:32:50,188 INFO L218 hiAutomatonCegarLoop]: Abstraction has 565 states and 680 transitions. [2024-11-13 15:32:50,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 565 states and 680 transitions. [2024-11-13 15:32:50,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 565 to 565. [2024-11-13 15:32:50,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 565 states, 565 states have (on average 1.2035398230088497) internal successors, (680), 564 states have internal predecessors, (680), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:50,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 565 states to 565 states and 680 transitions. [2024-11-13 15:32:50,199 INFO L240 hiAutomatonCegarLoop]: Abstraction has 565 states and 680 transitions. [2024-11-13 15:32:50,199 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:32:50,200 INFO L424 stractBuchiCegarLoop]: Abstraction has 565 states and 680 transitions. [2024-11-13 15:32:50,200 INFO L331 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-13 15:32:50,200 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 565 states and 680 transitions. [2024-11-13 15:32:50,203 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 436 [2024-11-13 15:32:50,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:50,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:50,203 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:50,203 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:50,203 INFO L745 eck$LassoCheckResult]: Stem: 39626#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 39627#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 39636#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39634#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39635#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 39527#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39503#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39504#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39487#L334 assume !(0 == ~M_E~0); 39488#L334-2 assume !(0 == ~T1_E~0); 39594#L339-1 assume !(0 == ~T2_E~0); 39588#L344-1 assume !(0 == ~E_1~0); 39589#L349-1 assume !(0 == ~E_2~0); 39501#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39502#L156 assume !(1 == ~m_pc~0); 39599#L156-2 is_master_triggered_~__retres1~0#1 := 0; 39617#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39608#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 39553#L405 assume !(0 != activate_threads_~tmp~1#1); 39535#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39536#L175 assume !(1 == ~t1_pc~0); 39540#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39537#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39498#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 39499#L413 assume !(0 != activate_threads_~tmp___0~0#1); 39598#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39651#L194 assume !(1 == ~t2_pc~0); 39586#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 39544#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39545#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 39476#L421 assume !(0 != activate_threads_~tmp___1~0#1); 39477#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39450#L367 assume !(1 == ~M_E~0); 39451#L367-2 assume !(1 == ~T1_E~0); 39609#L372-1 assume !(1 == ~T2_E~0); 39610#L377-1 assume !(1 == ~E_1~0); 39472#L382-1 assume !(1 == ~E_2~0); 39473#L387-1 assume { :end_inline_reset_delta_events } true; 39556#L528-2 assume !false; 39565#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39566#L309-1 [2024-11-13 15:32:50,204 INFO L747 eck$LassoCheckResult]: Loop: 39566#L309-1 assume !false; 39940#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 39939#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 39938#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 39447#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 39432#L276 assume 0 != eval_~tmp~0#1; 39433#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 39528#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 39529#L284-2 havoc eval_~tmp_ndt_1~0#1; 39571#L281-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 39572#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 39625#L298-2 havoc eval_~tmp_ndt_2~0#1; 39942#L295-1 assume !(0 == ~t2_st~0); 39566#L309-1 [2024-11-13 15:32:50,204 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:50,204 INFO L85 PathProgramCache]: Analyzing trace with hash -985920381, now seen corresponding path program 2 times [2024-11-13 15:32:50,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:50,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2002916703] [2024-11-13 15:32:50,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:50,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:50,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:50,212 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:32:50,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:50,220 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:32:50,220 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:50,220 INFO L85 PathProgramCache]: Analyzing trace with hash -46014506, now seen corresponding path program 1 times [2024-11-13 15:32:50,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:50,221 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1750760886] [2024-11-13 15:32:50,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:50,221 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:50,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:50,224 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:32:50,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:50,228 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:32:50,228 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:50,228 INFO L85 PathProgramCache]: Analyzing trace with hash -1315326316, now seen corresponding path program 1 times [2024-11-13 15:32:50,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:50,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [369952491] [2024-11-13 15:32:50,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:50,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:50,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:32:50,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:32:50,266 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:32:50,266 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [369952491] [2024-11-13 15:32:50,266 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [369952491] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:32:50,266 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:32:50,266 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:32:50,266 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [994283643] [2024-11-13 15:32:50,266 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:32:50,319 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:32:50,319 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:32:50,319 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:32:50,319 INFO L87 Difference]: Start difference. First operand 565 states and 680 transitions. cyclomatic complexity: 119 Second operand has 3 states, 2 states have (on average 26.5) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:50,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:32:50,369 INFO L93 Difference]: Finished difference Result 1007 states and 1200 transitions. [2024-11-13 15:32:50,369 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1200 transitions. [2024-11-13 15:32:50,375 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 790 [2024-11-13 15:32:50,380 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1007 states and 1200 transitions. [2024-11-13 15:32:50,380 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1007 [2024-11-13 15:32:50,382 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1007 [2024-11-13 15:32:50,382 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1007 states and 1200 transitions. [2024-11-13 15:32:50,384 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:32:50,384 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1200 transitions. [2024-11-13 15:32:50,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states and 1200 transitions. [2024-11-13 15:32:50,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1007. [2024-11-13 15:32:50,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.1916583912611718) internal successors, (1200), 1006 states have internal predecessors, (1200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:32:50,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1200 transitions. [2024-11-13 15:32:50,405 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1200 transitions. [2024-11-13 15:32:50,405 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:32:50,406 INFO L424 stractBuchiCegarLoop]: Abstraction has 1007 states and 1200 transitions. [2024-11-13 15:32:50,406 INFO L331 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-13 15:32:50,406 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1200 transitions. [2024-11-13 15:32:50,411 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 790 [2024-11-13 15:32:50,411 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:32:50,412 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:32:50,412 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:50,412 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:32:50,412 INFO L745 eck$LassoCheckResult]: Stem: 41210#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 41211#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 41219#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41217#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41218#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 41108#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41082#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41083#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41066#L334 assume !(0 == ~M_E~0); 41067#L334-2 assume !(0 == ~T1_E~0); 41179#L339-1 assume !(0 == ~T2_E~0); 41172#L344-1 assume !(0 == ~E_1~0); 41173#L349-1 assume !(0 == ~E_2~0); 41080#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41081#L156 assume !(1 == ~m_pc~0); 41184#L156-2 is_master_triggered_~__retres1~0#1 := 0; 41200#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41194#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 41135#L405 assume !(0 != activate_threads_~tmp~1#1); 41116#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41117#L175 assume !(1 == ~t1_pc~0); 41121#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41118#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41077#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 41078#L413 assume !(0 != activate_threads_~tmp___0~0#1); 41181#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41233#L194 assume !(1 == ~t2_pc~0); 41171#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41124#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41125#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 41055#L421 assume !(0 != activate_threads_~tmp___1~0#1); 41056#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41030#L367 assume !(1 == ~M_E~0); 41031#L367-2 assume !(1 == ~T1_E~0); 41195#L372-1 assume !(1 == ~T2_E~0); 41196#L377-1 assume !(1 == ~E_1~0); 41052#L382-1 assume !(1 == ~E_2~0); 41053#L387-1 assume { :end_inline_reset_delta_events } true; 41138#L528-2 assume !false; 41773#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41769#L309-1 [2024-11-13 15:32:50,413 INFO L747 eck$LassoCheckResult]: Loop: 41769#L309-1 assume !false; 41766#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 41763#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 41760#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 41756#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 41753#L276 assume 0 != eval_~tmp~0#1; 41751#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 41748#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 41749#L284-2 havoc eval_~tmp_ndt_1~0#1; 41154#L281-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 41155#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 41212#L298-2 havoc eval_~tmp_ndt_2~0#1; 41782#L295-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 41777#L312 assume !(0 != eval_~tmp_ndt_3~0#1); 41772#L312-2 havoc eval_~tmp_ndt_3~0#1; 41769#L309-1 [2024-11-13 15:32:50,413 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:50,413 INFO L85 PathProgramCache]: Analyzing trace with hash -985920381, now seen corresponding path program 3 times [2024-11-13 15:32:50,413 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:50,413 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [548961000] [2024-11-13 15:32:50,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:50,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:50,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:50,422 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:32:50,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:50,431 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:32:50,431 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:50,431 INFO L85 PathProgramCache]: Analyzing trace with hash -1270292242, now seen corresponding path program 1 times [2024-11-13 15:32:50,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:50,432 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2105702154] [2024-11-13 15:32:50,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:50,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:50,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:50,435 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:32:50,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:50,439 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:32:50,439 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:32:50,440 INFO L85 PathProgramCache]: Analyzing trace with hash -1308229588, now seen corresponding path program 1 times [2024-11-13 15:32:50,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:32:50,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [971615767] [2024-11-13 15:32:50,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:32:50,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:32:50,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:50,449 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:32:50,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:50,459 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:32:51,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:51,144 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:32:51,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:32:51,355 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.11 03:32:51 BoogieIcfgContainer [2024-11-13 15:32:51,355 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-13 15:32:51,355 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-13 15:32:51,356 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-13 15:32:51,359 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-13 15:32:51,360 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:32:40" (3/4) ... [2024-11-13 15:32:51,362 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-13 15:32:51,457 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/witness.graphml [2024-11-13 15:32:51,457 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-13 15:32:51,458 INFO L158 Benchmark]: Toolchain (without parser) took 12015.55ms. Allocated memory was 142.6MB in the beginning and 427.8MB in the end (delta: 285.2MB). Free memory was 118.4MB in the beginning and 377.2MB in the end (delta: -258.8MB). Peak memory consumption was 25.7MB. Max. memory is 16.1GB. [2024-11-13 15:32:51,458 INFO L158 Benchmark]: CDTParser took 1.57ms. Allocated memory is still 167.8MB. Free memory is still 104.3MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 15:32:51,459 INFO L158 Benchmark]: CACSL2BoogieTranslator took 385.25ms. Allocated memory is still 142.6MB. Free memory was 118.1MB in the beginning and 104.9MB in the end (delta: 13.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 15:32:51,459 INFO L158 Benchmark]: Boogie Procedure Inliner took 74.08ms. Allocated memory is still 142.6MB. Free memory was 104.9MB in the beginning and 102.3MB in the end (delta: 2.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 15:32:51,459 INFO L158 Benchmark]: Boogie Preprocessor took 92.12ms. Allocated memory is still 142.6MB. Free memory was 102.3MB in the beginning and 99.6MB in the end (delta: 2.7MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 15:32:51,460 INFO L158 Benchmark]: RCFGBuilder took 997.19ms. Allocated memory is still 142.6MB. Free memory was 99.6MB in the beginning and 70.0MB in the end (delta: 29.6MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. [2024-11-13 15:32:51,462 INFO L158 Benchmark]: BuchiAutomizer took 10358.90ms. Allocated memory was 142.6MB in the beginning and 427.8MB in the end (delta: 285.2MB). Free memory was 70.0MB in the beginning and 381.5MB in the end (delta: -311.5MB). Peak memory consumption was 205.4MB. Max. memory is 16.1GB. [2024-11-13 15:32:51,462 INFO L158 Benchmark]: Witness Printer took 101.74ms. Allocated memory is still 427.8MB. Free memory was 381.5MB in the beginning and 377.2MB in the end (delta: 4.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 15:32:51,464 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 1.57ms. Allocated memory is still 167.8MB. Free memory is still 104.3MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 385.25ms. Allocated memory is still 142.6MB. Free memory was 118.1MB in the beginning and 104.9MB in the end (delta: 13.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 74.08ms. Allocated memory is still 142.6MB. Free memory was 104.9MB in the beginning and 102.3MB in the end (delta: 2.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 92.12ms. Allocated memory is still 142.6MB. Free memory was 102.3MB in the beginning and 99.6MB in the end (delta: 2.7MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 997.19ms. Allocated memory is still 142.6MB. Free memory was 99.6MB in the beginning and 70.0MB in the end (delta: 29.6MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. * BuchiAutomizer took 10358.90ms. Allocated memory was 142.6MB in the beginning and 427.8MB in the end (delta: 285.2MB). Free memory was 70.0MB in the beginning and 381.5MB in the end (delta: -311.5MB). Peak memory consumption was 205.4MB. Max. memory is 16.1GB. * Witness Printer took 101.74ms. Allocated memory is still 427.8MB. Free memory was 381.5MB in the beginning and 377.2MB in the end (delta: 4.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 20 terminating modules (19 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -1 * M_E) + 1) and consists of 3 locations. 19 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1007 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 10.1s and 20 iterations. TraceHistogramMax:2. Analysis of lassos took 6.7s. Construction of modules took 0.8s. Büchi inclusion checks took 2.2s. Highest rank in rank-based complementation 3. Minimization of det autom 17. Minimization of nondet autom 3. Automata minimization 0.6s AutomataMinimizationTime, 20 MinimizatonAttempts, 876 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 4198 SdHoareTripleChecker+Valid, 1.0s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 4197 mSDsluCounter, 10883 SdHoareTripleChecker+Invalid, 0.8s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 4900 mSDsCounter, 173 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 499 IncrementalHoareTripleChecker+Invalid, 672 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 173 mSolverCounterUnsat, 5983 mSDtfsCounter, 499 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI7 SFLT0 conc2 concLT1 SILN2 SILU0 SILI7 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital64 mio100 ax100 hnf100 lsp15 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq179 hnf100 smp100 dnf166 smp73 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 24ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 14 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.4s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 271]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0] [L573] int __retres1 ; [L577] CALL init_model() [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L577] RET init_model() [L578] CALL start_simulation() [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L521] FCALL update_channels() [L522] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L522] RET init_threads() [L523] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L349] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L354] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L523] RET fire_delta_events() [L524] CALL activate_threads() [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L403] CALL, EXPR is_master_triggered() [L153] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L156] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L166] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L168] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L403] RET, EXPR is_master_triggered() [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L175] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L185] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L187] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] RET, EXPR is_transmit1_triggered() [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L194] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L204] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L206] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] RET, EXPR is_transmit2_triggered() [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L524] RET activate_threads() [L525] CALL reset_delta_events() [L367] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L382] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L387] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L525] RET reset_delta_events() [L528] COND TRUE 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L531] kernel_st = 1 [L532] CALL eval() [L267] int tmp ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] Loop: [L271] COND TRUE 1 [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] RET, EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE !(\read(tmp_ndt_1)) [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE !(\read(tmp_ndt_2)) [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 271]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0] [L573] int __retres1 ; [L577] CALL init_model() [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L577] RET init_model() [L578] CALL start_simulation() [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L521] FCALL update_channels() [L522] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L522] RET init_threads() [L523] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L349] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L354] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L523] RET fire_delta_events() [L524] CALL activate_threads() [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L403] CALL, EXPR is_master_triggered() [L153] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L156] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L166] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L168] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L403] RET, EXPR is_master_triggered() [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L175] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L185] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L187] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] RET, EXPR is_transmit1_triggered() [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L194] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L204] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L206] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] RET, EXPR is_transmit2_triggered() [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L524] RET activate_threads() [L525] CALL reset_delta_events() [L367] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L382] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L387] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L525] RET reset_delta_events() [L528] COND TRUE 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L531] kernel_st = 1 [L532] CALL eval() [L267] int tmp ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] Loop: [L271] COND TRUE 1 [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] RET, EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE !(\read(tmp_ndt_1)) [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE !(\read(tmp_ndt_2)) [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-13 15:32:51,507 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8cb3ff57-9f0c-4a18-b9db-3d59518fc820/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)