./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.03.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.03.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4edad7c083448b81b05575191757512095bfff0f094103ddb1a592d0cd702494 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 13:31:44,693 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 13:31:44,785 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 13:31:44,791 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 13:31:44,792 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 13:31:44,824 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 13:31:44,825 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 13:31:44,825 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 13:31:44,826 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 13:31:44,826 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 13:31:44,826 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 13:31:44,827 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 13:31:44,828 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 13:31:44,828 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 13:31:44,829 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 13:31:44,829 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 13:31:44,830 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 13:31:44,830 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 13:31:44,830 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 13:31:44,830 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 13:31:44,831 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 13:31:44,831 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 13:31:44,831 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 13:31:44,831 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 13:31:44,831 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 13:31:44,831 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 13:31:44,832 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 13:31:44,832 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 13:31:44,832 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 13:31:44,832 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 13:31:44,832 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 13:31:44,832 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 13:31:44,832 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 13:31:44,833 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 13:31:44,833 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 13:31:44,834 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 13:31:44,834 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 13:31:44,834 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 13:31:44,835 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 13:31:44,835 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4edad7c083448b81b05575191757512095bfff0f094103ddb1a592d0cd702494 [2024-11-13 13:31:45,201 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 13:31:45,212 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 13:31:45,215 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 13:31:45,217 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 13:31:45,217 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 13:31:45,219 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/transmitter.03.cil.c Unable to find full path for "g++" [2024-11-13 13:31:47,397 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 13:31:47,725 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 13:31:47,726 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/sv-benchmarks/c/systemc/transmitter.03.cil.c [2024-11-13 13:31:47,743 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/data/dcd8155eb/97987e7384844cc9bde8a549e8195db3/FLAG5de34c3b2 [2024-11-13 13:31:47,760 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/data/dcd8155eb/97987e7384844cc9bde8a549e8195db3 [2024-11-13 13:31:47,765 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 13:31:47,767 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 13:31:47,769 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 13:31:47,769 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 13:31:47,775 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 13:31:47,777 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 01:31:47" (1/1) ... [2024-11-13 13:31:47,780 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@15e85f3f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:47, skipping insertion in model container [2024-11-13 13:31:47,781 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 01:31:47" (1/1) ... [2024-11-13 13:31:47,831 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 13:31:48,138 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 13:31:48,158 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 13:31:48,227 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 13:31:48,249 INFO L204 MainTranslator]: Completed translation [2024-11-13 13:31:48,249 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:48 WrapperNode [2024-11-13 13:31:48,250 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 13:31:48,251 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 13:31:48,251 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 13:31:48,251 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 13:31:48,259 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:48" (1/1) ... [2024-11-13 13:31:48,269 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:48" (1/1) ... [2024-11-13 13:31:48,326 INFO L138 Inliner]: procedures = 34, calls = 40, calls flagged for inlining = 35, calls inlined = 57, statements flattened = 734 [2024-11-13 13:31:48,327 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 13:31:48,328 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 13:31:48,329 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 13:31:48,329 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 13:31:48,343 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:48" (1/1) ... [2024-11-13 13:31:48,343 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:48" (1/1) ... [2024-11-13 13:31:48,351 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:48" (1/1) ... [2024-11-13 13:31:48,388 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 13:31:48,391 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:48" (1/1) ... [2024-11-13 13:31:48,392 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:48" (1/1) ... [2024-11-13 13:31:48,413 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:48" (1/1) ... [2024-11-13 13:31:48,436 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:48" (1/1) ... [2024-11-13 13:31:48,438 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:48" (1/1) ... [2024-11-13 13:31:48,441 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:48" (1/1) ... [2024-11-13 13:31:48,445 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 13:31:48,446 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 13:31:48,446 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 13:31:48,447 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 13:31:48,448 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:48" (1/1) ... [2024-11-13 13:31:48,454 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:48,470 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:48,487 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:48,496 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 13:31:48,523 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 13:31:48,523 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 13:31:48,523 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 13:31:48,524 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 13:31:48,614 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 13:31:48,616 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 13:31:49,577 INFO L? ?]: Removed 128 outVars from TransFormulas that were not future-live. [2024-11-13 13:31:49,578 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 13:31:49,610 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 13:31:49,613 INFO L316 CfgBuilder]: Removed 7 assume(true) statements. [2024-11-13 13:31:49,614 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:31:49 BoogieIcfgContainer [2024-11-13 13:31:49,614 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 13:31:49,615 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 13:31:49,616 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 13:31:49,622 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 13:31:49,623 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:31:49,623 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 01:31:47" (1/3) ... [2024-11-13 13:31:49,624 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1eadb4da and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 01:31:49, skipping insertion in model container [2024-11-13 13:31:49,625 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:31:49,626 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:48" (2/3) ... [2024-11-13 13:31:49,626 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1eadb4da and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 01:31:49, skipping insertion in model container [2024-11-13 13:31:49,626 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:31:49,627 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:31:49" (3/3) ... [2024-11-13 13:31:49,628 INFO L333 chiAutomizerObserver]: Analyzing ICFG transmitter.03.cil.c [2024-11-13 13:31:49,711 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 13:31:49,712 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 13:31:49,712 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 13:31:49,712 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 13:31:49,712 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 13:31:49,713 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 13:31:49,713 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 13:31:49,713 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 13:31:49,722 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 296 states, 295 states have (on average 1.5322033898305085) internal successors, (452), 295 states have internal predecessors, (452), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:49,762 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 239 [2024-11-13 13:31:49,762 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:31:49,763 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:31:49,774 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:49,775 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:49,775 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 13:31:49,776 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 296 states, 295 states have (on average 1.5322033898305085) internal successors, (452), 295 states have internal predecessors, (452), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:49,801 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 239 [2024-11-13 13:31:49,801 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:31:49,801 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:31:49,803 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:49,803 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:49,812 INFO L745 eck$LassoCheckResult]: Stem: 192#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 205#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 292#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 200#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 178#L281true assume !(1 == ~m_i~0);~m_st~0 := 2; 241#L281-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 35#L286-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 219#L291-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 236#L296-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17#L418true assume !(0 == ~M_E~0); 177#L418-2true assume !(0 == ~T1_E~0); 227#L423-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 239#L428-1true assume !(0 == ~T3_E~0); 223#L433-1true assume !(0 == ~E_1~0); 209#L438-1true assume !(0 == ~E_2~0); 135#L443-1true assume !(0 == ~E_3~0); 130#L448-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96#L197true assume !(1 == ~m_pc~0); 268#L197-2true is_master_triggered_~__retres1~0#1 := 0; 271#L208true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 170#is_master_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 247#L510true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7#L510-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 269#L216true assume 1 == ~t1_pc~0; 29#L217true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 125#L227true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8#L518true assume !(0 != activate_threads_~tmp___0~0#1); 143#L518-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 278#L235true assume !(1 == ~t2_pc~0); 215#L235-2true is_transmit2_triggered_~__retres1~2#1 := 0; 85#L246true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 293#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 256#L526true assume !(0 != activate_threads_~tmp___1~0#1); 267#L526-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75#L254true assume 1 == ~t3_pc~0; 22#L255true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 91#L265true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 116#L534true assume !(0 != activate_threads_~tmp___2~0#1); 81#L534-2true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2#L461true assume !(1 == ~M_E~0); 36#L461-2true assume !(1 == ~T1_E~0); 237#L466-1true assume !(1 == ~T2_E~0); 274#L471-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 50#L476-1true assume !(1 == ~E_1~0); 277#L481-1true assume !(1 == ~E_2~0); 157#L486-1true assume !(1 == ~E_3~0); 59#L491-1true assume { :end_inline_reset_delta_events } true; 11#L652-2true [2024-11-13 13:31:49,813 INFO L747 eck$LassoCheckResult]: Loop: 11#L652-2true assume !false; 67#L653true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 162#L393-1true assume false; 114#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 147#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 294#L418-3true assume 0 == ~M_E~0;~M_E~0 := 1; 142#L418-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 166#L423-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 137#L428-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 95#L433-3true assume 0 == ~E_1~0;~E_1~0 := 1; 186#L438-3true assume !(0 == ~E_2~0); 193#L443-3true assume 0 == ~E_3~0;~E_3~0 := 1; 3#L448-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 195#L197-12true assume 1 == ~m_pc~0; 201#L198-4true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 73#L208-4true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 141#is_master_triggered_returnLabel#5true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10#L510-12true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 111#L510-14true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72#L216-12true assume 1 == ~t1_pc~0; 286#L217-4true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 108#L227-4true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 243#is_transmit1_triggered_returnLabel#5true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 78#L518-12true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34#L518-14true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 282#L235-12true assume !(1 == ~t2_pc~0); 84#L235-14true is_transmit2_triggered_~__retres1~2#1 := 0; 257#L246-4true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79#is_transmit2_triggered_returnLabel#5true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 289#L526-12true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 131#L526-14true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 250#L254-12true assume 1 == ~t3_pc~0; 25#L255-4true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 134#L265-4true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51#is_transmit3_triggered_returnLabel#5true activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 113#L534-12true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 158#L534-14true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74#L461-3true assume 1 == ~M_E~0;~M_E~0 := 2; 295#L461-5true assume !(1 == ~T1_E~0); 148#L466-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 246#L471-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 69#L476-3true assume 1 == ~E_1~0;~E_1~0 := 2; 139#L481-3true assume 1 == ~E_2~0;~E_2~0 := 2; 90#L486-3true assume 1 == ~E_3~0;~E_3~0 := 2; 264#L491-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 24#L309-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 37#L331-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 259#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 149#L671true assume !(0 == start_simulation_~tmp~3#1); 183#L671-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 296#L309-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 155#L331-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 48#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 234#L626true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 161#L633true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 164#stop_simulation_returnLabel#1true start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 169#L684true assume !(0 != start_simulation_~tmp___0~1#1); 11#L652-2true [2024-11-13 13:31:49,819 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:49,820 INFO L85 PathProgramCache]: Analyzing trace with hash -1773697160, now seen corresponding path program 1 times [2024-11-13 13:31:49,832 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:49,832 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1195377566] [2024-11-13 13:31:49,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:49,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:49,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:50,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:50,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:50,100 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1195377566] [2024-11-13 13:31:50,101 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1195377566] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:50,102 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:50,102 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:31:50,104 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [783423833] [2024-11-13 13:31:50,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:50,109 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:31:50,110 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:50,111 INFO L85 PathProgramCache]: Analyzing trace with hash 475758155, now seen corresponding path program 1 times [2024-11-13 13:31:50,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:50,111 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1820541772] [2024-11-13 13:31:50,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:50,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:50,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:50,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:50,189 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:50,189 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1820541772] [2024-11-13 13:31:50,189 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1820541772] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:50,189 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:50,189 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:31:50,189 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [934435903] [2024-11-13 13:31:50,189 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:50,191 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:31:50,191 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:50,225 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:31:50,225 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:31:50,228 INFO L87 Difference]: Start difference. First operand has 296 states, 295 states have (on average 1.5322033898305085) internal successors, (452), 295 states have internal predecessors, (452), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:50,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:50,284 INFO L93 Difference]: Finished difference Result 294 states and 434 transitions. [2024-11-13 13:31:50,285 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 294 states and 434 transitions. [2024-11-13 13:31:50,291 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2024-11-13 13:31:50,302 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 294 states to 288 states and 428 transitions. [2024-11-13 13:31:50,304 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 288 [2024-11-13 13:31:50,305 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 288 [2024-11-13 13:31:50,306 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 428 transitions. [2024-11-13 13:31:50,307 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:31:50,308 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 428 transitions. [2024-11-13 13:31:50,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 428 transitions. [2024-11-13 13:31:50,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2024-11-13 13:31:50,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 288 states, 288 states have (on average 1.4861111111111112) internal successors, (428), 287 states have internal predecessors, (428), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:50,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 428 transitions. [2024-11-13 13:31:50,350 INFO L240 hiAutomatonCegarLoop]: Abstraction has 288 states and 428 transitions. [2024-11-13 13:31:50,351 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:31:50,356 INFO L424 stractBuchiCegarLoop]: Abstraction has 288 states and 428 transitions. [2024-11-13 13:31:50,356 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 13:31:50,356 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 288 states and 428 transitions. [2024-11-13 13:31:50,359 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2024-11-13 13:31:50,359 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:31:50,360 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:31:50,362 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:50,362 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:50,363 INFO L745 eck$LassoCheckResult]: Stem: 857#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 858#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 867#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 866#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 841#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 842#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 668#L286-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 669#L291-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 874#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 628#L418 assume !(0 == ~M_E~0); 629#L418-2 assume !(0 == ~T1_E~0); 840#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 877#L428-1 assume !(0 == ~T3_E~0); 875#L433-1 assume !(0 == ~E_1~0); 869#L438-1 assume !(0 == ~E_2~0); 806#L443-1 assume !(0 == ~E_3~0); 800#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 767#L197 assume !(1 == ~m_pc~0); 764#L197-2 is_master_triggered_~__retres1~0#1 := 0; 763#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 833#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 834#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 607#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 608#L216 assume 1 == ~t1_pc~0; 656#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 657#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 693#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 609#L518 assume !(0 != activate_threads_~tmp___0~0#1); 610#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 814#L235 assume !(1 == ~t2_pc~0); 871#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 752#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 753#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 882#L526 assume !(0 != activate_threads_~tmp___1~0#1); 883#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 735#L254 assume 1 == ~t3_pc~0; 638#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 639#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 620#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 621#L534 assume !(0 != activate_threads_~tmp___2~0#1); 746#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 599#L461 assume !(1 == ~M_E~0); 600#L461-2 assume !(1 == ~T1_E~0); 670#L466-1 assume !(1 == ~T2_E~0); 880#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 696#L476-1 assume !(1 == ~E_1~0); 697#L481-1 assume !(1 == ~E_2~0); 828#L486-1 assume !(1 == ~E_3~0); 711#L491-1 assume { :end_inline_reset_delta_events } true; 618#L652-2 [2024-11-13 13:31:50,363 INFO L747 eck$LassoCheckResult]: Loop: 618#L652-2 assume !false; 619#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 687#L393-1 assume !false; 685#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 686#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 664#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 622#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 623#L346 assume !(0 != eval_~tmp~0#1); 716#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 787#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 818#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 811#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 812#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 809#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 765#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 766#L438-3 assume !(0 == ~E_2~0); 853#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 601#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 602#L197-12 assume !(1 == ~m_pc~0); 859#L197-14 is_master_triggered_~__retres1~0#1 := 0; 731#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 732#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 614#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 615#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 728#L216-12 assume 1 == ~t1_pc~0; 729#L217-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 781#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 782#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 741#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 666#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 667#L235-12 assume 1 == ~t2_pc~0; 868#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 750#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 742#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 743#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 801#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 802#L254-12 assume 1 == ~t3_pc~0; 647#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 648#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 694#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 695#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 786#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 733#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 734#L461-5 assume !(1 == ~T1_E~0); 819#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 820#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 725#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 726#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 757#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 758#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 641#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 642#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 671#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 821#L671 assume !(0 == start_simulation_~tmp~3#1); 625#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 846#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 723#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 691#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 692#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 829#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 830#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 831#L684 assume !(0 != start_simulation_~tmp___0~1#1); 618#L652-2 [2024-11-13 13:31:50,364 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:50,364 INFO L85 PathProgramCache]: Analyzing trace with hash 1627783798, now seen corresponding path program 1 times [2024-11-13 13:31:50,365 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:50,365 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1473732123] [2024-11-13 13:31:50,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:50,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:50,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:50,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:50,453 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:50,453 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1473732123] [2024-11-13 13:31:50,454 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1473732123] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:50,454 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:50,454 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:31:50,454 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1660408750] [2024-11-13 13:31:50,454 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:50,454 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:31:50,455 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:50,455 INFO L85 PathProgramCache]: Analyzing trace with hash 1858634150, now seen corresponding path program 1 times [2024-11-13 13:31:50,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:50,455 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [200597550] [2024-11-13 13:31:50,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:50,458 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:50,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:50,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:50,621 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:50,621 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [200597550] [2024-11-13 13:31:50,622 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [200597550] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:50,622 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:50,622 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:31:50,622 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1741429861] [2024-11-13 13:31:50,622 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:50,623 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:31:50,623 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:50,623 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:31:50,624 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:31:50,624 INFO L87 Difference]: Start difference. First operand 288 states and 428 transitions. cyclomatic complexity: 141 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:50,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:50,653 INFO L93 Difference]: Finished difference Result 288 states and 427 transitions. [2024-11-13 13:31:50,654 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 288 states and 427 transitions. [2024-11-13 13:31:50,657 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2024-11-13 13:31:50,660 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 288 states to 288 states and 427 transitions. [2024-11-13 13:31:50,660 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 288 [2024-11-13 13:31:50,661 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 288 [2024-11-13 13:31:50,661 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 427 transitions. [2024-11-13 13:31:50,663 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:31:50,663 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 427 transitions. [2024-11-13 13:31:50,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 427 transitions. [2024-11-13 13:31:50,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2024-11-13 13:31:50,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 288 states, 288 states have (on average 1.4826388888888888) internal successors, (427), 287 states have internal predecessors, (427), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:50,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 427 transitions. [2024-11-13 13:31:50,677 INFO L240 hiAutomatonCegarLoop]: Abstraction has 288 states and 427 transitions. [2024-11-13 13:31:50,677 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:31:50,678 INFO L424 stractBuchiCegarLoop]: Abstraction has 288 states and 427 transitions. [2024-11-13 13:31:50,678 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 13:31:50,678 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 288 states and 427 transitions. [2024-11-13 13:31:50,681 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2024-11-13 13:31:50,681 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:31:50,681 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:31:50,683 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:50,683 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:50,684 INFO L745 eck$LassoCheckResult]: Stem: 1440#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 1441#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1450#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1449#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1424#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 1425#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1251#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1252#L291-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1457#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1214#L418 assume !(0 == ~M_E~0); 1215#L418-2 assume !(0 == ~T1_E~0); 1423#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1460#L428-1 assume !(0 == ~T3_E~0); 1458#L433-1 assume !(0 == ~E_1~0); 1452#L438-1 assume !(0 == ~E_2~0); 1389#L443-1 assume !(0 == ~E_3~0); 1383#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1350#L197 assume !(1 == ~m_pc~0); 1347#L197-2 is_master_triggered_~__retres1~0#1 := 0; 1346#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1416#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1417#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1190#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1191#L216 assume 1 == ~t1_pc~0; 1239#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1240#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1276#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1192#L518 assume !(0 != activate_threads_~tmp___0~0#1); 1193#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1398#L235 assume !(1 == ~t2_pc~0); 1456#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1335#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1336#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1465#L526 assume !(0 != activate_threads_~tmp___1~0#1); 1466#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1318#L254 assume 1 == ~t3_pc~0; 1221#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1222#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1203#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1204#L534 assume !(0 != activate_threads_~tmp___2~0#1); 1329#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1182#L461 assume !(1 == ~M_E~0); 1183#L461-2 assume !(1 == ~T1_E~0); 1253#L466-1 assume !(1 == ~T2_E~0); 1463#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1279#L476-1 assume !(1 == ~E_1~0); 1280#L481-1 assume !(1 == ~E_2~0); 1411#L486-1 assume !(1 == ~E_3~0); 1298#L491-1 assume { :end_inline_reset_delta_events } true; 1201#L652-2 [2024-11-13 13:31:50,684 INFO L747 eck$LassoCheckResult]: Loop: 1201#L652-2 assume !false; 1202#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1270#L393-1 assume !false; 1268#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1269#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1247#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1205#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1206#L346 assume !(0 != eval_~tmp~0#1); 1299#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1370#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1401#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1394#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1395#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1392#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1348#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1349#L438-3 assume !(0 == ~E_2~0); 1436#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1184#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1185#L197-12 assume !(1 == ~m_pc~0); 1442#L197-14 is_master_triggered_~__retres1~0#1 := 0; 1314#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1315#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1197#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1198#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1311#L216-12 assume 1 == ~t1_pc~0; 1312#L217-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1364#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1365#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1322#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1249#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1250#L235-12 assume !(1 == ~t2_pc~0); 1332#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 1333#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1325#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1326#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1384#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1385#L254-12 assume !(1 == ~t3_pc~0); 1232#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 1231#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1277#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1278#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1369#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1316#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1317#L461-5 assume !(1 == ~T1_E~0); 1402#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1403#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1308#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1309#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1340#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1341#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1227#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1228#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1254#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1404#L671 assume !(0 == start_simulation_~tmp~3#1); 1208#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1429#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1306#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1274#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 1275#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1412#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1413#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1414#L684 assume !(0 != start_simulation_~tmp___0~1#1); 1201#L652-2 [2024-11-13 13:31:50,684 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:50,685 INFO L85 PathProgramCache]: Analyzing trace with hash -1769790220, now seen corresponding path program 1 times [2024-11-13 13:31:50,685 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:50,685 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1879645607] [2024-11-13 13:31:50,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:50,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:50,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:50,782 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:50,784 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:50,785 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1879645607] [2024-11-13 13:31:50,785 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1879645607] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:50,785 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:50,785 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:31:50,785 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [41112718] [2024-11-13 13:31:50,785 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:50,786 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:31:50,786 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:50,786 INFO L85 PathProgramCache]: Analyzing trace with hash -878574044, now seen corresponding path program 1 times [2024-11-13 13:31:50,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:50,787 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1841057227] [2024-11-13 13:31:50,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:50,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:50,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:50,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:50,908 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:50,908 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1841057227] [2024-11-13 13:31:50,909 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1841057227] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:50,909 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:50,909 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:31:50,909 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1655912916] [2024-11-13 13:31:50,909 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:50,910 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:31:50,910 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:50,910 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:31:50,910 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:31:50,911 INFO L87 Difference]: Start difference. First operand 288 states and 427 transitions. cyclomatic complexity: 140 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:50,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:50,935 INFO L93 Difference]: Finished difference Result 288 states and 426 transitions. [2024-11-13 13:31:50,936 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 288 states and 426 transitions. [2024-11-13 13:31:50,939 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2024-11-13 13:31:50,942 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 288 states to 288 states and 426 transitions. [2024-11-13 13:31:50,943 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 288 [2024-11-13 13:31:50,947 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 288 [2024-11-13 13:31:50,947 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 426 transitions. [2024-11-13 13:31:50,949 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:31:50,949 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 426 transitions. [2024-11-13 13:31:50,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 426 transitions. [2024-11-13 13:31:50,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2024-11-13 13:31:50,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 288 states, 288 states have (on average 1.4791666666666667) internal successors, (426), 287 states have internal predecessors, (426), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:50,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 426 transitions. [2024-11-13 13:31:50,973 INFO L240 hiAutomatonCegarLoop]: Abstraction has 288 states and 426 transitions. [2024-11-13 13:31:50,973 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:31:50,974 INFO L424 stractBuchiCegarLoop]: Abstraction has 288 states and 426 transitions. [2024-11-13 13:31:50,975 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 13:31:50,976 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 288 states and 426 transitions. [2024-11-13 13:31:50,980 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2024-11-13 13:31:50,980 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:31:50,981 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:31:50,983 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:50,984 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:50,984 INFO L745 eck$LassoCheckResult]: Stem: 2023#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 2024#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2033#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2032#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2007#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 2008#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1834#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1835#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2040#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1799#L418 assume !(0 == ~M_E~0); 1800#L418-2 assume !(0 == ~T1_E~0); 2006#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2043#L428-1 assume !(0 == ~T3_E~0); 2041#L433-1 assume !(0 == ~E_1~0); 2035#L438-1 assume !(0 == ~E_2~0); 1972#L443-1 assume !(0 == ~E_3~0); 1966#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1933#L197 assume !(1 == ~m_pc~0); 1930#L197-2 is_master_triggered_~__retres1~0#1 := 0; 1929#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1999#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2000#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1773#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1774#L216 assume 1 == ~t1_pc~0; 1822#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1823#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1859#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1778#L518 assume !(0 != activate_threads_~tmp___0~0#1); 1779#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1981#L235 assume !(1 == ~t2_pc~0); 2039#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1918#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1919#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2048#L526 assume !(0 != activate_threads_~tmp___1~0#1); 2049#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1904#L254 assume 1 == ~t3_pc~0; 1804#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1805#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1788#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1789#L534 assume !(0 != activate_threads_~tmp___2~0#1); 1912#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1765#L461 assume !(1 == ~M_E~0); 1766#L461-2 assume !(1 == ~T1_E~0); 1836#L466-1 assume !(1 == ~T2_E~0); 2046#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1862#L476-1 assume !(1 == ~E_1~0); 1863#L481-1 assume !(1 == ~E_2~0); 1994#L486-1 assume !(1 == ~E_3~0); 1881#L491-1 assume { :end_inline_reset_delta_events } true; 1784#L652-2 [2024-11-13 13:31:50,986 INFO L747 eck$LassoCheckResult]: Loop: 1784#L652-2 assume !false; 1785#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1851#L393-1 assume !false; 1855#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1856#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1830#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1786#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1787#L346 assume !(0 != eval_~tmp~0#1); 1882#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1953#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1984#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1977#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1978#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1973#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1931#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1932#L438-3 assume !(0 == ~E_2~0); 2017#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1767#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1768#L197-12 assume !(1 == ~m_pc~0); 2025#L197-14 is_master_triggered_~__retres1~0#1 := 0; 1897#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1898#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1780#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1781#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1894#L216-12 assume 1 == ~t1_pc~0; 1895#L217-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1947#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1948#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1907#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1832#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1833#L235-12 assume 1 == ~t2_pc~0; 2034#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1916#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1908#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1909#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1967#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1968#L254-12 assume 1 == ~t3_pc~0; 1813#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1814#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1860#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1861#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1952#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1899#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1900#L461-5 assume !(1 == ~T1_E~0); 1985#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1986#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1891#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1892#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1923#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1924#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1810#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1811#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1837#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1987#L671 assume !(0 == start_simulation_~tmp~3#1); 1793#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2012#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1889#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1857#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 1858#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1995#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1996#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1997#L684 assume !(0 != start_simulation_~tmp___0~1#1); 1784#L652-2 [2024-11-13 13:31:50,986 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:50,991 INFO L85 PathProgramCache]: Analyzing trace with hash -2017936714, now seen corresponding path program 1 times [2024-11-13 13:31:50,991 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:50,991 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1223229881] [2024-11-13 13:31:50,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:50,991 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:51,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:51,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:51,115 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:51,116 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1223229881] [2024-11-13 13:31:51,116 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1223229881] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:51,116 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:51,116 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:31:51,116 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [558716406] [2024-11-13 13:31:51,117 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:51,117 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:31:51,118 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:51,118 INFO L85 PathProgramCache]: Analyzing trace with hash 1858634150, now seen corresponding path program 2 times [2024-11-13 13:31:51,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:51,118 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1078446662] [2024-11-13 13:31:51,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:51,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:51,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:51,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:51,236 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:51,236 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1078446662] [2024-11-13 13:31:51,236 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1078446662] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:51,237 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:51,237 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:31:51,237 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [509947683] [2024-11-13 13:31:51,237 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:51,237 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:31:51,237 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:51,238 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:31:51,238 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:31:51,238 INFO L87 Difference]: Start difference. First operand 288 states and 426 transitions. cyclomatic complexity: 139 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:51,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:51,279 INFO L93 Difference]: Finished difference Result 288 states and 421 transitions. [2024-11-13 13:31:51,279 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 288 states and 421 transitions. [2024-11-13 13:31:51,283 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2024-11-13 13:31:51,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 288 states to 288 states and 421 transitions. [2024-11-13 13:31:51,286 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 288 [2024-11-13 13:31:51,286 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 288 [2024-11-13 13:31:51,287 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 421 transitions. [2024-11-13 13:31:51,287 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:31:51,288 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 421 transitions. [2024-11-13 13:31:51,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 421 transitions. [2024-11-13 13:31:51,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2024-11-13 13:31:51,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 288 states, 288 states have (on average 1.4618055555555556) internal successors, (421), 287 states have internal predecessors, (421), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:51,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 421 transitions. [2024-11-13 13:31:51,299 INFO L240 hiAutomatonCegarLoop]: Abstraction has 288 states and 421 transitions. [2024-11-13 13:31:51,299 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:31:51,300 INFO L424 stractBuchiCegarLoop]: Abstraction has 288 states and 421 transitions. [2024-11-13 13:31:51,301 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 13:31:51,301 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 288 states and 421 transitions. [2024-11-13 13:31:51,304 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2024-11-13 13:31:51,304 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:31:51,304 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:31:51,305 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:51,305 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:51,306 INFO L745 eck$LassoCheckResult]: Stem: 2606#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 2607#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2616#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2615#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2590#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 2591#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2417#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2418#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2623#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2377#L418 assume !(0 == ~M_E~0); 2378#L418-2 assume !(0 == ~T1_E~0); 2589#L423-1 assume !(0 == ~T2_E~0); 2626#L428-1 assume !(0 == ~T3_E~0); 2624#L433-1 assume !(0 == ~E_1~0); 2618#L438-1 assume !(0 == ~E_2~0); 2555#L443-1 assume !(0 == ~E_3~0); 2549#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2516#L197 assume !(1 == ~m_pc~0); 2513#L197-2 is_master_triggered_~__retres1~0#1 := 0; 2512#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2582#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2583#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2356#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2357#L216 assume 1 == ~t1_pc~0; 2405#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2406#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2442#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2358#L518 assume !(0 != activate_threads_~tmp___0~0#1); 2359#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2562#L235 assume !(1 == ~t2_pc~0); 2620#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2500#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2501#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2631#L526 assume !(0 != activate_threads_~tmp___1~0#1); 2632#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2484#L254 assume 1 == ~t3_pc~0; 2387#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2388#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2369#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2370#L534 assume !(0 != activate_threads_~tmp___2~0#1); 2495#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2348#L461 assume !(1 == ~M_E~0); 2349#L461-2 assume !(1 == ~T1_E~0); 2419#L466-1 assume !(1 == ~T2_E~0); 2629#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2443#L476-1 assume !(1 == ~E_1~0); 2444#L481-1 assume !(1 == ~E_2~0); 2577#L486-1 assume !(1 == ~E_3~0); 2460#L491-1 assume { :end_inline_reset_delta_events } true; 2365#L652-2 [2024-11-13 13:31:51,306 INFO L747 eck$LassoCheckResult]: Loop: 2365#L652-2 assume !false; 2366#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2436#L393-1 assume !false; 2434#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2435#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2413#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2371#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2372#L346 assume !(0 != eval_~tmp~0#1); 2465#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2536#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2567#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2560#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2561#L423-3 assume !(0 == ~T2_E~0); 2556#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2514#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2515#L438-3 assume !(0 == ~E_2~0); 2600#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2350#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2351#L197-12 assume !(1 == ~m_pc~0); 2608#L197-14 is_master_triggered_~__retres1~0#1 := 0; 2480#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2481#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2363#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2364#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2477#L216-12 assume 1 == ~t1_pc~0; 2478#L217-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2530#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2531#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2490#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2415#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2416#L235-12 assume !(1 == ~t2_pc~0); 2498#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 2499#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2491#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2492#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2550#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2551#L254-12 assume 1 == ~t3_pc~0; 2396#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2397#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2445#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2446#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2535#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2482#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2483#L461-5 assume !(1 == ~T1_E~0); 2568#L466-3 assume !(1 == ~T2_E~0); 2569#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2474#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2475#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2506#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2507#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2393#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2394#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2420#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2570#L671 assume !(0 == start_simulation_~tmp~3#1); 2376#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2595#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2472#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2440#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 2441#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2578#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2579#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 2580#L684 assume !(0 != start_simulation_~tmp___0~1#1); 2365#L652-2 [2024-11-13 13:31:51,307 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:51,307 INFO L85 PathProgramCache]: Analyzing trace with hash 1247671284, now seen corresponding path program 1 times [2024-11-13 13:31:51,307 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:51,307 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [779608033] [2024-11-13 13:31:51,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:51,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:51,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:51,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:51,410 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:51,410 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [779608033] [2024-11-13 13:31:51,410 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [779608033] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:51,410 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:51,410 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:31:51,411 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [699481462] [2024-11-13 13:31:51,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:51,411 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:31:51,412 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:51,412 INFO L85 PathProgramCache]: Analyzing trace with hash 302383809, now seen corresponding path program 1 times [2024-11-13 13:31:51,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:51,412 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [597156793] [2024-11-13 13:31:51,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:51,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:51,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:51,506 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:51,506 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:51,506 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [597156793] [2024-11-13 13:31:51,506 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [597156793] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:51,507 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:51,507 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:31:51,507 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [141406727] [2024-11-13 13:31:51,507 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:51,508 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:31:51,508 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:51,508 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:31:51,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:31:51,509 INFO L87 Difference]: Start difference. First operand 288 states and 421 transitions. cyclomatic complexity: 134 Second operand has 5 states, 5 states have (on average 9.8) internal successors, (49), 5 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:51,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:51,711 INFO L93 Difference]: Finished difference Result 306 states and 439 transitions. [2024-11-13 13:31:51,711 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 306 states and 439 transitions. [2024-11-13 13:31:51,716 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 250 [2024-11-13 13:31:51,719 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 306 states to 306 states and 439 transitions. [2024-11-13 13:31:51,720 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 306 [2024-11-13 13:31:51,720 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 306 [2024-11-13 13:31:51,721 INFO L73 IsDeterministic]: Start isDeterministic. Operand 306 states and 439 transitions. [2024-11-13 13:31:51,722 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:31:51,722 INFO L218 hiAutomatonCegarLoop]: Abstraction has 306 states and 439 transitions. [2024-11-13 13:31:51,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 306 states and 439 transitions. [2024-11-13 13:31:51,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 306 to 306. [2024-11-13 13:31:51,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 306 states, 306 states have (on average 1.434640522875817) internal successors, (439), 305 states have internal predecessors, (439), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:51,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 306 states to 306 states and 439 transitions. [2024-11-13 13:31:51,740 INFO L240 hiAutomatonCegarLoop]: Abstraction has 306 states and 439 transitions. [2024-11-13 13:31:51,740 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:31:51,741 INFO L424 stractBuchiCegarLoop]: Abstraction has 306 states and 439 transitions. [2024-11-13 13:31:51,743 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 13:31:51,743 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 306 states and 439 transitions. [2024-11-13 13:31:51,746 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 250 [2024-11-13 13:31:51,746 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:31:51,746 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:31:51,748 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:51,750 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:51,751 INFO L745 eck$LassoCheckResult]: Stem: 3211#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 3212#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3222#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3220#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3195#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 3196#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3020#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3021#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3229#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2980#L418 assume !(0 == ~M_E~0); 2981#L418-2 assume !(0 == ~T1_E~0); 3194#L423-1 assume !(0 == ~T2_E~0); 3232#L428-1 assume !(0 == ~T3_E~0); 3230#L433-1 assume !(0 == ~E_1~0); 3224#L438-1 assume !(0 == ~E_2~0); 3159#L443-1 assume !(0 == ~E_3~0); 3153#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3119#L197 assume !(1 == ~m_pc~0); 3116#L197-2 is_master_triggered_~__retres1~0#1 := 0; 3243#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3187#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3188#L510 assume !(0 != activate_threads_~tmp~1#1); 2959#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2960#L216 assume 1 == ~t1_pc~0; 3008#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3009#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3045#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2961#L518 assume !(0 != activate_threads_~tmp___0~0#1); 2962#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3166#L235 assume !(1 == ~t2_pc~0); 3226#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3103#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3104#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3237#L526 assume !(0 != activate_threads_~tmp___1~0#1); 3238#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3087#L254 assume 1 == ~t3_pc~0; 2990#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2991#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2972#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2973#L534 assume !(0 != activate_threads_~tmp___2~0#1); 3098#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2951#L461 assume !(1 == ~M_E~0); 2952#L461-2 assume !(1 == ~T1_E~0); 3022#L466-1 assume !(1 == ~T2_E~0); 3235#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3046#L476-1 assume !(1 == ~E_1~0); 3047#L481-1 assume !(1 == ~E_2~0); 3182#L486-1 assume !(1 == ~E_3~0); 3063#L491-1 assume { :end_inline_reset_delta_events } true; 2968#L652-2 [2024-11-13 13:31:51,751 INFO L747 eck$LassoCheckResult]: Loop: 2968#L652-2 assume !false; 2969#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3039#L393-1 assume !false; 3037#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3038#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3016#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2974#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2975#L346 assume !(0 != eval_~tmp~0#1); 3068#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3139#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3171#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3164#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3165#L423-3 assume !(0 == ~T2_E~0); 3160#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3117#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3118#L438-3 assume !(0 == ~E_2~0); 3205#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2953#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2954#L197-12 assume !(1 == ~m_pc~0); 3213#L197-14 is_master_triggered_~__retres1~0#1 := 0; 3083#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3084#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2966#L510-12 assume !(0 != activate_threads_~tmp~1#1); 2967#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3080#L216-12 assume 1 == ~t1_pc~0; 3081#L217-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3133#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3134#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3093#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3018#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3019#L235-12 assume 1 == ~t2_pc~0; 3223#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3102#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3094#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3095#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3154#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3155#L254-12 assume 1 == ~t3_pc~0; 2999#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3000#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3048#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3049#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3138#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3085#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3086#L461-5 assume !(1 == ~T1_E~0); 3172#L466-3 assume !(1 == ~T2_E~0); 3173#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3077#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3078#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3109#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3110#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2996#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2997#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3023#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 3174#L671 assume !(0 == start_simulation_~tmp~3#1); 2979#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3200#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3075#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3043#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 3044#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3183#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3184#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 3185#L684 assume !(0 != start_simulation_~tmp___0~1#1); 2968#L652-2 [2024-11-13 13:31:51,752 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:51,754 INFO L85 PathProgramCache]: Analyzing trace with hash 738198194, now seen corresponding path program 1 times [2024-11-13 13:31:51,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:51,755 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [644773934] [2024-11-13 13:31:51,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:51,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:51,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:51,872 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:51,872 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:51,872 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [644773934] [2024-11-13 13:31:51,872 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [644773934] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:51,872 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:51,873 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:31:51,873 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1393873935] [2024-11-13 13:31:51,873 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:51,873 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:31:51,873 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:51,874 INFO L85 PathProgramCache]: Analyzing trace with hash -1988398112, now seen corresponding path program 1 times [2024-11-13 13:31:51,874 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:51,874 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184083406] [2024-11-13 13:31:51,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:51,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:51,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:51,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:51,947 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:51,947 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [184083406] [2024-11-13 13:31:51,947 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [184083406] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:51,947 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:51,948 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:31:51,948 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1038713745] [2024-11-13 13:31:51,948 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:51,949 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:31:51,949 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:51,951 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:31:51,951 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:31:51,951 INFO L87 Difference]: Start difference. First operand 306 states and 439 transitions. cyclomatic complexity: 134 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:52,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:52,032 INFO L93 Difference]: Finished difference Result 517 states and 735 transitions. [2024-11-13 13:31:52,032 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 517 states and 735 transitions. [2024-11-13 13:31:52,040 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 460 [2024-11-13 13:31:52,046 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 517 states to 517 states and 735 transitions. [2024-11-13 13:31:52,046 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 517 [2024-11-13 13:31:52,047 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 517 [2024-11-13 13:31:52,048 INFO L73 IsDeterministic]: Start isDeterministic. Operand 517 states and 735 transitions. [2024-11-13 13:31:52,051 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:31:52,051 INFO L218 hiAutomatonCegarLoop]: Abstraction has 517 states and 735 transitions. [2024-11-13 13:31:52,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 517 states and 735 transitions. [2024-11-13 13:31:52,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 517 to 515. [2024-11-13 13:31:52,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 515 states, 515 states have (on average 1.4233009708737865) internal successors, (733), 514 states have internal predecessors, (733), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:52,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 515 states to 515 states and 733 transitions. [2024-11-13 13:31:52,074 INFO L240 hiAutomatonCegarLoop]: Abstraction has 515 states and 733 transitions. [2024-11-13 13:31:52,075 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:31:52,076 INFO L424 stractBuchiCegarLoop]: Abstraction has 515 states and 733 transitions. [2024-11-13 13:31:52,080 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 13:31:52,080 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 515 states and 733 transitions. [2024-11-13 13:31:52,084 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 458 [2024-11-13 13:31:52,086 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:31:52,086 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:31:52,090 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:52,090 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:52,091 INFO L745 eck$LassoCheckResult]: Stem: 4044#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 4045#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4055#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4053#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4028#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 4029#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3848#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3849#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4063#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3810#L418 assume !(0 == ~M_E~0); 3811#L418-2 assume !(0 == ~T1_E~0); 4027#L423-1 assume !(0 == ~T2_E~0); 4066#L428-1 assume !(0 == ~T3_E~0); 4064#L433-1 assume !(0 == ~E_1~0); 4057#L438-1 assume !(0 == ~E_2~0); 3987#L443-1 assume !(0 == ~E_3~0); 3981#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3946#L197 assume !(1 == ~m_pc~0); 3943#L197-2 is_master_triggered_~__retres1~0#1 := 0; 4081#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4020#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4021#L510 assume !(0 != activate_threads_~tmp~1#1); 3789#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3790#L216 assume !(1 == ~t1_pc~0); 3844#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3845#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3873#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3791#L518 assume !(0 != activate_threads_~tmp___0~0#1); 3792#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3995#L235 assume !(1 == ~t2_pc~0); 4059#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3930#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3931#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4075#L526 assume !(0 != activate_threads_~tmp___1~0#1); 4076#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3914#L254 assume 1 == ~t3_pc~0; 3820#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3821#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3802#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3803#L534 assume !(0 != activate_threads_~tmp___2~0#1); 3925#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3781#L461 assume !(1 == ~M_E~0); 3782#L461-2 assume !(1 == ~T1_E~0); 3850#L466-1 assume !(1 == ~T2_E~0); 4069#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3874#L476-1 assume !(1 == ~E_1~0); 3875#L481-1 assume !(1 == ~E_2~0); 4012#L486-1 assume !(1 == ~E_3~0); 3891#L491-1 assume { :end_inline_reset_delta_events } true; 3798#L652-2 [2024-11-13 13:31:52,095 INFO L747 eck$LassoCheckResult]: Loop: 3798#L652-2 assume !false; 3799#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3867#L393-1 assume !false; 3865#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3866#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3842#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3804#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3805#L346 assume !(0 != eval_~tmp~0#1); 3896#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3966#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4132#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4130#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4128#L423-3 assume !(0 == ~T2_E~0); 3989#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3944#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3945#L438-3 assume !(0 == ~E_2~0); 4038#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3783#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3784#L197-12 assume !(1 == ~m_pc~0); 4046#L197-14 is_master_triggered_~__retres1~0#1 := 0; 3910#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3911#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3796#L510-12 assume !(0 != activate_threads_~tmp~1#1); 3797#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3908#L216-12 assume !(1 == ~t1_pc~0); 3909#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 3960#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3961#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3918#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3846#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3847#L235-12 assume !(1 == ~t2_pc~0); 3928#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 3929#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3921#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3922#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3982#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3983#L254-12 assume 1 == ~t3_pc~0; 3828#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3829#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3876#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3877#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3965#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4279#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4089#L461-5 assume !(1 == ~T1_E~0); 4002#L466-3 assume !(1 == ~T2_E~0); 4003#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3905#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3906#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3936#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3937#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3825#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3826#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3851#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 4004#L671 assume !(0 == start_simulation_~tmp~3#1); 3809#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4033#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3903#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3871#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 3872#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4015#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4016#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 4017#L684 assume !(0 != start_simulation_~tmp___0~1#1); 3798#L652-2 [2024-11-13 13:31:52,095 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:52,096 INFO L85 PathProgramCache]: Analyzing trace with hash 1376982673, now seen corresponding path program 1 times [2024-11-13 13:31:52,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:52,096 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1115830878] [2024-11-13 13:31:52,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:52,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:52,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:52,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:52,218 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:52,219 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1115830878] [2024-11-13 13:31:52,219 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1115830878] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:52,219 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:52,219 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:31:52,219 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1726274631] [2024-11-13 13:31:52,219 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:52,220 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:31:52,220 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:52,220 INFO L85 PathProgramCache]: Analyzing trace with hash -546102818, now seen corresponding path program 1 times [2024-11-13 13:31:52,220 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:52,220 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [80284642] [2024-11-13 13:31:52,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:52,221 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:52,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:52,290 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:52,290 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:52,290 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [80284642] [2024-11-13 13:31:52,290 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [80284642] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:52,290 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:52,291 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:31:52,291 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1321652769] [2024-11-13 13:31:52,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:52,291 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:31:52,291 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:52,292 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:31:52,293 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:31:52,293 INFO L87 Difference]: Start difference. First operand 515 states and 733 transitions. cyclomatic complexity: 220 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:52,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:52,369 INFO L93 Difference]: Finished difference Result 961 states and 1352 transitions. [2024-11-13 13:31:52,369 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 961 states and 1352 transitions. [2024-11-13 13:31:52,380 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 901 [2024-11-13 13:31:52,390 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 961 states to 961 states and 1352 transitions. [2024-11-13 13:31:52,390 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 961 [2024-11-13 13:31:52,392 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 961 [2024-11-13 13:31:52,392 INFO L73 IsDeterministic]: Start isDeterministic. Operand 961 states and 1352 transitions. [2024-11-13 13:31:52,394 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:31:52,395 INFO L218 hiAutomatonCegarLoop]: Abstraction has 961 states and 1352 transitions. [2024-11-13 13:31:52,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 961 states and 1352 transitions. [2024-11-13 13:31:52,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 961 to 957. [2024-11-13 13:31:52,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 957 states, 957 states have (on average 1.4085684430512018) internal successors, (1348), 956 states have internal predecessors, (1348), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:52,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 957 states to 957 states and 1348 transitions. [2024-11-13 13:31:52,434 INFO L240 hiAutomatonCegarLoop]: Abstraction has 957 states and 1348 transitions. [2024-11-13 13:31:52,435 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:31:52,435 INFO L424 stractBuchiCegarLoop]: Abstraction has 957 states and 1348 transitions. [2024-11-13 13:31:52,436 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 13:31:52,436 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 957 states and 1348 transitions. [2024-11-13 13:31:52,444 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 897 [2024-11-13 13:31:52,444 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:31:52,444 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:31:52,445 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:52,446 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:52,446 INFO L745 eck$LassoCheckResult]: Stem: 5535#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 5536#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 5552#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5548#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5516#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 5517#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5328#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5329#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5563#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5293#L418 assume !(0 == ~M_E~0); 5294#L418-2 assume !(0 == ~T1_E~0); 5515#L423-1 assume !(0 == ~T2_E~0); 5568#L428-1 assume !(0 == ~T3_E~0); 5565#L433-1 assume !(0 == ~E_1~0); 5554#L438-1 assume !(0 == ~E_2~0); 5478#L443-1 assume !(0 == ~E_3~0); 5470#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5431#L197 assume !(1 == ~m_pc~0); 5428#L197-2 is_master_triggered_~__retres1~0#1 := 0; 5586#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5508#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5509#L510 assume !(0 != activate_threads_~tmp~1#1); 5272#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5273#L216 assume !(1 == ~t1_pc~0); 5324#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5325#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5355#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5274#L518 assume !(0 != activate_threads_~tmp___0~0#1); 5275#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5486#L235 assume !(1 == ~t2_pc~0); 5560#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5414#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5415#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5579#L526 assume !(0 != activate_threads_~tmp___1~0#1); 5580#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5398#L254 assume !(1 == ~t3_pc~0); 5332#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5333#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5285#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5286#L534 assume !(0 != activate_threads_~tmp___2~0#1); 5409#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5264#L461 assume !(1 == ~M_E~0); 5265#L461-2 assume !(1 == ~T1_E~0); 5330#L466-1 assume !(1 == ~T2_E~0); 5571#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5356#L476-1 assume !(1 == ~E_1~0); 5357#L481-1 assume !(1 == ~E_2~0); 5501#L486-1 assume !(1 == ~E_3~0); 5372#L491-1 assume { :end_inline_reset_delta_events } true; 5373#L652-2 [2024-11-13 13:31:52,446 INFO L747 eck$LassoCheckResult]: Loop: 5373#L652-2 assume !false; 6116#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5505#L393-1 assume !false; 5347#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 5348#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5322#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5287#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5288#L346 assume !(0 != eval_~tmp~0#1); 5379#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6220#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6219#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6218#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6217#L423-3 assume !(0 == ~T2_E~0); 6216#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6206#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5528#L438-3 assume !(0 == ~E_2~0); 5529#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5537#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5538#L197-12 assume !(1 == ~m_pc~0); 5539#L197-14 is_master_triggered_~__retres1~0#1 := 0; 5394#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5395#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5279#L510-12 assume !(0 != activate_threads_~tmp~1#1); 5280#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5392#L216-12 assume !(1 == ~t1_pc~0); 5393#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 5446#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5447#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5402#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5326#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5327#L235-12 assume 1 == ~t2_pc~0; 5553#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5413#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5405#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5406#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5471#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5472#L254-12 assume !(1 == ~t3_pc~0); 5574#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 5476#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5477#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6165#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6162#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6160#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6158#L461-5 assume !(1 == ~T1_E~0); 6156#L466-3 assume !(1 == ~T2_E~0); 6154#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6152#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6150#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6148#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6146#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 6136#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 6133#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 6131#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 6129#L671 assume !(0 == start_simulation_~tmp~3#1); 6127#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 6126#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 6122#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 6121#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 6120#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6119#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6118#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 6117#L684 assume !(0 != start_simulation_~tmp___0~1#1); 5373#L652-2 [2024-11-13 13:31:52,447 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:52,447 INFO L85 PathProgramCache]: Analyzing trace with hash 372621552, now seen corresponding path program 1 times [2024-11-13 13:31:52,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:52,447 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050250016] [2024-11-13 13:31:52,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:52,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:52,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:52,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:52,537 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:52,538 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2050250016] [2024-11-13 13:31:52,538 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2050250016] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:52,538 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:52,538 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:31:52,538 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1977277753] [2024-11-13 13:31:52,538 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:52,539 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:31:52,539 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:52,539 INFO L85 PathProgramCache]: Analyzing trace with hash -826292962, now seen corresponding path program 1 times [2024-11-13 13:31:52,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:52,540 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2051351640] [2024-11-13 13:31:52,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:52,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:52,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:52,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:52,592 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:52,592 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2051351640] [2024-11-13 13:31:52,592 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2051351640] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:52,593 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:52,593 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:31:52,593 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [216145728] [2024-11-13 13:31:52,593 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:52,593 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:31:52,593 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:52,594 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:31:52,594 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:31:52,594 INFO L87 Difference]: Start difference. First operand 957 states and 1348 transitions. cyclomatic complexity: 395 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:52,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:52,717 INFO L93 Difference]: Finished difference Result 2053 states and 2878 transitions. [2024-11-13 13:31:52,717 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2053 states and 2878 transitions. [2024-11-13 13:31:52,738 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1946 [2024-11-13 13:31:52,756 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2053 states to 2053 states and 2878 transitions. [2024-11-13 13:31:52,756 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2053 [2024-11-13 13:31:52,759 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2053 [2024-11-13 13:31:52,759 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2053 states and 2878 transitions. [2024-11-13 13:31:52,764 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:31:52,764 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2053 states and 2878 transitions. [2024-11-13 13:31:52,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2053 states and 2878 transitions. [2024-11-13 13:31:52,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2053 to 1146. [2024-11-13 13:31:52,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1146 states, 1146 states have (on average 1.4013961605584642) internal successors, (1606), 1145 states have internal predecessors, (1606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:52,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1146 states to 1146 states and 1606 transitions. [2024-11-13 13:31:52,812 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1146 states and 1606 transitions. [2024-11-13 13:31:52,812 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:31:52,813 INFO L424 stractBuchiCegarLoop]: Abstraction has 1146 states and 1606 transitions. [2024-11-13 13:31:52,813 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 13:31:52,813 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1146 states and 1606 transitions. [2024-11-13 13:31:52,821 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1049 [2024-11-13 13:31:52,822 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:31:52,822 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:31:52,823 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:52,823 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:52,823 INFO L745 eck$LassoCheckResult]: Stem: 8561#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 8562#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 8575#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8573#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8544#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 8545#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8347#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8348#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8589#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8313#L418 assume !(0 == ~M_E~0); 8314#L418-2 assume !(0 == ~T1_E~0); 8543#L423-1 assume !(0 == ~T2_E~0); 8596#L428-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8601#L433-1 assume !(0 == ~E_1~0); 8578#L438-1 assume !(0 == ~E_2~0); 8579#L443-1 assume !(0 == ~E_3~0); 8492#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8493#L197 assume !(1 == ~m_pc~0); 8449#L197-2 is_master_triggered_~__retres1~0#1 := 0; 8623#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8536#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8537#L510 assume !(0 != activate_threads_~tmp~1#1); 8292#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8293#L216 assume !(1 == ~t1_pc~0); 8343#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8344#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8658#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8657#L518 assume !(0 != activate_threads_~tmp___0~0#1); 8656#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8655#L235 assume !(1 == ~t2_pc~0); 8654#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8652#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8636#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8613#L526 assume !(0 != activate_threads_~tmp___1~0#1); 8614#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8416#L254 assume !(1 == ~t3_pc~0); 8417#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8442#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8443#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8478#L534 assume !(0 != activate_threads_~tmp___2~0#1); 8479#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8649#L461 assume !(1 == ~M_E~0); 8349#L461-2 assume !(1 == ~T1_E~0); 8350#L466-1 assume !(1 == ~T2_E~0); 8600#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8376#L476-1 assume !(1 == ~E_1~0); 8377#L481-1 assume !(1 == ~E_2~0); 8527#L486-1 assume !(1 == ~E_3~0); 8393#L491-1 assume { :end_inline_reset_delta_events } true; 8301#L652-2 [2024-11-13 13:31:52,824 INFO L747 eck$LassoCheckResult]: Loop: 8301#L652-2 assume !false; 8302#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8369#L393-1 assume !false; 8367#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8368#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8341#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8307#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8308#L346 assume !(0 != eval_~tmp~0#1); 8398#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9273#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9270#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9268#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8534#L423-3 assume !(0 == ~T2_E~0); 8503#L428-3 assume !(0 == ~T3_E~0); 8450#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8451#L438-3 assume !(0 == ~E_2~0); 8556#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8286#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8287#L197-12 assume !(1 == ~m_pc~0); 8563#L197-14 is_master_triggered_~__retres1~0#1 := 0; 8412#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8413#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8299#L510-12 assume !(0 != activate_threads_~tmp~1#1); 8300#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8410#L216-12 assume !(1 == ~t1_pc~0); 8411#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 9401#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9400#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8421#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8345#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8346#L235-12 assume 1 == ~t2_pc~0; 8576#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8432#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8424#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8425#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8494#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8495#L254-12 assume !(1 == ~t3_pc~0); 8608#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 8499#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8378#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8379#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8473#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8414#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8415#L461-5 assume !(1 == ~T1_E~0); 8516#L466-3 assume !(1 == ~T2_E~0); 8517#L471-3 assume !(1 == ~T3_E~0); 8407#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8408#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8440#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8441#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8324#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8325#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8351#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 8518#L671 assume !(0 == start_simulation_~tmp~3#1); 8310#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8551#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8405#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8373#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 8374#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8530#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8531#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 8533#L684 assume !(0 != start_simulation_~tmp___0~1#1); 8301#L652-2 [2024-11-13 13:31:52,824 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:52,824 INFO L85 PathProgramCache]: Analyzing trace with hash -286909970, now seen corresponding path program 1 times [2024-11-13 13:31:52,824 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:52,824 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2073302946] [2024-11-13 13:31:52,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:52,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:52,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:52,890 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:52,890 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:52,891 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2073302946] [2024-11-13 13:31:52,891 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2073302946] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:52,891 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:52,891 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:31:52,891 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [469786527] [2024-11-13 13:31:52,891 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:52,892 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:31:52,892 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:52,892 INFO L85 PathProgramCache]: Analyzing trace with hash 1864807714, now seen corresponding path program 1 times [2024-11-13 13:31:52,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:52,893 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856783576] [2024-11-13 13:31:52,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:52,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:52,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:52,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:52,951 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:52,951 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1856783576] [2024-11-13 13:31:52,952 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1856783576] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:52,952 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:52,952 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:31:52,952 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [145069015] [2024-11-13 13:31:52,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:52,952 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:31:52,953 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:52,953 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:31:52,954 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:31:52,954 INFO L87 Difference]: Start difference. First operand 1146 states and 1606 transitions. cyclomatic complexity: 464 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:53,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:53,013 INFO L93 Difference]: Finished difference Result 957 states and 1334 transitions. [2024-11-13 13:31:53,013 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 957 states and 1334 transitions. [2024-11-13 13:31:53,024 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 897 [2024-11-13 13:31:53,032 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 957 states to 957 states and 1334 transitions. [2024-11-13 13:31:53,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 957 [2024-11-13 13:31:53,034 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 957 [2024-11-13 13:31:53,034 INFO L73 IsDeterministic]: Start isDeterministic. Operand 957 states and 1334 transitions. [2024-11-13 13:31:53,036 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:31:53,036 INFO L218 hiAutomatonCegarLoop]: Abstraction has 957 states and 1334 transitions. [2024-11-13 13:31:53,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 957 states and 1334 transitions. [2024-11-13 13:31:53,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 957 to 957. [2024-11-13 13:31:53,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 957 states, 957 states have (on average 1.393939393939394) internal successors, (1334), 956 states have internal predecessors, (1334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:53,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 957 states to 957 states and 1334 transitions. [2024-11-13 13:31:53,067 INFO L240 hiAutomatonCegarLoop]: Abstraction has 957 states and 1334 transitions. [2024-11-13 13:31:53,068 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:31:53,070 INFO L424 stractBuchiCegarLoop]: Abstraction has 957 states and 1334 transitions. [2024-11-13 13:31:53,070 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 13:31:53,071 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 957 states and 1334 transitions. [2024-11-13 13:31:53,078 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 897 [2024-11-13 13:31:53,078 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:31:53,078 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:31:53,079 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:53,080 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:53,081 INFO L745 eck$LassoCheckResult]: Stem: 10672#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 10673#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 10687#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10684#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10654#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 10655#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10461#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10462#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10701#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10426#L418 assume !(0 == ~M_E~0); 10427#L418-2 assume !(0 == ~T1_E~0); 10653#L423-1 assume !(0 == ~T2_E~0); 10709#L428-1 assume !(0 == ~T3_E~0); 10705#L433-1 assume !(0 == ~E_1~0); 10691#L438-1 assume !(0 == ~E_2~0); 10612#L443-1 assume !(0 == ~E_3~0); 10605#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10566#L197 assume !(1 == ~m_pc~0); 10563#L197-2 is_master_triggered_~__retres1~0#1 := 0; 10737#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10645#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10646#L510 assume !(0 != activate_threads_~tmp~1#1); 10405#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10406#L216 assume !(1 == ~t1_pc~0); 10457#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10458#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10489#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10407#L518 assume !(0 != activate_threads_~tmp___0~0#1); 10408#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10622#L235 assume !(1 == ~t2_pc~0); 10697#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10549#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10550#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10726#L526 assume !(0 != activate_threads_~tmp___1~0#1); 10727#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10532#L254 assume !(1 == ~t3_pc~0); 10465#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10466#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10418#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10419#L534 assume !(0 != activate_threads_~tmp___2~0#1); 10543#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10397#L461 assume !(1 == ~M_E~0); 10398#L461-2 assume !(1 == ~T1_E~0); 10463#L466-1 assume !(1 == ~T2_E~0); 10714#L471-1 assume !(1 == ~T3_E~0); 10490#L476-1 assume !(1 == ~E_1~0); 10491#L481-1 assume !(1 == ~E_2~0); 10637#L486-1 assume !(1 == ~E_3~0); 10506#L491-1 assume { :end_inline_reset_delta_events } true; 10507#L652-2 [2024-11-13 13:31:53,081 INFO L747 eck$LassoCheckResult]: Loop: 10507#L652-2 assume !false; 11074#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11070#L393-1 assume !false; 11068#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 11066#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 11061#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 11059#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11057#L346 assume !(0 != eval_~tmp~0#1); 10588#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10589#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10626#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10619#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10620#L423-3 assume !(0 == ~T2_E~0); 10613#L428-3 assume !(0 == ~T3_E~0); 10564#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10565#L438-3 assume !(0 == ~E_2~0); 10665#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10399#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10400#L197-12 assume !(1 == ~m_pc~0); 11159#L197-14 is_master_triggered_~__retres1~0#1 := 0; 11158#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11157#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10412#L510-12 assume !(0 != activate_threads_~tmp~1#1); 10413#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10526#L216-12 assume !(1 == ~t1_pc~0); 10527#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 10580#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10581#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10536#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10459#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10460#L235-12 assume 1 == ~t2_pc~0; 10688#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10547#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10539#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10540#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10607#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10608#L254-12 assume !(1 == ~t3_pc~0); 10721#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 10611#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10492#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10493#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10587#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10530#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10531#L461-5 assume !(1 == ~T1_E~0); 10628#L466-3 assume !(1 == ~T2_E~0); 10629#L471-3 assume !(1 == ~T3_E~0); 10523#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10524#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10556#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10557#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 10438#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 10439#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 10464#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 10728#L671 assume !(0 == start_simulation_~tmp~3#1); 11173#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 11170#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 11166#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 11164#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 11165#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11160#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11161#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 11214#L684 assume !(0 != start_simulation_~tmp___0~1#1); 10507#L652-2 [2024-11-13 13:31:53,082 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:53,082 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 1 times [2024-11-13 13:31:53,082 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:53,082 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088228324] [2024-11-13 13:31:53,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:53,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:53,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:31:53,117 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:31:53,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:31:53,162 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:31:53,163 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:53,163 INFO L85 PathProgramCache]: Analyzing trace with hash 1864807714, now seen corresponding path program 2 times [2024-11-13 13:31:53,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:53,163 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1798187710] [2024-11-13 13:31:53,163 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:53,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:53,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:53,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:53,205 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:53,205 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1798187710] [2024-11-13 13:31:53,205 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1798187710] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:53,205 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:53,205 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:31:53,206 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [185139999] [2024-11-13 13:31:53,206 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:53,206 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:31:53,206 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:53,206 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:31:53,206 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:31:53,206 INFO L87 Difference]: Start difference. First operand 957 states and 1334 transitions. cyclomatic complexity: 381 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:53,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:53,245 INFO L93 Difference]: Finished difference Result 1146 states and 1591 transitions. [2024-11-13 13:31:53,245 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1146 states and 1591 transitions. [2024-11-13 13:31:53,254 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1049 [2024-11-13 13:31:53,262 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1146 states to 1146 states and 1591 transitions. [2024-11-13 13:31:53,262 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1146 [2024-11-13 13:31:53,264 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1146 [2024-11-13 13:31:53,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1146 states and 1591 transitions. [2024-11-13 13:31:53,266 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:31:53,267 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1146 states and 1591 transitions. [2024-11-13 13:31:53,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1146 states and 1591 transitions. [2024-11-13 13:31:53,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1146 to 1146. [2024-11-13 13:31:53,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1146 states, 1146 states have (on average 1.388307155322862) internal successors, (1591), 1145 states have internal predecessors, (1591), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:53,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1146 states to 1146 states and 1591 transitions. [2024-11-13 13:31:53,297 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1146 states and 1591 transitions. [2024-11-13 13:31:53,298 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:31:53,300 INFO L424 stractBuchiCegarLoop]: Abstraction has 1146 states and 1591 transitions. [2024-11-13 13:31:53,300 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 13:31:53,300 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1146 states and 1591 transitions. [2024-11-13 13:31:53,308 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1049 [2024-11-13 13:31:53,308 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:31:53,308 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:31:53,310 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:53,310 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:53,310 INFO L745 eck$LassoCheckResult]: Stem: 12788#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 12789#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12800#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12798#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12767#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 12768#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12570#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12571#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12809#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12535#L418 assume !(0 == ~M_E~0); 12536#L418-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12765#L423-1 assume !(0 == ~T2_E~0); 12948#L428-1 assume !(0 == ~T3_E~0); 12946#L433-1 assume !(0 == ~E_1~0); 12944#L438-1 assume !(0 == ~E_2~0); 12942#L443-1 assume !(0 == ~E_3~0); 12941#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12940#L197 assume !(1 == ~m_pc~0); 12939#L197-2 is_master_triggered_~__retres1~0#1 := 0; 12937#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12935#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 12932#L510 assume !(0 != activate_threads_~tmp~1#1); 12931#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12838#L216 assume !(1 == ~t1_pc~0); 12566#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12567#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12599#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12516#L518 assume !(0 != activate_threads_~tmp___0~0#1); 12517#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12840#L235 assume !(1 == ~t2_pc~0); 12806#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12659#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12660#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12827#L526 assume !(0 != activate_threads_~tmp___1~0#1); 12828#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12877#L254 assume !(1 == ~t3_pc~0); 12874#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12871#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12868#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12865#L534 assume !(0 != activate_threads_~tmp___2~0#1); 12863#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12861#L461 assume !(1 == ~M_E~0); 12572#L461-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12573#L466-1 assume !(1 == ~T2_E~0); 12816#L471-1 assume !(1 == ~T3_E~0); 12600#L476-1 assume !(1 == ~E_1~0); 12601#L481-1 assume !(1 == ~E_2~0); 12748#L486-1 assume !(1 == ~E_3~0); 12616#L491-1 assume { :end_inline_reset_delta_events } true; 12617#L652-2 [2024-11-13 13:31:53,310 INFO L747 eck$LassoCheckResult]: Loop: 12617#L652-2 assume !false; 13023#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13017#L393-1 assume !false; 13011#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13006#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13001#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13000#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12997#L346 assume !(0 != eval_~tmp~0#1); 12697#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12698#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12736#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12728#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12729#L423-3 assume !(0 == ~T2_E~0); 13563#L428-3 assume !(0 == ~T3_E~0); 13562#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13561#L438-3 assume !(0 == ~E_2~0); 12790#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12508#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12509#L197-12 assume !(1 == ~m_pc~0); 12791#L197-14 is_master_triggered_~__retres1~0#1 := 0; 13568#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13565#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 12521#L510-12 assume !(0 != activate_threads_~tmp~1#1); 12522#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12693#L216-12 assume !(1 == ~t1_pc~0); 13260#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 13259#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13216#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13213#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13207#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13203#L235-12 assume !(1 == ~t2_pc~0); 13198#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 13193#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13176#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13173#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13169#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13163#L254-12 assume !(1 == ~t3_pc~0); 13158#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 13153#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13148#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13143#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13138#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13132#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13126#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13120#L466-3 assume !(1 == ~T2_E~0); 13115#L471-3 assume !(1 == ~T3_E~0); 13111#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13107#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13102#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13098#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13092#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13087#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13082#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 13076#L671 assume !(0 == start_simulation_~tmp~3#1); 13069#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13064#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13056#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13051#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 13047#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13041#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13036#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 13032#L684 assume !(0 != start_simulation_~tmp___0~1#1); 12617#L652-2 [2024-11-13 13:31:53,311 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:53,311 INFO L85 PathProgramCache]: Analyzing trace with hash 444828398, now seen corresponding path program 1 times [2024-11-13 13:31:53,311 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:53,311 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1827137077] [2024-11-13 13:31:53,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:53,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:53,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:53,362 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:53,362 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:53,362 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1827137077] [2024-11-13 13:31:53,362 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1827137077] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:53,362 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:53,363 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:31:53,363 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1176675902] [2024-11-13 13:31:53,363 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:53,363 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:31:53,363 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:53,364 INFO L85 PathProgramCache]: Analyzing trace with hash 177758783, now seen corresponding path program 1 times [2024-11-13 13:31:53,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:53,364 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [265060439] [2024-11-13 13:31:53,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:53,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:53,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:53,438 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:53,438 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:53,438 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [265060439] [2024-11-13 13:31:53,438 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [265060439] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:53,438 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:53,438 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:31:53,439 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [251430065] [2024-11-13 13:31:53,439 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:53,439 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:31:53,439 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:53,440 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:31:53,440 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:31:53,440 INFO L87 Difference]: Start difference. First operand 1146 states and 1591 transitions. cyclomatic complexity: 449 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:53,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:53,469 INFO L93 Difference]: Finished difference Result 957 states and 1320 transitions. [2024-11-13 13:31:53,469 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 957 states and 1320 transitions. [2024-11-13 13:31:53,477 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 897 [2024-11-13 13:31:53,483 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 957 states to 957 states and 1320 transitions. [2024-11-13 13:31:53,484 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 957 [2024-11-13 13:31:53,485 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 957 [2024-11-13 13:31:53,485 INFO L73 IsDeterministic]: Start isDeterministic. Operand 957 states and 1320 transitions. [2024-11-13 13:31:53,487 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:31:53,487 INFO L218 hiAutomatonCegarLoop]: Abstraction has 957 states and 1320 transitions. [2024-11-13 13:31:53,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 957 states and 1320 transitions. [2024-11-13 13:31:53,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 957 to 957. [2024-11-13 13:31:53,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 957 states, 957 states have (on average 1.3793103448275863) internal successors, (1320), 956 states have internal predecessors, (1320), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:53,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 957 states to 957 states and 1320 transitions. [2024-11-13 13:31:53,510 INFO L240 hiAutomatonCegarLoop]: Abstraction has 957 states and 1320 transitions. [2024-11-13 13:31:53,511 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:31:53,512 INFO L424 stractBuchiCegarLoop]: Abstraction has 957 states and 1320 transitions. [2024-11-13 13:31:53,512 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 13:31:53,512 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 957 states and 1320 transitions. [2024-11-13 13:31:53,518 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 897 [2024-11-13 13:31:53,518 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:31:53,518 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:31:53,519 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:53,520 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:53,520 INFO L745 eck$LassoCheckResult]: Stem: 14889#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 14890#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 14903#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14902#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14870#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 14871#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14681#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14682#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14913#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14647#L418 assume !(0 == ~M_E~0); 14648#L418-2 assume !(0 == ~T1_E~0); 14869#L423-1 assume !(0 == ~T2_E~0); 14917#L428-1 assume !(0 == ~T3_E~0); 14915#L433-1 assume !(0 == ~E_1~0); 14905#L438-1 assume !(0 == ~E_2~0); 14827#L443-1 assume !(0 == ~E_3~0); 14820#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14782#L197 assume !(1 == ~m_pc~0); 14779#L197-2 is_master_triggered_~__retres1~0#1 := 0; 14942#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14862#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14863#L510 assume !(0 != activate_threads_~tmp~1#1); 14626#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14627#L216 assume !(1 == ~t1_pc~0); 14677#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14678#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14708#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14628#L518 assume !(0 != activate_threads_~tmp___0~0#1); 14629#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14837#L235 assume !(1 == ~t2_pc~0); 14909#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14766#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14767#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14932#L526 assume !(0 != activate_threads_~tmp___1~0#1); 14933#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14748#L254 assume !(1 == ~t3_pc~0); 14685#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 14686#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14639#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14640#L534 assume !(0 != activate_threads_~tmp___2~0#1); 14760#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14618#L461 assume !(1 == ~M_E~0); 14619#L461-2 assume !(1 == ~T1_E~0); 14683#L466-1 assume !(1 == ~T2_E~0); 14923#L471-1 assume !(1 == ~T3_E~0); 14711#L476-1 assume !(1 == ~E_1~0); 14712#L481-1 assume !(1 == ~E_2~0); 14854#L486-1 assume !(1 == ~E_3~0); 14727#L491-1 assume { :end_inline_reset_delta_events } true; 14637#L652-2 [2024-11-13 13:31:53,520 INFO L747 eck$LassoCheckResult]: Loop: 14637#L652-2 assume !false; 14638#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14702#L393-1 assume !false; 14700#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 14701#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 14675#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 14641#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14642#L346 assume !(0 != eval_~tmp~0#1); 14730#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15536#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15534#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15533#L418-5 assume !(0 == ~T1_E~0); 15528#L423-3 assume !(0 == ~T2_E~0); 15526#L428-3 assume !(0 == ~T3_E~0); 15524#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15523#L438-3 assume !(0 == ~E_2~0); 15522#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15521#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15520#L197-12 assume !(1 == ~m_pc~0); 15518#L197-14 is_master_triggered_~__retres1~0#1 := 0; 15516#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15514#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 15513#L510-12 assume !(0 != activate_threads_~tmp~1#1); 15511#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15510#L216-12 assume !(1 == ~t1_pc~0); 15509#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 15508#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15476#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14752#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14753#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15475#L235-12 assume !(1 == ~t2_pc~0); 15472#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 14934#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14756#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14757#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14822#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14823#L254-12 assume !(1 == ~t3_pc~0); 14927#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 15460#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15459#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 15458#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15457#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14746#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14747#L461-5 assume !(1 == ~T1_E~0); 15442#L466-3 assume !(1 == ~T2_E~0); 15441#L471-3 assume !(1 == ~T3_E~0); 15440#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15439#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15438#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15437#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 15424#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 15421#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 15419#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 15392#L671 assume !(0 == start_simulation_~tmp~3#1); 15393#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 15532#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 15527#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 15525#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 15448#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14858#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14859#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 14860#L684 assume !(0 != start_simulation_~tmp___0~1#1); 14637#L652-2 [2024-11-13 13:31:53,520 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:53,520 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 2 times [2024-11-13 13:31:53,521 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:53,521 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [604711999] [2024-11-13 13:31:53,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:53,521 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:53,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:31:53,532 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:31:53,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:31:53,549 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:31:53,550 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:53,550 INFO L85 PathProgramCache]: Analyzing trace with hash 755196227, now seen corresponding path program 1 times [2024-11-13 13:31:53,550 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:53,550 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [773237777] [2024-11-13 13:31:53,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:53,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:53,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:53,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:53,638 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:53,638 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [773237777] [2024-11-13 13:31:53,638 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [773237777] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:53,638 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:53,638 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:31:53,638 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1442509247] [2024-11-13 13:31:53,638 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:53,639 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:31:53,639 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:53,639 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:31:53,639 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:31:53,639 INFO L87 Difference]: Start difference. First operand 957 states and 1320 transitions. cyclomatic complexity: 367 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:53,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:53,731 INFO L93 Difference]: Finished difference Result 985 states and 1348 transitions. [2024-11-13 13:31:53,732 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 985 states and 1348 transitions. [2024-11-13 13:31:53,739 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 925 [2024-11-13 13:31:53,746 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 985 states to 985 states and 1348 transitions. [2024-11-13 13:31:53,746 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 985 [2024-11-13 13:31:53,748 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 985 [2024-11-13 13:31:53,749 INFO L73 IsDeterministic]: Start isDeterministic. Operand 985 states and 1348 transitions. [2024-11-13 13:31:53,751 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:31:53,751 INFO L218 hiAutomatonCegarLoop]: Abstraction has 985 states and 1348 transitions. [2024-11-13 13:31:53,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 985 states and 1348 transitions. [2024-11-13 13:31:53,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 985 to 969. [2024-11-13 13:31:53,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 969 states, 969 states have (on average 1.3746130030959753) internal successors, (1332), 968 states have internal predecessors, (1332), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:53,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 969 states to 969 states and 1332 transitions. [2024-11-13 13:31:53,777 INFO L240 hiAutomatonCegarLoop]: Abstraction has 969 states and 1332 transitions. [2024-11-13 13:31:53,777 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:31:53,778 INFO L424 stractBuchiCegarLoop]: Abstraction has 969 states and 1332 transitions. [2024-11-13 13:31:53,780 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 13:31:53,780 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 969 states and 1332 transitions. [2024-11-13 13:31:53,786 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 909 [2024-11-13 13:31:53,786 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:31:53,786 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:31:53,787 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:53,787 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:53,788 INFO L745 eck$LassoCheckResult]: Stem: 16840#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 16841#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 16853#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16851#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16823#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 16824#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16632#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16633#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16867#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16597#L418 assume !(0 == ~M_E~0); 16598#L418-2 assume !(0 == ~T1_E~0); 16822#L423-1 assume !(0 == ~T2_E~0); 16871#L428-1 assume !(0 == ~T3_E~0); 16869#L433-1 assume !(0 == ~E_1~0); 16856#L438-1 assume !(0 == ~E_2~0); 16781#L443-1 assume !(0 == ~E_3~0); 16775#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16737#L197 assume !(1 == ~m_pc~0); 16734#L197-2 is_master_triggered_~__retres1~0#1 := 0; 16892#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16815#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 16816#L510 assume !(0 != activate_threads_~tmp~1#1); 16576#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16577#L216 assume !(1 == ~t1_pc~0); 16628#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16629#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16659#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16578#L518 assume !(0 != activate_threads_~tmp___0~0#1); 16579#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16789#L235 assume !(1 == ~t2_pc~0); 16863#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16721#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16722#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16884#L526 assume !(0 != activate_threads_~tmp___1~0#1); 16885#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16704#L254 assume !(1 == ~t3_pc~0); 16636#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16637#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16589#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16590#L534 assume !(0 != activate_threads_~tmp___2~0#1); 16715#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16568#L461 assume !(1 == ~M_E~0); 16569#L461-2 assume !(1 == ~T1_E~0); 16634#L466-1 assume !(1 == ~T2_E~0); 16876#L471-1 assume !(1 == ~T3_E~0); 16660#L476-1 assume !(1 == ~E_1~0); 16661#L481-1 assume !(1 == ~E_2~0); 16806#L486-1 assume !(1 == ~E_3~0); 16676#L491-1 assume { :end_inline_reset_delta_events } true; 16677#L652-2 [2024-11-13 13:31:53,788 INFO L747 eck$LassoCheckResult]: Loop: 16677#L652-2 assume !false; 17398#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16653#L393-1 assume !false; 17397#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16879#L309 assume !(0 == ~m_st~0); 16625#L313 assume !(0 == ~t1_st~0); 16627#L317 assume !(0 == ~t2_st~0); 16814#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 16873#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 17409#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17386#L346 assume !(0 != eval_~tmp~0#1); 17387#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17381#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17380#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17378#L418-5 assume !(0 == ~T1_E~0); 16813#L423-3 assume !(0 == ~T2_E~0); 16782#L428-3 assume !(0 == ~T3_E~0); 16735#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16736#L438-3 assume !(0 == ~E_2~0); 16834#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16570#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16571#L197-12 assume !(1 == ~m_pc~0); 16842#L197-14 is_master_triggered_~__retres1~0#1 := 0; 17427#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17426#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 17424#L510-12 assume !(0 != activate_threads_~tmp~1#1); 17422#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16698#L216-12 assume !(1 == ~t1_pc~0); 16699#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 16751#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16752#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16708#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16630#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16631#L235-12 assume 1 == ~t2_pc~0; 16854#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16719#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16711#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16712#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16777#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16778#L254-12 assume !(1 == ~t3_pc~0); 16881#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 17340#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17338#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17337#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17336#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17335#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17334#L461-5 assume !(1 == ~T1_E~0); 17333#L466-3 assume !(1 == ~T2_E~0); 17332#L471-3 assume !(1 == ~T3_E~0); 17330#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17329#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17328#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17327#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 17318#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 17316#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 17315#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 17313#L671 assume !(0 == start_simulation_~tmp~3#1); 17314#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 17471#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 17467#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 17403#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 17402#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17401#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17400#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 17399#L684 assume !(0 != start_simulation_~tmp___0~1#1); 16677#L652-2 [2024-11-13 13:31:53,788 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:53,788 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 3 times [2024-11-13 13:31:53,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:53,788 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1943670025] [2024-11-13 13:31:53,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:53,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:53,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:31:53,805 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:31:53,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:31:53,829 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:31:53,829 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:53,830 INFO L85 PathProgramCache]: Analyzing trace with hash -426838244, now seen corresponding path program 1 times [2024-11-13 13:31:53,830 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:53,830 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1219474184] [2024-11-13 13:31:53,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:53,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:53,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:53,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:53,878 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:53,878 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1219474184] [2024-11-13 13:31:53,878 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1219474184] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:53,879 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:53,879 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:31:53,879 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [365050832] [2024-11-13 13:31:53,879 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:53,879 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:31:53,879 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:53,880 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:31:53,880 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:31:53,880 INFO L87 Difference]: Start difference. First operand 969 states and 1332 transitions. cyclomatic complexity: 367 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:53,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:53,952 INFO L93 Difference]: Finished difference Result 1700 states and 2301 transitions. [2024-11-13 13:31:53,952 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1700 states and 2301 transitions. [2024-11-13 13:31:53,969 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1634 [2024-11-13 13:31:53,981 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1700 states to 1700 states and 2301 transitions. [2024-11-13 13:31:53,981 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1700 [2024-11-13 13:31:53,983 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1700 [2024-11-13 13:31:53,984 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1700 states and 2301 transitions. [2024-11-13 13:31:53,987 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:31:53,987 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1700 states and 2301 transitions. [2024-11-13 13:31:53,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1700 states and 2301 transitions. [2024-11-13 13:31:54,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1700 to 1604. [2024-11-13 13:31:54,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1604 states, 1604 states have (on average 1.3572319201995013) internal successors, (2177), 1603 states have internal predecessors, (2177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:54,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1604 states to 1604 states and 2177 transitions. [2024-11-13 13:31:54,026 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1604 states and 2177 transitions. [2024-11-13 13:31:54,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:31:54,028 INFO L424 stractBuchiCegarLoop]: Abstraction has 1604 states and 2177 transitions. [2024-11-13 13:31:54,028 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 13:31:54,028 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1604 states and 2177 transitions. [2024-11-13 13:31:54,037 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1538 [2024-11-13 13:31:54,037 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:31:54,037 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:31:54,039 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:54,039 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:54,040 INFO L745 eck$LassoCheckResult]: Stem: 19517#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 19518#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 19531#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19529#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19500#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 19501#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19304#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19305#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19543#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19272#L418 assume !(0 == ~M_E~0); 19273#L418-2 assume !(0 == ~T1_E~0); 19499#L423-1 assume !(0 == ~T2_E~0); 19550#L428-1 assume !(0 == ~T3_E~0); 19548#L433-1 assume !(0 == ~E_1~0); 19533#L438-1 assume !(0 == ~E_2~0); 19458#L443-1 assume !(0 == ~E_3~0); 19451#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19408#L197 assume !(1 == ~m_pc~0); 19405#L197-2 is_master_triggered_~__retres1~0#1 := 0; 19575#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19491#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 19492#L510 assume !(0 != activate_threads_~tmp~1#1); 19251#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19252#L216 assume !(1 == ~t1_pc~0); 19300#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19301#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19332#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 19253#L518 assume !(0 != activate_threads_~tmp___0~0#1); 19254#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19466#L235 assume !(1 == ~t2_pc~0); 19538#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19391#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19392#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19566#L526 assume !(0 != activate_threads_~tmp___1~0#1); 19567#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19375#L254 assume !(1 == ~t3_pc~0); 19309#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19310#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19264#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 19265#L534 assume !(0 != activate_threads_~tmp___2~0#1); 19386#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19243#L461 assume !(1 == ~M_E~0); 19244#L461-2 assume !(1 == ~T1_E~0); 19306#L466-1 assume !(1 == ~T2_E~0); 19557#L471-1 assume !(1 == ~T3_E~0); 19333#L476-1 assume !(1 == ~E_1~0); 19334#L481-1 assume !(1 == ~E_2~0); 19484#L486-1 assume !(1 == ~E_3~0); 19349#L491-1 assume { :end_inline_reset_delta_events } true; 19350#L652-2 [2024-11-13 13:31:54,040 INFO L747 eck$LassoCheckResult]: Loop: 19350#L652-2 assume !false; 20354#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20348#L393-1 assume !false; 20346#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 20343#L309 assume !(0 == ~m_st~0); 20344#L313 assume !(0 == ~t1_st~0); 20742#L317 assume !(0 == ~t2_st~0); 20740#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 20739#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 20687#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20686#L346 assume !(0 != eval_~tmp~0#1); 20685#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20684#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20683#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20682#L418-5 assume !(0 == ~T1_E~0); 20681#L423-3 assume !(0 == ~T2_E~0); 20679#L428-3 assume !(0 == ~T3_E~0); 20678#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20677#L438-3 assume !(0 == ~E_2~0); 20675#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20674#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20673#L197-12 assume 1 == ~m_pc~0; 20672#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20671#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20667#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 20665#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20663#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20661#L216-12 assume !(1 == ~t1_pc~0); 20657#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 20655#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20653#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20651#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20649#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20423#L235-12 assume !(1 == ~t2_pc~0); 20420#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 20418#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20416#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20413#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20411#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20409#L254-12 assume !(1 == ~t3_pc~0); 20407#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 20405#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20403#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20401#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20399#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20397#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20395#L461-5 assume !(1 == ~T1_E~0); 20393#L466-3 assume !(1 == ~T2_E~0); 20391#L471-3 assume !(1 == ~T3_E~0); 20389#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20387#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20385#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20383#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 20380#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 20378#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 20377#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 20375#L671 assume !(0 == start_simulation_~tmp~3#1); 20372#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 20369#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 20367#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 20365#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 20363#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20361#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20359#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 20357#L684 assume !(0 != start_simulation_~tmp___0~1#1); 19350#L652-2 [2024-11-13 13:31:54,040 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:54,040 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 4 times [2024-11-13 13:31:54,040 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:54,040 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627899790] [2024-11-13 13:31:54,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:54,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:54,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:31:54,053 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:31:54,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:31:54,072 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:31:54,074 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:54,074 INFO L85 PathProgramCache]: Analyzing trace with hash -1155920930, now seen corresponding path program 1 times [2024-11-13 13:31:54,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:54,076 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [114744272] [2024-11-13 13:31:54,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:54,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:54,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:54,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:54,178 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:54,178 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [114744272] [2024-11-13 13:31:54,178 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [114744272] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:54,178 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:54,178 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:31:54,179 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1522645895] [2024-11-13 13:31:54,179 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:54,179 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:31:54,179 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:54,180 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:31:54,180 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:31:54,180 INFO L87 Difference]: Start difference. First operand 1604 states and 2177 transitions. cyclomatic complexity: 577 Second operand has 5 states, 5 states have (on average 13.0) internal successors, (65), 5 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:54,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:54,361 INFO L93 Difference]: Finished difference Result 1658 states and 2216 transitions. [2024-11-13 13:31:54,361 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1658 states and 2216 transitions. [2024-11-13 13:31:54,371 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1592 [2024-11-13 13:31:54,381 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1658 states to 1658 states and 2216 transitions. [2024-11-13 13:31:54,382 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1658 [2024-11-13 13:31:54,384 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1658 [2024-11-13 13:31:54,384 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1658 states and 2216 transitions. [2024-11-13 13:31:54,388 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:31:54,388 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1658 states and 2216 transitions. [2024-11-13 13:31:54,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1658 states and 2216 transitions. [2024-11-13 13:31:54,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1658 to 1658. [2024-11-13 13:31:54,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1658 states, 1658 states have (on average 1.3365500603136309) internal successors, (2216), 1657 states have internal predecessors, (2216), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:54,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1658 states to 1658 states and 2216 transitions. [2024-11-13 13:31:54,426 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1658 states and 2216 transitions. [2024-11-13 13:31:54,427 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:31:54,427 INFO L424 stractBuchiCegarLoop]: Abstraction has 1658 states and 2216 transitions. [2024-11-13 13:31:54,428 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 13:31:54,428 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1658 states and 2216 transitions. [2024-11-13 13:31:54,436 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1592 [2024-11-13 13:31:54,437 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:31:54,437 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:31:54,438 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:54,438 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:54,438 INFO L745 eck$LassoCheckResult]: Stem: 22790#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 22791#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 22802#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22801#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22772#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 22773#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22575#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22576#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22810#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22542#L418 assume !(0 == ~M_E~0); 22543#L418-2 assume !(0 == ~T1_E~0); 22771#L423-1 assume !(0 == ~T2_E~0); 22816#L428-1 assume !(0 == ~T3_E~0); 22813#L433-1 assume !(0 == ~E_1~0); 22804#L438-1 assume !(0 == ~E_2~0); 22722#L443-1 assume !(0 == ~E_3~0); 22716#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22678#L197 assume !(1 == ~m_pc~0); 22675#L197-2 is_master_triggered_~__retres1~0#1 := 0; 22835#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22760#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 22761#L510 assume !(0 != activate_threads_~tmp~1#1); 22521#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22522#L216 assume !(1 == ~t1_pc~0); 22571#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22572#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22605#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 22523#L518 assume !(0 != activate_threads_~tmp___0~0#1); 22524#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22732#L235 assume !(1 == ~t2_pc~0); 22806#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22661#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22662#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22828#L526 assume !(0 != activate_threads_~tmp___1~0#1); 22829#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22645#L254 assume !(1 == ~t3_pc~0); 22580#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22581#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22534#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 22535#L534 assume !(0 != activate_threads_~tmp___2~0#1); 22656#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22513#L461 assume !(1 == ~M_E~0); 22514#L461-2 assume !(1 == ~T1_E~0); 22577#L466-1 assume !(1 == ~T2_E~0); 22821#L471-1 assume !(1 == ~T3_E~0); 22606#L476-1 assume !(1 == ~E_1~0); 22607#L481-1 assume !(1 == ~E_2~0); 22751#L486-1 assume !(1 == ~E_3~0); 22622#L491-1 assume { :end_inline_reset_delta_events } true; 22623#L652-2 [2024-11-13 13:31:54,439 INFO L747 eck$LassoCheckResult]: Loop: 22623#L652-2 assume !false; 23590#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23582#L393-1 assume !false; 23577#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 23572#L309 assume !(0 == ~m_st~0); 23491#L313 assume !(0 == ~t1_st~0); 23492#L317 assume !(0 == ~t2_st~0); 23493#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 23490#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 23483#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23475#L346 assume !(0 != eval_~tmp~0#1); 23476#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23885#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23883#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23879#L418-5 assume !(0 == ~T1_E~0); 23877#L423-3 assume !(0 == ~T2_E~0); 23875#L428-3 assume !(0 == ~T3_E~0); 23874#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23871#L438-3 assume !(0 == ~E_2~0); 23870#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23869#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23866#L197-12 assume 1 == ~m_pc~0; 23864#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23863#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23861#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 23858#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23856#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23852#L216-12 assume !(1 == ~t1_pc~0); 23847#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 23844#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23840#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 23835#L518-12 assume !(0 != activate_threads_~tmp___0~0#1); 23831#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23827#L235-12 assume !(1 == ~t2_pc~0); 23809#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 23807#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23805#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 23803#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23801#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23799#L254-12 assume !(1 == ~t3_pc~0); 23797#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 23795#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23793#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23790#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23788#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23786#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 23784#L461-5 assume !(1 == ~T1_E~0); 23782#L466-3 assume !(1 == ~T2_E~0); 23762#L471-3 assume !(1 == ~T3_E~0); 23754#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23751#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23749#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23747#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 23744#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 23741#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 23738#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 23615#L671 assume !(0 == start_simulation_~tmp~3#1); 23611#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 23608#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 23606#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 23604#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 23602#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23600#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23598#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 23596#L684 assume !(0 != start_simulation_~tmp___0~1#1); 22623#L652-2 [2024-11-13 13:31:54,439 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:54,439 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 5 times [2024-11-13 13:31:54,439 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:54,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2105580918] [2024-11-13 13:31:54,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:54,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:54,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:31:54,452 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:31:54,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:31:54,464 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:31:54,465 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:54,465 INFO L85 PathProgramCache]: Analyzing trace with hash 895063068, now seen corresponding path program 1 times [2024-11-13 13:31:54,465 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:54,465 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1041395371] [2024-11-13 13:31:54,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:54,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:54,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:54,550 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:54,550 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:54,551 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1041395371] [2024-11-13 13:31:54,551 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1041395371] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:54,551 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:54,551 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:31:54,551 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1832187149] [2024-11-13 13:31:54,551 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:54,552 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:31:54,552 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:54,552 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:31:54,552 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:31:54,552 INFO L87 Difference]: Start difference. First operand 1658 states and 2216 transitions. cyclomatic complexity: 562 Second operand has 5 states, 5 states have (on average 13.0) internal successors, (65), 5 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:54,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:54,740 INFO L93 Difference]: Finished difference Result 1757 states and 2315 transitions. [2024-11-13 13:31:54,740 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1757 states and 2315 transitions. [2024-11-13 13:31:54,752 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1688 [2024-11-13 13:31:54,762 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1757 states to 1757 states and 2315 transitions. [2024-11-13 13:31:54,762 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1757 [2024-11-13 13:31:54,765 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1757 [2024-11-13 13:31:54,765 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1757 states and 2315 transitions. [2024-11-13 13:31:54,768 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:31:54,768 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1757 states and 2315 transitions. [2024-11-13 13:31:54,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1757 states and 2315 transitions. [2024-11-13 13:31:54,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1757 to 1757. [2024-11-13 13:31:54,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1757 states, 1757 states have (on average 1.3175867956744451) internal successors, (2315), 1756 states have internal predecessors, (2315), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:54,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1757 states to 1757 states and 2315 transitions. [2024-11-13 13:31:54,857 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1757 states and 2315 transitions. [2024-11-13 13:31:54,858 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:31:54,858 INFO L424 stractBuchiCegarLoop]: Abstraction has 1757 states and 2315 transitions. [2024-11-13 13:31:54,858 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 13:31:54,858 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1757 states and 2315 transitions. [2024-11-13 13:31:54,867 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1688 [2024-11-13 13:31:54,867 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:31:54,868 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:31:54,868 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:54,869 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:54,869 INFO L745 eck$LassoCheckResult]: Stem: 26221#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 26222#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 26236#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26232#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26202#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 26203#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25997#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25998#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26249#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25969#L418 assume !(0 == ~M_E~0); 25970#L418-2 assume !(0 == ~T1_E~0); 26201#L423-1 assume !(0 == ~T2_E~0); 26255#L428-1 assume !(0 == ~T3_E~0); 26253#L433-1 assume !(0 == ~E_1~0); 26240#L438-1 assume !(0 == ~E_2~0); 26152#L443-1 assume !(0 == ~E_3~0); 26144#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26104#L197 assume !(1 == ~m_pc~0); 26101#L197-2 is_master_triggered_~__retres1~0#1 := 0; 26278#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26193#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 26194#L510 assume !(0 != activate_threads_~tmp~1#1); 25944#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25945#L216 assume !(1 == ~t1_pc~0); 25995#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25996#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26026#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 25949#L518 assume !(0 != activate_threads_~tmp___0~0#1); 25950#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26165#L235 assume !(1 == ~t2_pc~0); 26247#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26248#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26291#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26270#L526 assume !(0 != activate_threads_~tmp___1~0#1); 26271#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26073#L254 assume !(1 == ~t3_pc~0); 26002#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26003#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25959#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 25960#L534 assume !(0 != activate_threads_~tmp___2~0#1); 26081#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25936#L461 assume !(1 == ~M_E~0); 25937#L461-2 assume !(1 == ~T1_E~0); 25999#L466-1 assume !(1 == ~T2_E~0); 26259#L471-1 assume !(1 == ~T3_E~0); 26029#L476-1 assume !(1 == ~E_1~0); 26030#L481-1 assume !(1 == ~E_2~0); 26185#L486-1 assume !(1 == ~E_3~0); 26047#L491-1 assume { :end_inline_reset_delta_events } true; 26048#L652-2 [2024-11-13 13:31:54,869 INFO L747 eck$LassoCheckResult]: Loop: 26048#L652-2 assume !false; 26365#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26347#L393-1 assume !false; 26348#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 26342#L309 assume !(0 == ~m_st~0); 26344#L313 assume !(0 == ~t1_st~0); 26992#L317 assume !(0 == ~t2_st~0); 26990#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 26989#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 26987#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26985#L346 assume !(0 != eval_~tmp~0#1); 26983#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26981#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26977#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26975#L418-5 assume !(0 == ~T1_E~0); 26973#L423-3 assume !(0 == ~T2_E~0); 26971#L428-3 assume !(0 == ~T3_E~0); 26968#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26966#L438-3 assume !(0 == ~E_2~0); 26964#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26962#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26960#L197-12 assume 1 == ~m_pc~0; 26958#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 26956#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26954#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 26953#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26952#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26951#L216-12 assume !(1 == ~t1_pc~0); 26950#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 26946#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26944#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 26942#L518-12 assume !(0 != activate_threads_~tmp___0~0#1); 26940#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26939#L235-12 assume !(1 == ~t2_pc~0); 26937#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 26935#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26933#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26932#L526-12 assume !(0 != activate_threads_~tmp___1~0#1); 26929#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26926#L254-12 assume !(1 == ~t3_pc~0); 26925#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 26924#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26921#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26918#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26915#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26913#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26910#L461-5 assume !(1 == ~T1_E~0); 26908#L466-3 assume !(1 == ~T2_E~0); 26906#L471-3 assume !(1 == ~T3_E~0); 26903#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26901#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26899#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26898#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 26897#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 26895#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 26894#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 26736#L671 assume !(0 == start_simulation_~tmp~3#1); 26733#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 26729#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 26727#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 26725#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 26723#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26721#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26386#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 26387#L684 assume !(0 != start_simulation_~tmp___0~1#1); 26048#L652-2 [2024-11-13 13:31:54,870 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:54,870 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 6 times [2024-11-13 13:31:54,870 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:54,870 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308307532] [2024-11-13 13:31:54,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:54,871 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:54,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:31:54,881 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:31:54,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:31:54,893 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:31:54,893 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:54,894 INFO L85 PathProgramCache]: Analyzing trace with hash 385589978, now seen corresponding path program 1 times [2024-11-13 13:31:54,894 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:54,894 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1404248049] [2024-11-13 13:31:54,894 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:54,894 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:54,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:54,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:54,980 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:54,980 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1404248049] [2024-11-13 13:31:54,980 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1404248049] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:54,980 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:54,980 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:31:54,980 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [710784686] [2024-11-13 13:31:54,980 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:54,981 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:31:54,981 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:54,981 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:31:54,981 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:31:54,982 INFO L87 Difference]: Start difference. First operand 1757 states and 2315 transitions. cyclomatic complexity: 562 Second operand has 5 states, 5 states have (on average 13.0) internal successors, (65), 5 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:55,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:55,151 INFO L93 Difference]: Finished difference Result 1805 states and 2346 transitions. [2024-11-13 13:31:55,151 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1805 states and 2346 transitions. [2024-11-13 13:31:55,162 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1736 [2024-11-13 13:31:55,174 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1805 states to 1805 states and 2346 transitions. [2024-11-13 13:31:55,178 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1805 [2024-11-13 13:31:55,181 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1805 [2024-11-13 13:31:55,181 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1805 states and 2346 transitions. [2024-11-13 13:31:55,185 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:31:55,185 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1805 states and 2346 transitions. [2024-11-13 13:31:55,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1805 states and 2346 transitions. [2024-11-13 13:31:55,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1805 to 1805. [2024-11-13 13:31:55,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1805 states, 1805 states have (on average 1.2997229916897506) internal successors, (2346), 1804 states have internal predecessors, (2346), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:55,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1805 states to 1805 states and 2346 transitions. [2024-11-13 13:31:55,226 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1805 states and 2346 transitions. [2024-11-13 13:31:55,227 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:31:55,228 INFO L424 stractBuchiCegarLoop]: Abstraction has 1805 states and 2346 transitions. [2024-11-13 13:31:55,228 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 13:31:55,228 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1805 states and 2346 transitions. [2024-11-13 13:31:55,237 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1736 [2024-11-13 13:31:55,237 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:31:55,237 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:31:55,239 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:55,239 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:55,240 INFO L745 eck$LassoCheckResult]: Stem: 29791#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 29792#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 29804#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29802#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29773#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 29774#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29569#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29570#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29822#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29537#L418 assume !(0 == ~M_E~0); 29538#L418-2 assume !(0 == ~T1_E~0); 29772#L423-1 assume !(0 == ~T2_E~0); 29830#L428-1 assume !(0 == ~T3_E~0); 29828#L433-1 assume !(0 == ~E_1~0); 29809#L438-1 assume !(0 == ~E_2~0); 29723#L443-1 assume !(0 == ~E_3~0); 29714#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29676#L197 assume !(1 == ~m_pc~0); 29673#L197-2 is_master_triggered_~__retres1~0#1 := 0; 29858#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29761#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 29762#L510 assume !(0 != activate_threads_~tmp~1#1); 29514#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29515#L216 assume !(1 == ~t1_pc~0); 29567#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29568#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29598#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 29516#L518 assume !(0 != activate_threads_~tmp___0~0#1); 29517#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29732#L235 assume !(1 == ~t2_pc~0); 29817#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29818#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29870#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 29847#L526 assume !(0 != activate_threads_~tmp___1~0#1); 29848#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29642#L254 assume !(1 == ~t3_pc~0); 29574#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29575#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29527#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 29528#L534 assume !(0 != activate_threads_~tmp___2~0#1); 29653#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29506#L461 assume !(1 == ~M_E~0); 29507#L461-2 assume !(1 == ~T1_E~0); 29571#L466-1 assume !(1 == ~T2_E~0); 29836#L471-1 assume !(1 == ~T3_E~0); 29601#L476-1 assume !(1 == ~E_1~0); 29602#L481-1 assume !(1 == ~E_2~0); 29751#L486-1 assume !(1 == ~E_3~0); 29619#L491-1 assume { :end_inline_reset_delta_events } true; 29523#L652-2 [2024-11-13 13:31:55,240 INFO L747 eck$LassoCheckResult]: Loop: 29523#L652-2 assume !false; 29524#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29592#L393-1 assume !false; 29590#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 29591#L309 assume !(0 == ~m_st~0); 29562#L313 assume !(0 == ~t1_st~0); 29564#L317 assume !(0 == ~t2_st~0); 29760#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 29832#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 31171#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 31172#L346 assume !(0 != eval_~tmp~0#1); 29698#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29699#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29736#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29730#L418-5 assume !(0 == ~T1_E~0); 29731#L423-3 assume !(0 == ~T2_E~0); 29759#L428-3 assume !(0 == ~T3_E~0); 31134#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31133#L438-3 assume !(0 == ~E_2~0); 31132#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31131#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31129#L197-12 assume 1 == ~m_pc~0; 31126#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31127#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31236#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 31235#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31234#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31233#L216-12 assume !(1 == ~t1_pc~0); 31232#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 31229#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31227#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 31225#L518-12 assume !(0 != activate_threads_~tmp___0~0#1); 31223#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31222#L235-12 assume !(1 == ~t2_pc~0); 31220#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 31218#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31216#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 31215#L526-12 assume !(0 != activate_threads_~tmp___1~0#1); 31213#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31212#L254-12 assume !(1 == ~t3_pc~0); 31211#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 31210#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31209#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 31208#L534-12 assume !(0 != activate_threads_~tmp___2~0#1); 31207#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31206#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 31205#L461-5 assume !(1 == ~T1_E~0); 31204#L466-3 assume !(1 == ~T2_E~0); 31203#L471-3 assume !(1 == ~T3_E~0); 31202#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 31201#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31199#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31197#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 31196#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 31195#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 31194#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 31192#L671 assume !(0 == start_simulation_~tmp~3#1); 31190#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 31189#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 29748#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 29596#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 29597#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29755#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29756#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 29757#L684 assume !(0 != start_simulation_~tmp___0~1#1); 29523#L652-2 [2024-11-13 13:31:55,240 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:55,241 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 7 times [2024-11-13 13:31:55,241 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:55,241 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1979437524] [2024-11-13 13:31:55,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:55,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:55,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:31:55,251 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:31:55,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:31:55,265 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:31:55,267 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:55,268 INFO L85 PathProgramCache]: Analyzing trace with hash 604444696, now seen corresponding path program 1 times [2024-11-13 13:31:55,268 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:55,268 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1222603639] [2024-11-13 13:31:55,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:55,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:55,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:31:55,290 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:31:55,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:31:55,310 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:31:55,312 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:55,313 INFO L85 PathProgramCache]: Analyzing trace with hash 917122631, now seen corresponding path program 1 times [2024-11-13 13:31:55,313 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:55,313 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [607015247] [2024-11-13 13:31:55,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:55,313 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:55,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:55,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:55,372 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:55,373 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [607015247] [2024-11-13 13:31:55,373 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [607015247] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:55,373 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:55,373 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:31:55,373 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1513650654] [2024-11-13 13:31:55,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:56,377 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 13:31:56,378 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 13:31:56,378 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 13:31:56,378 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 13:31:56,379 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-13 13:31:56,379 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:56,379 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 13:31:56,379 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 13:31:56,379 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.03.cil.c_Iteration17_Loop [2024-11-13 13:31:56,379 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 13:31:56,379 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 13:31:56,406 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,415 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,420 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,423 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,427 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,430 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,433 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,437 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,441 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,444 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,448 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,452 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,456 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,465 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,468 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,476 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,480 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,483 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,492 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,496 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,504 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,509 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,513 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,524 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,528 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,532 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,536 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,540 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,552 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,555 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,559 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,562 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,567 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,570 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,573 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,581 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,584 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,588 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,596 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,599 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,602 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,605 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,608 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,612 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,615 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,619 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,622 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,626 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,630 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,638 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:56,641 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,147 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 13:31:57,149 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-13 13:31:57,151 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:57,152 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:57,155 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:57,160 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-13 13:31:57,161 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:31:57,161 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:31:57,186 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:31:57,186 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:31:57,209 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-11-13 13:31:57,209 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:57,210 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:57,212 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:57,214 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-13 13:31:57,217 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:31:57,218 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:31:57,264 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:31:57,264 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t2_st~0=4} Honda state: {~t2_st~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:31:57,287 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2024-11-13 13:31:57,287 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:57,287 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:57,290 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:57,292 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-13 13:31:57,294 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:31:57,294 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:31:57,315 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:31:57,315 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:31:57,337 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2024-11-13 13:31:57,338 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:57,338 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:57,340 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:57,368 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-13 13:31:57,369 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:31:57,370 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:31:57,393 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:31:57,394 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret10#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret10#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:31:57,415 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2024-11-13 13:31:57,415 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:57,416 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:57,419 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:57,421 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-13 13:31:57,423 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:31:57,423 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:31:57,453 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:31:57,453 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:31:57,470 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2024-11-13 13:31:57,470 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:57,471 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:57,473 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:57,474 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-13 13:31:57,475 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:31:57,475 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:31:57,491 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:31:57,491 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:31:57,504 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2024-11-13 13:31:57,505 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:57,505 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:57,506 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:57,507 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-13 13:31:57,508 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:31:57,508 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:31:57,522 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:31:57,522 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret9#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret9#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:31:57,540 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-11-13 13:31:57,540 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:57,540 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:57,542 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:57,545 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-13 13:31:57,546 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:31:57,546 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:31:57,559 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:31:57,559 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:31:57,570 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2024-11-13 13:31:57,571 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:57,571 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:57,573 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:57,576 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-13 13:31:57,577 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:31:57,577 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:31:57,593 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:31:57,593 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret12#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret12#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:31:57,608 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2024-11-13 13:31:57,608 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:57,608 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:57,610 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:57,611 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-13 13:31:57,612 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:31:57,612 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:31:57,631 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:31:57,632 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=4} Honda state: {~t1_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:31:57,644 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2024-11-13 13:31:57,644 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:57,644 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:57,646 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:57,651 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-11-13 13:31:57,652 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:31:57,652 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:31:57,665 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:31:57,665 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:31:57,678 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2024-11-13 13:31:57,678 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:57,678 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:57,680 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:57,681 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-11-13 13:31:57,682 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:31:57,682 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:31:57,705 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:31:57,705 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=4} Honda state: {~t3_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:31:57,719 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2024-11-13 13:31:57,720 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:57,720 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:57,722 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:57,725 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-11-13 13:31:57,726 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:31:57,726 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:31:57,768 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2024-11-13 13:31:57,768 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:57,768 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:57,770 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:57,773 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-11-13 13:31:57,774 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-13 13:31:57,774 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:31:57,798 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-13 13:31:57,819 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2024-11-13 13:31:57,820 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 13:31:57,820 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 13:31:57,820 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 13:31:57,820 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 13:31:57,820 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-13 13:31:57,820 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:57,820 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 13:31:57,820 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 13:31:57,820 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.03.cil.c_Iteration17_Loop [2024-11-13 13:31:57,820 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 13:31:57,820 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 13:31:57,828 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,835 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,840 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,849 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,852 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,855 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,860 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,865 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,868 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,872 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,875 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,879 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,883 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,894 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,898 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,906 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,909 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,912 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,923 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,926 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,934 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,941 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,945 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,948 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,951 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,955 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,960 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,967 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,970 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,973 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,976 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,979 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,982 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,985 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,988 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,994 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:57,997 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:58,000 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:58,008 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:58,011 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:58,014 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:58,017 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:58,020 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:58,023 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:58,026 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:58,032 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:58,035 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:58,038 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:58,042 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:58,045 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:58,049 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:31:58,508 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 13:31:58,513 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-13 13:31:58,514 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:58,515 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:58,517 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:58,522 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-11-13 13:31:58,523 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:31:58,544 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:31:58,544 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:31:58,545 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:31:58,545 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:31:58,547 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:31:58,554 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:31:58,555 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:31:58,558 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:31:58,579 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2024-11-13 13:31:58,579 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:58,579 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:58,582 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:58,584 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-11-13 13:31:58,585 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:31:58,603 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:31:58,603 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:31:58,603 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:31:58,603 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:31:58,603 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:31:58,604 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:31:58,604 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:31:58,607 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:31:58,628 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2024-11-13 13:31:58,628 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:58,628 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:58,631 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:58,634 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-11-13 13:31:58,634 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:31:58,652 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:31:58,652 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:31:58,653 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:31:58,653 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 13:31:58,653 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:31:58,656 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 13:31:58,656 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:31:58,659 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:31:58,682 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2024-11-13 13:31:58,682 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:58,682 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:58,685 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:58,687 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-11-13 13:31:58,688 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:31:58,705 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:31:58,705 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:31:58,705 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:31:58,705 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:31:58,705 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:31:58,707 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:31:58,707 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:31:58,709 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:31:58,730 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2024-11-13 13:31:58,731 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:58,731 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:58,734 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:58,737 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2024-11-13 13:31:58,737 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:31:58,754 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:31:58,754 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:31:58,754 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:31:58,755 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:31:58,755 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:31:58,755 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:31:58,755 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:31:58,757 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:31:58,779 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2024-11-13 13:31:58,780 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:58,780 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:58,782 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:58,783 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2024-11-13 13:31:58,784 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:31:58,797 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:31:58,797 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:31:58,797 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:31:58,797 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:31:58,797 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:31:58,798 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:31:58,798 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:31:58,802 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:31:58,817 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2024-11-13 13:31:58,818 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:58,818 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:58,820 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:58,821 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2024-11-13 13:31:58,822 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:31:58,835 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:31:58,835 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:31:58,835 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:31:58,836 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:31:58,836 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:31:58,836 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:31:58,836 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:31:58,838 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:31:58,852 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Ended with exit code 0 [2024-11-13 13:31:58,853 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:58,853 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:58,854 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:58,856 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2024-11-13 13:31:58,857 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:31:58,870 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:31:58,870 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:31:58,870 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:31:58,870 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:31:58,870 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:31:58,871 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:31:58,871 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:31:58,876 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:31:58,897 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Ended with exit code 0 [2024-11-13 13:31:58,897 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:58,897 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:58,901 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:58,905 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2024-11-13 13:31:58,906 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:31:58,923 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:31:58,923 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:31:58,923 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:31:58,923 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:31:58,923 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:31:58,924 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:31:58,924 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:31:58,927 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:31:58,949 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Ended with exit code 0 [2024-11-13 13:31:58,949 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:58,950 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:58,952 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:58,956 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2024-11-13 13:31:58,956 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:31:58,971 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:31:58,971 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:31:58,971 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:31:58,971 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:31:58,971 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:31:58,972 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:31:58,972 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:31:58,974 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:31:58,988 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Ended with exit code 0 [2024-11-13 13:31:58,989 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:58,989 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:58,991 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:58,992 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2024-11-13 13:31:58,993 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:31:59,005 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:31:59,005 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:31:59,005 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:31:59,005 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 13:31:59,005 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:31:59,006 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 13:31:59,006 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:31:59,008 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:31:59,021 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Ended with exit code 0 [2024-11-13 13:31:59,021 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:59,021 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:59,023 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:59,024 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2024-11-13 13:31:59,025 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:31:59,042 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:31:59,042 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:31:59,042 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:31:59,042 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 13:31:59,042 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:31:59,043 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 13:31:59,043 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:31:59,047 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:31:59,068 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Ended with exit code 0 [2024-11-13 13:31:59,068 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:59,068 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:59,071 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:59,073 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2024-11-13 13:31:59,074 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:31:59,091 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:31:59,091 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:31:59,091 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:31:59,091 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:31:59,091 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:31:59,093 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:31:59,093 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:31:59,096 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-13 13:31:59,100 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-13 13:31:59,104 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-13 13:31:59,105 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:31:59,106 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:59,108 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:59,111 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2024-11-13 13:31:59,111 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-13 13:31:59,112 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-13 13:31:59,112 INFO L474 LassoAnalysis]: Proved termination. [2024-11-13 13:31:59,112 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_3~0) = -1*~E_3~0 + 1 Supporting invariants [] [2024-11-13 13:31:59,134 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Ended with exit code 0 [2024-11-13 13:31:59,137 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-13 13:31:59,174 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:59,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:59,223 INFO L255 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-13 13:31:59,225 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:31:59,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:59,371 INFO L255 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-13 13:31:59,374 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:31:59,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:59,612 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-13 13:31:59,613 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 1805 states and 2346 transitions. cyclomatic complexity: 545 Second operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:59,833 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 1805 states and 2346 transitions. cyclomatic complexity: 545. Second operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 4751 states and 6201 transitions. Complement of second has 5 states. [2024-11-13 13:31:59,835 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-13 13:31:59,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:31:59,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 365 transitions. [2024-11-13 13:31:59,846 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 365 transitions. Stem has 49 letters. Loop has 65 letters. [2024-11-13 13:31:59,850 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:31:59,852 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 365 transitions. Stem has 114 letters. Loop has 65 letters. [2024-11-13 13:31:59,853 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:31:59,854 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 365 transitions. Stem has 49 letters. Loop has 130 letters. [2024-11-13 13:31:59,859 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:31:59,859 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4751 states and 6201 transitions. [2024-11-13 13:31:59,894 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3168 [2024-11-13 13:31:59,938 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4751 states to 4743 states and 6193 transitions. [2024-11-13 13:31:59,938 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3258 [2024-11-13 13:31:59,942 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3279 [2024-11-13 13:31:59,943 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4743 states and 6193 transitions. [2024-11-13 13:31:59,943 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:31:59,943 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4743 states and 6193 transitions. [2024-11-13 13:31:59,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4743 states and 6193 transitions. [2024-11-13 13:32:00,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4743 to 4714. [2024-11-13 13:32:00,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4714 states, 4714 states have (on average 1.305897327110734) internal successors, (6156), 4713 states have internal predecessors, (6156), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:32:00,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4714 states to 4714 states and 6156 transitions. [2024-11-13 13:32:00,058 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4714 states and 6156 transitions. [2024-11-13 13:32:00,058 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:32:00,058 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:32:00,058 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:32:00,058 INFO L87 Difference]: Start difference. First operand 4714 states and 6156 transitions. Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:32:00,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:32:00,139 INFO L93 Difference]: Finished difference Result 5074 states and 6540 transitions. [2024-11-13 13:32:00,139 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5074 states and 6540 transitions. [2024-11-13 13:32:00,171 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3408 [2024-11-13 13:32:00,264 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5074 states to 5074 states and 6540 transitions. [2024-11-13 13:32:00,264 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3490 [2024-11-13 13:32:00,269 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3490 [2024-11-13 13:32:00,273 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5074 states and 6540 transitions. [2024-11-13 13:32:00,273 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:32:00,273 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5074 states and 6540 transitions. [2024-11-13 13:32:00,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5074 states and 6540 transitions. [2024-11-13 13:32:00,306 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Ended with exit code 0 [2024-11-13 13:32:00,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5074 to 4714. [2024-11-13 13:32:00,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4714 states, 4714 states have (on average 1.295714891811625) internal successors, (6108), 4713 states have internal predecessors, (6108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:32:00,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4714 states to 4714 states and 6108 transitions. [2024-11-13 13:32:00,388 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4714 states and 6108 transitions. [2024-11-13 13:32:00,388 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:32:00,389 INFO L424 stractBuchiCegarLoop]: Abstraction has 4714 states and 6108 transitions. [2024-11-13 13:32:00,389 INFO L331 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-13 13:32:00,389 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4714 states and 6108 transitions. [2024-11-13 13:32:00,413 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3168 [2024-11-13 13:32:00,413 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:32:00,413 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:32:00,416 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:32:00,416 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:32:00,416 INFO L745 eck$LassoCheckResult]: Stem: 46734#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 46735#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 46766#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46759#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46701#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 46702#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46322#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46323#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46789#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46262#L418 assume !(0 == ~M_E~0); 46263#L418-2 assume !(0 == ~T1_E~0); 46700#L423-1 assume !(0 == ~T2_E~0); 46798#L428-1 assume !(0 == ~T3_E~0); 46795#L433-1 assume !(0 == ~E_1~0); 46773#L438-1 assume !(0 == ~E_2~0); 46609#L443-1 assume !(0 == ~E_3~0); 46596#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46522#L197 assume !(1 == ~m_pc~0); 46517#L197-2 is_master_triggered_~__retres1~0#1 := 0; 46848#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46877#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 46819#L510 assume !(0 != activate_threads_~tmp~1#1); 46226#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46227#L216 assume !(1 == ~t1_pc~0); 46316#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46317#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46375#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 46228#L518 assume !(0 != activate_threads_~tmp___0~0#1); 46229#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46624#L235 assume !(1 == ~t2_pc~0); 46783#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46784#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46878#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 46832#L526 assume !(0 != activate_threads_~tmp___1~0#1); 46833#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46457#L254 assume !(1 == ~t3_pc~0); 46329#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46330#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46248#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 46249#L534 assume !(0 != activate_threads_~tmp___2~0#1); 46478#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46214#L461 assume !(1 == ~M_E~0); 46215#L461-2 assume !(1 == ~T1_E~0); 46324#L466-1 assume !(1 == ~T2_E~0); 46812#L471-1 assume !(1 == ~T3_E~0); 46376#L476-1 assume !(1 == ~E_1~0); 46377#L481-1 assume !(1 == ~E_2~0); 46668#L486-1 assume !(1 == ~E_3~0); 46409#L491-1 assume { :end_inline_reset_delta_events } true; 46410#L652-2 assume !false; 47341#L653 [2024-11-13 13:32:00,417 INFO L747 eck$LassoCheckResult]: Loop: 47341#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49256#L393-1 assume !false; 49252#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 49250#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 49248#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 49246#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49243#L346 assume 0 != eval_~tmp~0#1; 49241#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 49238#L354 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 49239#L53 assume !(0 == ~m_pc~0); 49705#L56 assume 1 == ~m_pc~0; 49702#$Ultimate##157 assume !false; 49700#L73 ~m_pc~0 := 1;~m_st~0 := 2; 49698#master_returnLabel#1 assume { :end_inline_master } true; 49690#L354-2 havoc eval_~tmp_ndt_1~0#1; 49684#L351-1 assume !(0 == ~t1_st~0); 49681#L365-1 assume !(0 == ~t2_st~0); 49653#L379-1 assume !(0 == ~t3_st~0); 49650#L393-1 assume !false; 49648#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 49646#L309 assume !(0 == ~m_st~0); 49644#L313 assume !(0 == ~t1_st~0); 49642#L317 assume !(0 == ~t2_st~0); 49639#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 49637#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 49633#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49630#L346 assume !(0 != eval_~tmp~0#1); 49628#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49626#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49623#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49621#L418-5 assume !(0 == ~T1_E~0); 49619#L423-3 assume !(0 == ~T2_E~0); 49617#L428-3 assume !(0 == ~T3_E~0); 49615#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49613#L438-3 assume !(0 == ~E_2~0); 49611#L443-3 assume !(0 == ~E_3~0); 49607#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49605#L197-12 assume 1 == ~m_pc~0; 49602#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 49603#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50845#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 50843#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46557#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46445#L216-12 assume !(1 == ~t1_pc~0); 46446#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 49349#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49345#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 49343#L518-12 assume !(0 != activate_threads_~tmp___0~0#1); 49341#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49336#L235-12 assume !(1 == ~t2_pc~0); 49334#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 49332#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49330#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 49325#L526-12 assume !(0 != activate_threads_~tmp___1~0#1); 49322#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49320#L254-12 assume !(1 == ~t3_pc~0); 49318#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 49316#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49314#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 49311#L534-12 assume !(0 != activate_threads_~tmp___2~0#1); 49309#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49307#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49304#L461-5 assume !(1 == ~T1_E~0); 49302#L466-3 assume !(1 == ~T2_E~0); 49300#L471-3 assume !(1 == ~T3_E~0); 49298#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49296#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49294#L486-3 assume !(1 == ~E_3~0); 49290#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 49288#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 49286#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 49284#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 49280#L671 assume !(0 == start_simulation_~tmp~3#1); 49277#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 49275#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 49272#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 49270#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 49268#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49266#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49264#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 49262#L684 assume !(0 != start_simulation_~tmp___0~1#1); 49260#L652-2 assume !false; 47341#L653 [2024-11-13 13:32:00,418 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:00,419 INFO L85 PathProgramCache]: Analyzing trace with hash -1276375253, now seen corresponding path program 1 times [2024-11-13 13:32:00,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:32:00,419 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [595410862] [2024-11-13 13:32:00,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:32:00,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:32:00,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:00,438 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:32:00,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:00,459 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:32:00,460 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:00,461 INFO L85 PathProgramCache]: Analyzing trace with hash 1511027026, now seen corresponding path program 1 times [2024-11-13 13:32:00,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:32:00,461 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1276748306] [2024-11-13 13:32:00,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:32:00,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:32:00,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:00,482 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:32:00,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:00,505 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:32:00,506 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:00,506 INFO L85 PathProgramCache]: Analyzing trace with hash -955221508, now seen corresponding path program 1 times [2024-11-13 13:32:00,507 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:32:00,507 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1144793001] [2024-11-13 13:32:00,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:32:00,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:32:00,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:32:00,634 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:32:00,634 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:32:00,634 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1144793001] [2024-11-13 13:32:00,634 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1144793001] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:32:00,634 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:32:00,634 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:32:00,635 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [86978470] [2024-11-13 13:32:00,635 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:32:01,566 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 13:32:01,566 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 13:32:01,566 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 13:32:01,566 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 13:32:01,566 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-13 13:32:01,566 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:01,566 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 13:32:01,567 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 13:32:01,567 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.03.cil.c_Iteration18_Loop [2024-11-13 13:32:01,567 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 13:32:01,567 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 13:32:01,570 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,573 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,576 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,579 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,582 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,585 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,592 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,595 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,599 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,602 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,605 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,609 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,612 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,615 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,618 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,621 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,624 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,627 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,634 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,637 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,641 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,644 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,647 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,650 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,654 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,665 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,674 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,677 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,683 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,686 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,689 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,696 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,704 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,711 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,714 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,717 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,720 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,723 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,726 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,729 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,739 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,744 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,747 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,750 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,752 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,757 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,761 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,768 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,771 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,774 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:01,782 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:02,238 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 13:32:02,239 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-13 13:32:02,239 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:02,239 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:02,241 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:02,247 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:02,248 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:02,252 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2024-11-13 13:32:02,271 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:02,271 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Honda state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:02,293 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:02,293 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:02,294 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:02,296 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:02,338 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2024-11-13 13:32:02,339 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:02,339 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:02,362 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:02,362 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:02,380 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Ended with exit code 0 [2024-11-13 13:32:02,381 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:02,381 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:02,383 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:02,386 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2024-11-13 13:32:02,387 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:02,387 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:02,407 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:02,407 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet8#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet8#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:02,429 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Ended with exit code 0 [2024-11-13 13:32:02,429 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:02,430 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:02,432 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:02,436 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2024-11-13 13:32:02,437 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:02,437 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:02,458 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:02,458 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit3_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit3_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:02,481 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Ended with exit code 0 [2024-11-13 13:32:02,482 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:02,482 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:02,485 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:02,488 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:02,489 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:02,489 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2024-11-13 13:32:02,513 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:02,513 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_~__retres1~4#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_~__retres1~4#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:02,533 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Ended with exit code 0 [2024-11-13 13:32:02,533 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:02,533 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:02,535 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:02,536 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2024-11-13 13:32:02,537 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:02,537 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:02,564 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:02,564 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_3~0=-1} Honda state: {~E_3~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:02,586 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Ended with exit code 0 [2024-11-13 13:32:02,587 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:02,587 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:02,589 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:02,591 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2024-11-13 13:32:02,591 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:02,591 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:02,607 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:02,607 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:02,621 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Ended with exit code 0 [2024-11-13 13:32:02,621 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:02,621 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:02,623 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:02,624 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2024-11-13 13:32:02,625 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:02,625 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:02,649 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:02,649 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t2_st~0=4} Honda state: {~t2_st~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:02,664 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Ended with exit code 0 [2024-11-13 13:32:02,664 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:02,665 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:02,666 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:02,669 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2024-11-13 13:32:02,669 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:02,669 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:02,685 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:02,685 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet5#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet5#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:02,700 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Ended with exit code 0 [2024-11-13 13:32:02,700 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:02,700 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:02,703 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:02,704 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Waiting until timeout for monitored process [2024-11-13 13:32:02,705 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:02,705 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:02,721 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:02,721 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:02,737 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Ended with exit code 0 [2024-11-13 13:32:02,737 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:02,737 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:02,739 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:02,741 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Waiting until timeout for monitored process [2024-11-13 13:32:02,741 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:02,741 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:02,764 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:02,765 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=4} Honda state: {~t1_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:02,778 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Ended with exit code 0 [2024-11-13 13:32:02,779 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:02,779 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:02,781 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:02,782 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Waiting until timeout for monitored process [2024-11-13 13:32:02,783 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:02,783 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:02,807 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:02,807 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~ret4#1=0} Honda state: {ULTIMATE.start_eval_#t~ret4#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:02,824 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Ended with exit code 0 [2024-11-13 13:32:02,824 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:02,824 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:02,826 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:02,827 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Waiting until timeout for monitored process [2024-11-13 13:32:02,828 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:02,828 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:02,843 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:02,843 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_1~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:02,858 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Ended with exit code 0 [2024-11-13 13:32:02,859 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:02,859 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:02,861 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:02,862 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Waiting until timeout for monitored process [2024-11-13 13:32:02,862 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:02,862 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:02,877 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:02,877 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:02,893 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:02,893 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:02,893 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:02,895 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:02,897 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Waiting until timeout for monitored process [2024-11-13 13:32:02,898 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:02,898 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:02,913 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:02,914 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret11#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret11#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:02,928 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Ended with exit code 0 [2024-11-13 13:32:02,928 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:02,928 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:02,930 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:02,932 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Waiting until timeout for monitored process [2024-11-13 13:32:02,932 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:02,932 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:02,948 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:02,948 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_4~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_4~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:02,962 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:02,963 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:02,963 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:02,964 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:02,966 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Waiting until timeout for monitored process [2024-11-13 13:32:02,966 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:02,966 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:02,981 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:02,981 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~tmp~2#1=0} Honda state: {ULTIMATE.start_stop_simulation_~tmp~2#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:02,996 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Ended with exit code 0 [2024-11-13 13:32:02,996 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:02,996 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:02,998 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:02,999 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Waiting until timeout for monitored process [2024-11-13 13:32:03,000 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:03,000 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:03,015 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:03,016 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:03,030 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Ended with exit code 0 [2024-11-13 13:32:03,030 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:03,030 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:03,032 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:03,034 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Waiting until timeout for monitored process [2024-11-13 13:32:03,036 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:03,036 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:03,054 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:03,054 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_#res#1=0} Honda state: {ULTIMATE.start_stop_simulation_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:03,068 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:03,069 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:03,069 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:03,071 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:03,072 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Waiting until timeout for monitored process [2024-11-13 13:32:03,073 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:03,073 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:03,097 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:03,097 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=4} Honda state: {~t3_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:03,111 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Ended with exit code 0 [2024-11-13 13:32:03,112 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:03,112 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:03,114 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:03,115 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Waiting until timeout for monitored process [2024-11-13 13:32:03,115 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:03,116 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:03,131 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:03,131 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret9#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret9#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:03,146 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:03,147 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:03,147 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:03,149 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:03,150 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Waiting until timeout for monitored process [2024-11-13 13:32:03,151 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:03,151 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:03,166 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:03,166 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_3~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_3~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:03,181 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Ended with exit code 0 [2024-11-13 13:32:03,181 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:03,181 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:03,184 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:03,185 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Waiting until timeout for monitored process [2024-11-13 13:32:03,187 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:03,187 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:03,202 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:03,202 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:03,218 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:03,218 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:03,219 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:03,221 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:03,224 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Waiting until timeout for monitored process [2024-11-13 13:32:03,225 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:03,225 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:03,255 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:03,255 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_st~0=-1} Honda state: {~t3_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:03,277 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Ended with exit code 0 [2024-11-13 13:32:03,277 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:03,278 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:03,280 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:03,283 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Waiting until timeout for monitored process [2024-11-13 13:32:03,284 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:03,284 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:03,305 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:03,305 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_st~0=0} Honda state: {~m_st~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:03,326 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Ended with exit code 0 [2024-11-13 13:32:03,327 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:03,327 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:03,330 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:03,332 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Waiting until timeout for monitored process [2024-11-13 13:32:03,333 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:03,334 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:03,355 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:03,355 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~tmp~3#1=0} Honda state: {ULTIMATE.start_start_simulation_~tmp~3#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:03,377 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:03,377 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:03,377 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:03,380 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:03,381 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (56)] Waiting until timeout for monitored process [2024-11-13 13:32:03,383 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:03,383 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:03,403 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:03,403 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___1~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:03,424 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (56)] Ended with exit code 0 [2024-11-13 13:32:03,425 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:03,425 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:03,427 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:03,428 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (57)] Waiting until timeout for monitored process [2024-11-13 13:32:03,429 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:03,429 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:03,452 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:03,452 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit1_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit1_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:03,473 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (57)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:03,473 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:03,473 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:03,475 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:03,476 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (58)] Waiting until timeout for monitored process [2024-11-13 13:32:03,477 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:03,477 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:03,493 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:03,493 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~tmp___0~1#1=0} Honda state: {ULTIMATE.start_start_simulation_~tmp___0~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:03,508 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (58)] Ended with exit code 0 [2024-11-13 13:32:03,509 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:03,509 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:03,511 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:03,513 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (59)] Waiting until timeout for monitored process [2024-11-13 13:32:03,514 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:03,514 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:03,529 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:03,529 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___0~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___0~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:03,543 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (59)] Ended with exit code 0 [2024-11-13 13:32:03,544 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:03,544 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:03,545 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:03,546 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (60)] Waiting until timeout for monitored process [2024-11-13 13:32:03,547 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:03,547 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:03,570 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:03,570 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~T1_E~0=-1} Honda state: {~T1_E~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:03,583 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (60)] Ended with exit code 0 [2024-11-13 13:32:03,583 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:03,583 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:03,585 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:03,586 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (61)] Waiting until timeout for monitored process [2024-11-13 13:32:03,587 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:03,587 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:03,608 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:32:03,608 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~T3_E~0=-8} Honda state: {~T3_E~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:32:03,622 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (61)] Ended with exit code 0 [2024-11-13 13:32:03,622 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:03,622 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:03,624 INFO L229 MonitoredProcess]: Starting monitored process 62 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:03,625 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (62)] Waiting until timeout for monitored process [2024-11-13 13:32:03,626 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:32:03,626 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:03,655 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (62)] Ended with exit code 0 [2024-11-13 13:32:03,655 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:03,655 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:03,657 INFO L229 MonitoredProcess]: Starting monitored process 63 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:03,659 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (63)] Waiting until timeout for monitored process [2024-11-13 13:32:03,659 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-13 13:32:03,659 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:32:03,679 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-13 13:32:03,700 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (63)] Ended with exit code 0 [2024-11-13 13:32:03,700 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 13:32:03,700 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 13:32:03,701 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 13:32:03,701 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 13:32:03,701 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-13 13:32:03,701 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:03,701 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 13:32:03,701 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 13:32:03,701 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.03.cil.c_Iteration18_Loop [2024-11-13 13:32:03,701 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 13:32:03,701 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 13:32:03,704 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,709 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,712 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,717 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,720 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,722 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,729 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,732 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,735 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,738 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,741 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,744 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,746 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,750 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,753 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,756 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,759 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,761 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,764 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,774 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,777 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,781 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,783 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,786 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,789 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,792 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,798 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,801 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,804 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,806 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,813 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,815 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,822 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,824 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,835 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,838 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,840 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,845 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,848 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,855 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,861 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,871 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,875 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,877 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,881 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,883 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,890 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,893 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,895 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,902 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:03,905 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:32:04,329 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 13:32:04,329 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-13 13:32:04,329 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:04,329 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:04,331 INFO L229 MonitoredProcess]: Starting monitored process 64 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:04,333 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (64)] Waiting until timeout for monitored process [2024-11-13 13:32:04,334 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:04,348 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:04,348 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:04,348 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:04,348 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:04,349 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:04,349 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:04,349 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:04,351 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:04,366 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (64)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:04,366 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:04,366 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:04,368 INFO L229 MonitoredProcess]: Starting monitored process 65 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:04,369 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (65)] Waiting until timeout for monitored process [2024-11-13 13:32:04,370 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:04,383 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:04,384 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:04,384 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:04,384 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:04,384 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:04,384 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:04,384 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:04,386 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:04,400 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (65)] Ended with exit code 0 [2024-11-13 13:32:04,400 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:04,400 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:04,402 INFO L229 MonitoredProcess]: Starting monitored process 66 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:04,403 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (66)] Waiting until timeout for monitored process [2024-11-13 13:32:04,404 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:04,417 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:04,417 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:04,417 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:04,417 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:04,417 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:04,418 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:04,418 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:04,419 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:04,432 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (66)] Ended with exit code 0 [2024-11-13 13:32:04,433 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:04,433 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:04,435 INFO L229 MonitoredProcess]: Starting monitored process 67 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:04,436 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (67)] Waiting until timeout for monitored process [2024-11-13 13:32:04,436 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:04,449 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:04,450 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:04,450 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:04,450 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:04,450 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:04,450 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:04,450 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:04,452 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:04,465 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (67)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:04,465 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:04,465 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:04,467 INFO L229 MonitoredProcess]: Starting monitored process 68 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:04,468 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (68)] Waiting until timeout for monitored process [2024-11-13 13:32:04,469 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:04,482 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:04,482 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:04,482 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:04,482 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:04,482 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:04,483 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:04,483 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:04,485 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:04,504 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (68)] Ended with exit code 0 [2024-11-13 13:32:04,504 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:04,504 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:04,506 INFO L229 MonitoredProcess]: Starting monitored process 69 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:04,508 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (69)] Waiting until timeout for monitored process [2024-11-13 13:32:04,508 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:04,522 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:04,522 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:04,522 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:04,522 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 13:32:04,522 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:04,523 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 13:32:04,523 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:04,526 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:04,540 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (69)] Ended with exit code 0 [2024-11-13 13:32:04,540 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:04,540 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:04,542 INFO L229 MonitoredProcess]: Starting monitored process 70 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:04,543 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (70)] Waiting until timeout for monitored process [2024-11-13 13:32:04,543 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:04,556 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:04,556 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:04,556 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:04,556 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:04,556 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:04,556 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:04,556 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:04,558 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:04,570 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (70)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:04,571 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:04,571 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:04,573 INFO L229 MonitoredProcess]: Starting monitored process 71 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:04,574 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (71)] Waiting until timeout for monitored process [2024-11-13 13:32:04,574 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:04,587 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:04,587 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:04,587 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:04,587 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 13:32:04,587 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:04,588 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 13:32:04,588 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:04,593 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:04,614 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (71)] Ended with exit code 0 [2024-11-13 13:32:04,614 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:04,614 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:04,617 INFO L229 MonitoredProcess]: Starting monitored process 72 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:04,620 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (72)] Waiting until timeout for monitored process [2024-11-13 13:32:04,621 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:04,638 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:04,638 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:04,638 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:04,638 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:04,638 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:04,639 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:04,639 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:04,642 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:04,663 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (72)] Ended with exit code 0 [2024-11-13 13:32:04,665 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:04,665 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:04,667 INFO L229 MonitoredProcess]: Starting monitored process 73 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:04,669 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (73)] Waiting until timeout for monitored process [2024-11-13 13:32:04,671 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:04,688 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:04,688 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:04,689 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:04,689 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:04,689 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:04,689 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:04,690 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:04,694 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:04,716 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (73)] Ended with exit code 0 [2024-11-13 13:32:04,717 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:04,717 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:04,719 INFO L229 MonitoredProcess]: Starting monitored process 74 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:04,721 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (74)] Waiting until timeout for monitored process [2024-11-13 13:32:04,723 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:04,739 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:04,739 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:04,740 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:04,740 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:04,740 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:04,740 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:04,740 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:04,742 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:04,757 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (74)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:04,757 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:04,757 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:04,759 INFO L229 MonitoredProcess]: Starting monitored process 75 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:04,760 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (75)] Waiting until timeout for monitored process [2024-11-13 13:32:04,761 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:04,774 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:04,774 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:04,775 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:04,775 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:04,775 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:04,775 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:04,775 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:04,777 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:04,790 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (75)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:04,790 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:04,791 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:04,792 INFO L229 MonitoredProcess]: Starting monitored process 76 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:04,794 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (76)] Waiting until timeout for monitored process [2024-11-13 13:32:04,798 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:04,813 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:04,813 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:04,813 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:04,813 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 13:32:04,813 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:04,814 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 13:32:04,814 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:04,816 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:04,829 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (76)] Ended with exit code 0 [2024-11-13 13:32:04,830 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:04,830 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:04,831 INFO L229 MonitoredProcess]: Starting monitored process 77 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:04,832 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (77)] Waiting until timeout for monitored process [2024-11-13 13:32:04,833 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:04,846 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:04,846 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:04,846 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:04,846 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:04,846 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:04,847 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:04,847 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:04,848 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:04,860 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (77)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:04,861 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:04,861 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:04,863 INFO L229 MonitoredProcess]: Starting monitored process 78 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:04,864 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (78)] Waiting until timeout for monitored process [2024-11-13 13:32:04,864 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:04,877 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:04,877 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:04,878 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:04,878 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:04,878 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:04,878 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:04,878 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:04,880 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:04,893 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (78)] Ended with exit code 0 [2024-11-13 13:32:04,893 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:04,893 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:04,895 INFO L229 MonitoredProcess]: Starting monitored process 79 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:04,896 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (79)] Waiting until timeout for monitored process [2024-11-13 13:32:04,896 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:04,909 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:04,910 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:04,910 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:04,910 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:04,910 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:04,910 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:04,910 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:04,912 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:04,926 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (79)] Ended with exit code 0 [2024-11-13 13:32:04,926 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:04,926 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:04,928 INFO L229 MonitoredProcess]: Starting monitored process 80 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:04,929 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (80)] Waiting until timeout for monitored process [2024-11-13 13:32:04,930 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:04,942 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:04,942 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:04,942 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:04,943 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:04,943 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:04,943 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:04,943 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:04,945 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:04,957 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (80)] Ended with exit code 0 [2024-11-13 13:32:04,958 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:04,958 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:04,960 INFO L229 MonitoredProcess]: Starting monitored process 81 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:04,961 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (81)] Waiting until timeout for monitored process [2024-11-13 13:32:04,961 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:04,974 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:04,974 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:04,974 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:04,974 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:04,974 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:04,975 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:04,975 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:04,978 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:04,999 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (81)] Ended with exit code 0 [2024-11-13 13:32:04,999 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:04,999 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:05,001 INFO L229 MonitoredProcess]: Starting monitored process 82 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:05,002 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (82)] Waiting until timeout for monitored process [2024-11-13 13:32:05,005 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:05,019 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:05,019 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:05,019 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:05,019 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:05,019 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:05,020 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:05,020 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:05,023 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:05,036 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (82)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:05,037 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:05,037 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:05,038 INFO L229 MonitoredProcess]: Starting monitored process 83 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:05,039 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (83)] Waiting until timeout for monitored process [2024-11-13 13:32:05,040 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:05,057 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:05,057 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:05,057 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:05,057 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:05,057 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:05,058 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:05,058 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:05,060 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:05,081 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (83)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:05,081 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:05,082 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:05,084 INFO L229 MonitoredProcess]: Starting monitored process 84 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:05,086 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (84)] Waiting until timeout for monitored process [2024-11-13 13:32:05,087 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:05,104 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:05,104 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:05,105 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:05,105 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 13:32:05,105 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:05,105 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 13:32:05,106 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:05,110 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:05,131 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (84)] Ended with exit code 0 [2024-11-13 13:32:05,132 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:05,132 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:05,134 INFO L229 MonitoredProcess]: Starting monitored process 85 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:05,136 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (85)] Waiting until timeout for monitored process [2024-11-13 13:32:05,137 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:05,151 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:05,151 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:05,151 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:05,151 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:05,151 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:05,152 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:05,152 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:05,153 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:05,167 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (85)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:05,167 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:05,167 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:05,169 INFO L229 MonitoredProcess]: Starting monitored process 86 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:05,170 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (86)] Waiting until timeout for monitored process [2024-11-13 13:32:05,171 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:05,184 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:05,184 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:05,184 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:05,184 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:05,185 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:05,185 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:05,185 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:05,187 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:05,201 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (86)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:05,201 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:05,201 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:05,203 INFO L229 MonitoredProcess]: Starting monitored process 87 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:05,204 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (87)] Waiting until timeout for monitored process [2024-11-13 13:32:05,205 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:05,219 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:05,219 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:05,219 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:05,219 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:05,219 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:05,220 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:05,220 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:05,221 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:05,235 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (87)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:05,235 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:05,236 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:05,237 INFO L229 MonitoredProcess]: Starting monitored process 88 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:05,239 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (88)] Waiting until timeout for monitored process [2024-11-13 13:32:05,239 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:05,252 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:05,252 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:05,253 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:05,253 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 13:32:05,253 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:05,253 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 13:32:05,254 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:05,256 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:05,269 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (88)] Ended with exit code 0 [2024-11-13 13:32:05,269 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:05,269 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:05,271 INFO L229 MonitoredProcess]: Starting monitored process 89 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:05,272 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (89)] Waiting until timeout for monitored process [2024-11-13 13:32:05,273 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:05,286 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:05,286 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:05,286 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:05,286 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:05,286 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:05,287 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:05,287 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:05,289 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:05,304 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (89)] Ended with exit code 0 [2024-11-13 13:32:05,305 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:05,305 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:05,306 INFO L229 MonitoredProcess]: Starting monitored process 90 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:05,308 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (90)] Waiting until timeout for monitored process [2024-11-13 13:32:05,308 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:05,322 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:05,322 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:05,322 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:05,322 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:05,322 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:05,322 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:05,322 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:05,324 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:05,337 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (90)] Ended with exit code 0 [2024-11-13 13:32:05,337 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:05,337 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:05,339 INFO L229 MonitoredProcess]: Starting monitored process 91 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:05,340 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (91)] Waiting until timeout for monitored process [2024-11-13 13:32:05,341 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:05,354 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:05,354 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:05,354 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:05,354 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:05,354 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:05,355 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:05,355 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:05,356 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:05,370 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (91)] Ended with exit code 0 [2024-11-13 13:32:05,371 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:05,371 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:05,372 INFO L229 MonitoredProcess]: Starting monitored process 92 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:05,373 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (92)] Waiting until timeout for monitored process [2024-11-13 13:32:05,374 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:05,387 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:05,387 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:05,387 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:05,387 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:05,387 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:05,387 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:05,387 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:05,389 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:05,403 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (92)] Ended with exit code 0 [2024-11-13 13:32:05,403 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:05,403 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:05,405 INFO L229 MonitoredProcess]: Starting monitored process 93 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:05,406 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (93)] Waiting until timeout for monitored process [2024-11-13 13:32:05,407 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:05,420 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:05,420 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:05,420 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:05,420 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 13:32:05,420 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:05,421 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 13:32:05,421 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:05,424 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:05,442 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (93)] Ended with exit code 0 [2024-11-13 13:32:05,443 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:05,443 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:05,444 INFO L229 MonitoredProcess]: Starting monitored process 94 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:05,446 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (94)] Waiting until timeout for monitored process [2024-11-13 13:32:05,446 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:05,460 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:05,460 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:05,460 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:05,460 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:05,460 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:05,460 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:05,460 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:05,462 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:05,476 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (94)] Ended with exit code 0 [2024-11-13 13:32:05,476 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:05,476 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:05,478 INFO L229 MonitoredProcess]: Starting monitored process 95 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:05,479 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (95)] Waiting until timeout for monitored process [2024-11-13 13:32:05,480 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:05,493 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:05,493 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:05,493 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:05,493 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 13:32:05,493 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:05,494 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 13:32:05,494 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:05,496 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:05,509 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (95)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:05,510 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:05,510 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:05,512 INFO L229 MonitoredProcess]: Starting monitored process 96 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:05,513 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (96)] Waiting until timeout for monitored process [2024-11-13 13:32:05,513 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:05,527 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:05,527 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:05,527 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:05,527 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:05,527 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:05,528 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:05,528 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:05,530 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:32:05,549 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (96)] Ended with exit code 0 [2024-11-13 13:32:05,549 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:05,549 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:05,551 INFO L229 MonitoredProcess]: Starting monitored process 97 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:05,552 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (97)] Waiting until timeout for monitored process [2024-11-13 13:32:05,553 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:32:05,567 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:32:05,567 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:32:05,567 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:32:05,567 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:32:05,567 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:32:05,568 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:32:05,568 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:32:05,570 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-13 13:32:05,573 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-13 13:32:05,573 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-13 13:32:05,573 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:32:05,573 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:05,575 INFO L229 MonitoredProcess]: Starting monitored process 98 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:32:05,576 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (98)] Waiting until timeout for monitored process [2024-11-13 13:32:05,577 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-13 13:32:05,577 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-13 13:32:05,577 INFO L474 LassoAnalysis]: Proved termination. [2024-11-13 13:32:05,577 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_1~0) = -1*~E_1~0 + 1 Supporting invariants [] [2024-11-13 13:32:05,590 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (97)] Ended with exit code 0 [2024-11-13 13:32:05,591 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-13 13:32:05,612 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:05,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:32:05,654 INFO L255 TraceCheckSpWp]: Trace formula consists of 144 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-13 13:32:05,656 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:32:05,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:32:05,812 INFO L255 TraceCheckSpWp]: Trace formula consists of 154 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-13 13:32:05,814 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:32:06,103 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-11-13 13:32:06,134 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-13 13:32:06,134 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 4714 states and 6108 transitions. cyclomatic complexity: 1406 Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:32:06,176 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (98)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:06,355 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 4714 states and 6108 transitions. cyclomatic complexity: 1406. Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 13261 states and 17329 transitions. Complement of second has 5 states. [2024-11-13 13:32:06,356 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-13 13:32:06,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:32:06,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 369 transitions. [2024-11-13 13:32:06,358 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 369 transitions. Stem has 50 letters. Loop has 82 letters. [2024-11-13 13:32:06,359 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:32:06,360 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 369 transitions. Stem has 132 letters. Loop has 82 letters. [2024-11-13 13:32:06,361 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:32:06,361 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 369 transitions. Stem has 50 letters. Loop has 164 letters. [2024-11-13 13:32:06,363 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:32:06,363 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13261 states and 17329 transitions. [2024-11-13 13:32:06,482 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6024 [2024-11-13 13:32:06,558 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13261 states to 13237 states and 17293 transitions. [2024-11-13 13:32:06,559 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6167 [2024-11-13 13:32:06,568 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6208 [2024-11-13 13:32:06,568 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13237 states and 17293 transitions. [2024-11-13 13:32:06,568 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:32:06,568 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13237 states and 17293 transitions. [2024-11-13 13:32:06,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13237 states and 17293 transitions. [2024-11-13 13:32:06,776 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13237 to 13172. [2024-11-13 13:32:06,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13172 states, 13172 states have (on average 1.3064075311266323) internal successors, (17208), 13171 states have internal predecessors, (17208), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:32:06,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13172 states to 13172 states and 17208 transitions. [2024-11-13 13:32:06,854 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13172 states and 17208 transitions. [2024-11-13 13:32:06,854 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:32:06,855 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:32:06,855 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:32:06,855 INFO L87 Difference]: Start difference. First operand 13172 states and 17208 transitions. Second operand has 3 states, 3 states have (on average 44.0) internal successors, (132), 2 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:32:06,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:32:06,929 INFO L93 Difference]: Finished difference Result 6592 states and 8439 transitions. [2024-11-13 13:32:06,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6592 states and 8439 transitions. [2024-11-13 13:32:06,959 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3968 [2024-11-13 13:32:06,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6592 states to 5874 states and 7534 transitions. [2024-11-13 13:32:06,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4067 [2024-11-13 13:32:06,991 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4067 [2024-11-13 13:32:06,991 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5874 states and 7534 transitions. [2024-11-13 13:32:06,992 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:32:06,992 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5874 states and 7534 transitions. [2024-11-13 13:32:06,999 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5874 states and 7534 transitions. [2024-11-13 13:32:07,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5874 to 5466. [2024-11-13 13:32:07,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5466 states, 5466 states have (on average 1.2905232345407978) internal successors, (7054), 5465 states have internal predecessors, (7054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:32:07,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5466 states to 5466 states and 7054 transitions. [2024-11-13 13:32:07,105 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5466 states and 7054 transitions. [2024-11-13 13:32:07,105 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:32:07,106 INFO L424 stractBuchiCegarLoop]: Abstraction has 5466 states and 7054 transitions. [2024-11-13 13:32:07,106 INFO L331 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-13 13:32:07,106 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5466 states and 7054 transitions. [2024-11-13 13:32:07,123 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3696 [2024-11-13 13:32:07,125 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:32:07,125 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:32:07,126 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:32:07,126 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:32:07,127 INFO L745 eck$LassoCheckResult]: Stem: 84885#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 84886#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 84909#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 84904#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 84851#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 84852#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 84475#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 84476#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 84934#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 84421#L418 assume !(0 == ~M_E~0); 84422#L418-2 assume !(0 == ~T1_E~0); 84850#L423-1 assume !(0 == ~T2_E~0); 84945#L428-1 assume !(0 == ~T3_E~0); 84943#L433-1 assume !(0 == ~E_1~0); 84917#L438-1 assume !(0 == ~E_2~0); 84765#L443-1 assume !(0 == ~E_3~0); 84750#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84672#L197 assume !(1 == ~m_pc~0); 84673#L197-2 is_master_triggered_~__retres1~0#1 := 0; 84995#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84839#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 84840#L510 assume !(0 != activate_threads_~tmp~1#1); 84383#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84384#L216 assume !(1 == ~t1_pc~0); 84473#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 84474#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84524#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 84391#L518 assume !(0 != activate_threads_~tmp___0~0#1); 84392#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84783#L235 assume !(1 == ~t2_pc~0); 84928#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 84929#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85021#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 84983#L526 assume !(0 != activate_threads_~tmp___1~0#1); 84984#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 84615#L254 assume !(1 == ~t3_pc~0); 84481#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 84482#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 84409#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 84410#L534 assume !(0 != activate_threads_~tmp___2~0#1); 84630#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84371#L461 assume !(1 == ~M_E~0); 84372#L461-2 assume !(1 == ~T1_E~0); 84477#L466-1 assume !(1 == ~T2_E~0); 84958#L471-1 assume !(1 == ~T3_E~0); 84529#L476-1 assume !(1 == ~E_1~0); 84530#L481-1 assume !(1 == ~E_2~0); 84815#L486-1 assume !(1 == ~E_3~0); 84567#L491-1 assume { :end_inline_reset_delta_events } true; 84568#L652-2 assume !false; 86216#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 86738#L393-1 [2024-11-13 13:32:07,127 INFO L747 eck$LassoCheckResult]: Loop: 86738#L393-1 assume !false; 86734#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 86731#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 86727#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 86728#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 88548#L346 assume 0 != eval_~tmp~0#1; 88546#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 88543#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 88541#L354-2 havoc eval_~tmp_ndt_1~0#1; 88538#L351-1 assume !(0 == ~t1_st~0); 86750#L365-1 assume !(0 == ~t2_st~0); 86742#L379-1 assume !(0 == ~t3_st~0); 86738#L393-1 [2024-11-13 13:32:07,128 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:07,128 INFO L85 PathProgramCache]: Analyzing trace with hash -912926956, now seen corresponding path program 1 times [2024-11-13 13:32:07,129 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:32:07,129 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1386740548] [2024-11-13 13:32:07,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:32:07,129 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:32:07,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:07,140 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:32:07,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:07,153 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:32:07,153 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:07,153 INFO L85 PathProgramCache]: Analyzing trace with hash 665623515, now seen corresponding path program 1 times [2024-11-13 13:32:07,153 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:32:07,155 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2033054772] [2024-11-13 13:32:07,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:32:07,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:32:07,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:07,159 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:32:07,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:07,163 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:32:07,163 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:07,164 INFO L85 PathProgramCache]: Analyzing trace with hash -135172498, now seen corresponding path program 1 times [2024-11-13 13:32:07,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:32:07,164 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1891589813] [2024-11-13 13:32:07,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:32:07,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:32:07,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:32:07,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:32:07,205 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:32:07,205 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1891589813] [2024-11-13 13:32:07,205 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1891589813] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:32:07,205 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:32:07,205 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:32:07,205 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1937877187] [2024-11-13 13:32:07,205 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:32:07,270 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:32:07,270 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:32:07,270 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:32:07,271 INFO L87 Difference]: Start difference. First operand 5466 states and 7054 transitions. cyclomatic complexity: 1612 Second operand has 3 states, 3 states have (on average 21.0) internal successors, (63), 3 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:32:07,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:32:07,356 INFO L93 Difference]: Finished difference Result 9490 states and 12083 transitions. [2024-11-13 13:32:07,357 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9490 states and 12083 transitions. [2024-11-13 13:32:07,454 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 5972 [2024-11-13 13:32:07,492 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9490 states to 9490 states and 12083 transitions. [2024-11-13 13:32:07,492 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6632 [2024-11-13 13:32:07,498 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6632 [2024-11-13 13:32:07,499 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9490 states and 12083 transitions. [2024-11-13 13:32:07,499 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:32:07,499 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9490 states and 12083 transitions. [2024-11-13 13:32:07,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9490 states and 12083 transitions. [2024-11-13 13:32:07,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9490 to 9094. [2024-11-13 13:32:07,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9094 states, 9094 states have (on average 1.2762260831317351) internal successors, (11606), 9093 states have internal predecessors, (11606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:32:07,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9094 states to 9094 states and 11606 transitions. [2024-11-13 13:32:07,649 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9094 states and 11606 transitions. [2024-11-13 13:32:07,650 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:32:07,650 INFO L424 stractBuchiCegarLoop]: Abstraction has 9094 states and 11606 transitions. [2024-11-13 13:32:07,650 INFO L331 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-13 13:32:07,651 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9094 states and 11606 transitions. [2024-11-13 13:32:07,678 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 5708 [2024-11-13 13:32:07,678 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:32:07,678 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:32:07,679 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:32:07,679 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:32:07,680 INFO L745 eck$LassoCheckResult]: Stem: 99853#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 99854#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 99885#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 99879#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 99826#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 99827#L281-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 99438#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 99439#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 99905#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 99383#L418 assume !(0 == ~M_E~0); 99384#L418-2 assume !(0 == ~T1_E~0); 99825#L423-1 assume !(0 == ~T2_E~0); 99918#L428-1 assume !(0 == ~T3_E~0); 99914#L433-1 assume !(0 == ~E_1~0); 99891#L438-1 assume !(0 == ~E_2~0); 99732#L443-1 assume !(0 == ~E_3~0); 99715#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 99634#L197 assume !(1 == ~m_pc~0); 99635#L197-2 is_master_triggered_~__retres1~0#1 := 0; 99972#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 99811#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 99812#L510 assume !(0 != activate_threads_~tmp~1#1); 99347#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99348#L216 assume !(1 == ~t1_pc~0); 99432#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 99433#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99488#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 99349#L518 assume !(0 != activate_threads_~tmp___0~0#1); 99350#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 99747#L235 assume !(1 == ~t2_pc~0); 101098#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 101097#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 101095#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 99955#L526 assume !(0 != activate_threads_~tmp___1~0#1); 99956#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 99573#L254 assume !(1 == ~t3_pc~0); 99574#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 99618#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 99619#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 99687#L534 assume !(0 != activate_threads_~tmp___2~0#1); 99688#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 99335#L461 assume !(1 == ~M_E~0); 99336#L461-2 assume !(1 == ~T1_E~0); 99931#L466-1 assume !(1 == ~T2_E~0); 99932#L471-1 assume !(1 == ~T3_E~0); 99489#L476-1 assume !(1 == ~E_1~0); 99490#L481-1 assume !(1 == ~E_2~0); 99782#L486-1 assume !(1 == ~E_3~0); 99783#L491-1 assume { :end_inline_reset_delta_events } true; 101040#L652-2 assume !false; 101041#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 105755#L393-1 [2024-11-13 13:32:07,680 INFO L747 eck$LassoCheckResult]: Loop: 105755#L393-1 assume !false; 105775#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 105774#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 105773#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 105772#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 105769#L346 assume 0 != eval_~tmp~0#1; 105767#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 105764#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 105763#L354-2 havoc eval_~tmp_ndt_1~0#1; 105759#L351-1 assume !(0 == ~t1_st~0); 105757#L365-1 assume !(0 == ~t2_st~0); 105754#L379-1 assume !(0 == ~t3_st~0); 105755#L393-1 [2024-11-13 13:32:07,681 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:07,681 INFO L85 PathProgramCache]: Analyzing trace with hash 1015345746, now seen corresponding path program 1 times [2024-11-13 13:32:07,681 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:32:07,681 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221247225] [2024-11-13 13:32:07,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:32:07,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:32:07,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:32:07,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:32:07,709 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:32:07,709 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1221247225] [2024-11-13 13:32:07,709 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1221247225] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:32:07,709 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:32:07,709 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:32:07,710 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [984097330] [2024-11-13 13:32:07,710 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:32:07,710 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:32:07,711 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:07,711 INFO L85 PathProgramCache]: Analyzing trace with hash 665623515, now seen corresponding path program 2 times [2024-11-13 13:32:07,711 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:32:07,712 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [461491227] [2024-11-13 13:32:07,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:32:07,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:32:07,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:07,717 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:32:07,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:07,722 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:32:07,781 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:32:07,782 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:32:07,782 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:32:07,783 INFO L87 Difference]: Start difference. First operand 9094 states and 11606 transitions. cyclomatic complexity: 2552 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:32:07,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:32:07,812 INFO L93 Difference]: Finished difference Result 6106 states and 7808 transitions. [2024-11-13 13:32:07,812 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6106 states and 7808 transitions. [2024-11-13 13:32:07,835 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4147 [2024-11-13 13:32:07,861 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6106 states to 6106 states and 7808 transitions. [2024-11-13 13:32:07,861 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4325 [2024-11-13 13:32:07,867 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4325 [2024-11-13 13:32:07,867 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6106 states and 7808 transitions. [2024-11-13 13:32:07,867 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:32:07,868 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6106 states and 7808 transitions. [2024-11-13 13:32:07,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6106 states and 7808 transitions. [2024-11-13 13:32:07,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6106 to 6106. [2024-11-13 13:32:07,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6106 states, 6106 states have (on average 1.2787422207664592) internal successors, (7808), 6105 states have internal predecessors, (7808), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:32:07,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6106 states to 6106 states and 7808 transitions. [2024-11-13 13:32:07,967 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6106 states and 7808 transitions. [2024-11-13 13:32:07,968 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:32:07,968 INFO L424 stractBuchiCegarLoop]: Abstraction has 6106 states and 7808 transitions. [2024-11-13 13:32:07,968 INFO L331 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-13 13:32:07,968 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6106 states and 7808 transitions. [2024-11-13 13:32:07,987 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4147 [2024-11-13 13:32:07,987 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:32:07,987 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:32:07,988 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:32:07,988 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:32:07,988 INFO L745 eck$LassoCheckResult]: Stem: 115052#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 115053#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 115080#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 115075#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 115025#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 115026#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 114645#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 114646#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 115100#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 114589#L418 assume !(0 == ~M_E~0); 114590#L418-2 assume !(0 == ~T1_E~0); 115024#L423-1 assume !(0 == ~T2_E~0); 115111#L428-1 assume !(0 == ~T3_E~0); 115108#L433-1 assume !(0 == ~E_1~0); 115085#L438-1 assume !(0 == ~E_2~0); 114932#L443-1 assume !(0 == ~E_3~0); 114918#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 114843#L197 assume !(1 == ~m_pc~0); 114844#L197-2 is_master_triggered_~__retres1~0#1 := 0; 115155#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115010#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 115011#L510 assume !(0 != activate_threads_~tmp~1#1); 114553#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 114554#L216 assume !(1 == ~t1_pc~0); 114639#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 114640#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 114693#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 114555#L518 assume !(0 != activate_threads_~tmp___0~0#1); 114556#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 114949#L235 assume !(1 == ~t2_pc~0); 115096#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 114811#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 114812#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 115145#L526 assume !(0 != activate_threads_~tmp___1~0#1); 115146#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 114779#L254 assume !(1 == ~t3_pc~0); 114650#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 114651#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 114575#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 114576#L534 assume !(0 != activate_threads_~tmp___2~0#1); 114800#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 114541#L461 assume !(1 == ~M_E~0); 114542#L461-2 assume !(1 == ~T1_E~0); 114647#L466-1 assume !(1 == ~T2_E~0); 115120#L471-1 assume !(1 == ~T3_E~0); 114694#L476-1 assume !(1 == ~E_1~0); 114695#L481-1 assume !(1 == ~E_2~0); 114986#L486-1 assume !(1 == ~E_3~0); 114727#L491-1 assume { :end_inline_reset_delta_events } true; 114728#L652-2 assume !false; 116500#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 118747#L393-1 [2024-11-13 13:32:07,988 INFO L747 eck$LassoCheckResult]: Loop: 118747#L393-1 assume !false; 118772#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 118770#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 118768#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 118767#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 118766#L346 assume 0 != eval_~tmp~0#1; 118763#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 118760#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 118758#L354-2 havoc eval_~tmp_ndt_1~0#1; 118757#L351-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 118753#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 118752#L368-2 havoc eval_~tmp_ndt_2~0#1; 118750#L365-1 assume !(0 == ~t2_st~0); 118746#L379-1 assume !(0 == ~t3_st~0); 118747#L393-1 [2024-11-13 13:32:07,989 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:07,989 INFO L85 PathProgramCache]: Analyzing trace with hash -912926956, now seen corresponding path program 2 times [2024-11-13 13:32:07,993 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:32:07,993 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [468858149] [2024-11-13 13:32:07,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:32:07,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:32:08,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:08,003 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:32:08,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:08,017 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:32:08,018 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:08,018 INFO L85 PathProgramCache]: Analyzing trace with hash -411205478, now seen corresponding path program 1 times [2024-11-13 13:32:08,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:32:08,019 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1967441106] [2024-11-13 13:32:08,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:32:08,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:32:08,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:08,023 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:32:08,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:08,027 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:32:08,029 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:08,029 INFO L85 PathProgramCache]: Analyzing trace with hash -1177027987, now seen corresponding path program 1 times [2024-11-13 13:32:08,029 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:32:08,029 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [94819550] [2024-11-13 13:32:08,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:32:08,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:32:08,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:32:08,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:32:08,077 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:32:08,078 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [94819550] [2024-11-13 13:32:08,078 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [94819550] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:32:08,078 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:32:08,078 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:32:08,078 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [479191528] [2024-11-13 13:32:08,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:32:08,146 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:32:08,147 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:32:08,147 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:32:08,148 INFO L87 Difference]: Start difference. First operand 6106 states and 7808 transitions. cyclomatic complexity: 1726 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:32:08,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:32:08,226 INFO L93 Difference]: Finished difference Result 10888 states and 13778 transitions. [2024-11-13 13:32:08,226 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10888 states and 13778 transitions. [2024-11-13 13:32:08,268 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7294 [2024-11-13 13:32:08,314 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10888 states to 10888 states and 13778 transitions. [2024-11-13 13:32:08,315 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7595 [2024-11-13 13:32:08,324 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7595 [2024-11-13 13:32:08,324 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10888 states and 13778 transitions. [2024-11-13 13:32:08,325 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:32:08,326 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10888 states and 13778 transitions. [2024-11-13 13:32:08,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10888 states and 13778 transitions. [2024-11-13 13:32:08,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10888 to 10672. [2024-11-13 13:32:08,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10672 states, 10672 states have (on average 1.2682721139430284) internal successors, (13535), 10671 states have internal predecessors, (13535), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:32:08,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10672 states to 10672 states and 13535 transitions. [2024-11-13 13:32:08,561 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10672 states and 13535 transitions. [2024-11-13 13:32:08,562 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:32:08,562 INFO L424 stractBuchiCegarLoop]: Abstraction has 10672 states and 13535 transitions. [2024-11-13 13:32:08,562 INFO L331 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-13 13:32:08,562 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10672 states and 13535 transitions. [2024-11-13 13:32:08,594 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7078 [2024-11-13 13:32:08,594 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:32:08,594 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:32:08,595 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:32:08,595 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:32:08,596 INFO L745 eck$LassoCheckResult]: Stem: 132068#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 132069#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 132092#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 132088#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 132039#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 132040#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 131647#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 131648#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 132113#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 131589#L418 assume !(0 == ~M_E~0); 131590#L418-2 assume !(0 == ~T1_E~0); 132038#L423-1 assume !(0 == ~T2_E~0); 132124#L428-1 assume !(0 == ~T3_E~0); 132121#L433-1 assume !(0 == ~E_1~0); 132099#L438-1 assume !(0 == ~E_2~0); 131946#L443-1 assume !(0 == ~E_3~0); 131926#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 131846#L197 assume !(1 == ~m_pc~0); 131847#L197-2 is_master_triggered_~__retres1~0#1 := 0; 132189#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 132024#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 132025#L510 assume !(0 != activate_threads_~tmp~1#1); 131555#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 131556#L216 assume !(1 == ~t1_pc~0); 131641#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 131642#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 131696#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 131557#L518 assume !(0 != activate_threads_~tmp___0~0#1); 131558#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 131967#L235 assume !(1 == ~t2_pc~0); 132109#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 131816#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131817#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 132172#L526 assume !(0 != activate_threads_~tmp___1~0#1); 132173#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 131782#L254 assume !(1 == ~t3_pc~0); 131654#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 131655#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 131575#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 131576#L534 assume !(0 != activate_threads_~tmp___2~0#1); 131802#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131543#L461 assume !(1 == ~M_E~0); 131544#L461-2 assume !(1 == ~T1_E~0); 131649#L466-1 assume !(1 == ~T2_E~0); 132141#L471-1 assume !(1 == ~T3_E~0); 131697#L476-1 assume !(1 == ~E_1~0); 131698#L481-1 assume !(1 == ~E_2~0); 132001#L486-1 assume !(1 == ~E_3~0); 131731#L491-1 assume { :end_inline_reset_delta_events } true; 131732#L652-2 assume !false; 133702#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 140161#L393-1 [2024-11-13 13:32:08,596 INFO L747 eck$LassoCheckResult]: Loop: 140161#L393-1 assume !false; 140159#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 140156#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 140154#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 140152#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 140150#L346 assume 0 != eval_~tmp~0#1; 140148#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 140145#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 140146#L354-2 havoc eval_~tmp_ndt_1~0#1; 140214#L351-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 140209#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 140204#L368-2 havoc eval_~tmp_ndt_2~0#1; 140173#L365-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 140170#L382 assume !(0 != eval_~tmp_ndt_3~0#1); 140168#L382-2 havoc eval_~tmp_ndt_3~0#1; 140164#L379-1 assume !(0 == ~t3_st~0); 140161#L393-1 [2024-11-13 13:32:08,596 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:08,597 INFO L85 PathProgramCache]: Analyzing trace with hash -912926956, now seen corresponding path program 3 times [2024-11-13 13:32:08,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:32:08,597 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1845243381] [2024-11-13 13:32:08,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:32:08,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:32:08,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:08,606 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:32:08,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:08,617 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:32:08,617 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:08,618 INFO L85 PathProgramCache]: Analyzing trace with hash -35402085, now seen corresponding path program 1 times [2024-11-13 13:32:08,618 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:32:08,618 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1195814384] [2024-11-13 13:32:08,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:32:08,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:32:08,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:08,622 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:32:08,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:08,630 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:32:08,630 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:08,630 INFO L85 PathProgramCache]: Analyzing trace with hash -1551425618, now seen corresponding path program 1 times [2024-11-13 13:32:08,630 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:32:08,630 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [683316917] [2024-11-13 13:32:08,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:32:08,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:32:08,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:32:08,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:32:08,681 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:32:08,681 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [683316917] [2024-11-13 13:32:08,681 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [683316917] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:32:08,681 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:32:08,681 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:32:08,681 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [598792880] [2024-11-13 13:32:08,681 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:32:08,751 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:32:08,752 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:32:08,752 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:32:08,752 INFO L87 Difference]: Start difference. First operand 10672 states and 13535 transitions. cyclomatic complexity: 2887 Second operand has 3 states, 2 states have (on average 33.5) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:32:08,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:32:08,835 INFO L93 Difference]: Finished difference Result 13389 states and 16922 transitions. [2024-11-13 13:32:08,835 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13389 states and 16922 transitions. [2024-11-13 13:32:08,891 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8918 [2024-11-13 13:32:08,942 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13389 states to 13389 states and 16922 transitions. [2024-11-13 13:32:08,942 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9329 [2024-11-13 13:32:08,955 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9329 [2024-11-13 13:32:08,959 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13389 states and 16922 transitions. [2024-11-13 13:32:08,959 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:32:08,959 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13389 states and 16922 transitions. [2024-11-13 13:32:08,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13389 states and 16922 transitions. [2024-11-13 13:32:09,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13389 to 13389. [2024-11-13 13:32:09,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13389 states, 13389 states have (on average 1.2638733288520427) internal successors, (16922), 13388 states have internal predecessors, (16922), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:32:09,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13389 states to 13389 states and 16922 transitions. [2024-11-13 13:32:09,137 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13389 states and 16922 transitions. [2024-11-13 13:32:09,137 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:32:09,137 INFO L424 stractBuchiCegarLoop]: Abstraction has 13389 states and 16922 transitions. [2024-11-13 13:32:09,138 INFO L331 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-13 13:32:09,138 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13389 states and 16922 transitions. [2024-11-13 13:32:09,178 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8918 [2024-11-13 13:32:09,179 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:32:09,179 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:32:09,180 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:32:09,180 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:32:09,180 INFO L745 eck$LassoCheckResult]: Stem: 156130#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 156131#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 156157#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 156151#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 156102#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 156103#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 155717#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 155718#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 156175#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 155658#L418 assume !(0 == ~M_E~0); 155659#L418-2 assume !(0 == ~T1_E~0); 156101#L423-1 assume !(0 == ~T2_E~0); 156190#L428-1 assume !(0 == ~T3_E~0); 156186#L433-1 assume !(0 == ~E_1~0); 156163#L438-1 assume !(0 == ~E_2~0); 156009#L443-1 assume !(0 == ~E_3~0); 155994#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 155913#L197 assume !(1 == ~m_pc~0); 155914#L197-2 is_master_triggered_~__retres1~0#1 := 0; 156241#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 156090#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 156091#L510 assume !(0 != activate_threads_~tmp~1#1); 155624#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 155625#L216 assume !(1 == ~t1_pc~0); 155711#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 155712#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 155766#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 155626#L518 assume !(0 != activate_threads_~tmp___0~0#1); 155627#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 156027#L235 assume !(1 == ~t2_pc~0); 156170#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 155882#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 155883#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 156225#L526 assume !(0 != activate_threads_~tmp___1~0#1); 156226#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 155852#L254 assume !(1 == ~t3_pc~0); 155724#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 155725#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 155644#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 155645#L534 assume !(0 != activate_threads_~tmp___2~0#1); 155871#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 155612#L461 assume !(1 == ~M_E~0); 155613#L461-2 assume !(1 == ~T1_E~0); 155719#L466-1 assume !(1 == ~T2_E~0); 156201#L471-1 assume !(1 == ~T3_E~0); 155767#L476-1 assume !(1 == ~E_1~0); 155768#L481-1 assume !(1 == ~E_2~0); 156065#L486-1 assume !(1 == ~E_3~0); 155800#L491-1 assume { :end_inline_reset_delta_events } true; 155801#L652-2 assume !false; 164587#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 164585#L393-1 [2024-11-13 13:32:09,182 INFO L747 eck$LassoCheckResult]: Loop: 164585#L393-1 assume !false; 164583#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 164581#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 164579#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 164577#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 164575#L346 assume 0 != eval_~tmp~0#1; 164573#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 164571#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 164570#L354-2 havoc eval_~tmp_ndt_1~0#1; 164568#L351-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 164565#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 164566#L368-2 havoc eval_~tmp_ndt_2~0#1; 164386#L365-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 164382#L382 assume !(0 != eval_~tmp_ndt_3~0#1); 164380#L382-2 havoc eval_~tmp_ndt_3~0#1; 164378#L379-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 164375#L396 assume !(0 != eval_~tmp_ndt_4~0#1); 164376#L396-2 havoc eval_~tmp_ndt_4~0#1; 164585#L393-1 [2024-11-13 13:32:09,182 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:09,183 INFO L85 PathProgramCache]: Analyzing trace with hash -912926956, now seen corresponding path program 4 times [2024-11-13 13:32:09,183 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:32:09,183 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1870106497] [2024-11-13 13:32:09,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:32:09,183 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:32:09,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:09,193 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:32:09,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:09,211 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:32:09,215 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:09,215 INFO L85 PathProgramCache]: Analyzing trace with hash 338317395, now seen corresponding path program 1 times [2024-11-13 13:32:09,215 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:32:09,215 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [173318348] [2024-11-13 13:32:09,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:32:09,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:32:09,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:09,223 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:32:09,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:09,230 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:32:09,231 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:09,231 INFO L85 PathProgramCache]: Analyzing trace with hash -566384474, now seen corresponding path program 1 times [2024-11-13 13:32:09,231 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:32:09,231 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2085361544] [2024-11-13 13:32:09,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:32:09,232 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:32:09,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:09,243 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:32:09,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:09,257 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:32:10,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:10,214 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:32:10,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:10,416 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.11 01:32:10 BoogieIcfgContainer [2024-11-13 13:32:10,416 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-13 13:32:10,416 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-13 13:32:10,416 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-13 13:32:10,417 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-13 13:32:10,418 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:31:49" (3/4) ... [2024-11-13 13:32:10,423 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-13 13:32:10,535 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/witness.graphml [2024-11-13 13:32:10,535 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-13 13:32:10,536 INFO L158 Benchmark]: Toolchain (without parser) took 22769.81ms. Allocated memory was 117.4MB in the beginning and 427.8MB in the end (delta: 310.4MB). Free memory was 94.1MB in the beginning and 271.1MB in the end (delta: -177.1MB). Peak memory consumption was 128.0MB. Max. memory is 16.1GB. [2024-11-13 13:32:10,537 INFO L158 Benchmark]: CDTParser took 0.54ms. Allocated memory is still 167.8MB. Free memory is still 104.1MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 13:32:10,537 INFO L158 Benchmark]: CACSL2BoogieTranslator took 481.26ms. Allocated memory is still 117.4MB. Free memory was 94.1MB in the beginning and 80.0MB in the end (delta: 14.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 13:32:10,538 INFO L158 Benchmark]: Boogie Procedure Inliner took 76.82ms. Allocated memory is still 117.4MB. Free memory was 80.0MB in the beginning and 76.7MB in the end (delta: 3.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 13:32:10,538 INFO L158 Benchmark]: Boogie Preprocessor took 117.22ms. Allocated memory is still 117.4MB. Free memory was 76.7MB in the beginning and 73.4MB in the end (delta: 3.3MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 13:32:10,538 INFO L158 Benchmark]: RCFGBuilder took 1168.28ms. Allocated memory is still 117.4MB. Free memory was 73.4MB in the beginning and 86.2MB in the end (delta: -12.8MB). Peak memory consumption was 49.2MB. Max. memory is 16.1GB. [2024-11-13 13:32:10,539 INFO L158 Benchmark]: BuchiAutomizer took 20800.46ms. Allocated memory was 117.4MB in the beginning and 427.8MB in the end (delta: 310.4MB). Free memory was 86.2MB in the beginning and 279.4MB in the end (delta: -193.3MB). Peak memory consumption was 114.0MB. Max. memory is 16.1GB. [2024-11-13 13:32:10,539 INFO L158 Benchmark]: Witness Printer took 119.06ms. Allocated memory is still 427.8MB. Free memory was 279.4MB in the beginning and 271.1MB in the end (delta: 8.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 13:32:10,541 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.54ms. Allocated memory is still 167.8MB. Free memory is still 104.1MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 481.26ms. Allocated memory is still 117.4MB. Free memory was 94.1MB in the beginning and 80.0MB in the end (delta: 14.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 76.82ms. Allocated memory is still 117.4MB. Free memory was 80.0MB in the beginning and 76.7MB in the end (delta: 3.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 117.22ms. Allocated memory is still 117.4MB. Free memory was 76.7MB in the beginning and 73.4MB in the end (delta: 3.3MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 1168.28ms. Allocated memory is still 117.4MB. Free memory was 73.4MB in the beginning and 86.2MB in the end (delta: -12.8MB). Peak memory consumption was 49.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 20800.46ms. Allocated memory was 117.4MB in the beginning and 427.8MB in the end (delta: 310.4MB). Free memory was 86.2MB in the beginning and 279.4MB in the end (delta: -193.3MB). Peak memory consumption was 114.0MB. Max. memory is 16.1GB. * Witness Printer took 119.06ms. Allocated memory is still 427.8MB. Free memory was 279.4MB in the beginning and 271.1MB in the end (delta: 8.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 24 terminating modules (22 trivial, 2 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -1 * E_3) + 1) and consists of 3 locations. One deterministic module has affine ranking function (((long long) -1 * E_1) + 1) and consists of 3 locations. 22 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 13389 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 20.5s and 23 iterations. TraceHistogramMax:2. Analysis of lassos took 13.5s. Construction of modules took 1.0s. Büchi inclusion checks took 4.7s. Highest rank in rank-based complementation 3. Minimization of det autom 16. Minimization of nondet autom 8. Automata minimization 1.8s AutomataMinimizationTime, 24 MinimizatonAttempts, 2499 StatesRemovedByMinimization, 11 NontrivialMinimizations. Non-live state removal took 1.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [2, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 6/6 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 7027 SdHoareTripleChecker+Valid, 1.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 7025 mSDsluCounter, 21014 SdHoareTripleChecker+Invalid, 1.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 10416 mSDsCounter, 202 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 763 IncrementalHoareTripleChecker+Invalid, 965 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 202 mSolverCounterUnsat, 10598 mSDtfsCounter, 763 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI6 SFLT0 conc3 concLT2 SILN1 SILU0 SILI10 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital86 mio100 ax100 hnf100 lsp11 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq179 hnf100 smp100 dnf166 smp60 tf111 neg100 sie108 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 30ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 44 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 2 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 1.3s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 341]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int M_E = 2; [L38] int T1_E = 2; [L39] int T2_E = 2; [L40] int T3_E = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0] [L697] int __retres1 ; [L701] CALL init_model() [L610] m_i = 1 [L611] t1_i = 1 [L612] t2_i = 1 [L613] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L701] RET init_model() [L702] CALL start_simulation() [L638] int kernel_st ; [L639] int tmp ; [L640] int tmp___0 ; [L644] kernel_st = 0 [L645] FCALL update_channels() [L646] CALL init_threads() [L281] COND TRUE m_i == 1 [L282] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t1_i == 1 [L287] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L291] COND TRUE t2_i == 1 [L292] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L296] COND TRUE t3_i == 1 [L297] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L646] RET init_threads() [L647] CALL fire_delta_events() [L418] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L443] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L448] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L647] RET fire_delta_events() [L648] CALL activate_threads() [L501] int tmp ; [L502] int tmp___0 ; [L503] int tmp___1 ; [L504] int tmp___2 ; [L508] CALL, EXPR is_master_triggered() [L194] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L197] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L207] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L209] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L508] RET, EXPR is_master_triggered() [L508] tmp = is_master_triggered() [L510] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] CALL, EXPR is_transmit1_triggered() [L213] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L216] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L226] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L228] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] RET, EXPR is_transmit1_triggered() [L516] tmp___0 = is_transmit1_triggered() [L518] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] CALL, EXPR is_transmit2_triggered() [L232] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L235] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L245] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L247] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] RET, EXPR is_transmit2_triggered() [L524] tmp___1 = is_transmit2_triggered() [L526] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] CALL, EXPR is_transmit3_triggered() [L251] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L254] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L264] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L266] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] RET, EXPR is_transmit3_triggered() [L532] tmp___2 = is_transmit3_triggered() [L534] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L648] RET activate_threads() [L649] CALL reset_delta_events() [L461] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L486] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L491] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L649] RET reset_delta_events() [L652] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L655] kernel_st = 1 [L656] CALL eval() [L337] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] Loop: [L341] COND TRUE 1 [L344] CALL, EXPR exists_runnable_thread() [L306] int __retres1 ; [L309] COND TRUE m_st == 0 [L310] __retres1 = 1 [L332] return (__retres1); [L344] RET, EXPR exists_runnable_thread() [L344] tmp = exists_runnable_thread() [L346] COND TRUE \read(tmp) [L351] COND TRUE m_st == 0 [L352] int tmp_ndt_1; [L353] tmp_ndt_1 = __VERIFIER_nondet_int() [L354] COND FALSE !(\read(tmp_ndt_1)) [L365] COND TRUE t1_st == 0 [L366] int tmp_ndt_2; [L367] tmp_ndt_2 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp_ndt_2)) [L379] COND TRUE t2_st == 0 [L380] int tmp_ndt_3; [L381] tmp_ndt_3 = __VERIFIER_nondet_int() [L382] COND FALSE !(\read(tmp_ndt_3)) [L393] COND TRUE t3_st == 0 [L394] int tmp_ndt_4; [L395] tmp_ndt_4 = __VERIFIER_nondet_int() [L396] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 341]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int M_E = 2; [L38] int T1_E = 2; [L39] int T2_E = 2; [L40] int T3_E = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0] [L697] int __retres1 ; [L701] CALL init_model() [L610] m_i = 1 [L611] t1_i = 1 [L612] t2_i = 1 [L613] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L701] RET init_model() [L702] CALL start_simulation() [L638] int kernel_st ; [L639] int tmp ; [L640] int tmp___0 ; [L644] kernel_st = 0 [L645] FCALL update_channels() [L646] CALL init_threads() [L281] COND TRUE m_i == 1 [L282] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t1_i == 1 [L287] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L291] COND TRUE t2_i == 1 [L292] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L296] COND TRUE t3_i == 1 [L297] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L646] RET init_threads() [L647] CALL fire_delta_events() [L418] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L443] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L448] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L647] RET fire_delta_events() [L648] CALL activate_threads() [L501] int tmp ; [L502] int tmp___0 ; [L503] int tmp___1 ; [L504] int tmp___2 ; [L508] CALL, EXPR is_master_triggered() [L194] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L197] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L207] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L209] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L508] RET, EXPR is_master_triggered() [L508] tmp = is_master_triggered() [L510] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] CALL, EXPR is_transmit1_triggered() [L213] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L216] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L226] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L228] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] RET, EXPR is_transmit1_triggered() [L516] tmp___0 = is_transmit1_triggered() [L518] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] CALL, EXPR is_transmit2_triggered() [L232] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L235] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L245] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L247] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] RET, EXPR is_transmit2_triggered() [L524] tmp___1 = is_transmit2_triggered() [L526] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] CALL, EXPR is_transmit3_triggered() [L251] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L254] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L264] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L266] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] RET, EXPR is_transmit3_triggered() [L532] tmp___2 = is_transmit3_triggered() [L534] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L648] RET activate_threads() [L649] CALL reset_delta_events() [L461] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L486] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L491] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L649] RET reset_delta_events() [L652] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L655] kernel_st = 1 [L656] CALL eval() [L337] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] Loop: [L341] COND TRUE 1 [L344] CALL, EXPR exists_runnable_thread() [L306] int __retres1 ; [L309] COND TRUE m_st == 0 [L310] __retres1 = 1 [L332] return (__retres1); [L344] RET, EXPR exists_runnable_thread() [L344] tmp = exists_runnable_thread() [L346] COND TRUE \read(tmp) [L351] COND TRUE m_st == 0 [L352] int tmp_ndt_1; [L353] tmp_ndt_1 = __VERIFIER_nondet_int() [L354] COND FALSE !(\read(tmp_ndt_1)) [L365] COND TRUE t1_st == 0 [L366] int tmp_ndt_2; [L367] tmp_ndt_2 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp_ndt_2)) [L379] COND TRUE t2_st == 0 [L380] int tmp_ndt_3; [L381] tmp_ndt_3 = __VERIFIER_nondet_int() [L382] COND FALSE !(\read(tmp_ndt_3)) [L393] COND TRUE t3_st == 0 [L394] int tmp_ndt_4; [L395] tmp_ndt_4 = __VERIFIER_nondet_int() [L396] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-13 13:32:10,584 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_892dcda0-8699-4133-ab41-9989374bb3e9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)