./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.04.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac588a0d-f6db-4b6d-9d9e-c3549edb2ef9/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac588a0d-f6db-4b6d-9d9e-c3549edb2ef9/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac588a0d-f6db-4b6d-9d9e-c3549edb2ef9/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac588a0d-f6db-4b6d-9d9e-c3549edb2ef9/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.04.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac588a0d-f6db-4b6d-9d9e-c3549edb2ef9/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac588a0d-f6db-4b6d-9d9e-c3549edb2ef9/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1de07d37d630bd073064bf436fb9512b72ab982b0eaf3fcb1582f689c57482fa --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 14:29:09,950 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 14:29:10,074 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac588a0d-f6db-4b6d-9d9e-c3549edb2ef9/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 14:29:10,080 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 14:29:10,081 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 14:29:10,129 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 14:29:10,132 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 14:29:10,132 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 14:29:10,133 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 14:29:10,133 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 14:29:10,134 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 14:29:10,135 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 14:29:10,135 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 14:29:10,135 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 14:29:10,135 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 14:29:10,136 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 14:29:10,138 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 14:29:10,138 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 14:29:10,138 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 14:29:10,139 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 14:29:10,139 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 14:29:10,139 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 14:29:10,139 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 14:29:10,139 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 14:29:10,139 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 14:29:10,140 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 14:29:10,140 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 14:29:10,140 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 14:29:10,140 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 14:29:10,140 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 14:29:10,140 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 14:29:10,141 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 14:29:10,141 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 14:29:10,141 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 14:29:10,141 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 14:29:10,141 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 14:29:10,141 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 14:29:10,142 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 14:29:10,142 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 14:29:10,142 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac588a0d-f6db-4b6d-9d9e-c3549edb2ef9/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1de07d37d630bd073064bf436fb9512b72ab982b0eaf3fcb1582f689c57482fa [2024-11-13 14:29:10,572 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 14:29:10,582 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 14:29:10,585 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 14:29:10,590 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 14:29:10,590 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 14:29:10,593 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac588a0d-f6db-4b6d-9d9e-c3549edb2ef9/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/transmitter.04.cil.c Unable to find full path for "g++" [2024-11-13 14:29:12,999 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 14:29:13,377 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 14:29:13,378 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac588a0d-f6db-4b6d-9d9e-c3549edb2ef9/sv-benchmarks/c/systemc/transmitter.04.cil.c [2024-11-13 14:29:13,396 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac588a0d-f6db-4b6d-9d9e-c3549edb2ef9/bin/uautomizer-verify-qhAvR1uOyd/data/a4a1a47c1/a7ddbfb6065242ed967d1b7304f3f20e/FLAG01aeeed08 [2024-11-13 14:29:13,415 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac588a0d-f6db-4b6d-9d9e-c3549edb2ef9/bin/uautomizer-verify-qhAvR1uOyd/data/a4a1a47c1/a7ddbfb6065242ed967d1b7304f3f20e [2024-11-13 14:29:13,418 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 14:29:13,420 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 14:29:13,422 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 14:29:13,422 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 14:29:13,430 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 14:29:13,431 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 02:29:13" (1/1) ... [2024-11-13 14:29:13,432 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2640164a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:29:13, skipping insertion in model container [2024-11-13 14:29:13,432 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 02:29:13" (1/1) ... [2024-11-13 14:29:13,465 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 14:29:13,805 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 14:29:13,825 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 14:29:13,882 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 14:29:13,903 INFO L204 MainTranslator]: Completed translation [2024-11-13 14:29:13,904 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:29:13 WrapperNode [2024-11-13 14:29:13,904 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 14:29:13,905 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 14:29:13,905 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 14:29:13,905 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 14:29:13,913 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:29:13" (1/1) ... [2024-11-13 14:29:13,923 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:29:13" (1/1) ... [2024-11-13 14:29:13,996 INFO L138 Inliner]: procedures = 36, calls = 43, calls flagged for inlining = 38, calls inlined = 71, statements flattened = 968 [2024-11-13 14:29:13,999 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 14:29:14,000 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 14:29:14,000 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 14:29:14,000 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 14:29:14,022 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:29:13" (1/1) ... [2024-11-13 14:29:14,023 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:29:13" (1/1) ... [2024-11-13 14:29:14,031 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:29:13" (1/1) ... [2024-11-13 14:29:14,050 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 14:29:14,050 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:29:13" (1/1) ... [2024-11-13 14:29:14,051 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:29:13" (1/1) ... [2024-11-13 14:29:14,064 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:29:13" (1/1) ... [2024-11-13 14:29:14,084 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:29:13" (1/1) ... [2024-11-13 14:29:14,088 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:29:13" (1/1) ... [2024-11-13 14:29:14,091 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:29:13" (1/1) ... [2024-11-13 14:29:14,104 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 14:29:14,105 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 14:29:14,105 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 14:29:14,105 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 14:29:14,110 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:29:13" (1/1) ... [2024-11-13 14:29:14,120 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 14:29:14,146 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac588a0d-f6db-4b6d-9d9e-c3549edb2ef9/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 14:29:14,164 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac588a0d-f6db-4b6d-9d9e-c3549edb2ef9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 14:29:14,173 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac588a0d-f6db-4b6d-9d9e-c3549edb2ef9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 14:29:14,207 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 14:29:14,207 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 14:29:14,207 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 14:29:14,208 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 14:29:14,322 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 14:29:14,324 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 14:29:15,557 INFO L? ?]: Removed 174 outVars from TransFormulas that were not future-live. [2024-11-13 14:29:15,559 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 14:29:15,602 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 14:29:15,602 INFO L316 CfgBuilder]: Removed 8 assume(true) statements. [2024-11-13 14:29:15,603 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 02:29:15 BoogieIcfgContainer [2024-11-13 14:29:15,603 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 14:29:15,604 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 14:29:15,604 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 14:29:15,611 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 14:29:15,611 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 14:29:15,612 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 02:29:13" (1/3) ... [2024-11-13 14:29:15,613 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@205ddc12 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 02:29:15, skipping insertion in model container [2024-11-13 14:29:15,613 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 14:29:15,613 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:29:13" (2/3) ... [2024-11-13 14:29:15,614 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@205ddc12 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 02:29:15, skipping insertion in model container [2024-11-13 14:29:15,614 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 14:29:15,614 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 02:29:15" (3/3) ... [2024-11-13 14:29:15,615 INFO L333 chiAutomizerObserver]: Analyzing ICFG transmitter.04.cil.c [2024-11-13 14:29:15,705 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 14:29:15,705 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 14:29:15,706 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 14:29:15,706 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 14:29:15,707 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 14:29:15,707 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 14:29:15,707 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 14:29:15,707 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 14:29:15,720 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 397 states, 396 states have (on average 1.5303030303030303) internal successors, (606), 396 states have internal predecessors, (606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:15,772 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 328 [2024-11-13 14:29:15,777 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:15,777 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:15,793 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:15,793 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:15,793 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 14:29:15,796 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 397 states, 396 states have (on average 1.5303030303030303) internal successors, (606), 396 states have internal predecessors, (606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:15,819 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 328 [2024-11-13 14:29:15,819 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:15,819 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:15,825 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:15,825 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:15,837 INFO L745 eck$LassoCheckResult]: Stem: 119#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 330#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 183#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 326#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 56#L341true assume !(1 == ~m_i~0);~m_st~0 := 2; 368#L341-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 213#L346-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 117#L351-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 22#L356-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 108#L361-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32#L502true assume !(0 == ~M_E~0); 85#L502-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 16#L507-1true assume !(0 == ~T2_E~0); 57#L512-1true assume !(0 == ~T3_E~0); 316#L517-1true assume !(0 == ~T4_E~0); 10#L522-1true assume !(0 == ~E_1~0); 281#L527-1true assume !(0 == ~E_2~0); 121#L532-1true assume !(0 == ~E_3~0); 360#L537-1true assume !(0 == ~E_4~0); 136#L542-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 116#L238true assume 1 == ~m_pc~0; 321#L239true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 192#L249true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102#is_master_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 101#L615true assume !(0 != activate_threads_~tmp~1#1); 199#L615-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91#L257true assume 1 == ~t1_pc~0; 322#L258true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 113#L268true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 189#L623true assume !(0 != activate_threads_~tmp___0~0#1); 23#L623-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 188#L276true assume !(1 == ~t2_pc~0); 283#L276-2true is_transmit2_triggered_~__retres1~2#1 := 0; 341#L287true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 187#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 345#L631true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 358#L631-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100#L295true assume 1 == ~t3_pc~0; 37#L296true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 93#L306true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 324#L639true assume !(0 != activate_threads_~tmp___2~0#1); 319#L639-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 378#L314true assume !(1 == ~t4_pc~0); 349#L314-2true is_transmit4_triggered_~__retres1~4#1 := 0; 143#L325true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 90#L647true assume !(0 != activate_threads_~tmp___3~0#1); 277#L647-2true havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 392#L555true assume !(1 == ~M_E~0); 39#L555-2true assume !(1 == ~T1_E~0); 371#L560-1true assume !(1 == ~T2_E~0); 11#L565-1true assume !(1 == ~T3_E~0); 95#L570-1true assume !(1 == ~T4_E~0); 219#L575-1true assume !(1 == ~E_1~0); 295#L580-1true assume !(1 == ~E_2~0); 129#L585-1true assume 1 == ~E_3~0;~E_3~0 := 2; 29#L590-1true assume !(1 == ~E_4~0); 26#L595-1true assume { :end_inline_reset_delta_events } true; 175#L776-2true [2024-11-13 14:29:15,841 INFO L747 eck$LassoCheckResult]: Loop: 175#L776-2true assume !false; 18#L777true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 272#L477-1true assume !true; 54#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 289#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78#L502-3true assume 0 == ~M_E~0;~M_E~0 := 1; 303#L502-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 314#L507-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 55#L512-3true assume !(0 == ~T3_E~0); 397#L517-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 48#L522-3true assume 0 == ~E_1~0;~E_1~0 := 1; 92#L527-3true assume 0 == ~E_2~0;~E_2~0 := 1; 142#L532-3true assume 0 == ~E_3~0;~E_3~0 := 1; 268#L537-3true assume 0 == ~E_4~0;~E_4~0 := 1; 60#L542-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86#L238-15true assume 1 == ~m_pc~0; 9#L239-5true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 311#L249-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50#is_master_triggered_returnLabel#6true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 227#L615-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 155#L615-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 211#L257-15true assume !(1 == ~t1_pc~0); 74#L257-17true is_transmit1_triggered_~__retres1~1#1 := 0; 338#L268-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 246#is_transmit1_triggered_returnLabel#6true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 307#L623-15true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 315#L623-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 372#L276-15true assume !(1 == ~t2_pc~0); 382#L276-17true is_transmit2_triggered_~__retres1~2#1 := 0; 248#L287-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 367#is_transmit2_triggered_returnLabel#6true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 179#L631-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 290#L631-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24#L295-15true assume !(1 == ~t3_pc~0); 172#L295-17true is_transmit3_triggered_~__retres1~3#1 := 0; 335#L306-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 343#is_transmit3_triggered_returnLabel#6true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 162#L639-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 122#L639-17true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 161#L314-15true assume 1 == ~t4_pc~0; 285#L315-5true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 181#L325-5true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 308#is_transmit4_triggered_returnLabel#6true activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 318#L647-15true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 120#L647-17true havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84#L555-3true assume 1 == ~M_E~0;~M_E~0 := 2; 195#L555-5true assume !(1 == ~T1_E~0); 42#L560-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 309#L565-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 350#L570-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 291#L575-3true assume 1 == ~E_1~0;~E_1~0 := 2; 191#L580-3true assume 1 == ~E_2~0;~E_2~0 := 2; 395#L585-3true assume 1 == ~E_3~0;~E_3~0 := 2; 234#L590-3true assume 1 == ~E_4~0;~E_4~0 := 2; 276#L595-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 163#L374-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 73#L401-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 160#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 99#L795true assume !(0 == start_simulation_~tmp~3#1); 320#L795-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 110#L374-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 273#L401-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 30#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 168#L750true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40#L757true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 299#stop_simulation_returnLabel#1true start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 280#L808true assume !(0 != start_simulation_~tmp___0~1#1); 175#L776-2true [2024-11-13 14:29:15,848 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:15,848 INFO L85 PathProgramCache]: Analyzing trace with hash 1110077256, now seen corresponding path program 1 times [2024-11-13 14:29:15,861 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:15,861 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123636697] [2024-11-13 14:29:15,861 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:15,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:15,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:16,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:16,184 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:16,184 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2123636697] [2024-11-13 14:29:16,185 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2123636697] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:16,185 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:16,186 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:29:16,189 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1450611437] [2024-11-13 14:29:16,190 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:16,196 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:29:16,197 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:16,198 INFO L85 PathProgramCache]: Analyzing trace with hash -1694563050, now seen corresponding path program 1 times [2024-11-13 14:29:16,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:16,198 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [836049367] [2024-11-13 14:29:16,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:16,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:16,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:16,291 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:16,291 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:16,291 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [836049367] [2024-11-13 14:29:16,291 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [836049367] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:16,292 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:16,292 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:29:16,292 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1752712153] [2024-11-13 14:29:16,292 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:16,293 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:29:16,294 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:29:16,330 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:29:16,331 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:29:16,335 INFO L87 Difference]: Start difference. First operand has 397 states, 396 states have (on average 1.5303030303030303) internal successors, (606), 396 states have internal predecessors, (606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:16,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:29:16,420 INFO L93 Difference]: Finished difference Result 395 states and 586 transitions. [2024-11-13 14:29:16,422 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 395 states and 586 transitions. [2024-11-13 14:29:16,438 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2024-11-13 14:29:16,454 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 395 states to 389 states and 580 transitions. [2024-11-13 14:29:16,457 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2024-11-13 14:29:16,458 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2024-11-13 14:29:16,462 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389 states and 580 transitions. [2024-11-13 14:29:16,465 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:29:16,465 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389 states and 580 transitions. [2024-11-13 14:29:16,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states and 580 transitions. [2024-11-13 14:29:16,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2024-11-13 14:29:16,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4910025706940875) internal successors, (580), 388 states have internal predecessors, (580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:16,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 580 transitions. [2024-11-13 14:29:16,529 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389 states and 580 transitions. [2024-11-13 14:29:16,532 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:29:16,538 INFO L424 stractBuchiCegarLoop]: Abstraction has 389 states and 580 transitions. [2024-11-13 14:29:16,538 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 14:29:16,538 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 580 transitions. [2024-11-13 14:29:16,542 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2024-11-13 14:29:16,542 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:16,542 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:16,545 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:16,545 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:16,545 INFO L745 eck$LassoCheckResult]: Stem: 1010#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1011#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1077#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1078#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 910#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 911#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1104#L346-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1008#L351-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 845#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 846#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 865#L502 assume !(0 == ~M_E~0); 866#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 831#L507-1 assume !(0 == ~T2_E~0); 832#L512-1 assume !(0 == ~T3_E~0); 912#L517-1 assume !(0 == ~T4_E~0); 819#L522-1 assume !(0 == ~E_1~0); 820#L527-1 assume !(0 == ~E_2~0); 1013#L532-1 assume !(0 == ~E_3~0); 1014#L537-1 assume !(0 == ~E_4~0); 1029#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1005#L238 assume 1 == ~m_pc~0; 1006#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1052#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 988#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 986#L615 assume !(0 != activate_threads_~tmp~1#1); 987#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 968#L257 assume 1 == ~t1_pc~0; 969#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1003#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 863#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 864#L623 assume !(0 != activate_threads_~tmp___0~0#1); 847#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 848#L276 assume !(1 == ~t2_pc~0); 1082#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1158#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1080#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1081#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1182#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 985#L295 assume 1 == ~t3_pc~0; 877#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 853#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 814#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 815#L639 assume !(0 != activate_threads_~tmp___2~0#1); 1176#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1177#L314 assume !(1 == ~t4_pc~0); 871#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 870#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 902#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 903#L647 assume !(0 != activate_threads_~tmp___3~0#1); 967#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1154#L555 assume !(1 == ~M_E~0); 880#L555-2 assume !(1 == ~T1_E~0); 881#L560-1 assume !(1 == ~T2_E~0); 821#L565-1 assume !(1 == ~T3_E~0); 822#L570-1 assume !(1 == ~T4_E~0); 974#L575-1 assume !(1 == ~E_1~0); 1109#L580-1 assume !(1 == ~E_2~0); 1021#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 860#L590-1 assume !(1 == ~E_4~0); 854#L595-1 assume { :end_inline_reset_delta_events } true; 855#L776-2 [2024-11-13 14:29:16,546 INFO L747 eck$LassoCheckResult]: Loop: 855#L776-2 assume !false; 836#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 837#L477-1 assume !false; 1127#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1128#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 956#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1089#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1093#L416 assume !(0 != eval_~tmp~0#1); 906#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 907#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 948#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 949#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1168#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 908#L512-3 assume !(0 == ~T3_E~0); 909#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 896#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 897#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 971#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1037#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 916#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 917#L238-15 assume 1 == ~m_pc~0; 816#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 817#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 900#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 901#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1047#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1048#L257-15 assume 1 == ~t1_pc~0; 1057#L258-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 942#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1132#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1133#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1169#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1175#L276-15 assume 1 == ~t2_pc~0; 1143#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1138#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1139#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1070#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1071#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 849#L295-15 assume !(1 == ~t3_pc~0); 850#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 1065#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1179#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1055#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1015#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1016#L314-15 assume 1 == ~t4_pc~0; 1053#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1074#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1075#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1170#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1012#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 961#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 962#L555-5 assume !(1 == ~T1_E~0); 887#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 888#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1171#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1161#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1085#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1086#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1123#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1124#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1056#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 841#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 940#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 983#L795 assume !(0 == start_simulation_~tmp~3#1); 984#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 999#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1000#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 861#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 862#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 882#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 883#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1157#L808 assume !(0 != start_simulation_~tmp___0~1#1); 855#L776-2 [2024-11-13 14:29:16,547 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:16,547 INFO L85 PathProgramCache]: Analyzing trace with hash 1069402506, now seen corresponding path program 1 times [2024-11-13 14:29:16,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:16,547 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2060360337] [2024-11-13 14:29:16,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:16,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:16,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:16,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:16,664 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:16,664 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2060360337] [2024-11-13 14:29:16,664 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2060360337] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:16,664 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:16,664 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:29:16,664 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1192910871] [2024-11-13 14:29:16,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:16,665 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:29:16,665 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:16,666 INFO L85 PathProgramCache]: Analyzing trace with hash -714465624, now seen corresponding path program 1 times [2024-11-13 14:29:16,666 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:16,666 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [109062736] [2024-11-13 14:29:16,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:16,669 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:16,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:16,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:16,857 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:16,857 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [109062736] [2024-11-13 14:29:16,857 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [109062736] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:16,857 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:16,857 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:29:16,857 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1401120471] [2024-11-13 14:29:16,858 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:16,858 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:29:16,858 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:29:16,858 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:29:16,859 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:29:16,859 INFO L87 Difference]: Start difference. First operand 389 states and 580 transitions. cyclomatic complexity: 192 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:16,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:29:16,930 INFO L93 Difference]: Finished difference Result 389 states and 579 transitions. [2024-11-13 14:29:16,930 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 389 states and 579 transitions. [2024-11-13 14:29:16,935 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2024-11-13 14:29:16,938 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 389 states to 389 states and 579 transitions. [2024-11-13 14:29:16,938 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2024-11-13 14:29:16,939 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2024-11-13 14:29:16,939 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389 states and 579 transitions. [2024-11-13 14:29:16,941 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:29:16,942 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389 states and 579 transitions. [2024-11-13 14:29:16,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states and 579 transitions. [2024-11-13 14:29:16,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2024-11-13 14:29:16,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4884318766066837) internal successors, (579), 388 states have internal predecessors, (579), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:16,971 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 579 transitions. [2024-11-13 14:29:16,971 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389 states and 579 transitions. [2024-11-13 14:29:16,972 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:29:16,973 INFO L424 stractBuchiCegarLoop]: Abstraction has 389 states and 579 transitions. [2024-11-13 14:29:16,973 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 14:29:16,973 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 579 transitions. [2024-11-13 14:29:16,979 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2024-11-13 14:29:16,979 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:16,979 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:16,985 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:16,985 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:16,986 INFO L745 eck$LassoCheckResult]: Stem: 1795#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1796#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1862#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1863#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1695#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 1696#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1889#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1793#L351-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1630#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1631#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1650#L502 assume !(0 == ~M_E~0); 1651#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1616#L507-1 assume !(0 == ~T2_E~0); 1617#L512-1 assume !(0 == ~T3_E~0); 1697#L517-1 assume !(0 == ~T4_E~0); 1604#L522-1 assume !(0 == ~E_1~0); 1605#L527-1 assume !(0 == ~E_2~0); 1798#L532-1 assume !(0 == ~E_3~0); 1799#L537-1 assume !(0 == ~E_4~0); 1814#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1790#L238 assume 1 == ~m_pc~0; 1791#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1837#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1773#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1771#L615 assume !(0 != activate_threads_~tmp~1#1); 1772#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1753#L257 assume 1 == ~t1_pc~0; 1754#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1788#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1648#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1649#L623 assume !(0 != activate_threads_~tmp___0~0#1); 1632#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1633#L276 assume !(1 == ~t2_pc~0); 1867#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1943#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1865#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1866#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1967#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1770#L295 assume 1 == ~t3_pc~0; 1662#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1638#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1599#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1600#L639 assume !(0 != activate_threads_~tmp___2~0#1); 1961#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1962#L314 assume !(1 == ~t4_pc~0); 1656#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1655#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1687#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1688#L647 assume !(0 != activate_threads_~tmp___3~0#1); 1752#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1939#L555 assume !(1 == ~M_E~0); 1665#L555-2 assume !(1 == ~T1_E~0); 1666#L560-1 assume !(1 == ~T2_E~0); 1606#L565-1 assume !(1 == ~T3_E~0); 1607#L570-1 assume !(1 == ~T4_E~0); 1759#L575-1 assume !(1 == ~E_1~0); 1894#L580-1 assume !(1 == ~E_2~0); 1806#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1645#L590-1 assume !(1 == ~E_4~0); 1639#L595-1 assume { :end_inline_reset_delta_events } true; 1640#L776-2 [2024-11-13 14:29:16,986 INFO L747 eck$LassoCheckResult]: Loop: 1640#L776-2 assume !false; 1621#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1622#L477-1 assume !false; 1912#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1913#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1741#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1874#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1878#L416 assume !(0 != eval_~tmp~0#1); 1691#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1692#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1733#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1734#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1953#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1693#L512-3 assume !(0 == ~T3_E~0); 1694#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1681#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1682#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1756#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1822#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1701#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1702#L238-15 assume 1 == ~m_pc~0; 1601#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1602#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1685#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1686#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1832#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1833#L257-15 assume 1 == ~t1_pc~0; 1842#L258-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1727#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1917#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1918#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1954#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1960#L276-15 assume 1 == ~t2_pc~0; 1928#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1923#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1924#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1855#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1856#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1634#L295-15 assume !(1 == ~t3_pc~0); 1635#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 1850#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1964#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1840#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1800#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1801#L314-15 assume 1 == ~t4_pc~0; 1838#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1859#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1860#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1955#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1797#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1746#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1747#L555-5 assume !(1 == ~T1_E~0); 1672#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1673#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1956#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1946#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1870#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1871#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1908#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1909#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1841#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1626#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1725#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1768#L795 assume !(0 == start_simulation_~tmp~3#1); 1769#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1784#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1785#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1646#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 1647#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1667#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1668#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1942#L808 assume !(0 != start_simulation_~tmp___0~1#1); 1640#L776-2 [2024-11-13 14:29:16,987 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:16,987 INFO L85 PathProgramCache]: Analyzing trace with hash 193383500, now seen corresponding path program 1 times [2024-11-13 14:29:16,987 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:16,987 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1150843280] [2024-11-13 14:29:16,987 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:16,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:17,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:17,107 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:17,111 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:17,111 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1150843280] [2024-11-13 14:29:17,112 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1150843280] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:17,112 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:17,112 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:29:17,112 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1599242838] [2024-11-13 14:29:17,112 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:17,112 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:29:17,113 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:17,113 INFO L85 PathProgramCache]: Analyzing trace with hash -714465624, now seen corresponding path program 2 times [2024-11-13 14:29:17,113 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:17,113 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [861009925] [2024-11-13 14:29:17,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:17,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:17,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:17,259 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:17,260 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:17,260 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [861009925] [2024-11-13 14:29:17,260 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [861009925] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:17,260 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:17,261 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:29:17,261 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1216862275] [2024-11-13 14:29:17,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:17,264 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:29:17,264 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:29:17,265 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:29:17,265 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:29:17,265 INFO L87 Difference]: Start difference. First operand 389 states and 579 transitions. cyclomatic complexity: 191 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:17,299 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:29:17,299 INFO L93 Difference]: Finished difference Result 389 states and 578 transitions. [2024-11-13 14:29:17,300 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 389 states and 578 transitions. [2024-11-13 14:29:17,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2024-11-13 14:29:17,316 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 389 states to 389 states and 578 transitions. [2024-11-13 14:29:17,317 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2024-11-13 14:29:17,319 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2024-11-13 14:29:17,320 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389 states and 578 transitions. [2024-11-13 14:29:17,327 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:29:17,327 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389 states and 578 transitions. [2024-11-13 14:29:17,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states and 578 transitions. [2024-11-13 14:29:17,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2024-11-13 14:29:17,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4858611825192802) internal successors, (578), 388 states have internal predecessors, (578), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:17,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 578 transitions. [2024-11-13 14:29:17,357 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389 states and 578 transitions. [2024-11-13 14:29:17,360 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:29:17,361 INFO L424 stractBuchiCegarLoop]: Abstraction has 389 states and 578 transitions. [2024-11-13 14:29:17,363 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 14:29:17,363 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 578 transitions. [2024-11-13 14:29:17,367 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2024-11-13 14:29:17,368 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:17,368 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:17,372 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:17,374 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:17,375 INFO L745 eck$LassoCheckResult]: Stem: 2580#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 2581#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2647#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2648#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2480#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 2481#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2674#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2578#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2415#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2416#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2435#L502 assume !(0 == ~M_E~0); 2436#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2404#L507-1 assume !(0 == ~T2_E~0); 2405#L512-1 assume !(0 == ~T3_E~0); 2483#L517-1 assume !(0 == ~T4_E~0); 2391#L522-1 assume !(0 == ~E_1~0); 2392#L527-1 assume !(0 == ~E_2~0); 2583#L532-1 assume !(0 == ~E_3~0); 2584#L537-1 assume !(0 == ~E_4~0); 2599#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2575#L238 assume 1 == ~m_pc~0; 2576#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2622#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2558#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2556#L615 assume !(0 != activate_threads_~tmp~1#1); 2557#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2538#L257 assume 1 == ~t1_pc~0; 2539#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2574#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2433#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2434#L623 assume !(0 != activate_threads_~tmp___0~0#1); 2417#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2418#L276 assume !(1 == ~t2_pc~0); 2652#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2728#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2650#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2651#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2753#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2555#L295 assume 1 == ~t3_pc~0; 2447#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2423#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2384#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2385#L639 assume !(0 != activate_threads_~tmp___2~0#1); 2746#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2747#L314 assume !(1 == ~t4_pc~0); 2441#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2440#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2473#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2474#L647 assume !(0 != activate_threads_~tmp___3~0#1); 2537#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2724#L555 assume !(1 == ~M_E~0); 2450#L555-2 assume !(1 == ~T1_E~0); 2451#L560-1 assume !(1 == ~T2_E~0); 2393#L565-1 assume !(1 == ~T3_E~0); 2394#L570-1 assume !(1 == ~T4_E~0); 2544#L575-1 assume !(1 == ~E_1~0); 2679#L580-1 assume !(1 == ~E_2~0); 2592#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2432#L590-1 assume !(1 == ~E_4~0); 2424#L595-1 assume { :end_inline_reset_delta_events } true; 2425#L776-2 [2024-11-13 14:29:17,375 INFO L747 eck$LassoCheckResult]: Loop: 2425#L776-2 assume !false; 2406#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2407#L477-1 assume !false; 2697#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2698#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2526#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2659#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2663#L416 assume !(0 != eval_~tmp~0#1); 2476#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2477#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2518#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2519#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2738#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2478#L512-3 assume !(0 == ~T3_E~0); 2479#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2466#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2467#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2541#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2607#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2486#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2487#L238-15 assume 1 == ~m_pc~0; 2386#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2387#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2470#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2471#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2617#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2618#L257-15 assume 1 == ~t1_pc~0; 2627#L258-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2512#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2702#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2703#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2739#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2745#L276-15 assume 1 == ~t2_pc~0; 2713#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2708#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2709#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2640#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2641#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2419#L295-15 assume !(1 == ~t3_pc~0); 2420#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 2635#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2749#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2625#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2585#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2586#L314-15 assume !(1 == ~t4_pc~0); 2624#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 2644#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2645#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2740#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2582#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2531#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2532#L555-5 assume !(1 == ~T1_E~0); 2457#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2458#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2741#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2731#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2655#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2656#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2693#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2694#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2626#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2411#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2510#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2553#L795 assume !(0 == start_simulation_~tmp~3#1); 2554#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2569#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2570#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2430#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2431#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2452#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2453#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2727#L808 assume !(0 != start_simulation_~tmp___0~1#1); 2425#L776-2 [2024-11-13 14:29:17,376 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:17,376 INFO L85 PathProgramCache]: Analyzing trace with hash -250517174, now seen corresponding path program 1 times [2024-11-13 14:29:17,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:17,377 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2007350080] [2024-11-13 14:29:17,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:17,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:17,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:17,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:17,444 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:17,444 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2007350080] [2024-11-13 14:29:17,444 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2007350080] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:17,444 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:17,445 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:29:17,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1696993278] [2024-11-13 14:29:17,445 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:17,445 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:29:17,446 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:17,446 INFO L85 PathProgramCache]: Analyzing trace with hash -1022904633, now seen corresponding path program 1 times [2024-11-13 14:29:17,446 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:17,447 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1438115949] [2024-11-13 14:29:17,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:17,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:17,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:17,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:17,566 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:17,566 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1438115949] [2024-11-13 14:29:17,566 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1438115949] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:17,566 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:17,566 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:29:17,566 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [27193547] [2024-11-13 14:29:17,567 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:17,570 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:29:17,571 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:29:17,571 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:29:17,571 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:29:17,572 INFO L87 Difference]: Start difference. First operand 389 states and 578 transitions. cyclomatic complexity: 190 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:17,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:29:17,597 INFO L93 Difference]: Finished difference Result 389 states and 577 transitions. [2024-11-13 14:29:17,598 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 389 states and 577 transitions. [2024-11-13 14:29:17,602 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2024-11-13 14:29:17,606 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 389 states to 389 states and 577 transitions. [2024-11-13 14:29:17,607 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2024-11-13 14:29:17,607 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2024-11-13 14:29:17,608 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389 states and 577 transitions. [2024-11-13 14:29:17,609 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:29:17,609 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389 states and 577 transitions. [2024-11-13 14:29:17,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states and 577 transitions. [2024-11-13 14:29:17,625 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2024-11-13 14:29:17,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4832904884318765) internal successors, (577), 388 states have internal predecessors, (577), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:17,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 577 transitions. [2024-11-13 14:29:17,633 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389 states and 577 transitions. [2024-11-13 14:29:17,633 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:29:17,634 INFO L424 stractBuchiCegarLoop]: Abstraction has 389 states and 577 transitions. [2024-11-13 14:29:17,637 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 14:29:17,637 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 577 transitions. [2024-11-13 14:29:17,642 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2024-11-13 14:29:17,642 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:17,642 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:17,647 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:17,647 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:17,648 INFO L745 eck$LassoCheckResult]: Stem: 3365#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 3366#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3432#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3433#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3265#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 3266#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3459#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3363#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3200#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3201#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3220#L502 assume !(0 == ~M_E~0); 3221#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3186#L507-1 assume !(0 == ~T2_E~0); 3187#L512-1 assume !(0 == ~T3_E~0); 3267#L517-1 assume !(0 == ~T4_E~0); 3174#L522-1 assume !(0 == ~E_1~0); 3175#L527-1 assume !(0 == ~E_2~0); 3368#L532-1 assume !(0 == ~E_3~0); 3369#L537-1 assume !(0 == ~E_4~0); 3384#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3360#L238 assume 1 == ~m_pc~0; 3361#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3407#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3343#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3341#L615 assume !(0 != activate_threads_~tmp~1#1); 3342#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3323#L257 assume 1 == ~t1_pc~0; 3324#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3359#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3218#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3219#L623 assume !(0 != activate_threads_~tmp___0~0#1); 3202#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3203#L276 assume !(1 == ~t2_pc~0); 3437#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3513#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3435#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3436#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3537#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3340#L295 assume 1 == ~t3_pc~0; 3232#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3208#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3169#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3170#L639 assume !(0 != activate_threads_~tmp___2~0#1); 3531#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3532#L314 assume !(1 == ~t4_pc~0); 3226#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3225#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3258#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3259#L647 assume !(0 != activate_threads_~tmp___3~0#1); 3322#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3509#L555 assume !(1 == ~M_E~0); 3235#L555-2 assume !(1 == ~T1_E~0); 3236#L560-1 assume !(1 == ~T2_E~0); 3176#L565-1 assume !(1 == ~T3_E~0); 3177#L570-1 assume !(1 == ~T4_E~0); 3329#L575-1 assume !(1 == ~E_1~0); 3464#L580-1 assume !(1 == ~E_2~0); 3376#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 3217#L590-1 assume !(1 == ~E_4~0); 3209#L595-1 assume { :end_inline_reset_delta_events } true; 3210#L776-2 [2024-11-13 14:29:17,648 INFO L747 eck$LassoCheckResult]: Loop: 3210#L776-2 assume !false; 3191#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3192#L477-1 assume !false; 3482#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3483#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3311#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3446#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3448#L416 assume !(0 != eval_~tmp~0#1); 3261#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3262#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3303#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3304#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3523#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3263#L512-3 assume !(0 == ~T3_E~0); 3264#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3251#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3252#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3326#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3392#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3271#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3272#L238-15 assume 1 == ~m_pc~0; 3171#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3172#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3255#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3256#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3402#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3403#L257-15 assume !(1 == ~t1_pc~0); 3296#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 3297#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3489#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3490#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3524#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3530#L276-15 assume 1 == ~t2_pc~0; 3498#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3493#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3494#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3427#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3428#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3204#L295-15 assume !(1 == ~t3_pc~0); 3205#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 3420#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3534#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3410#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3370#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3371#L314-15 assume 1 == ~t4_pc~0; 3408#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3425#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3426#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3525#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3367#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3316#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3317#L555-5 assume !(1 == ~T1_E~0); 3242#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3243#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3526#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3516#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3440#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3441#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3478#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3479#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3411#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3196#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3295#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 3338#L795 assume !(0 == start_simulation_~tmp~3#1); 3339#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3353#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3354#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3215#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 3216#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3237#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3238#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3512#L808 assume !(0 != start_simulation_~tmp___0~1#1); 3210#L776-2 [2024-11-13 14:29:17,649 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:17,649 INFO L85 PathProgramCache]: Analyzing trace with hash -1788857204, now seen corresponding path program 1 times [2024-11-13 14:29:17,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:17,650 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [354223920] [2024-11-13 14:29:17,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:17,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:17,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:17,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:17,753 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:17,753 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [354223920] [2024-11-13 14:29:17,754 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [354223920] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:17,754 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:17,754 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:29:17,754 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1246535598] [2024-11-13 14:29:17,754 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:17,755 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:29:17,755 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:17,755 INFO L85 PathProgramCache]: Analyzing trace with hash -2022470393, now seen corresponding path program 1 times [2024-11-13 14:29:17,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:17,756 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1374965634] [2024-11-13 14:29:17,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:17,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:17,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:17,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:17,840 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:17,840 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1374965634] [2024-11-13 14:29:17,841 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1374965634] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:17,841 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:17,841 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:29:17,841 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2050461194] [2024-11-13 14:29:17,841 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:17,842 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:29:17,842 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:29:17,842 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:29:17,843 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:29:17,843 INFO L87 Difference]: Start difference. First operand 389 states and 577 transitions. cyclomatic complexity: 189 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:17,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:29:17,884 INFO L93 Difference]: Finished difference Result 389 states and 572 transitions. [2024-11-13 14:29:17,884 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 389 states and 572 transitions. [2024-11-13 14:29:17,889 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2024-11-13 14:29:17,893 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 389 states to 389 states and 572 transitions. [2024-11-13 14:29:17,893 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2024-11-13 14:29:17,894 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2024-11-13 14:29:17,894 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389 states and 572 transitions. [2024-11-13 14:29:17,895 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:29:17,895 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389 states and 572 transitions. [2024-11-13 14:29:17,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states and 572 transitions. [2024-11-13 14:29:17,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2024-11-13 14:29:17,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4704370179948587) internal successors, (572), 388 states have internal predecessors, (572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:17,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 572 transitions. [2024-11-13 14:29:17,908 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389 states and 572 transitions. [2024-11-13 14:29:17,909 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:29:17,910 INFO L424 stractBuchiCegarLoop]: Abstraction has 389 states and 572 transitions. [2024-11-13 14:29:17,910 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 14:29:17,910 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 572 transitions. [2024-11-13 14:29:17,913 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2024-11-13 14:29:17,914 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:17,914 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:17,916 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:17,917 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:17,917 INFO L745 eck$LassoCheckResult]: Stem: 4150#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 4151#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4217#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4218#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4050#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 4051#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4244#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4148#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3985#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3986#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4005#L502 assume !(0 == ~M_E~0); 4006#L502-2 assume !(0 == ~T1_E~0); 3971#L507-1 assume !(0 == ~T2_E~0); 3972#L512-1 assume !(0 == ~T3_E~0); 4052#L517-1 assume !(0 == ~T4_E~0); 3959#L522-1 assume !(0 == ~E_1~0); 3960#L527-1 assume !(0 == ~E_2~0); 4153#L532-1 assume !(0 == ~E_3~0); 4154#L537-1 assume !(0 == ~E_4~0); 4169#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4145#L238 assume 1 == ~m_pc~0; 4146#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4192#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4128#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4126#L615 assume !(0 != activate_threads_~tmp~1#1); 4127#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4108#L257 assume 1 == ~t1_pc~0; 4109#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4143#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4003#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4004#L623 assume !(0 != activate_threads_~tmp___0~0#1); 3987#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3988#L276 assume !(1 == ~t2_pc~0); 4222#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4298#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4220#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4221#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4322#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4125#L295 assume 1 == ~t3_pc~0; 4017#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3993#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3954#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3955#L639 assume !(0 != activate_threads_~tmp___2~0#1); 4316#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4317#L314 assume !(1 == ~t4_pc~0); 4011#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4010#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4042#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4043#L647 assume !(0 != activate_threads_~tmp___3~0#1); 4107#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4294#L555 assume !(1 == ~M_E~0); 4020#L555-2 assume !(1 == ~T1_E~0); 4021#L560-1 assume !(1 == ~T2_E~0); 3961#L565-1 assume !(1 == ~T3_E~0); 3962#L570-1 assume !(1 == ~T4_E~0); 4114#L575-1 assume !(1 == ~E_1~0); 4249#L580-1 assume !(1 == ~E_2~0); 4161#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4000#L590-1 assume !(1 == ~E_4~0); 3994#L595-1 assume { :end_inline_reset_delta_events } true; 3995#L776-2 [2024-11-13 14:29:17,917 INFO L747 eck$LassoCheckResult]: Loop: 3995#L776-2 assume !false; 3976#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3977#L477-1 assume !false; 4267#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4268#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4096#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4229#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4233#L416 assume !(0 != eval_~tmp~0#1); 4046#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4047#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4088#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4089#L502-5 assume !(0 == ~T1_E~0); 4308#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4048#L512-3 assume !(0 == ~T3_E~0); 4049#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4036#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4037#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4111#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4177#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4056#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4057#L238-15 assume 1 == ~m_pc~0; 3956#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3957#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4040#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4041#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4187#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4188#L257-15 assume !(1 == ~t1_pc~0); 4081#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 4082#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4272#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4273#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4309#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4315#L276-15 assume 1 == ~t2_pc~0; 4283#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4278#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4279#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4210#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4211#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3989#L295-15 assume !(1 == ~t3_pc~0); 3990#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 4205#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4319#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4195#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4155#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4156#L314-15 assume 1 == ~t4_pc~0; 4193#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4214#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4215#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4310#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4152#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4101#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4102#L555-5 assume !(1 == ~T1_E~0); 4027#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4028#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4311#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4301#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4225#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4226#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4263#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4264#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4196#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3981#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4080#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 4123#L795 assume !(0 == start_simulation_~tmp~3#1); 4124#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4139#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4140#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4001#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 4002#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4022#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4023#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4297#L808 assume !(0 != start_simulation_~tmp___0~1#1); 3995#L776-2 [2024-11-13 14:29:17,920 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:17,923 INFO L85 PathProgramCache]: Analyzing trace with hash -1804375922, now seen corresponding path program 1 times [2024-11-13 14:29:17,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:17,924 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922395447] [2024-11-13 14:29:17,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:17,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:17,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:18,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:18,047 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:18,047 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1922395447] [2024-11-13 14:29:18,047 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1922395447] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:18,048 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:18,048 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:29:18,048 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1262942528] [2024-11-13 14:29:18,048 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:18,048 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:29:18,049 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:18,049 INFO L85 PathProgramCache]: Analyzing trace with hash -60895735, now seen corresponding path program 1 times [2024-11-13 14:29:18,049 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:18,049 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1788192231] [2024-11-13 14:29:18,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:18,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:18,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:18,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:18,219 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:18,219 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1788192231] [2024-11-13 14:29:18,219 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1788192231] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:18,219 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:18,219 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:29:18,219 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [135358946] [2024-11-13 14:29:18,220 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:18,220 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:29:18,220 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:29:18,220 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:29:18,221 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:29:18,221 INFO L87 Difference]: Start difference. First operand 389 states and 572 transitions. cyclomatic complexity: 184 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:18,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:29:18,342 INFO L93 Difference]: Finished difference Result 705 states and 1024 transitions. [2024-11-13 14:29:18,342 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 705 states and 1024 transitions. [2024-11-13 14:29:18,351 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 639 [2024-11-13 14:29:18,357 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 705 states to 705 states and 1024 transitions. [2024-11-13 14:29:18,358 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 705 [2024-11-13 14:29:18,359 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 705 [2024-11-13 14:29:18,359 INFO L73 IsDeterministic]: Start isDeterministic. Operand 705 states and 1024 transitions. [2024-11-13 14:29:18,361 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:29:18,361 INFO L218 hiAutomatonCegarLoop]: Abstraction has 705 states and 1024 transitions. [2024-11-13 14:29:18,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 705 states and 1024 transitions. [2024-11-13 14:29:18,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 705 to 669. [2024-11-13 14:29:18,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 669 states, 669 states have (on average 1.4573991031390134) internal successors, (975), 668 states have internal predecessors, (975), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:18,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 669 states to 669 states and 975 transitions. [2024-11-13 14:29:18,397 INFO L240 hiAutomatonCegarLoop]: Abstraction has 669 states and 975 transitions. [2024-11-13 14:29:18,398 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:29:18,401 INFO L424 stractBuchiCegarLoop]: Abstraction has 669 states and 975 transitions. [2024-11-13 14:29:18,401 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 14:29:18,401 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 669 states and 975 transitions. [2024-11-13 14:29:18,410 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 603 [2024-11-13 14:29:18,410 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:18,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:18,412 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:18,412 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:18,412 INFO L745 eck$LassoCheckResult]: Stem: 5253#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 5254#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5324#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5325#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5153#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 5154#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5353#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5251#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5088#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5089#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5108#L502 assume !(0 == ~M_E~0); 5109#L502-2 assume !(0 == ~T1_E~0); 5074#L507-1 assume !(0 == ~T2_E~0); 5075#L512-1 assume !(0 == ~T3_E~0); 5155#L517-1 assume !(0 == ~T4_E~0); 5062#L522-1 assume !(0 == ~E_1~0); 5063#L527-1 assume !(0 == ~E_2~0); 5256#L532-1 assume !(0 == ~E_3~0); 5257#L537-1 assume !(0 == ~E_4~0); 5276#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5249#L238 assume !(1 == ~m_pc~0); 5250#L238-2 is_master_triggered_~__retres1~0#1 := 0; 5299#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5232#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5230#L615 assume !(0 != activate_threads_~tmp~1#1); 5231#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5213#L257 assume 1 == ~t1_pc~0; 5214#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5247#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5106#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5107#L623 assume !(0 != activate_threads_~tmp___0~0#1); 5090#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5091#L276 assume !(1 == ~t2_pc~0); 5329#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5412#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5327#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5328#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5439#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5229#L295 assume 1 == ~t3_pc~0; 5120#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5096#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5057#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5058#L639 assume !(0 != activate_threads_~tmp___2~0#1); 5432#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5433#L314 assume !(1 == ~t4_pc~0); 5114#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5113#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5145#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5146#L647 assume !(0 != activate_threads_~tmp___3~0#1); 5212#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5408#L555 assume !(1 == ~M_E~0); 5123#L555-2 assume !(1 == ~T1_E~0); 5124#L560-1 assume !(1 == ~T2_E~0); 5064#L565-1 assume !(1 == ~T3_E~0); 5065#L570-1 assume !(1 == ~T4_E~0); 5219#L575-1 assume !(1 == ~E_1~0); 5358#L580-1 assume !(1 == ~E_2~0); 5268#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5103#L590-1 assume !(1 == ~E_4~0); 5097#L595-1 assume { :end_inline_reset_delta_events } true; 5098#L776-2 [2024-11-13 14:29:18,412 INFO L747 eck$LassoCheckResult]: Loop: 5098#L776-2 assume !false; 5079#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5080#L477-1 assume !false; 5376#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5377#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5200#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5336#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5341#L416 assume !(0 != eval_~tmp~0#1); 5346#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5657#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5656#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5655#L502-5 assume !(0 == ~T1_E~0); 5654#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5653#L512-3 assume !(0 == ~T3_E~0); 5652#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5651#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5650#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5647#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5646#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5159#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5160#L238-15 assume !(1 == ~m_pc~0); 5207#L238-17 is_master_triggered_~__retres1~0#1 := 0; 5699#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5698#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5697#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5696#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5695#L257-15 assume !(1 == ~t1_pc~0); 5693#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 5692#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5691#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5690#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5689#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5688#L276-15 assume 1 == ~t2_pc~0; 5686#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5672#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5671#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5670#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5669#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5668#L295-15 assume !(1 == ~t3_pc~0); 5666#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 5665#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5664#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5663#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5662#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5661#L314-15 assume 1 == ~t4_pc~0; 5659#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5658#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5645#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5431#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5255#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5205#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5206#L555-5 assume !(1 == ~T1_E~0); 5130#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5131#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5441#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5415#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5332#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5333#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5372#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5373#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5303#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5084#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5184#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 5227#L795 assume !(0 == start_simulation_~tmp~3#1); 5228#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5243#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5244#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5104#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 5105#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5125#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5126#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 5411#L808 assume !(0 != start_simulation_~tmp___0~1#1); 5098#L776-2 [2024-11-13 14:29:18,413 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:18,413 INFO L85 PathProgramCache]: Analyzing trace with hash -1404384723, now seen corresponding path program 1 times [2024-11-13 14:29:18,413 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:18,417 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1391731850] [2024-11-13 14:29:18,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:18,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:18,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:18,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:18,528 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:18,528 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1391731850] [2024-11-13 14:29:18,528 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1391731850] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:18,528 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:18,528 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:29:18,528 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1606574066] [2024-11-13 14:29:18,529 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:18,529 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:29:18,530 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:18,530 INFO L85 PathProgramCache]: Analyzing trace with hash -762463960, now seen corresponding path program 1 times [2024-11-13 14:29:18,530 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:18,530 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2044350738] [2024-11-13 14:29:18,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:18,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:18,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:18,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:18,628 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:18,628 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2044350738] [2024-11-13 14:29:18,628 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2044350738] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:18,628 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:18,628 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:29:18,628 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1189215145] [2024-11-13 14:29:18,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:18,629 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:29:18,629 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:29:18,629 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:29:18,629 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:29:18,629 INFO L87 Difference]: Start difference. First operand 669 states and 975 transitions. cyclomatic complexity: 308 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:18,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:29:18,724 INFO L93 Difference]: Finished difference Result 1189 states and 1721 transitions. [2024-11-13 14:29:18,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1189 states and 1721 transitions. [2024-11-13 14:29:18,737 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1118 [2024-11-13 14:29:18,749 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1189 states to 1189 states and 1721 transitions. [2024-11-13 14:29:18,750 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1189 [2024-11-13 14:29:18,753 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1189 [2024-11-13 14:29:18,753 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1189 states and 1721 transitions. [2024-11-13 14:29:18,757 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:29:18,761 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1189 states and 1721 transitions. [2024-11-13 14:29:18,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1189 states and 1721 transitions. [2024-11-13 14:29:18,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1189 to 1185. [2024-11-13 14:29:18,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.448945147679325) internal successors, (1717), 1184 states have internal predecessors, (1717), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:18,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1717 transitions. [2024-11-13 14:29:18,817 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1717 transitions. [2024-11-13 14:29:18,817 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:29:18,819 INFO L424 stractBuchiCegarLoop]: Abstraction has 1185 states and 1717 transitions. [2024-11-13 14:29:18,821 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 14:29:18,821 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1717 transitions. [2024-11-13 14:29:18,831 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1114 [2024-11-13 14:29:18,831 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:18,832 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:18,833 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:18,833 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:18,834 INFO L745 eck$LassoCheckResult]: Stem: 7122#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 7123#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 7202#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7203#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7022#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 7023#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7235#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7120#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6955#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6956#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6975#L502 assume !(0 == ~M_E~0); 6976#L502-2 assume !(0 == ~T1_E~0); 6944#L507-1 assume !(0 == ~T2_E~0); 6945#L512-1 assume !(0 == ~T3_E~0); 7025#L517-1 assume !(0 == ~T4_E~0); 6931#L522-1 assume !(0 == ~E_1~0); 6932#L527-1 assume !(0 == ~E_2~0); 7125#L532-1 assume !(0 == ~E_3~0); 7126#L537-1 assume !(0 == ~E_4~0); 7145#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7118#L238 assume !(1 == ~m_pc~0); 7119#L238-2 is_master_triggered_~__retres1~0#1 := 0; 7175#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7101#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7099#L615 assume !(0 != activate_threads_~tmp~1#1); 7100#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7082#L257 assume !(1 == ~t1_pc~0); 7083#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7117#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6973#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6974#L623 assume !(0 != activate_threads_~tmp___0~0#1); 6957#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6958#L276 assume !(1 == ~t2_pc~0); 7210#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7304#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7208#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7209#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7338#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7098#L295 assume 1 == ~t3_pc~0; 6987#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6963#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6924#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6925#L639 assume !(0 != activate_threads_~tmp___2~0#1); 7326#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7327#L314 assume !(1 == ~t4_pc~0); 6981#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6980#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7015#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7016#L647 assume !(0 != activate_threads_~tmp___3~0#1); 7081#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7298#L555 assume !(1 == ~M_E~0); 6990#L555-2 assume !(1 == ~T1_E~0); 6991#L560-1 assume !(1 == ~T2_E~0); 6933#L565-1 assume !(1 == ~T3_E~0); 6934#L570-1 assume !(1 == ~T4_E~0); 7088#L575-1 assume !(1 == ~E_1~0); 7242#L580-1 assume !(1 == ~E_2~0); 7137#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 6972#L590-1 assume !(1 == ~E_4~0); 6964#L595-1 assume { :end_inline_reset_delta_events } true; 6965#L776-2 [2024-11-13 14:29:18,834 INFO L747 eck$LassoCheckResult]: Loop: 6965#L776-2 assume !false; 7718#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7714#L477-1 assume !false; 7713#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7314#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7070#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7217#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7221#L416 assume !(0 != eval_~tmp~0#1); 7227#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8010#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8009#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7316#L502-5 assume !(0 == ~T1_E~0); 7317#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7020#L512-3 assume !(0 == ~T3_E~0); 7021#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7956#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7955#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7954#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7953#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7952#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7951#L238-15 assume !(1 == ~m_pc~0); 7950#L238-17 is_master_triggered_~__retres1~0#1 := 0; 7949#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7948#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7947#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7946#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7944#L257-15 assume !(1 == ~t1_pc~0); 7942#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 7940#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7938#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7936#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7933#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7931#L276-15 assume 1 == ~t2_pc~0; 7928#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7926#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7924#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7922#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7919#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7917#L295-15 assume !(1 == ~t3_pc~0); 7914#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 7912#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7910#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7908#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7905#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7903#L314-15 assume 1 == ~t4_pc~0; 7829#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7827#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7825#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7823#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7821#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7819#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7816#L555-5 assume !(1 == ~T1_E~0); 7814#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7812#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7810#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7808#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7792#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7787#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7781#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7775#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7766#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7758#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7756#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 7753#L795 assume !(0 == start_simulation_~tmp~3#1); 7750#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7745#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7742#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7741#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 7739#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7737#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7735#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 7732#L808 assume !(0 != start_simulation_~tmp___0~1#1); 6965#L776-2 [2024-11-13 14:29:18,835 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:18,835 INFO L85 PathProgramCache]: Analyzing trace with hash 1261932300, now seen corresponding path program 1 times [2024-11-13 14:29:18,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:18,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1611825256] [2024-11-13 14:29:18,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:18,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:18,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:18,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:18,959 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:18,959 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1611825256] [2024-11-13 14:29:18,959 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1611825256] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:18,960 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:18,960 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:29:18,960 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618284349] [2024-11-13 14:29:18,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:18,960 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:29:18,961 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:18,961 INFO L85 PathProgramCache]: Analyzing trace with hash -762463960, now seen corresponding path program 2 times [2024-11-13 14:29:18,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:18,961 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1058186506] [2024-11-13 14:29:18,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:18,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:18,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:19,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:19,065 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:19,065 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1058186506] [2024-11-13 14:29:19,066 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1058186506] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:19,066 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:19,066 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:29:19,066 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1990660327] [2024-11-13 14:29:19,068 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:19,069 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:29:19,069 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:29:19,070 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 14:29:19,070 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 14:29:19,070 INFO L87 Difference]: Start difference. First operand 1185 states and 1717 transitions. cyclomatic complexity: 536 Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:19,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:29:19,342 INFO L93 Difference]: Finished difference Result 1248 states and 1780 transitions. [2024-11-13 14:29:19,343 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1248 states and 1780 transitions. [2024-11-13 14:29:19,356 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1174 [2024-11-13 14:29:19,367 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1248 states to 1248 states and 1780 transitions. [2024-11-13 14:29:19,367 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1248 [2024-11-13 14:29:19,369 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1248 [2024-11-13 14:29:19,369 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1248 states and 1780 transitions. [2024-11-13 14:29:19,373 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:29:19,373 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1248 states and 1780 transitions. [2024-11-13 14:29:19,375 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1248 states and 1780 transitions. [2024-11-13 14:29:19,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1248 to 1248. [2024-11-13 14:29:19,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1248 states, 1248 states have (on average 1.4262820512820513) internal successors, (1780), 1247 states have internal predecessors, (1780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:19,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1248 states to 1248 states and 1780 transitions. [2024-11-13 14:29:19,413 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1248 states and 1780 transitions. [2024-11-13 14:29:19,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 14:29:19,418 INFO L424 stractBuchiCegarLoop]: Abstraction has 1248 states and 1780 transitions. [2024-11-13 14:29:19,420 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 14:29:19,420 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1248 states and 1780 transitions. [2024-11-13 14:29:19,430 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1174 [2024-11-13 14:29:19,430 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:19,430 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:19,432 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:19,432 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:19,432 INFO L745 eck$LassoCheckResult]: Stem: 9565#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 9566#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 9642#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9643#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9466#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 9467#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9672#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9563#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9399#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9400#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9419#L502 assume !(0 == ~M_E~0); 9420#L502-2 assume !(0 == ~T1_E~0); 9388#L507-1 assume !(0 == ~T2_E~0); 9389#L512-1 assume !(0 == ~T3_E~0); 9469#L517-1 assume !(0 == ~T4_E~0); 9375#L522-1 assume !(0 == ~E_1~0); 9376#L527-1 assume !(0 == ~E_2~0); 9568#L532-1 assume !(0 == ~E_3~0); 9569#L537-1 assume !(0 == ~E_4~0); 9586#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9561#L238 assume !(1 == ~m_pc~0); 9562#L238-2 is_master_triggered_~__retres1~0#1 := 0; 9614#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9543#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9541#L615 assume !(0 != activate_threads_~tmp~1#1); 9542#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9524#L257 assume !(1 == ~t1_pc~0); 9525#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9560#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9417#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9418#L623 assume !(0 != activate_threads_~tmp___0~0#1); 9401#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9402#L276 assume !(1 == ~t2_pc~0); 9647#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9733#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9645#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9646#L631 assume !(0 != activate_threads_~tmp___1~0#1); 9764#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9540#L295 assume 1 == ~t3_pc~0; 9431#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9407#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9368#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9369#L639 assume !(0 != activate_threads_~tmp___2~0#1); 9753#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9754#L314 assume !(1 == ~t4_pc~0); 9425#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9424#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9459#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9460#L647 assume !(0 != activate_threads_~tmp___3~0#1); 9523#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9729#L555 assume !(1 == ~M_E~0); 9434#L555-2 assume !(1 == ~T1_E~0); 9435#L560-1 assume !(1 == ~T2_E~0); 9377#L565-1 assume !(1 == ~T3_E~0); 9378#L570-1 assume !(1 == ~T4_E~0); 9530#L575-1 assume !(1 == ~E_1~0); 9678#L580-1 assume !(1 == ~E_2~0); 9579#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 9416#L590-1 assume !(1 == ~E_4~0); 9408#L595-1 assume { :end_inline_reset_delta_events } true; 9409#L776-2 [2024-11-13 14:29:19,432 INFO L747 eck$LassoCheckResult]: Loop: 9409#L776-2 assume !false; 9390#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9391#L477-1 assume !false; 9696#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 9697#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 9512#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 9654#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9658#L416 assume !(0 != eval_~tmp~0#1); 9462#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9463#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9504#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9505#L502-5 assume !(0 == ~T1_E~0); 9746#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9464#L512-3 assume !(0 == ~T3_E~0); 9465#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9452#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9453#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9526#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9594#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9472#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9473#L238-15 assume !(1 == ~m_pc~0); 9519#L238-17 is_master_triggered_~__retres1~0#1 := 0; 9558#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9456#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9457#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9609#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9610#L257-15 assume !(1 == ~t1_pc~0); 9497#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 9498#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9702#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9703#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9747#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9752#L276-15 assume 1 == ~t2_pc~0; 9715#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9716#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10556#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10553#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9635#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9403#L295-15 assume !(1 == ~t3_pc~0); 9404#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 9629#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9759#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9617#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9570#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9571#L314-15 assume !(1 == ~t4_pc~0); 9616#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 9638#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9639#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9748#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9567#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9517#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9518#L555-5 assume !(1 == ~T1_E~0); 9441#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9442#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9749#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9737#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9650#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9651#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9692#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9693#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 9618#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 9395#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 9496#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 9538#L795 assume !(0 == start_simulation_~tmp~3#1); 9539#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 9554#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 9555#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 9414#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 9415#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9436#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9437#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 9732#L808 assume !(0 != start_simulation_~tmp___0~1#1); 9409#L776-2 [2024-11-13 14:29:19,433 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:19,433 INFO L85 PathProgramCache]: Analyzing trace with hash 1127918794, now seen corresponding path program 1 times [2024-11-13 14:29:19,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:19,433 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2130941427] [2024-11-13 14:29:19,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:19,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:19,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:19,556 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:19,557 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:19,557 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2130941427] [2024-11-13 14:29:19,557 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2130941427] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:19,557 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:19,557 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:29:19,557 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2087101190] [2024-11-13 14:29:19,558 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:19,558 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:29:19,558 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:19,558 INFO L85 PathProgramCache]: Analyzing trace with hash -1070902969, now seen corresponding path program 1 times [2024-11-13 14:29:19,558 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:19,558 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [623282994] [2024-11-13 14:29:19,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:19,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:19,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:19,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:19,656 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:19,656 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [623282994] [2024-11-13 14:29:19,656 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [623282994] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:19,657 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:19,657 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:29:19,657 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [500606214] [2024-11-13 14:29:19,657 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:19,657 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:29:19,657 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:29:19,658 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:29:19,658 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:29:19,658 INFO L87 Difference]: Start difference. First operand 1248 states and 1780 transitions. cyclomatic complexity: 536 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:19,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:29:19,746 INFO L93 Difference]: Finished difference Result 2249 states and 3191 transitions. [2024-11-13 14:29:19,747 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2249 states and 3191 transitions. [2024-11-13 14:29:19,767 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2164 [2024-11-13 14:29:19,785 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2249 states to 2249 states and 3191 transitions. [2024-11-13 14:29:19,785 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2249 [2024-11-13 14:29:19,788 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2249 [2024-11-13 14:29:19,789 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2249 states and 3191 transitions. [2024-11-13 14:29:19,793 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:29:19,794 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2249 states and 3191 transitions. [2024-11-13 14:29:19,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2249 states and 3191 transitions. [2024-11-13 14:29:19,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2249 to 2241. [2024-11-13 14:29:19,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2241 states, 2241 states have (on average 1.4203480589022757) internal successors, (3183), 2240 states have internal predecessors, (3183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:19,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2241 states to 2241 states and 3183 transitions. [2024-11-13 14:29:19,857 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2241 states and 3183 transitions. [2024-11-13 14:29:19,857 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:29:19,860 INFO L424 stractBuchiCegarLoop]: Abstraction has 2241 states and 3183 transitions. [2024-11-13 14:29:19,860 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 14:29:19,860 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2241 states and 3183 transitions. [2024-11-13 14:29:19,875 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2156 [2024-11-13 14:29:19,875 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:19,875 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:19,878 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:19,878 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:19,878 INFO L745 eck$LassoCheckResult]: Stem: 13069#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 13070#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 13147#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13148#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12968#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 12969#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13187#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13067#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12905#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12906#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12924#L502 assume !(0 == ~M_E~0); 12925#L502-2 assume !(0 == ~T1_E~0); 12891#L507-1 assume !(0 == ~T2_E~0); 12892#L512-1 assume !(0 == ~T3_E~0); 12971#L517-1 assume !(0 == ~T4_E~0); 12879#L522-1 assume !(0 == ~E_1~0); 12880#L527-1 assume !(0 == ~E_2~0); 13072#L532-1 assume !(0 == ~E_3~0); 13073#L537-1 assume !(0 == ~E_4~0); 13092#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13065#L238 assume !(1 == ~m_pc~0); 13066#L238-2 is_master_triggered_~__retres1~0#1 := 0; 13116#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13047#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13045#L615 assume !(0 != activate_threads_~tmp~1#1); 13046#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13027#L257 assume !(1 == ~t1_pc~0); 13028#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13063#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12922#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12923#L623 assume !(0 != activate_threads_~tmp___0~0#1); 12907#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12908#L276 assume !(1 == ~t2_pc~0); 13155#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13253#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13153#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13154#L631 assume !(0 != activate_threads_~tmp___1~0#1); 13295#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13044#L295 assume !(1 == ~t3_pc~0); 12911#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12912#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12874#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12875#L639 assume !(0 != activate_threads_~tmp___2~0#1); 13281#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13282#L314 assume !(1 == ~t4_pc~0); 12930#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12929#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12961#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12962#L647 assume !(0 != activate_threads_~tmp___3~0#1); 13026#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13249#L555 assume !(1 == ~M_E~0); 12938#L555-2 assume !(1 == ~T1_E~0); 12939#L560-1 assume !(1 == ~T2_E~0); 12881#L565-1 assume !(1 == ~T3_E~0); 12882#L570-1 assume !(1 == ~T4_E~0); 13033#L575-1 assume !(1 == ~E_1~0); 13193#L580-1 assume !(1 == ~E_2~0); 13084#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 12921#L590-1 assume !(1 == ~E_4~0); 12913#L595-1 assume { :end_inline_reset_delta_events } true; 12914#L776-2 [2024-11-13 14:29:19,878 INFO L747 eck$LassoCheckResult]: Loop: 12914#L776-2 assume !false; 14683#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14680#L477-1 assume !false; 14679#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 14675#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 14670#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 14668#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14665#L416 assume !(0 != eval_~tmp~0#1); 14666#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14956#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14954#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14952#L502-5 assume !(0 == ~T1_E~0); 14950#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14948#L512-3 assume !(0 == ~T3_E~0); 13311#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13312#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14862#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14861#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13247#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12974#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12975#L238-15 assume !(1 == ~m_pc~0); 13021#L238-17 is_master_triggered_~__retres1~0#1 := 0; 13064#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12956#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12957#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13111#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13112#L257-15 assume !(1 == ~t1_pc~0); 13186#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 13290#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13223#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13224#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13271#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13278#L276-15 assume 1 == ~t2_pc~0; 13234#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13235#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14791#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14790#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13144#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12909#L295-15 assume !(1 == ~t3_pc~0); 12910#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 15040#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15038#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15037#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15036#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15029#L314-15 assume 1 == ~t4_pc~0; 15026#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13139#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13140#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13279#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13071#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13019#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13020#L555-5 assume !(1 == ~T1_E~0); 12945#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12946#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13274#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14858#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14857#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14856#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14855#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14854#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 14821#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 14817#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 14815#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 14813#L795 assume !(0 == start_simulation_~tmp~3#1); 13280#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 13057#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 13058#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12919#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 12920#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12940#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12941#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 13266#L808 assume !(0 != start_simulation_~tmp___0~1#1); 12914#L776-2 [2024-11-13 14:29:19,878 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:19,879 INFO L85 PathProgramCache]: Analyzing trace with hash 1014532137, now seen corresponding path program 1 times [2024-11-13 14:29:19,879 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:19,879 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [783129197] [2024-11-13 14:29:19,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:19,879 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:19,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:19,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:19,968 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:19,968 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [783129197] [2024-11-13 14:29:19,968 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [783129197] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:19,968 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:19,968 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:29:19,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1746952108] [2024-11-13 14:29:19,969 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:19,969 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:29:19,969 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:19,969 INFO L85 PathProgramCache]: Analyzing trace with hash -762463960, now seen corresponding path program 3 times [2024-11-13 14:29:19,969 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:19,969 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [244075423] [2024-11-13 14:29:19,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:19,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:19,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:20,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:20,059 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:20,060 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [244075423] [2024-11-13 14:29:20,060 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [244075423] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:20,060 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:20,060 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:29:20,060 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [83960107] [2024-11-13 14:29:20,060 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:20,061 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:29:20,061 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:29:20,061 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 14:29:20,061 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 14:29:20,061 INFO L87 Difference]: Start difference. First operand 2241 states and 3183 transitions. cyclomatic complexity: 950 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:20,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:29:20,296 INFO L93 Difference]: Finished difference Result 4638 states and 6533 transitions. [2024-11-13 14:29:20,297 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4638 states and 6533 transitions. [2024-11-13 14:29:20,339 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4428 [2024-11-13 14:29:20,371 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4638 states to 4638 states and 6533 transitions. [2024-11-13 14:29:20,371 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4638 [2024-11-13 14:29:20,379 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4638 [2024-11-13 14:29:20,379 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4638 states and 6533 transitions. [2024-11-13 14:29:20,388 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:29:20,388 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4638 states and 6533 transitions. [2024-11-13 14:29:20,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4638 states and 6533 transitions. [2024-11-13 14:29:20,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4638 to 4578. [2024-11-13 14:29:20,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4578 states, 4578 states have (on average 1.4104412407164701) internal successors, (6457), 4577 states have internal predecessors, (6457), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:20,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4578 states to 4578 states and 6457 transitions. [2024-11-13 14:29:20,500 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4578 states and 6457 transitions. [2024-11-13 14:29:20,500 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 14:29:20,501 INFO L424 stractBuchiCegarLoop]: Abstraction has 4578 states and 6457 transitions. [2024-11-13 14:29:20,501 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 14:29:20,502 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4578 states and 6457 transitions. [2024-11-13 14:29:20,526 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4376 [2024-11-13 14:29:20,526 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:20,527 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:20,529 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:20,529 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:20,529 INFO L745 eck$LassoCheckResult]: Stem: 19964#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 19965#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 20048#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20049#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19862#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 19863#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20083#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19962#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19797#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19798#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19816#L502 assume !(0 == ~M_E~0); 19817#L502-2 assume !(0 == ~T1_E~0); 19785#L507-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19786#L512-1 assume !(0 == ~T3_E~0); 19865#L517-1 assume !(0 == ~T4_E~0); 19772#L522-1 assume !(0 == ~E_1~0); 19773#L527-1 assume !(0 == ~E_2~0); 19967#L532-1 assume 0 == ~E_3~0;~E_3~0 := 1; 19968#L537-1 assume !(0 == ~E_4~0); 20263#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20262#L238 assume !(1 == ~m_pc~0); 20261#L238-2 is_master_triggered_~__retres1~0#1 := 0; 20260#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20259#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20258#L615 assume !(0 != activate_threads_~tmp~1#1); 20257#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20256#L257 assume !(1 == ~t1_pc~0); 20255#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20254#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20253#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20252#L623 assume !(0 != activate_threads_~tmp___0~0#1); 20251#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20250#L276 assume !(1 == ~t2_pc~0); 20249#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20269#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20267#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20244#L631 assume !(0 != activate_threads_~tmp___1~0#1); 20243#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20242#L295 assume !(1 == ~t3_pc~0); 20241#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20240#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20239#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20238#L639 assume !(0 != activate_threads_~tmp___2~0#1); 20237#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20236#L314 assume !(1 == ~t4_pc~0); 20235#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20233#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20232#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20231#L647 assume !(0 != activate_threads_~tmp___3~0#1); 20230#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20229#L555 assume !(1 == ~M_E~0); 20228#L555-2 assume !(1 == ~T1_E~0); 20227#L560-1 assume !(1 == ~T2_E~0); 20226#L565-1 assume !(1 == ~T3_E~0); 20225#L570-1 assume !(1 == ~T4_E~0); 20224#L575-1 assume !(1 == ~E_1~0); 20223#L580-1 assume !(1 == ~E_2~0); 20221#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 20222#L590-1 assume !(1 == ~E_4~0); 22724#L595-1 assume { :end_inline_reset_delta_events } true; 22722#L776-2 [2024-11-13 14:29:20,530 INFO L747 eck$LassoCheckResult]: Loop: 22722#L776-2 assume !false; 22720#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22715#L477-1 assume !false; 22713#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 22705#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 22701#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 22698#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 22695#L416 assume !(0 != eval_~tmp~0#1); 22696#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22877#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22876#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22875#L502-5 assume !(0 == ~T1_E~0); 22873#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22870#L512-3 assume !(0 == ~T3_E~0); 22869#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22868#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22867#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22865#L532-3 assume !(0 == ~E_3~0); 22864#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22862#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22860#L238-15 assume !(1 == ~m_pc~0); 22858#L238-17 is_master_triggered_~__retres1~0#1 := 0; 22857#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22856#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 22854#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22852#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22850#L257-15 assume !(1 == ~t1_pc~0); 22846#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 22844#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22842#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22840#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22838#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22835#L276-15 assume 1 == ~t2_pc~0; 22832#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22830#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22828#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 22823#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22821#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22819#L295-15 assume !(1 == ~t3_pc~0); 22817#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 22815#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22812#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22810#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22808#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22806#L314-15 assume 1 == ~t4_pc~0; 22803#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22799#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22797#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22795#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22793#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22790#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22788#L555-5 assume !(1 == ~T1_E~0); 22786#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22784#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22782#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22780#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22778#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22776#L585-3 assume !(1 == ~E_3~0); 22773#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22772#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 22763#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 22759#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 22756#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 22753#L795 assume !(0 == start_simulation_~tmp~3#1); 22750#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 22740#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 22736#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 22733#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 22731#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22729#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22727#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 22725#L808 assume !(0 != start_simulation_~tmp___0~1#1); 22722#L776-2 [2024-11-13 14:29:20,530 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:20,530 INFO L85 PathProgramCache]: Analyzing trace with hash -27236631, now seen corresponding path program 1 times [2024-11-13 14:29:20,530 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:20,530 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [351262333] [2024-11-13 14:29:20,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:20,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:20,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:20,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:20,595 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:20,595 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [351262333] [2024-11-13 14:29:20,595 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [351262333] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:20,595 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:20,595 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:29:20,596 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1393723015] [2024-11-13 14:29:20,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:20,596 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:29:20,597 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:20,597 INFO L85 PathProgramCache]: Analyzing trace with hash -655542228, now seen corresponding path program 1 times [2024-11-13 14:29:20,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:20,597 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1325586902] [2024-11-13 14:29:20,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:20,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:20,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:20,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:20,688 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:20,688 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1325586902] [2024-11-13 14:29:20,688 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1325586902] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:20,689 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:20,689 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:29:20,689 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [252923282] [2024-11-13 14:29:20,689 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:20,689 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:29:20,690 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:29:20,690 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:29:20,691 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:29:20,691 INFO L87 Difference]: Start difference. First operand 4578 states and 6457 transitions. cyclomatic complexity: 1895 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:20,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:29:20,747 INFO L93 Difference]: Finished difference Result 4528 states and 6344 transitions. [2024-11-13 14:29:20,747 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4528 states and 6344 transitions. [2024-11-13 14:29:20,776 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4376 [2024-11-13 14:29:20,809 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4528 states to 4528 states and 6344 transitions. [2024-11-13 14:29:20,809 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4528 [2024-11-13 14:29:20,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4528 [2024-11-13 14:29:20,817 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4528 states and 6344 transitions. [2024-11-13 14:29:20,825 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:29:20,825 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4528 states and 6344 transitions. [2024-11-13 14:29:20,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4528 states and 6344 transitions. [2024-11-13 14:29:20,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4528 to 2658. [2024-11-13 14:29:20,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2658 states, 2658 states have (on average 1.3954100827689992) internal successors, (3709), 2657 states have internal predecessors, (3709), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:20,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2658 states to 2658 states and 3709 transitions. [2024-11-13 14:29:20,901 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2658 states and 3709 transitions. [2024-11-13 14:29:20,901 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:29:20,902 INFO L424 stractBuchiCegarLoop]: Abstraction has 2658 states and 3709 transitions. [2024-11-13 14:29:20,902 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 14:29:20,902 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2658 states and 3709 transitions. [2024-11-13 14:29:20,917 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2528 [2024-11-13 14:29:20,920 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:20,920 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:20,921 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:20,921 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:20,921 INFO L745 eck$LassoCheckResult]: Stem: 29082#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 29083#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 29167#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29168#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28976#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 28977#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29209#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29080#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28911#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28912#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28930#L502 assume !(0 == ~M_E~0); 28931#L502-2 assume !(0 == ~T1_E~0); 28900#L507-1 assume !(0 == ~T2_E~0); 28901#L512-1 assume !(0 == ~T3_E~0); 28979#L517-1 assume !(0 == ~T4_E~0); 28887#L522-1 assume !(0 == ~E_1~0); 28888#L527-1 assume !(0 == ~E_2~0); 29085#L532-1 assume 0 == ~E_3~0;~E_3~0 := 1; 29086#L537-1 assume !(0 == ~E_4~0); 29106#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29107#L238 assume !(1 == ~m_pc~0); 29136#L238-2 is_master_triggered_~__retres1~0#1 := 0; 29137#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29060#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 29061#L615 assume !(0 != activate_threads_~tmp~1#1); 29195#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29196#L257 assume !(1 == ~t1_pc~0); 29229#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29230#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28928#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28929#L623 assume !(0 != activate_threads_~tmp___0~0#1); 28913#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28914#L276 assume !(1 == ~t2_pc~0); 29282#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29283#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29173#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 29174#L631 assume !(0 != activate_threads_~tmp___1~0#1); 29332#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29333#L295 assume !(1 == ~t3_pc~0); 28917#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 28918#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28880#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 28881#L639 assume !(0 != activate_threads_~tmp___2~0#1); 29309#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29310#L314 assume !(1 == ~t4_pc~0); 28936#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28935#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28969#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 28970#L647 assume !(0 != activate_threads_~tmp___3~0#1); 29277#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29278#L555 assume !(1 == ~M_E~0); 28944#L555-2 assume !(1 == ~T1_E~0); 28945#L560-1 assume !(1 == ~T2_E~0); 28889#L565-1 assume !(1 == ~T3_E~0); 28890#L570-1 assume !(1 == ~T4_E~0); 29215#L575-1 assume !(1 == ~E_1~0); 29216#L580-1 assume !(1 == ~E_2~0); 29353#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 28927#L590-1 assume !(1 == ~E_4~0); 28919#L595-1 assume { :end_inline_reset_delta_events } true; 28920#L776-2 [2024-11-13 14:29:20,922 INFO L747 eck$LassoCheckResult]: Loop: 28920#L776-2 assume !false; 28902#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28903#L477-1 assume !false; 29243#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 29244#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 29023#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 29187#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 29191#L416 assume !(0 != eval_~tmp~0#1); 28972#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28973#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29015#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29016#L502-5 assume !(0 == ~T1_E~0); 29299#L507-3 assume !(0 == ~T2_E~0); 28974#L512-3 assume !(0 == ~T3_E~0); 28975#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28962#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28963#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29039#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29115#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31455#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31454#L238-15 assume !(1 == ~m_pc~0); 31453#L238-17 is_master_triggered_~__retres1~0#1 := 0; 31452#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31451#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 31450#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31449#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31448#L257-15 assume !(1 == ~t1_pc~0); 31447#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 31446#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31445#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 31444#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31443#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31442#L276-15 assume 1 == ~t2_pc~0; 31440#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31438#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31436#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 31434#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31433#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31432#L295-15 assume !(1 == ~t3_pc~0); 31431#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 31430#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31429#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31428#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31427#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31426#L314-15 assume 1 == ~t4_pc~0; 31424#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31423#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31422#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31421#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31420#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31419#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 31418#L555-5 assume !(1 == ~T1_E~0); 31417#L560-3 assume !(1 == ~T2_E~0); 31416#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31415#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31414#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 31413#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31412#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29237#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29238#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 29141#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 28907#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 29007#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 29054#L795 assume !(0 == start_simulation_~tmp~3#1); 29055#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 29071#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 29072#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 28925#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 28926#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28946#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28947#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 29281#L808 assume !(0 != start_simulation_~tmp___0~1#1); 28920#L776-2 [2024-11-13 14:29:20,922 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:20,923 INFO L85 PathProgramCache]: Analyzing trace with hash 1911925415, now seen corresponding path program 1 times [2024-11-13 14:29:20,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:20,923 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1534270627] [2024-11-13 14:29:20,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:20,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:20,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:21,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:21,059 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:21,059 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1534270627] [2024-11-13 14:29:21,059 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1534270627] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:21,059 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:21,059 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:29:21,059 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1703681210] [2024-11-13 14:29:21,060 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:21,060 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:29:21,060 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:21,060 INFO L85 PathProgramCache]: Analyzing trace with hash -1378288476, now seen corresponding path program 1 times [2024-11-13 14:29:21,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:21,061 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [474736064] [2024-11-13 14:29:21,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:21,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:21,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:21,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:21,132 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:21,133 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [474736064] [2024-11-13 14:29:21,133 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [474736064] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:21,133 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:21,133 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:29:21,133 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [585664059] [2024-11-13 14:29:21,133 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:21,134 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:29:21,134 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:29:21,134 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 14:29:21,134 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 14:29:21,134 INFO L87 Difference]: Start difference. First operand 2658 states and 3709 transitions. cyclomatic complexity: 1059 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:21,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:29:21,251 INFO L93 Difference]: Finished difference Result 4117 states and 5747 transitions. [2024-11-13 14:29:21,251 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4117 states and 5747 transitions. [2024-11-13 14:29:21,277 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4004 [2024-11-13 14:29:21,301 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4117 states to 4117 states and 5747 transitions. [2024-11-13 14:29:21,301 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4117 [2024-11-13 14:29:21,306 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4117 [2024-11-13 14:29:21,307 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4117 states and 5747 transitions. [2024-11-13 14:29:21,314 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:29:21,315 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4117 states and 5747 transitions. [2024-11-13 14:29:21,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4117 states and 5747 transitions. [2024-11-13 14:29:21,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4117 to 2241. [2024-11-13 14:29:21,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2241 states, 2241 states have (on average 1.390004462293619) internal successors, (3115), 2240 states have internal predecessors, (3115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:21,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2241 states to 2241 states and 3115 transitions. [2024-11-13 14:29:21,375 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2241 states and 3115 transitions. [2024-11-13 14:29:21,376 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 14:29:21,376 INFO L424 stractBuchiCegarLoop]: Abstraction has 2241 states and 3115 transitions. [2024-11-13 14:29:21,376 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 14:29:21,377 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2241 states and 3115 transitions. [2024-11-13 14:29:21,388 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2156 [2024-11-13 14:29:21,388 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:21,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:21,389 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:21,389 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:21,390 INFO L745 eck$LassoCheckResult]: Stem: 35863#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 35864#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 35940#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35941#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35764#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 35765#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35971#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35861#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35698#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35699#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35718#L502 assume !(0 == ~M_E~0); 35719#L502-2 assume !(0 == ~T1_E~0); 35687#L507-1 assume !(0 == ~T2_E~0); 35688#L512-1 assume !(0 == ~T3_E~0); 35767#L517-1 assume !(0 == ~T4_E~0); 35674#L522-1 assume !(0 == ~E_1~0); 35675#L527-1 assume !(0 == ~E_2~0); 35866#L532-1 assume !(0 == ~E_3~0); 35867#L537-1 assume !(0 == ~E_4~0); 35887#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35859#L238 assume !(1 == ~m_pc~0); 35860#L238-2 is_master_triggered_~__retres1~0#1 := 0; 35912#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35842#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 35840#L615 assume !(0 != activate_threads_~tmp~1#1); 35841#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35823#L257 assume !(1 == ~t1_pc~0); 35824#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35858#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35716#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 35717#L623 assume !(0 != activate_threads_~tmp___0~0#1); 35700#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35701#L276 assume !(1 == ~t2_pc~0); 35946#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 36036#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35944#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 35945#L631 assume !(0 != activate_threads_~tmp___1~0#1); 36069#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35839#L295 assume !(1 == ~t3_pc~0); 35705#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 35706#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35667#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 35668#L639 assume !(0 != activate_threads_~tmp___2~0#1); 36056#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36057#L314 assume !(1 == ~t4_pc~0); 35724#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 35723#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35757#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 35758#L647 assume !(0 != activate_threads_~tmp___3~0#1); 35822#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36032#L555 assume !(1 == ~M_E~0); 35732#L555-2 assume !(1 == ~T1_E~0); 35733#L560-1 assume !(1 == ~T2_E~0); 35676#L565-1 assume !(1 == ~T3_E~0); 35677#L570-1 assume !(1 == ~T4_E~0); 35829#L575-1 assume !(1 == ~E_1~0); 35977#L580-1 assume !(1 == ~E_2~0); 35879#L585-1 assume !(1 == ~E_3~0); 35715#L590-1 assume !(1 == ~E_4~0); 35707#L595-1 assume { :end_inline_reset_delta_events } true; 35708#L776-2 [2024-11-13 14:29:21,390 INFO L747 eck$LassoCheckResult]: Loop: 35708#L776-2 assume !false; 37297#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37293#L477-1 assume !false; 37292#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 37285#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 37281#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 37279#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 37276#L416 assume !(0 != eval_~tmp~0#1); 37277#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37606#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37605#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37604#L502-5 assume !(0 == ~T1_E~0); 37602#L507-3 assume !(0 == ~T2_E~0); 37601#L512-3 assume !(0 == ~T3_E~0); 37600#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37599#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37597#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37595#L532-3 assume !(0 == ~E_3~0); 37593#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37591#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37589#L238-15 assume !(1 == ~m_pc~0); 37587#L238-17 is_master_triggered_~__retres1~0#1 := 0; 37585#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37583#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 37581#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37579#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37577#L257-15 assume !(1 == ~t1_pc~0); 37575#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 37571#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37569#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 37567#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37565#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37562#L276-15 assume !(1 == ~t2_pc~0); 37558#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 37556#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37554#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 37552#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 37549#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37547#L295-15 assume !(1 == ~t3_pc~0); 37545#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 37543#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37540#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 37538#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37536#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37534#L314-15 assume 1 == ~t4_pc~0; 37531#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37529#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37527#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 37525#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37523#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37521#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37519#L555-5 assume !(1 == ~T1_E~0); 37517#L560-3 assume !(1 == ~T2_E~0); 37515#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37513#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37512#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37511#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37510#L585-3 assume !(1 == ~E_3~0); 37508#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37506#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 37327#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 37323#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 37322#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 37318#L795 assume !(0 == start_simulation_~tmp~3#1); 37316#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 37313#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 37310#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 37307#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 37303#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37302#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37301#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 37299#L808 assume !(0 != start_simulation_~tmp___0~1#1); 35708#L776-2 [2024-11-13 14:29:21,391 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:21,391 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 1 times [2024-11-13 14:29:21,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:21,391 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1756344756] [2024-11-13 14:29:21,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:21,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:21,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:21,408 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:29:21,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:21,465 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:29:21,465 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:21,465 INFO L85 PathProgramCache]: Analyzing trace with hash -1265742331, now seen corresponding path program 1 times [2024-11-13 14:29:21,466 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:21,466 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1949675224] [2024-11-13 14:29:21,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:21,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:21,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:21,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:21,549 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:21,549 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1949675224] [2024-11-13 14:29:21,549 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1949675224] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:21,549 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:21,549 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:29:21,550 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1269891049] [2024-11-13 14:29:21,550 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:21,550 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:29:21,550 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:29:21,550 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 14:29:21,550 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 14:29:21,551 INFO L87 Difference]: Start difference. First operand 2241 states and 3115 transitions. cyclomatic complexity: 882 Second operand has 5 states, 5 states have (on average 14.4) internal successors, (72), 5 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:21,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:29:21,662 INFO L93 Difference]: Finished difference Result 2297 states and 3171 transitions. [2024-11-13 14:29:21,662 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2297 states and 3171 transitions. [2024-11-13 14:29:21,676 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2212 [2024-11-13 14:29:21,688 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2297 states to 2297 states and 3171 transitions. [2024-11-13 14:29:21,688 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2297 [2024-11-13 14:29:21,691 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2297 [2024-11-13 14:29:21,691 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2297 states and 3171 transitions. [2024-11-13 14:29:21,696 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:29:21,696 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2297 states and 3171 transitions. [2024-11-13 14:29:21,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2297 states and 3171 transitions. [2024-11-13 14:29:21,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2297 to 2265. [2024-11-13 14:29:21,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2265 states, 2265 states have (on average 1.3858719646799118) internal successors, (3139), 2264 states have internal predecessors, (3139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:21,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2265 states to 2265 states and 3139 transitions. [2024-11-13 14:29:21,745 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2265 states and 3139 transitions. [2024-11-13 14:29:21,746 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 14:29:21,747 INFO L424 stractBuchiCegarLoop]: Abstraction has 2265 states and 3139 transitions. [2024-11-13 14:29:21,747 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 14:29:21,747 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2265 states and 3139 transitions. [2024-11-13 14:29:21,759 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2180 [2024-11-13 14:29:21,759 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:21,759 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:21,760 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:21,760 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:21,760 INFO L745 eck$LassoCheckResult]: Stem: 40412#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 40413#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 40492#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40493#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40309#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 40310#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40525#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40410#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40244#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40245#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40263#L502 assume !(0 == ~M_E~0); 40264#L502-2 assume !(0 == ~T1_E~0); 40230#L507-1 assume !(0 == ~T2_E~0); 40231#L512-1 assume !(0 == ~T3_E~0); 40311#L517-1 assume !(0 == ~T4_E~0); 40218#L522-1 assume !(0 == ~E_1~0); 40219#L527-1 assume !(0 == ~E_2~0); 40415#L532-1 assume !(0 == ~E_3~0); 40416#L537-1 assume !(0 == ~E_4~0); 40434#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40408#L238 assume !(1 == ~m_pc~0); 40409#L238-2 is_master_triggered_~__retres1~0#1 := 0; 40463#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40390#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 40388#L615 assume !(0 != activate_threads_~tmp~1#1); 40389#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40370#L257 assume !(1 == ~t1_pc~0); 40371#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40406#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40261#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 40262#L623 assume !(0 != activate_threads_~tmp___0~0#1); 40246#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40247#L276 assume !(1 == ~t2_pc~0); 40498#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 40594#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40496#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 40497#L631 assume !(0 != activate_threads_~tmp___1~0#1); 40636#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40387#L295 assume !(1 == ~t3_pc~0); 40250#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40251#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40213#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 40214#L639 assume !(0 != activate_threads_~tmp___2~0#1); 40624#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40625#L314 assume !(1 == ~t4_pc~0); 40269#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 40268#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40301#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 40302#L647 assume !(0 != activate_threads_~tmp___3~0#1); 40369#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40589#L555 assume !(1 == ~M_E~0); 40277#L555-2 assume !(1 == ~T1_E~0); 40278#L560-1 assume !(1 == ~T2_E~0); 40220#L565-1 assume !(1 == ~T3_E~0); 40221#L570-1 assume !(1 == ~T4_E~0); 40376#L575-1 assume !(1 == ~E_1~0); 40531#L580-1 assume !(1 == ~E_2~0); 40427#L585-1 assume !(1 == ~E_3~0); 40258#L590-1 assume !(1 == ~E_4~0); 40252#L595-1 assume { :end_inline_reset_delta_events } true; 40253#L776-2 [2024-11-13 14:29:21,761 INFO L747 eck$LassoCheckResult]: Loop: 40253#L776-2 assume !false; 41274#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41269#L477-1 assume !false; 41267#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 41140#L374 assume !(0 == ~m_st~0); 41141#L378 assume !(0 == ~t1_st~0); 41143#L382 assume !(0 == ~t2_st~0); 41138#L386 assume !(0 == ~t3_st~0); 41139#L390 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 41142#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 42399#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42396#L416 assume !(0 != eval_~tmp~0#1); 42397#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42423#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42422#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 42421#L502-5 assume !(0 == ~T1_E~0); 42420#L507-3 assume !(0 == ~T2_E~0); 40307#L512-3 assume !(0 == ~T3_E~0); 40308#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40295#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40296#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40372#L532-3 assume !(0 == ~E_3~0); 40442#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40315#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40316#L238-15 assume !(1 == ~m_pc~0); 42363#L238-17 is_master_triggered_~__retres1~0#1 := 0; 42426#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42425#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 42424#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42354#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42352#L257-15 assume !(1 == ~t1_pc~0); 42350#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 42348#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42346#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 42344#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42342#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42340#L276-15 assume !(1 == ~t2_pc~0); 42336#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 42334#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42332#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 42330#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 42327#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42325#L295-15 assume !(1 == ~t3_pc~0); 42322#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 42320#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42318#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 42316#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42315#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42314#L314-15 assume 1 == ~t4_pc~0; 42312#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 42311#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42310#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 42308#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42306#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42304#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42302#L555-5 assume !(1 == ~T1_E~0); 42300#L560-3 assume !(1 == ~T2_E~0); 42298#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42296#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42294#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42292#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42290#L585-3 assume !(1 == ~E_3~0); 42288#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 42286#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 42199#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 42194#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 41952#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 41949#L795 assume !(0 == start_simulation_~tmp~3#1); 41806#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 41803#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 41652#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 41286#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 41284#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41282#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41280#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 41278#L808 assume !(0 != start_simulation_~tmp___0~1#1); 40253#L776-2 [2024-11-13 14:29:21,761 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:21,761 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 2 times [2024-11-13 14:29:21,761 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:21,761 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [680947497] [2024-11-13 14:29:21,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:21,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:21,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:21,774 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:29:21,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:21,797 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:29:21,797 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:21,797 INFO L85 PathProgramCache]: Analyzing trace with hash -1868606599, now seen corresponding path program 1 times [2024-11-13 14:29:21,798 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:21,798 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2014404597] [2024-11-13 14:29:21,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:21,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:21,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:21,890 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:21,890 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:21,890 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2014404597] [2024-11-13 14:29:21,890 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2014404597] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:21,890 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:21,890 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:29:21,890 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1546282764] [2024-11-13 14:29:21,891 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:21,891 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:29:21,891 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:29:21,891 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 14:29:21,892 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 14:29:21,892 INFO L87 Difference]: Start difference. First operand 2265 states and 3139 transitions. cyclomatic complexity: 882 Second operand has 5 states, 5 states have (on average 15.2) internal successors, (76), 5 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:22,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:29:22,088 INFO L93 Difference]: Finished difference Result 2325 states and 3182 transitions. [2024-11-13 14:29:22,088 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2325 states and 3182 transitions. [2024-11-13 14:29:22,102 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2240 [2024-11-13 14:29:22,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2325 states to 2325 states and 3182 transitions. [2024-11-13 14:29:22,114 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2325 [2024-11-13 14:29:22,116 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2325 [2024-11-13 14:29:22,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2325 states and 3182 transitions. [2024-11-13 14:29:22,121 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:29:22,121 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2325 states and 3182 transitions. [2024-11-13 14:29:22,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2325 states and 3182 transitions. [2024-11-13 14:29:22,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2325 to 2325. [2024-11-13 14:29:22,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2325 states, 2325 states have (on average 1.3686021505376345) internal successors, (3182), 2324 states have internal predecessors, (3182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:22,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2325 states to 2325 states and 3182 transitions. [2024-11-13 14:29:22,170 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2325 states and 3182 transitions. [2024-11-13 14:29:22,170 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 14:29:22,171 INFO L424 stractBuchiCegarLoop]: Abstraction has 2325 states and 3182 transitions. [2024-11-13 14:29:22,171 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 14:29:22,171 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2325 states and 3182 transitions. [2024-11-13 14:29:22,183 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2240 [2024-11-13 14:29:22,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:22,184 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:22,185 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:22,185 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:22,185 INFO L745 eck$LassoCheckResult]: Stem: 45008#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 45009#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 45088#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45089#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44907#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 44908#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45121#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45006#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 44842#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 44843#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44861#L502 assume !(0 == ~M_E~0); 44862#L502-2 assume !(0 == ~T1_E~0); 44828#L507-1 assume !(0 == ~T2_E~0); 44829#L512-1 assume !(0 == ~T3_E~0); 44909#L517-1 assume !(0 == ~T4_E~0); 44816#L522-1 assume !(0 == ~E_1~0); 44817#L527-1 assume !(0 == ~E_2~0); 45011#L532-1 assume !(0 == ~E_3~0); 45012#L537-1 assume !(0 == ~E_4~0); 45031#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45004#L238 assume !(1 == ~m_pc~0); 45005#L238-2 is_master_triggered_~__retres1~0#1 := 0; 45059#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44985#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 44983#L615 assume !(0 != activate_threads_~tmp~1#1); 44984#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44966#L257 assume !(1 == ~t1_pc~0); 44967#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 45000#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44859#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 44860#L623 assume !(0 != activate_threads_~tmp___0~0#1); 44844#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44845#L276 assume !(1 == ~t2_pc~0); 45095#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45187#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45093#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 45094#L631 assume !(0 != activate_threads_~tmp___1~0#1); 45228#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44982#L295 assume !(1 == ~t3_pc~0); 44848#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44849#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44811#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 44812#L639 assume !(0 != activate_threads_~tmp___2~0#1); 45217#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45218#L314 assume !(1 == ~t4_pc~0); 44867#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 44866#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44899#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 44900#L647 assume !(0 != activate_threads_~tmp___3~0#1); 44965#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45183#L555 assume !(1 == ~M_E~0); 44875#L555-2 assume !(1 == ~T1_E~0); 44876#L560-1 assume !(1 == ~T2_E~0); 44818#L565-1 assume !(1 == ~T3_E~0); 44819#L570-1 assume !(1 == ~T4_E~0); 44972#L575-1 assume !(1 == ~E_1~0); 45127#L580-1 assume !(1 == ~E_2~0); 45023#L585-1 assume !(1 == ~E_3~0); 44856#L590-1 assume !(1 == ~E_4~0); 44850#L595-1 assume { :end_inline_reset_delta_events } true; 44851#L776-2 [2024-11-13 14:29:22,185 INFO L747 eck$LassoCheckResult]: Loop: 44851#L776-2 assume !false; 44833#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44834#L477-1 assume !false; 45149#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 45150#L374 assume !(0 == ~m_st~0); 45201#L378 assume !(0 == ~t1_st~0); 44953#L382 assume !(0 == ~t2_st~0); 44955#L386 assume !(0 == ~t3_st~0); 45047#L390 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 45056#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 47108#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 47107#L416 assume !(0 != eval_~tmp~0#1); 47106#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45190#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44946#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44947#L502-5 assume !(0 == ~T1_E~0); 45202#L507-3 assume !(0 == ~T2_E~0); 44905#L512-3 assume !(0 == ~T3_E~0); 44906#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44893#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44894#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44968#L532-3 assume !(0 == ~E_3~0); 45039#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44913#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44914#L238-15 assume !(1 == ~m_pc~0); 44960#L238-17 is_master_triggered_~__retres1~0#1 := 0; 47110#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47109#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 45137#L615-15 assume !(0 != activate_threads_~tmp~1#1); 45053#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45054#L257-15 assume !(1 == ~t1_pc~0); 44939#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 44940#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45155#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 45156#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45207#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45214#L276-15 assume 1 == ~t2_pc~0; 45168#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 45169#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47117#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 47115#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45081#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44846#L295-15 assume !(1 == ~t3_pc~0); 44847#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 45074#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45223#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 45062#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45013#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45014#L314-15 assume 1 == ~t4_pc~0; 45060#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45082#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45083#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45208#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45010#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44958#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 44959#L555-5 assume !(1 == ~T1_E~0); 44882#L560-3 assume !(1 == ~T2_E~0); 44883#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45209#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45191#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45098#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 45099#L585-3 assume !(1 == ~E_3~0); 45143#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45144#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 45063#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 44838#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 44938#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 44980#L795 assume !(0 == start_simulation_~tmp~3#1); 44981#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 44996#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 44997#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 44857#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 44858#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44877#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44878#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 45186#L808 assume !(0 != start_simulation_~tmp___0~1#1); 44851#L776-2 [2024-11-13 14:29:22,186 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:22,186 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 3 times [2024-11-13 14:29:22,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:22,186 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1233781028] [2024-11-13 14:29:22,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:22,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:22,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:22,199 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:29:22,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:22,220 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:29:22,221 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:22,221 INFO L85 PathProgramCache]: Analyzing trace with hash 64931034, now seen corresponding path program 1 times [2024-11-13 14:29:22,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:22,221 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [277868910] [2024-11-13 14:29:22,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:22,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:22,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:22,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:22,276 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:22,276 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [277868910] [2024-11-13 14:29:22,276 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [277868910] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:22,276 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:22,276 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:29:22,276 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1466736374] [2024-11-13 14:29:22,276 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:22,277 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:29:22,277 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:29:22,277 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:29:22,277 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:29:22,278 INFO L87 Difference]: Start difference. First operand 2325 states and 3182 transitions. cyclomatic complexity: 865 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:22,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:29:22,361 INFO L93 Difference]: Finished difference Result 3819 states and 5144 transitions. [2024-11-13 14:29:22,362 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3819 states and 5144 transitions. [2024-11-13 14:29:22,433 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 3720 [2024-11-13 14:29:22,451 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3819 states to 3819 states and 5144 transitions. [2024-11-13 14:29:22,452 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3819 [2024-11-13 14:29:22,456 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3819 [2024-11-13 14:29:22,457 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3819 states and 5144 transitions. [2024-11-13 14:29:22,464 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:29:22,464 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3819 states and 5144 transitions. [2024-11-13 14:29:22,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3819 states and 5144 transitions. [2024-11-13 14:29:22,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3819 to 3683. [2024-11-13 14:29:22,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3683 states, 3683 states have (on average 1.3494433885419495) internal successors, (4970), 3682 states have internal predecessors, (4970), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:22,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3683 states to 3683 states and 4970 transitions. [2024-11-13 14:29:22,549 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3683 states and 4970 transitions. [2024-11-13 14:29:22,549 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:29:22,550 INFO L424 stractBuchiCegarLoop]: Abstraction has 3683 states and 4970 transitions. [2024-11-13 14:29:22,550 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 14:29:22,550 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3683 states and 4970 transitions. [2024-11-13 14:29:22,569 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 3584 [2024-11-13 14:29:22,569 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:22,569 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:22,570 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:22,570 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:22,571 INFO L745 eck$LassoCheckResult]: Stem: 51160#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 51161#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 51244#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 51245#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51055#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 51056#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51275#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 51157#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50992#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50993#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 51011#L502 assume !(0 == ~M_E~0); 51012#L502-2 assume !(0 == ~T1_E~0); 50981#L507-1 assume !(0 == ~T2_E~0); 50982#L512-1 assume !(0 == ~T3_E~0); 51059#L517-1 assume !(0 == ~T4_E~0); 50968#L522-1 assume !(0 == ~E_1~0); 50969#L527-1 assume !(0 == ~E_2~0); 51163#L532-1 assume !(0 == ~E_3~0); 51164#L537-1 assume !(0 == ~E_4~0); 51184#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51155#L238 assume !(1 == ~m_pc~0); 51156#L238-2 is_master_triggered_~__retres1~0#1 := 0; 51212#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51137#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 51135#L615 assume !(0 != activate_threads_~tmp~1#1); 51136#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51117#L257 assume !(1 == ~t1_pc~0); 51118#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 51154#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51009#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 51010#L623 assume !(0 != activate_threads_~tmp___0~0#1); 50994#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50995#L276 assume !(1 == ~t2_pc~0); 51250#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 51343#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51248#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 51249#L631 assume !(0 != activate_threads_~tmp___1~0#1); 51389#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51134#L295 assume !(1 == ~t3_pc~0); 50998#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 50999#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50961#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 50962#L639 assume !(0 != activate_threads_~tmp___2~0#1); 51371#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51372#L314 assume !(1 == ~t4_pc~0); 51017#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51016#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51048#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 51049#L647 assume !(0 != activate_threads_~tmp___3~0#1); 51116#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51339#L555 assume !(1 == ~M_E~0); 51025#L555-2 assume !(1 == ~T1_E~0); 51026#L560-1 assume !(1 == ~T2_E~0); 50970#L565-1 assume !(1 == ~T3_E~0); 50971#L570-1 assume !(1 == ~T4_E~0); 51123#L575-1 assume !(1 == ~E_1~0); 51282#L580-1 assume !(1 == ~E_2~0); 51176#L585-1 assume !(1 == ~E_3~0); 51008#L590-1 assume !(1 == ~E_4~0); 51000#L595-1 assume { :end_inline_reset_delta_events } true; 51001#L776-2 assume !false; 54219#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54213#L477-1 [2024-11-13 14:29:22,571 INFO L747 eck$LassoCheckResult]: Loop: 54213#L477-1 assume !false; 54211#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 54209#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 54208#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 54207#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 54173#L416 assume 0 != eval_~tmp~0#1; 54171#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 51399#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 51331#L424-2 havoc eval_~tmp_ndt_1~0#1; 51332#L421-1 assume !(0 == ~t1_st~0); 54080#L435-1 assume !(0 == ~t2_st~0); 54076#L449-1 assume !(0 == ~t3_st~0); 54077#L463-1 assume !(0 == ~t4_st~0); 54213#L477-1 [2024-11-13 14:29:22,571 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:22,571 INFO L85 PathProgramCache]: Analyzing trace with hash 9663277, now seen corresponding path program 1 times [2024-11-13 14:29:22,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:22,572 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [329056199] [2024-11-13 14:29:22,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:22,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:22,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:22,587 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:29:22,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:22,604 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:29:22,604 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:22,607 INFO L85 PathProgramCache]: Analyzing trace with hash -1638329420, now seen corresponding path program 1 times [2024-11-13 14:29:22,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:22,607 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [542887938] [2024-11-13 14:29:22,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:22,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:22,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:22,613 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:29:22,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:22,618 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:29:22,620 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:22,620 INFO L85 PathProgramCache]: Analyzing trace with hash -665376760, now seen corresponding path program 1 times [2024-11-13 14:29:22,620 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:22,621 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1743111855] [2024-11-13 14:29:22,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:22,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:22,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:22,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:22,687 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:22,687 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1743111855] [2024-11-13 14:29:22,687 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1743111855] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:22,687 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:22,688 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:29:22,688 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [29328252] [2024-11-13 14:29:22,688 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:22,804 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:29:22,804 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:29:22,804 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:29:22,804 INFO L87 Difference]: Start difference. First operand 3683 states and 4970 transitions. cyclomatic complexity: 1299 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:22,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:29:22,932 INFO L93 Difference]: Finished difference Result 6850 states and 9143 transitions. [2024-11-13 14:29:22,932 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6850 states and 9143 transitions. [2024-11-13 14:29:22,978 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 6080 [2024-11-13 14:29:23,015 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6850 states to 6850 states and 9143 transitions. [2024-11-13 14:29:23,015 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6850 [2024-11-13 14:29:23,023 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6850 [2024-11-13 14:29:23,023 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6850 states and 9143 transitions. [2024-11-13 14:29:23,036 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:29:23,037 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6850 states and 9143 transitions. [2024-11-13 14:29:23,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6850 states and 9143 transitions. [2024-11-13 14:29:23,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6850 to 6630. [2024-11-13 14:29:23,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6630 states, 6630 states have (on average 1.3368024132730014) internal successors, (8863), 6629 states have internal predecessors, (8863), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:23,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6630 states to 6630 states and 8863 transitions. [2024-11-13 14:29:23,191 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6630 states and 8863 transitions. [2024-11-13 14:29:23,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:29:23,192 INFO L424 stractBuchiCegarLoop]: Abstraction has 6630 states and 8863 transitions. [2024-11-13 14:29:23,192 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 14:29:23,192 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6630 states and 8863 transitions. [2024-11-13 14:29:23,225 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 5860 [2024-11-13 14:29:23,226 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:23,226 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:23,227 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:23,227 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:23,227 INFO L745 eck$LassoCheckResult]: Stem: 61705#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 61706#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 61798#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 61799#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 61600#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 61601#L341-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 61835#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61702#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61533#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 61534#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61552#L502 assume !(0 == ~M_E~0); 61553#L502-2 assume !(0 == ~T1_E~0); 61519#L507-1 assume !(0 == ~T2_E~0); 61520#L512-1 assume !(0 == ~T3_E~0); 61602#L517-1 assume !(0 == ~T4_E~0); 61507#L522-1 assume !(0 == ~E_1~0); 61508#L527-1 assume !(0 == ~E_2~0); 61708#L532-1 assume !(0 == ~E_3~0); 61709#L537-1 assume !(0 == ~E_4~0); 61729#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61700#L238 assume !(1 == ~m_pc~0); 61701#L238-2 is_master_triggered_~__retres1~0#1 := 0; 61763#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61683#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 61681#L615 assume !(0 != activate_threads_~tmp~1#1); 61682#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61661#L257 assume !(1 == ~t1_pc~0); 61662#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 61697#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61550#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 61551#L623 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 61807#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65919#L276 assume !(1 == ~t2_pc~0); 65916#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 65915#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61803#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 61804#L631 assume !(0 != activate_threads_~tmp___1~0#1); 65911#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65909#L295 assume !(1 == ~t3_pc~0); 61539#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 61540#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61502#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 61503#L639 assume !(0 != activate_threads_~tmp___2~0#1); 65898#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65896#L314 assume !(1 == ~t4_pc~0); 61558#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 61557#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65878#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 65876#L647 assume !(0 != activate_threads_~tmp___3~0#1); 61900#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61901#L555 assume !(1 == ~M_E~0); 61566#L555-2 assume !(1 == ~T1_E~0); 61567#L560-1 assume !(1 == ~T2_E~0); 61978#L565-1 assume !(1 == ~T3_E~0); 65820#L570-1 assume !(1 == ~T4_E~0); 65818#L575-1 assume !(1 == ~E_1~0); 65816#L580-1 assume !(1 == ~E_2~0); 65815#L585-1 assume !(1 == ~E_3~0); 61547#L590-1 assume !(1 == ~E_4~0); 61541#L595-1 assume { :end_inline_reset_delta_events } true; 61542#L776-2 assume !false; 66148#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 66144#L477-1 [2024-11-13 14:29:23,227 INFO L747 eck$LassoCheckResult]: Loop: 66144#L477-1 assume !false; 66143#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 66142#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 66141#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 66140#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 66138#L416 assume 0 != eval_~tmp~0#1; 66136#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 61984#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 61985#L424-2 havoc eval_~tmp_ndt_1~0#1; 66139#L421-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 65809#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 66137#L438-2 havoc eval_~tmp_ndt_2~0#1; 66157#L435-1 assume !(0 == ~t2_st~0); 66152#L449-1 assume !(0 == ~t3_st~0); 66146#L463-1 assume !(0 == ~t4_st~0); 66144#L477-1 [2024-11-13 14:29:23,228 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:23,228 INFO L85 PathProgramCache]: Analyzing trace with hash 995820913, now seen corresponding path program 1 times [2024-11-13 14:29:23,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:23,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [890733030] [2024-11-13 14:29:23,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:23,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:23,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:23,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:23,263 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:23,263 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [890733030] [2024-11-13 14:29:23,263 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [890733030] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:23,263 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:23,263 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:29:23,263 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2063425719] [2024-11-13 14:29:23,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:23,264 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:29:23,264 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:23,264 INFO L85 PathProgramCache]: Analyzing trace with hash 1545253964, now seen corresponding path program 1 times [2024-11-13 14:29:23,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:23,264 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [413411832] [2024-11-13 14:29:23,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:23,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:23,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:23,269 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:29:23,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:23,274 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:29:23,373 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:29:23,373 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:29:23,373 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:29:23,373 INFO L87 Difference]: Start difference. First operand 6630 states and 8863 transitions. cyclomatic complexity: 2251 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:23,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:29:23,405 INFO L93 Difference]: Finished difference Result 4386 states and 5863 transitions. [2024-11-13 14:29:23,405 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4386 states and 5863 transitions. [2024-11-13 14:29:23,431 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 4279 [2024-11-13 14:29:23,450 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4386 states to 4386 states and 5863 transitions. [2024-11-13 14:29:23,451 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4386 [2024-11-13 14:29:23,456 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4386 [2024-11-13 14:29:23,456 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4386 states and 5863 transitions. [2024-11-13 14:29:23,463 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:29:23,463 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4386 states and 5863 transitions. [2024-11-13 14:29:23,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4386 states and 5863 transitions. [2024-11-13 14:29:23,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4386 to 4386. [2024-11-13 14:29:23,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4386 states, 4386 states have (on average 1.3367533059735521) internal successors, (5863), 4385 states have internal predecessors, (5863), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:23,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4386 states to 4386 states and 5863 transitions. [2024-11-13 14:29:23,548 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4386 states and 5863 transitions. [2024-11-13 14:29:23,548 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:29:23,549 INFO L424 stractBuchiCegarLoop]: Abstraction has 4386 states and 5863 transitions. [2024-11-13 14:29:23,549 INFO L331 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-13 14:29:23,549 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4386 states and 5863 transitions. [2024-11-13 14:29:23,611 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 4279 [2024-11-13 14:29:23,612 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:23,612 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:23,613 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:23,613 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:23,613 INFO L745 eck$LassoCheckResult]: Stem: 72721#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 72722#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 72811#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 72812#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 72620#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 72621#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 72842#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 72719#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 72555#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 72556#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 72574#L502 assume !(0 == ~M_E~0); 72575#L502-2 assume !(0 == ~T1_E~0); 72541#L507-1 assume !(0 == ~T2_E~0); 72542#L512-1 assume !(0 == ~T3_E~0); 72622#L517-1 assume !(0 == ~T4_E~0); 72529#L522-1 assume !(0 == ~E_1~0); 72530#L527-1 assume !(0 == ~E_2~0); 72725#L532-1 assume !(0 == ~E_3~0); 72726#L537-1 assume !(0 == ~E_4~0); 72746#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 72717#L238 assume !(1 == ~m_pc~0); 72718#L238-2 is_master_triggered_~__retres1~0#1 := 0; 72781#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 72701#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 72699#L615 assume !(0 != activate_threads_~tmp~1#1); 72700#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72681#L257 assume !(1 == ~t1_pc~0); 72682#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 72714#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 72572#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 72573#L623 assume !(0 != activate_threads_~tmp___0~0#1); 72557#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72558#L276 assume !(1 == ~t2_pc~0); 72817#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 72911#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 72815#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 72816#L631 assume !(0 != activate_threads_~tmp___1~0#1); 72962#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72698#L295 assume !(1 == ~t3_pc~0); 72561#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 72562#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 72524#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 72525#L639 assume !(0 != activate_threads_~tmp___2~0#1); 72945#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 72946#L314 assume !(1 == ~t4_pc~0); 72580#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 72579#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 72612#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 72613#L647 assume !(0 != activate_threads_~tmp___3~0#1); 72680#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 72906#L555 assume !(1 == ~M_E~0); 72588#L555-2 assume !(1 == ~T1_E~0); 72589#L560-1 assume !(1 == ~T2_E~0); 72531#L565-1 assume !(1 == ~T3_E~0); 72532#L570-1 assume !(1 == ~T4_E~0); 72687#L575-1 assume !(1 == ~E_1~0); 72848#L580-1 assume !(1 == ~E_2~0); 72737#L585-1 assume !(1 == ~E_3~0); 72569#L590-1 assume !(1 == ~E_4~0); 72563#L595-1 assume { :end_inline_reset_delta_events } true; 72564#L776-2 assume !false; 73069#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 73062#L477-1 [2024-11-13 14:29:23,614 INFO L747 eck$LassoCheckResult]: Loop: 73062#L477-1 assume !false; 73060#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 73057#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 73054#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 73052#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 73050#L416 assume 0 != eval_~tmp~0#1; 73047#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 73043#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 73044#L424-2 havoc eval_~tmp_ndt_1~0#1; 73108#L421-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 73104#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 73099#L438-2 havoc eval_~tmp_ndt_2~0#1; 73090#L435-1 assume !(0 == ~t2_st~0); 73078#L449-1 assume !(0 == ~t3_st~0); 73067#L463-1 assume !(0 == ~t4_st~0); 73062#L477-1 [2024-11-13 14:29:23,614 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:23,614 INFO L85 PathProgramCache]: Analyzing trace with hash 9663277, now seen corresponding path program 2 times [2024-11-13 14:29:23,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:23,615 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [478615622] [2024-11-13 14:29:23,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:23,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:23,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:23,628 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:29:23,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:23,645 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:29:23,646 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:23,646 INFO L85 PathProgramCache]: Analyzing trace with hash 1545253964, now seen corresponding path program 2 times [2024-11-13 14:29:23,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:23,647 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [884746261] [2024-11-13 14:29:23,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:23,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:23,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:23,653 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:29:23,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:23,658 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:29:23,659 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:23,659 INFO L85 PathProgramCache]: Analyzing trace with hash 249889696, now seen corresponding path program 1 times [2024-11-13 14:29:23,659 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:23,659 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [745749076] [2024-11-13 14:29:23,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:23,660 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:23,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:23,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:23,732 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:23,732 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [745749076] [2024-11-13 14:29:23,732 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [745749076] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:23,733 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:23,733 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:29:23,733 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [491765405] [2024-11-13 14:29:23,733 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:23,835 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:29:23,836 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:29:23,836 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:29:23,837 INFO L87 Difference]: Start difference. First operand 4386 states and 5863 transitions. cyclomatic complexity: 1489 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:23,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:29:23,961 INFO L93 Difference]: Finished difference Result 7743 states and 10293 transitions. [2024-11-13 14:29:23,961 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7743 states and 10293 transitions. [2024-11-13 14:29:24,008 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7596 [2024-11-13 14:29:24,052 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7743 states to 7743 states and 10293 transitions. [2024-11-13 14:29:24,052 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7743 [2024-11-13 14:29:24,063 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7743 [2024-11-13 14:29:24,063 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7743 states and 10293 transitions. [2024-11-13 14:29:24,077 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:29:24,078 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7743 states and 10293 transitions. [2024-11-13 14:29:24,088 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7743 states and 10293 transitions. [2024-11-13 14:29:24,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7743 to 7323. [2024-11-13 14:29:24,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7323 states, 7323 states have (on average 1.3318312167144613) internal successors, (9753), 7322 states have internal predecessors, (9753), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:24,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7323 states to 7323 states and 9753 transitions. [2024-11-13 14:29:24,265 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7323 states and 9753 transitions. [2024-11-13 14:29:24,266 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:29:24,267 INFO L424 stractBuchiCegarLoop]: Abstraction has 7323 states and 9753 transitions. [2024-11-13 14:29:24,267 INFO L331 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-13 14:29:24,267 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7323 states and 9753 transitions. [2024-11-13 14:29:24,294 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7176 [2024-11-13 14:29:24,294 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:24,294 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:24,295 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:24,295 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:24,296 INFO L745 eck$LassoCheckResult]: Stem: 84858#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 84859#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 84945#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 84946#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 84755#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 84756#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 84981#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 84856#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 84691#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 84692#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 84711#L502 assume !(0 == ~M_E~0); 84712#L502-2 assume !(0 == ~T1_E~0); 84681#L507-1 assume !(0 == ~T2_E~0); 84682#L512-1 assume !(0 == ~T3_E~0); 84758#L517-1 assume !(0 == ~T4_E~0); 84666#L522-1 assume !(0 == ~E_1~0); 84667#L527-1 assume !(0 == ~E_2~0); 84861#L532-1 assume !(0 == ~E_3~0); 84862#L537-1 assume !(0 == ~E_4~0); 84883#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84854#L238 assume !(1 == ~m_pc~0); 84855#L238-2 is_master_triggered_~__retres1~0#1 := 0; 84915#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84836#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 84834#L615 assume !(0 != activate_threads_~tmp~1#1); 84835#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84816#L257 assume !(1 == ~t1_pc~0); 84817#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 84852#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84709#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 84710#L623 assume !(0 != activate_threads_~tmp___0~0#1); 84693#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84694#L276 assume !(1 == ~t2_pc~0); 84953#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 85056#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 84951#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 84952#L631 assume !(0 != activate_threads_~tmp___1~0#1); 85098#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 84833#L295 assume !(1 == ~t3_pc~0); 84698#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 84699#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 84661#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 84662#L639 assume !(0 != activate_threads_~tmp___2~0#1); 85088#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85089#L314 assume !(1 == ~t4_pc~0); 84717#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 84716#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84748#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 84749#L647 assume !(0 != activate_threads_~tmp___3~0#1); 84815#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85052#L555 assume !(1 == ~M_E~0); 84725#L555-2 assume !(1 == ~T1_E~0); 84726#L560-1 assume !(1 == ~T2_E~0); 84668#L565-1 assume !(1 == ~T3_E~0); 84669#L570-1 assume !(1 == ~T4_E~0); 84822#L575-1 assume !(1 == ~E_1~0); 84987#L580-1 assume !(1 == ~E_2~0); 84875#L585-1 assume !(1 == ~E_3~0); 84708#L590-1 assume !(1 == ~E_4~0); 84700#L595-1 assume { :end_inline_reset_delta_events } true; 84701#L776-2 assume !false; 85847#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85839#L477-1 [2024-11-13 14:29:24,296 INFO L747 eck$LassoCheckResult]: Loop: 85839#L477-1 assume !false; 85836#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 85831#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 85827#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 85824#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 85821#L416 assume 0 != eval_~tmp~0#1; 85816#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 85810#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 85806#L424-2 havoc eval_~tmp_ndt_1~0#1; 85803#L421-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 85794#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 85796#L438-2 havoc eval_~tmp_ndt_2~0#1; 85865#L435-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 85863#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 85861#L452-2 havoc eval_~tmp_ndt_3~0#1; 85859#L449-1 assume !(0 == ~t3_st~0); 85845#L463-1 assume !(0 == ~t4_st~0); 85839#L477-1 [2024-11-13 14:29:24,297 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:24,297 INFO L85 PathProgramCache]: Analyzing trace with hash 9663277, now seen corresponding path program 3 times [2024-11-13 14:29:24,298 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:24,298 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [876341551] [2024-11-13 14:29:24,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:24,298 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:24,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:24,317 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:29:24,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:24,341 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:29:24,342 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:24,342 INFO L85 PathProgramCache]: Analyzing trace with hash -1216840460, now seen corresponding path program 1 times [2024-11-13 14:29:24,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:24,342 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [544920354] [2024-11-13 14:29:24,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:24,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:24,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:24,356 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:29:24,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:24,364 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:29:24,367 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:24,368 INFO L85 PathProgramCache]: Analyzing trace with hash -521386168, now seen corresponding path program 1 times [2024-11-13 14:29:24,368 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:24,368 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [725143884] [2024-11-13 14:29:24,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:24,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:24,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:24,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:24,424 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:24,426 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [725143884] [2024-11-13 14:29:24,427 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [725143884] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:24,427 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:24,427 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:29:24,427 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [778611808] [2024-11-13 14:29:24,427 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:24,533 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:29:24,533 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:29:24,533 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:29:24,533 INFO L87 Difference]: Start difference. First operand 7323 states and 9753 transitions. cyclomatic complexity: 2442 Second operand has 3 states, 3 states have (on average 26.333333333333332) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:24,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:29:24,629 INFO L93 Difference]: Finished difference Result 9230 states and 12214 transitions. [2024-11-13 14:29:24,629 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9230 states and 12214 transitions. [2024-11-13 14:29:24,671 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9055 [2024-11-13 14:29:24,708 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9230 states to 9230 states and 12214 transitions. [2024-11-13 14:29:24,708 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9230 [2024-11-13 14:29:24,718 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9230 [2024-11-13 14:29:24,718 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9230 states and 12214 transitions. [2024-11-13 14:29:24,730 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:29:24,730 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9230 states and 12214 transitions. [2024-11-13 14:29:24,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9230 states and 12214 transitions. [2024-11-13 14:29:24,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9230 to 8966. [2024-11-13 14:29:24,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8966 states, 8966 states have (on average 1.3247825117109078) internal successors, (11878), 8965 states have internal predecessors, (11878), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:24,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8966 states to 8966 states and 11878 transitions. [2024-11-13 14:29:24,898 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8966 states and 11878 transitions. [2024-11-13 14:29:24,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:29:24,900 INFO L424 stractBuchiCegarLoop]: Abstraction has 8966 states and 11878 transitions. [2024-11-13 14:29:24,900 INFO L331 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-13 14:29:24,900 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8966 states and 11878 transitions. [2024-11-13 14:29:24,931 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8791 [2024-11-13 14:29:24,931 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:24,931 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:24,933 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:24,933 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:24,934 INFO L745 eck$LassoCheckResult]: Stem: 101427#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 101428#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 101527#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 101528#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 101318#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 101319#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 101566#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 101425#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 101252#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 101253#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 101272#L502 assume !(0 == ~M_E~0); 101273#L502-2 assume !(0 == ~T1_E~0); 101242#L507-1 assume !(0 == ~T2_E~0); 101243#L512-1 assume !(0 == ~T3_E~0); 101322#L517-1 assume !(0 == ~T4_E~0); 101227#L522-1 assume !(0 == ~E_1~0); 101228#L527-1 assume !(0 == ~E_2~0); 101430#L532-1 assume !(0 == ~E_3~0); 101431#L537-1 assume !(0 == ~E_4~0); 101455#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101423#L238 assume !(1 == ~m_pc~0); 101424#L238-2 is_master_triggered_~__retres1~0#1 := 0; 101486#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 101404#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 101402#L615 assume !(0 != activate_threads_~tmp~1#1); 101403#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 101383#L257 assume !(1 == ~t1_pc~0); 101384#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 101421#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 101270#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 101271#L623 assume !(0 != activate_threads_~tmp___0~0#1); 101254#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 101255#L276 assume !(1 == ~t2_pc~0); 101535#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 101650#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 101533#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 101534#L631 assume !(0 != activate_threads_~tmp___1~0#1); 101696#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101401#L295 assume !(1 == ~t3_pc~0); 101259#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 101260#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 101222#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 101223#L639 assume !(0 != activate_threads_~tmp___2~0#1); 101683#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101684#L314 assume !(1 == ~t4_pc~0); 101278#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 101277#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 101310#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 101311#L647 assume !(0 != activate_threads_~tmp___3~0#1); 101382#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 101643#L555 assume !(1 == ~M_E~0); 101286#L555-2 assume !(1 == ~T1_E~0); 101287#L560-1 assume !(1 == ~T2_E~0); 101229#L565-1 assume !(1 == ~T3_E~0); 101230#L570-1 assume !(1 == ~T4_E~0); 101390#L575-1 assume !(1 == ~E_1~0); 101573#L580-1 assume !(1 == ~E_2~0); 101443#L585-1 assume !(1 == ~E_3~0); 101269#L590-1 assume !(1 == ~E_4~0); 101261#L595-1 assume { :end_inline_reset_delta_events } true; 101262#L776-2 assume !false; 106159#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 106154#L477-1 [2024-11-13 14:29:24,934 INFO L747 eck$LassoCheckResult]: Loop: 106154#L477-1 assume !false; 106152#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 106149#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 106147#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 106138#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 106132#L416 assume 0 != eval_~tmp~0#1; 106126#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 106119#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 106116#L424-2 havoc eval_~tmp_ndt_1~0#1; 106114#L421-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 106111#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 106109#L438-2 havoc eval_~tmp_ndt_2~0#1; 106107#L435-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 106052#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 106105#L452-2 havoc eval_~tmp_ndt_3~0#1; 106173#L449-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 106171#L466 assume !(0 != eval_~tmp_ndt_4~0#1); 106169#L466-2 havoc eval_~tmp_ndt_4~0#1; 106157#L463-1 assume !(0 == ~t4_st~0); 106154#L477-1 [2024-11-13 14:29:24,935 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:24,935 INFO L85 PathProgramCache]: Analyzing trace with hash 9663277, now seen corresponding path program 4 times [2024-11-13 14:29:24,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:24,935 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [593041895] [2024-11-13 14:29:24,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:24,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:24,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:24,954 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:29:24,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:24,969 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:29:24,970 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:24,970 INFO L85 PathProgramCache]: Analyzing trace with hash -1157182580, now seen corresponding path program 1 times [2024-11-13 14:29:24,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:24,970 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [907888223] [2024-11-13 14:29:24,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:24,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:24,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:24,976 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:29:24,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:24,980 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:29:24,981 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:24,981 INFO L85 PathProgramCache]: Analyzing trace with hash 1454461152, now seen corresponding path program 1 times [2024-11-13 14:29:24,981 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:24,982 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905993017] [2024-11-13 14:29:24,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:24,982 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:24,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:29:25,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:29:25,040 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:29:25,040 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [905993017] [2024-11-13 14:29:25,040 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [905993017] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:29:25,041 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:29:25,041 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:29:25,041 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1790331985] [2024-11-13 14:29:25,041 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:29:25,202 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:29:25,203 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:29:25,203 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:29:25,203 INFO L87 Difference]: Start difference. First operand 8966 states and 11878 transitions. cyclomatic complexity: 2924 Second operand has 3 states, 2 states have (on average 40.5) internal successors, (81), 3 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:25,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:29:25,326 INFO L93 Difference]: Finished difference Result 17050 states and 22492 transitions. [2024-11-13 14:29:25,327 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17050 states and 22492 transitions. [2024-11-13 14:29:25,405 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 16767 [2024-11-13 14:29:25,485 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17050 states to 17050 states and 22492 transitions. [2024-11-13 14:29:25,485 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17050 [2024-11-13 14:29:25,515 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17050 [2024-11-13 14:29:25,515 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17050 states and 22492 transitions. [2024-11-13 14:29:25,536 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:29:25,536 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17050 states and 22492 transitions. [2024-11-13 14:29:25,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17050 states and 22492 transitions. [2024-11-13 14:29:25,745 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17050 to 17050. [2024-11-13 14:29:25,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17050 states, 17050 states have (on average 1.3191788856304985) internal successors, (22492), 17049 states have internal predecessors, (22492), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:29:25,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17050 states to 17050 states and 22492 transitions. [2024-11-13 14:29:25,831 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17050 states and 22492 transitions. [2024-11-13 14:29:25,832 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:29:25,832 INFO L424 stractBuchiCegarLoop]: Abstraction has 17050 states and 22492 transitions. [2024-11-13 14:29:25,833 INFO L331 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-13 14:29:25,833 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17050 states and 22492 transitions. [2024-11-13 14:29:25,893 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 16767 [2024-11-13 14:29:25,894 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:29:25,894 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:29:25,895 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:25,895 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:29:25,895 INFO L745 eck$LassoCheckResult]: Stem: 127445#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 127446#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 127533#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 127534#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 127342#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 127343#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 127570#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 127443#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 127276#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 127277#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 127296#L502 assume !(0 == ~M_E~0); 127297#L502-2 assume !(0 == ~T1_E~0); 127263#L507-1 assume !(0 == ~T2_E~0); 127264#L512-1 assume !(0 == ~T3_E~0); 127344#L517-1 assume !(0 == ~T4_E~0); 127251#L522-1 assume !(0 == ~E_1~0); 127252#L527-1 assume !(0 == ~E_2~0); 127448#L532-1 assume !(0 == ~E_3~0); 127449#L537-1 assume !(0 == ~E_4~0); 127470#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 127441#L238 assume !(1 == ~m_pc~0); 127442#L238-2 is_master_triggered_~__retres1~0#1 := 0; 127498#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 127425#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 127423#L615 assume !(0 != activate_threads_~tmp~1#1); 127424#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 127404#L257 assume !(1 == ~t1_pc~0); 127405#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 127438#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 127294#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 127295#L623 assume !(0 != activate_threads_~tmp___0~0#1); 127278#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 127279#L276 assume !(1 == ~t2_pc~0); 127540#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 127647#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 127538#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 127539#L631 assume !(0 != activate_threads_~tmp___1~0#1); 127687#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 127422#L295 assume !(1 == ~t3_pc~0); 127283#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 127284#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 127246#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 127247#L639 assume !(0 != activate_threads_~tmp___2~0#1); 127675#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 127676#L314 assume !(1 == ~t4_pc~0); 127302#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 127301#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 127334#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 127335#L647 assume !(0 != activate_threads_~tmp___3~0#1); 127403#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127642#L555 assume !(1 == ~M_E~0); 127310#L555-2 assume !(1 == ~T1_E~0); 127311#L560-1 assume !(1 == ~T2_E~0); 127253#L565-1 assume !(1 == ~T3_E~0); 127254#L570-1 assume !(1 == ~T4_E~0); 127410#L575-1 assume !(1 == ~E_1~0); 127577#L580-1 assume !(1 == ~E_2~0); 127460#L585-1 assume !(1 == ~E_3~0); 127291#L590-1 assume !(1 == ~E_4~0); 127285#L595-1 assume { :end_inline_reset_delta_events } true; 127286#L776-2 assume !false; 133601#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 133598#L477-1 [2024-11-13 14:29:25,896 INFO L747 eck$LassoCheckResult]: Loop: 133598#L477-1 assume !false; 133596#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 133592#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 133590#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 133588#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 133586#L416 assume 0 != eval_~tmp~0#1; 133582#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 133578#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 133576#L424-2 havoc eval_~tmp_ndt_1~0#1; 133574#L421-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 133571#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 133572#L438-2 havoc eval_~tmp_ndt_2~0#1; 133646#L435-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 133643#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 133641#L452-2 havoc eval_~tmp_ndt_3~0#1; 133638#L449-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 133635#L466 assume !(0 != eval_~tmp_ndt_4~0#1); 133636#L466-2 havoc eval_~tmp_ndt_4~0#1; 133605#L463-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 133602#L480 assume !(0 != eval_~tmp_ndt_5~0#1); 133600#L480-2 havoc eval_~tmp_ndt_5~0#1; 133598#L477-1 [2024-11-13 14:29:25,897 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:25,897 INFO L85 PathProgramCache]: Analyzing trace with hash 9663277, now seen corresponding path program 5 times [2024-11-13 14:29:25,897 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:25,898 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1126722251] [2024-11-13 14:29:25,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:25,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:25,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:25,913 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:29:25,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:25,933 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:29:25,934 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:25,934 INFO L85 PathProgramCache]: Analyzing trace with hash 344062116, now seen corresponding path program 1 times [2024-11-13 14:29:25,934 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:25,934 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [502882279] [2024-11-13 14:29:25,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:25,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:25,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:25,939 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:29:25,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:25,945 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:29:25,945 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:29:25,945 INFO L85 PathProgramCache]: Analyzing trace with hash 1872787704, now seen corresponding path program 1 times [2024-11-13 14:29:25,946 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:29:25,946 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1166739610] [2024-11-13 14:29:25,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:29:25,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:29:25,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:25,963 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:29:25,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:25,990 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:29:27,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:27,889 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:29:27,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:29:28,151 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.11 02:29:28 BoogieIcfgContainer [2024-11-13 14:29:28,152 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-13 14:29:28,152 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-13 14:29:28,156 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-13 14:29:28,156 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-13 14:29:28,157 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 02:29:15" (3/4) ... [2024-11-13 14:29:28,159 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-13 14:29:28,269 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac588a0d-f6db-4b6d-9d9e-c3549edb2ef9/bin/uautomizer-verify-qhAvR1uOyd/witness.graphml [2024-11-13 14:29:28,269 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-13 14:29:28,271 INFO L158 Benchmark]: Toolchain (without parser) took 14850.30ms. Allocated memory was 142.6MB in the beginning and 453.0MB in the end (delta: 310.4MB). Free memory was 110.7MB in the beginning and 246.2MB in the end (delta: -135.5MB). Peak memory consumption was 169.5MB. Max. memory is 16.1GB. [2024-11-13 14:29:28,271 INFO L158 Benchmark]: CDTParser took 1.35ms. Allocated memory is still 167.8MB. Free memory is still 105.2MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 14:29:28,271 INFO L158 Benchmark]: CACSL2BoogieTranslator took 482.29ms. Allocated memory is still 142.6MB. Free memory was 110.7MB in the beginning and 95.9MB in the end (delta: 14.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-13 14:29:28,272 INFO L158 Benchmark]: Boogie Procedure Inliner took 94.67ms. Allocated memory is still 142.6MB. Free memory was 95.9MB in the beginning and 92.1MB in the end (delta: 3.7MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 14:29:28,272 INFO L158 Benchmark]: Boogie Preprocessor took 103.81ms. Allocated memory is still 142.6MB. Free memory was 92.1MB in the beginning and 87.9MB in the end (delta: 4.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 14:29:28,272 INFO L158 Benchmark]: RCFGBuilder took 1498.30ms. Allocated memory is still 142.6MB. Free memory was 87.9MB in the beginning and 95.1MB in the end (delta: -7.2MB). Peak memory consumption was 48.7MB. Max. memory is 16.1GB. [2024-11-13 14:29:28,273 INFO L158 Benchmark]: BuchiAutomizer took 12547.59ms. Allocated memory was 142.6MB in the beginning and 453.0MB in the end (delta: 310.4MB). Free memory was 95.1MB in the beginning and 254.6MB in the end (delta: -159.4MB). Peak memory consumption was 145.9MB. Max. memory is 16.1GB. [2024-11-13 14:29:28,273 INFO L158 Benchmark]: Witness Printer took 117.07ms. Allocated memory is still 453.0MB. Free memory was 254.6MB in the beginning and 246.2MB in the end (delta: 8.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 14:29:28,276 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 1.35ms. Allocated memory is still 167.8MB. Free memory is still 105.2MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 482.29ms. Allocated memory is still 142.6MB. Free memory was 110.7MB in the beginning and 95.9MB in the end (delta: 14.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 94.67ms. Allocated memory is still 142.6MB. Free memory was 95.9MB in the beginning and 92.1MB in the end (delta: 3.7MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 103.81ms. Allocated memory is still 142.6MB. Free memory was 92.1MB in the beginning and 87.9MB in the end (delta: 4.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 1498.30ms. Allocated memory is still 142.6MB. Free memory was 87.9MB in the beginning and 95.1MB in the end (delta: -7.2MB). Peak memory consumption was 48.7MB. Max. memory is 16.1GB. * BuchiAutomizer took 12547.59ms. Allocated memory was 142.6MB in the beginning and 453.0MB in the end (delta: 310.4MB). Free memory was 95.1MB in the beginning and 254.6MB in the end (delta: -159.4MB). Peak memory consumption was 145.9MB. Max. memory is 16.1GB. * Witness Printer took 117.07ms. Allocated memory is still 453.0MB. Free memory was 254.6MB in the beginning and 246.2MB in the end (delta: 8.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 20 terminating modules (20 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.20 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 17050 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 12.2s and 21 iterations. TraceHistogramMax:1. Analysis of lassos took 6.5s. Construction of modules took 0.9s. Büchi inclusion checks took 4.1s. Highest rank in rank-based complementation 0. Minimization of det autom 20. Minimization of nondet autom 0. Automata minimization 1.7s AutomataMinimizationTime, 20 MinimizatonAttempts, 4926 StatesRemovedByMinimization, 11 NontrivialMinimizations. Non-live state removal took 0.9s Buchi closure took 0.1s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 9672 SdHoareTripleChecker+Valid, 1.2s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 9672 mSDsluCounter, 21544 SdHoareTripleChecker+Invalid, 1.0s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 9694 mSDsCounter, 202 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 574 IncrementalHoareTripleChecker+Invalid, 776 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 202 mSolverCounterUnsat, 11850 mSDtfsCounter, 574 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc4 concLT0 SILN1 SILU0 SILI12 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 411]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int m_i ; [L36] int t1_i ; [L37] int t2_i ; [L38] int t3_i ; [L39] int t4_i ; [L40] int M_E = 2; [L41] int T1_E = 2; [L42] int T2_E = 2; [L43] int T3_E = 2; [L44] int T4_E = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0] [L821] int __retres1 ; [L825] CALL init_model() [L733] m_i = 1 [L734] t1_i = 1 [L735] t2_i = 1 [L736] t3_i = 1 [L737] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L825] RET init_model() [L826] CALL start_simulation() [L762] int kernel_st ; [L763] int tmp ; [L764] int tmp___0 ; [L768] kernel_st = 0 [L769] FCALL update_channels() [L770] CALL init_threads() [L341] COND TRUE m_i == 1 [L342] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t1_i == 1 [L347] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t2_i == 1 [L352] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L356] COND TRUE t3_i == 1 [L357] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L361] COND TRUE t4_i == 1 [L362] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L770] RET init_threads() [L771] CALL fire_delta_events() [L502] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L537] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L542] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L771] RET fire_delta_events() [L772] CALL activate_threads() [L605] int tmp ; [L606] int tmp___0 ; [L607] int tmp___1 ; [L608] int tmp___2 ; [L609] int tmp___3 ; [L613] CALL, EXPR is_master_triggered() [L235] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L238] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L248] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L250] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L613] RET, EXPR is_master_triggered() [L613] tmp = is_master_triggered() [L615] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L621] CALL, EXPR is_transmit1_triggered() [L254] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L257] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L267] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L269] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L621] RET, EXPR is_transmit1_triggered() [L621] tmp___0 = is_transmit1_triggered() [L623] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L629] CALL, EXPR is_transmit2_triggered() [L273] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L276] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L286] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L288] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L629] RET, EXPR is_transmit2_triggered() [L629] tmp___1 = is_transmit2_triggered() [L631] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L637] CALL, EXPR is_transmit3_triggered() [L292] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L295] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L305] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L307] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L637] RET, EXPR is_transmit3_triggered() [L637] tmp___2 = is_transmit3_triggered() [L639] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L645] CALL, EXPR is_transmit4_triggered() [L311] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L314] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L324] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L326] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L645] RET, EXPR is_transmit4_triggered() [L645] tmp___3 = is_transmit4_triggered() [L647] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L772] RET activate_threads() [L773] CALL reset_delta_events() [L555] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L590] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L595] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L773] RET reset_delta_events() [L776] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L779] kernel_st = 1 [L780] CALL eval() [L407] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] Loop: [L411] COND TRUE 1 [L414] CALL, EXPR exists_runnable_thread() [L371] int __retres1 ; [L374] COND TRUE m_st == 0 [L375] __retres1 = 1 [L402] return (__retres1); [L414] RET, EXPR exists_runnable_thread() [L414] tmp = exists_runnable_thread() [L416] COND TRUE \read(tmp) [L421] COND TRUE m_st == 0 [L422] int tmp_ndt_1; [L423] tmp_ndt_1 = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp_ndt_1)) [L435] COND TRUE t1_st == 0 [L436] int tmp_ndt_2; [L437] tmp_ndt_2 = __VERIFIER_nondet_int() [L438] COND FALSE !(\read(tmp_ndt_2)) [L449] COND TRUE t2_st == 0 [L450] int tmp_ndt_3; [L451] tmp_ndt_3 = __VERIFIER_nondet_int() [L452] COND FALSE !(\read(tmp_ndt_3)) [L463] COND TRUE t3_st == 0 [L464] int tmp_ndt_4; [L465] tmp_ndt_4 = __VERIFIER_nondet_int() [L466] COND FALSE !(\read(tmp_ndt_4)) [L477] COND TRUE t4_st == 0 [L478] int tmp_ndt_5; [L479] tmp_ndt_5 = __VERIFIER_nondet_int() [L480] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 411]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int m_i ; [L36] int t1_i ; [L37] int t2_i ; [L38] int t3_i ; [L39] int t4_i ; [L40] int M_E = 2; [L41] int T1_E = 2; [L42] int T2_E = 2; [L43] int T3_E = 2; [L44] int T4_E = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0] [L821] int __retres1 ; [L825] CALL init_model() [L733] m_i = 1 [L734] t1_i = 1 [L735] t2_i = 1 [L736] t3_i = 1 [L737] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L825] RET init_model() [L826] CALL start_simulation() [L762] int kernel_st ; [L763] int tmp ; [L764] int tmp___0 ; [L768] kernel_st = 0 [L769] FCALL update_channels() [L770] CALL init_threads() [L341] COND TRUE m_i == 1 [L342] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t1_i == 1 [L347] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t2_i == 1 [L352] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L356] COND TRUE t3_i == 1 [L357] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L361] COND TRUE t4_i == 1 [L362] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L770] RET init_threads() [L771] CALL fire_delta_events() [L502] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L537] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L542] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L771] RET fire_delta_events() [L772] CALL activate_threads() [L605] int tmp ; [L606] int tmp___0 ; [L607] int tmp___1 ; [L608] int tmp___2 ; [L609] int tmp___3 ; [L613] CALL, EXPR is_master_triggered() [L235] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L238] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L248] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L250] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L613] RET, EXPR is_master_triggered() [L613] tmp = is_master_triggered() [L615] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L621] CALL, EXPR is_transmit1_triggered() [L254] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L257] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L267] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L269] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L621] RET, EXPR is_transmit1_triggered() [L621] tmp___0 = is_transmit1_triggered() [L623] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L629] CALL, EXPR is_transmit2_triggered() [L273] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L276] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L286] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L288] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L629] RET, EXPR is_transmit2_triggered() [L629] tmp___1 = is_transmit2_triggered() [L631] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L637] CALL, EXPR is_transmit3_triggered() [L292] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L295] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L305] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L307] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L637] RET, EXPR is_transmit3_triggered() [L637] tmp___2 = is_transmit3_triggered() [L639] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L645] CALL, EXPR is_transmit4_triggered() [L311] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L314] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L324] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L326] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L645] RET, EXPR is_transmit4_triggered() [L645] tmp___3 = is_transmit4_triggered() [L647] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L772] RET activate_threads() [L773] CALL reset_delta_events() [L555] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L590] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L595] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L773] RET reset_delta_events() [L776] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L779] kernel_st = 1 [L780] CALL eval() [L407] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] Loop: [L411] COND TRUE 1 [L414] CALL, EXPR exists_runnable_thread() [L371] int __retres1 ; [L374] COND TRUE m_st == 0 [L375] __retres1 = 1 [L402] return (__retres1); [L414] RET, EXPR exists_runnable_thread() [L414] tmp = exists_runnable_thread() [L416] COND TRUE \read(tmp) [L421] COND TRUE m_st == 0 [L422] int tmp_ndt_1; [L423] tmp_ndt_1 = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp_ndt_1)) [L435] COND TRUE t1_st == 0 [L436] int tmp_ndt_2; [L437] tmp_ndt_2 = __VERIFIER_nondet_int() [L438] COND FALSE !(\read(tmp_ndt_2)) [L449] COND TRUE t2_st == 0 [L450] int tmp_ndt_3; [L451] tmp_ndt_3 = __VERIFIER_nondet_int() [L452] COND FALSE !(\read(tmp_ndt_3)) [L463] COND TRUE t3_st == 0 [L464] int tmp_ndt_4; [L465] tmp_ndt_4 = __VERIFIER_nondet_int() [L466] COND FALSE !(\read(tmp_ndt_4)) [L477] COND TRUE t4_st == 0 [L478] int tmp_ndt_5; [L479] tmp_ndt_5 = __VERIFIER_nondet_int() [L480] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-13 14:29:28,319 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ac588a0d-f6db-4b6d-9d9e-c3549edb2ef9/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)