./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.05.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8f323f9-944e-4f13-9133-164c2e8ea6f8/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8f323f9-944e-4f13-9133-164c2e8ea6f8/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8f323f9-944e-4f13-9133-164c2e8ea6f8/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8f323f9-944e-4f13-9133-164c2e8ea6f8/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.05.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8f323f9-944e-4f13-9133-164c2e8ea6f8/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8f323f9-944e-4f13-9133-164c2e8ea6f8/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 13:55:55,360 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 13:55:55,422 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8f323f9-944e-4f13-9133-164c2e8ea6f8/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 13:55:55,427 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 13:55:55,428 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 13:55:55,467 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 13:55:55,469 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 13:55:55,469 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 13:55:55,469 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 13:55:55,470 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 13:55:55,471 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 13:55:55,471 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 13:55:55,471 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 13:55:55,472 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 13:55:55,472 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 13:55:55,472 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 13:55:55,472 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 13:55:55,473 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 13:55:55,473 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 13:55:55,474 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 13:55:55,474 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 13:55:55,474 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 13:55:55,474 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 13:55:55,474 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 13:55:55,474 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 13:55:55,474 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 13:55:55,474 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 13:55:55,474 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 13:55:55,475 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 13:55:55,475 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 13:55:55,475 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 13:55:55,475 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 13:55:55,475 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 13:55:55,475 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 13:55:55,475 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 13:55:55,475 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 13:55:55,476 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 13:55:55,476 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 13:55:55,477 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 13:55:55,477 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8f323f9-944e-4f13-9133-164c2e8ea6f8/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f [2024-11-13 13:55:55,841 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 13:55:55,853 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 13:55:55,858 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 13:55:55,860 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 13:55:55,861 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 13:55:55,863 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8f323f9-944e-4f13-9133-164c2e8ea6f8/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/transmitter.05.cil.c Unable to find full path for "g++" [2024-11-13 13:55:57,875 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 13:55:58,190 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 13:55:58,190 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8f323f9-944e-4f13-9133-164c2e8ea6f8/sv-benchmarks/c/systemc/transmitter.05.cil.c [2024-11-13 13:55:58,208 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8f323f9-944e-4f13-9133-164c2e8ea6f8/bin/uautomizer-verify-qhAvR1uOyd/data/366508a31/c404cd7c34954d8f95dc63a796814309/FLAGe7c69181f [2024-11-13 13:55:58,224 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8f323f9-944e-4f13-9133-164c2e8ea6f8/bin/uautomizer-verify-qhAvR1uOyd/data/366508a31/c404cd7c34954d8f95dc63a796814309 [2024-11-13 13:55:58,226 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 13:55:58,228 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 13:55:58,230 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 13:55:58,230 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 13:55:58,235 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 13:55:58,236 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 01:55:58" (1/1) ... [2024-11-13 13:55:58,237 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4e10e942 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:55:58, skipping insertion in model container [2024-11-13 13:55:58,237 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 01:55:58" (1/1) ... [2024-11-13 13:55:58,277 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 13:55:58,506 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 13:55:58,529 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 13:55:58,634 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 13:55:58,655 INFO L204 MainTranslator]: Completed translation [2024-11-13 13:55:58,656 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:55:58 WrapperNode [2024-11-13 13:55:58,656 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 13:55:58,657 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 13:55:58,657 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 13:55:58,658 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 13:55:58,665 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:55:58" (1/1) ... [2024-11-13 13:55:58,679 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:55:58" (1/1) ... [2024-11-13 13:55:58,761 INFO L138 Inliner]: procedures = 38, calls = 46, calls flagged for inlining = 41, calls inlined = 87, statements flattened = 1232 [2024-11-13 13:55:58,761 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 13:55:58,762 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 13:55:58,762 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 13:55:58,762 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 13:55:58,779 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:55:58" (1/1) ... [2024-11-13 13:55:58,779 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:55:58" (1/1) ... [2024-11-13 13:55:58,788 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:55:58" (1/1) ... [2024-11-13 13:55:58,826 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 13:55:58,826 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:55:58" (1/1) ... [2024-11-13 13:55:58,827 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:55:58" (1/1) ... [2024-11-13 13:55:58,853 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:55:58" (1/1) ... [2024-11-13 13:55:58,881 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:55:58" (1/1) ... [2024-11-13 13:55:58,884 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:55:58" (1/1) ... [2024-11-13 13:55:58,891 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:55:58" (1/1) ... [2024-11-13 13:55:58,902 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 13:55:58,903 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 13:55:58,907 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 13:55:58,907 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 13:55:58,908 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:55:58" (1/1) ... [2024-11-13 13:55:58,917 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:55:58,938 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8f323f9-944e-4f13-9133-164c2e8ea6f8/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:55:58,955 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8f323f9-944e-4f13-9133-164c2e8ea6f8/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:55:58,958 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8f323f9-944e-4f13-9133-164c2e8ea6f8/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 13:55:58,990 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 13:55:58,990 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 13:55:58,990 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 13:55:58,990 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 13:55:59,109 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 13:55:59,111 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 13:56:00,561 INFO L? ?]: Removed 228 outVars from TransFormulas that were not future-live. [2024-11-13 13:56:00,561 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 13:56:00,600 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 13:56:00,604 INFO L316 CfgBuilder]: Removed 9 assume(true) statements. [2024-11-13 13:56:00,605 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:56:00 BoogieIcfgContainer [2024-11-13 13:56:00,605 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 13:56:00,606 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 13:56:00,608 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 13:56:00,613 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 13:56:00,614 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:56:00,614 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 01:55:58" (1/3) ... [2024-11-13 13:56:00,615 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1404756c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 01:56:00, skipping insertion in model container [2024-11-13 13:56:00,616 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:56:00,616 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:55:58" (2/3) ... [2024-11-13 13:56:00,616 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1404756c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 01:56:00, skipping insertion in model container [2024-11-13 13:56:00,616 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:56:00,617 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:56:00" (3/3) ... [2024-11-13 13:56:00,618 INFO L333 chiAutomizerObserver]: Analyzing ICFG transmitter.05.cil.c [2024-11-13 13:56:00,703 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 13:56:00,703 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 13:56:00,703 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 13:56:00,704 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 13:56:00,704 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 13:56:00,704 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 13:56:00,704 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 13:56:00,705 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 13:56:00,717 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 512 states, 511 states have (on average 1.5264187866927592) internal successors, (780), 511 states have internal predecessors, (780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:00,778 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 431 [2024-11-13 13:56:00,779 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:00,779 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:00,793 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:00,794 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:00,795 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 13:56:00,798 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 512 states, 511 states have (on average 1.5264187866927592) internal successors, (780), 511 states have internal predecessors, (780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:00,815 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 431 [2024-11-13 13:56:00,815 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:00,815 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:00,818 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:00,818 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:00,827 INFO L745 eck$LassoCheckResult]: Stem: 151#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 412#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 243#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 409#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 257#L401true assume !(1 == ~m_i~0);~m_st~0 := 2; 348#L401-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 114#L406-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 402#L411-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 389#L416-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 467#L421-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 330#L426-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 93#L586true assume 0 == ~M_E~0;~M_E~0 := 1; 125#L586-2true assume !(0 == ~T1_E~0); 232#L591-1true assume !(0 == ~T2_E~0); 207#L596-1true assume !(0 == ~T3_E~0); 273#L601-1true assume !(0 == ~T4_E~0); 249#L606-1true assume !(0 == ~T5_E~0); 471#L611-1true assume !(0 == ~E_1~0); 347#L616-1true assume !(0 == ~E_2~0); 353#L621-1true assume 0 == ~E_3~0;~E_3~0 := 1; 49#L626-1true assume !(0 == ~E_4~0); 304#L631-1true assume !(0 == ~E_5~0); 147#L636-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47#L279true assume 1 == ~m_pc~0; 215#L280true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 371#L290true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131#is_master_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 272#L720true assume !(0 != activate_threads_~tmp~1#1); 493#L720-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 152#L298true assume !(1 == ~t1_pc~0); 21#L298-2true is_transmit1_triggered_~__retres1~1#1 := 0; 457#L309true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 54#L728true assume !(0 != activate_threads_~tmp___0~0#1); 264#L728-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 128#L317true assume 1 == ~t2_pc~0; 240#L318true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 475#L328true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 246#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 157#L736true assume !(0 != activate_threads_~tmp___1~0#1); 424#L736-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 326#L336true assume 1 == ~t3_pc~0; 188#L337true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 494#L347true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 281#L744true assume !(0 != activate_threads_~tmp___2~0#1); 337#L744-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 403#L355true assume !(1 == ~t4_pc~0); 335#L355-2true is_transmit4_triggered_~__retres1~4#1 := 0; 106#L366true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 71#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 318#L752true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 61#L752-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 375#L374true assume 1 == ~t5_pc~0; 387#L375true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 390#L385true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 135#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 430#L760true assume !(0 != activate_threads_~tmp___4~0#1); 234#L760-2true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 438#L649true assume 1 == ~M_E~0;~M_E~0 := 2; 499#L649-2true assume !(1 == ~T1_E~0); 39#L654-1true assume !(1 == ~T2_E~0); 269#L659-1true assume !(1 == ~T3_E~0); 156#L664-1true assume !(1 == ~T4_E~0); 35#L669-1true assume !(1 == ~T5_E~0); 320#L674-1true assume !(1 == ~E_1~0); 333#L679-1true assume !(1 == ~E_2~0); 96#L684-1true assume 1 == ~E_3~0;~E_3~0 := 2; 202#L689-1true assume !(1 == ~E_4~0); 490#L694-1true assume !(1 == ~E_5~0); 201#L699-1true assume { :end_inline_reset_delta_events } true; 480#L900-2true [2024-11-13 13:56:00,828 INFO L747 eck$LassoCheckResult]: Loop: 480#L900-2true assume !false; 508#L901true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 212#L561-1true assume !true; 75#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 363#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 425#L586-3true assume 0 == ~M_E~0;~M_E~0 := 1; 319#L586-5true assume !(0 == ~T1_E~0); 218#L591-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 109#L596-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 229#L601-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 377#L606-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 261#L611-3true assume 0 == ~E_1~0;~E_1~0 := 1; 265#L616-3true assume 0 == ~E_2~0;~E_2~0 := 1; 43#L621-3true assume 0 == ~E_3~0;~E_3~0 := 1; 20#L626-3true assume !(0 == ~E_4~0); 509#L631-3true assume 0 == ~E_5~0;~E_5~0 := 1; 23#L636-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 435#L279-18true assume !(1 == ~m_pc~0); 164#L279-20true is_master_triggered_~__retres1~0#1 := 0; 222#L290-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 161#is_master_triggered_returnLabel#7true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 395#L720-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 349#L720-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 233#L298-18true assume !(1 == ~t1_pc~0); 8#L298-20true is_transmit1_triggered_~__retres1~1#1 := 0; 113#L309-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 422#is_transmit1_triggered_returnLabel#7true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 123#L728-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 450#L728-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 208#L317-18true assume !(1 == ~t2_pc~0); 228#L317-20true is_transmit2_triggered_~__retres1~2#1 := 0; 242#L328-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 238#is_transmit2_triggered_returnLabel#7true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 115#L736-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 356#L736-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 352#L336-18true assume 1 == ~t3_pc~0; 323#L337-6true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 398#L347-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 263#is_transmit3_triggered_returnLabel#7true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 177#L744-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78#L744-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 291#L355-18true assume 1 == ~t4_pc~0; 414#L356-6true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 421#L366-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 180#is_transmit4_triggered_returnLabel#7true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 213#L752-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 132#L752-20true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 336#L374-18true assume !(1 == ~t5_pc~0); 294#L374-20true is_transmit5_triggered_~__retres1~5#1 := 0; 173#L385-6true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 133#is_transmit5_triggered_returnLabel#7true activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 452#L760-18true assume !(0 != activate_threads_~tmp___4~0#1); 275#L760-20true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 462#L649-3true assume 1 == ~M_E~0;~M_E~0 := 2; 187#L649-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 170#L654-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 83#L659-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 456#L664-3true assume !(1 == ~T4_E~0); 24#L669-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 484#L674-3true assume 1 == ~E_1~0;~E_1~0 := 2; 19#L679-3true assume 1 == ~E_2~0;~E_2~0 := 2; 183#L684-3true assume 1 == ~E_3~0;~E_3~0 := 2; 2#L689-3true assume 1 == ~E_4~0;~E_4~0 := 2; 137#L694-3true assume 1 == ~E_5~0;~E_5~0 := 2; 17#L699-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 419#L439-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 483#L471-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 217#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 200#L919true assume !(0 == start_simulation_~tmp~3#1); 492#L919-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 301#L439-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 380#L471-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 31#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 193#L874true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 355#L881true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 372#stop_simulation_returnLabel#1true start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 332#L932true assume !(0 != start_simulation_~tmp___0~1#1); 480#L900-2true [2024-11-13 13:56:00,834 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:00,834 INFO L85 PathProgramCache]: Analyzing trace with hash -777385748, now seen corresponding path program 1 times [2024-11-13 13:56:00,842 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:00,843 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1461705350] [2024-11-13 13:56:00,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:00,844 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:00,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:01,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:01,144 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:01,145 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1461705350] [2024-11-13 13:56:01,147 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1461705350] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:01,147 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:01,148 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:01,149 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1551780383] [2024-11-13 13:56:01,150 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:01,155 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:56:01,156 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:01,157 INFO L85 PathProgramCache]: Analyzing trace with hash 809869017, now seen corresponding path program 1 times [2024-11-13 13:56:01,157 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:01,158 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [784916388] [2024-11-13 13:56:01,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:01,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:01,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:01,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:01,220 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:01,221 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [784916388] [2024-11-13 13:56:01,221 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [784916388] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:01,221 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:01,221 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:56:01,221 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [750623137] [2024-11-13 13:56:01,221 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:01,222 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:56:01,223 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:01,252 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:56:01,253 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:56:01,256 INFO L87 Difference]: Start difference. First operand has 512 states, 511 states have (on average 1.5264187866927592) internal successors, (780), 511 states have internal predecessors, (780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:01,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:01,323 INFO L93 Difference]: Finished difference Result 510 states and 758 transitions. [2024-11-13 13:56:01,325 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 510 states and 758 transitions. [2024-11-13 13:56:01,331 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2024-11-13 13:56:01,344 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 510 states to 504 states and 752 transitions. [2024-11-13 13:56:01,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2024-11-13 13:56:01,348 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2024-11-13 13:56:01,349 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 752 transitions. [2024-11-13 13:56:01,351 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:01,352 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 752 transitions. [2024-11-13 13:56:01,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 752 transitions. [2024-11-13 13:56:01,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 504. [2024-11-13 13:56:01,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 504 states, 504 states have (on average 1.492063492063492) internal successors, (752), 503 states have internal predecessors, (752), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:01,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 752 transitions. [2024-11-13 13:56:01,402 INFO L240 hiAutomatonCegarLoop]: Abstraction has 504 states and 752 transitions. [2024-11-13 13:56:01,403 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:56:01,407 INFO L424 stractBuchiCegarLoop]: Abstraction has 504 states and 752 transitions. [2024-11-13 13:56:01,407 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 13:56:01,407 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 504 states and 752 transitions. [2024-11-13 13:56:01,411 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2024-11-13 13:56:01,412 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:01,412 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:01,414 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:01,415 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:01,415 INFO L745 eck$LassoCheckResult]: Stem: 1302#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 1303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1408#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1409#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1426#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 1427#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1237#L406-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1238#L411-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1515#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1516#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1482#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1206#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 1207#L586-2 assume !(0 == ~T1_E~0); 1258#L591-1 assume !(0 == ~T2_E~0); 1372#L596-1 assume !(0 == ~T3_E~0); 1373#L601-1 assume !(0 == ~T4_E~0); 1414#L606-1 assume !(0 == ~T5_E~0); 1415#L611-1 assume !(0 == ~E_1~0); 1490#L616-1 assume !(0 == ~E_2~0); 1491#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 1133#L626-1 assume !(0 == ~E_4~0); 1134#L631-1 assume !(0 == ~E_5~0); 1297#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1128#L279 assume 1 == ~m_pc~0; 1129#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1378#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1272#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1273#L720 assume !(0 != activate_threads_~tmp~1#1); 1437#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1304#L298 assume !(1 == ~t1_pc~0); 1075#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1076#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1101#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1102#L728 assume !(0 != activate_threads_~tmp___0~0#1); 1142#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1264#L317 assume 1 == ~t2_pc~0; 1265#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1406#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1413#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1313#L736 assume !(0 != activate_threads_~tmp___1~0#1); 1314#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1479#L336 assume 1 == ~t3_pc~0; 1351#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1352#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1048#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1049#L744 assume !(0 != activate_threads_~tmp___2~0#1); 1445#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1486#L355 assume !(1 == ~t4_pc~0); 1369#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1224#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1172#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1173#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1152#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1153#L374 assume 1 == ~t5_pc~0; 1508#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1288#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1278#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1279#L760 assume !(0 != activate_threads_~tmp___4~0#1); 1397#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1398#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 1527#L649-2 assume !(1 == ~T1_E~0); 1114#L654-1 assume !(1 == ~T2_E~0); 1115#L659-1 assume !(1 == ~T3_E~0); 1312#L664-1 assume !(1 == ~T4_E~0); 1106#L669-1 assume !(1 == ~T5_E~0); 1107#L674-1 assume !(1 == ~E_1~0); 1471#L679-1 assume !(1 == ~E_2~0); 1211#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1212#L689-1 assume !(1 == ~E_4~0); 1365#L694-1 assume !(1 == ~E_5~0); 1363#L699-1 assume { :end_inline_reset_delta_events } true; 1364#L900-2 [2024-11-13 13:56:01,416 INFO L747 eck$LassoCheckResult]: Loop: 1364#L900-2 assume !false; 1533#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1283#L561-1 assume !false; 1339#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1331#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1077#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1078#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1200#L486 assume !(0 != eval_~tmp~0#1); 1179#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1180#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1502#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1470#L586-5 assume !(0 == ~T1_E~0); 1380#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1228#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1229#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1393#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1429#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1430#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1122#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1073#L626-3 assume !(0 == ~E_4~0); 1074#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1079#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1080#L279-18 assume 1 == ~m_pc~0; 1187#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1189#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1317#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1318#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1492#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1396#L298-18 assume !(1 == ~t1_pc~0); 1046#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 1047#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1236#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1254#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1255#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1374#L317-18 assume 1 == ~t2_pc~0; 1289#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1290#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1404#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1239#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1240#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1495#L336-18 assume 1 == ~t3_pc~0; 1475#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1476#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1431#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1340#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1181#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1182#L355-18 assume !(1 == ~t4_pc~0); 1443#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 1444#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1345#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1346#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1274#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1275#L374-18 assume !(1 == ~t5_pc~0); 1457#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 1336#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1276#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1277#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 1438#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1439#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1350#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1330#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1191#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1192#L664-3 assume !(1 == ~T4_E~0); 1083#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1084#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1071#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1072#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1031#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1032#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1066#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1067#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1070#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1379#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1362#L919 assume !(0 == start_simulation_~tmp~3#1); 1082#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1461#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1060#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1098#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 1099#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1358#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1496#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1484#L932 assume !(0 != start_simulation_~tmp___0~1#1); 1364#L900-2 [2024-11-13 13:56:01,417 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:01,417 INFO L85 PathProgramCache]: Analyzing trace with hash 438767978, now seen corresponding path program 1 times [2024-11-13 13:56:01,417 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:01,417 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [316451391] [2024-11-13 13:56:01,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:01,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:01,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:01,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:01,532 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:01,532 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [316451391] [2024-11-13 13:56:01,532 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [316451391] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:01,532 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:01,532 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:01,532 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [557345038] [2024-11-13 13:56:01,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:01,533 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:56:01,533 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:01,533 INFO L85 PathProgramCache]: Analyzing trace with hash 518819204, now seen corresponding path program 1 times [2024-11-13 13:56:01,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:01,533 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2121239816] [2024-11-13 13:56:01,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:01,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:01,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:01,696 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:01,696 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:01,696 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2121239816] [2024-11-13 13:56:01,696 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2121239816] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:01,696 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:01,696 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:01,697 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [609880155] [2024-11-13 13:56:01,697 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:01,697 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:56:01,697 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:01,698 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:56:01,698 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:56:01,698 INFO L87 Difference]: Start difference. First operand 504 states and 752 transitions. cyclomatic complexity: 249 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:01,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:01,744 INFO L93 Difference]: Finished difference Result 504 states and 751 transitions. [2024-11-13 13:56:01,745 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 751 transitions. [2024-11-13 13:56:01,750 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2024-11-13 13:56:01,755 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 504 states and 751 transitions. [2024-11-13 13:56:01,755 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2024-11-13 13:56:01,756 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2024-11-13 13:56:01,756 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 751 transitions. [2024-11-13 13:56:01,758 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:01,758 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 751 transitions. [2024-11-13 13:56:01,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 751 transitions. [2024-11-13 13:56:01,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 504. [2024-11-13 13:56:01,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 504 states, 504 states have (on average 1.4900793650793651) internal successors, (751), 503 states have internal predecessors, (751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:01,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 751 transitions. [2024-11-13 13:56:01,778 INFO L240 hiAutomatonCegarLoop]: Abstraction has 504 states and 751 transitions. [2024-11-13 13:56:01,778 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:56:01,779 INFO L424 stractBuchiCegarLoop]: Abstraction has 504 states and 751 transitions. [2024-11-13 13:56:01,779 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 13:56:01,779 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 504 states and 751 transitions. [2024-11-13 13:56:01,783 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2024-11-13 13:56:01,784 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:01,784 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:01,790 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:01,790 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:01,790 INFO L745 eck$LassoCheckResult]: Stem: 2317#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 2318#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2423#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2424#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2441#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 2442#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2252#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2253#L411-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2530#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2531#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2497#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2221#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 2222#L586-2 assume !(0 == ~T1_E~0); 2273#L591-1 assume !(0 == ~T2_E~0); 2387#L596-1 assume !(0 == ~T3_E~0); 2388#L601-1 assume !(0 == ~T4_E~0); 2429#L606-1 assume !(0 == ~T5_E~0); 2430#L611-1 assume !(0 == ~E_1~0); 2505#L616-1 assume !(0 == ~E_2~0); 2506#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 2148#L626-1 assume !(0 == ~E_4~0); 2149#L631-1 assume !(0 == ~E_5~0); 2312#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2143#L279 assume 1 == ~m_pc~0; 2144#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2393#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2287#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2288#L720 assume !(0 != activate_threads_~tmp~1#1); 2452#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2319#L298 assume !(1 == ~t1_pc~0); 2090#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2091#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2116#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2117#L728 assume !(0 != activate_threads_~tmp___0~0#1); 2157#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2279#L317 assume 1 == ~t2_pc~0; 2280#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2421#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2428#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2328#L736 assume !(0 != activate_threads_~tmp___1~0#1); 2329#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2494#L336 assume 1 == ~t3_pc~0; 2366#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2367#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2063#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2064#L744 assume !(0 != activate_threads_~tmp___2~0#1); 2460#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2501#L355 assume !(1 == ~t4_pc~0); 2384#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2239#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2187#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2188#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2167#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2168#L374 assume 1 == ~t5_pc~0; 2523#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2303#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2293#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2294#L760 assume !(0 != activate_threads_~tmp___4~0#1); 2412#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2413#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 2542#L649-2 assume !(1 == ~T1_E~0); 2129#L654-1 assume !(1 == ~T2_E~0); 2130#L659-1 assume !(1 == ~T3_E~0); 2327#L664-1 assume !(1 == ~T4_E~0); 2121#L669-1 assume !(1 == ~T5_E~0); 2122#L674-1 assume !(1 == ~E_1~0); 2486#L679-1 assume !(1 == ~E_2~0); 2226#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2227#L689-1 assume !(1 == ~E_4~0); 2380#L694-1 assume !(1 == ~E_5~0); 2378#L699-1 assume { :end_inline_reset_delta_events } true; 2379#L900-2 [2024-11-13 13:56:01,791 INFO L747 eck$LassoCheckResult]: Loop: 2379#L900-2 assume !false; 2548#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2298#L561-1 assume !false; 2354#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2346#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2092#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2093#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2215#L486 assume !(0 != eval_~tmp~0#1); 2194#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2195#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2517#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2485#L586-5 assume !(0 == ~T1_E~0); 2395#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2243#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2244#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2408#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2444#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2445#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2137#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2088#L626-3 assume !(0 == ~E_4~0); 2089#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2094#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2095#L279-18 assume 1 == ~m_pc~0; 2202#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2204#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2332#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2333#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2507#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2411#L298-18 assume 1 == ~t1_pc~0; 2068#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2062#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2251#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2269#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2270#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2389#L317-18 assume 1 == ~t2_pc~0; 2304#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2305#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2419#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2254#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2255#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2510#L336-18 assume 1 == ~t3_pc~0; 2490#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2491#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2446#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2355#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2196#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2197#L355-18 assume 1 == ~t4_pc~0; 2470#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2459#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2360#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2361#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2289#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2290#L374-18 assume 1 == ~t5_pc~0; 2500#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2351#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2291#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2292#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 2453#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2454#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2365#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2345#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2206#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2207#L664-3 assume !(1 == ~T4_E~0); 2096#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2097#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2086#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2087#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2046#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2047#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2081#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2082#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2085#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2394#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2377#L919 assume !(0 == start_simulation_~tmp~3#1); 2099#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2476#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2075#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2113#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 2114#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2373#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2511#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2499#L932 assume !(0 != start_simulation_~tmp___0~1#1); 2379#L900-2 [2024-11-13 13:56:01,791 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:01,791 INFO L85 PathProgramCache]: Analyzing trace with hash 2124947816, now seen corresponding path program 1 times [2024-11-13 13:56:01,792 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:01,792 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1942076125] [2024-11-13 13:56:01,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:01,792 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:01,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:01,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:01,854 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:01,854 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1942076125] [2024-11-13 13:56:01,854 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1942076125] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:01,854 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:01,854 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:01,854 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [366044640] [2024-11-13 13:56:01,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:01,855 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:56:01,855 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:01,855 INFO L85 PathProgramCache]: Analyzing trace with hash -2056988505, now seen corresponding path program 1 times [2024-11-13 13:56:01,856 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:01,856 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1780932826] [2024-11-13 13:56:01,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:01,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:01,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:01,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:01,946 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:01,946 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1780932826] [2024-11-13 13:56:01,946 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1780932826] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:01,946 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:01,946 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:01,947 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [577221706] [2024-11-13 13:56:01,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:01,947 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:56:01,948 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:01,948 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:56:01,949 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:56:01,949 INFO L87 Difference]: Start difference. First operand 504 states and 751 transitions. cyclomatic complexity: 248 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:01,973 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:01,973 INFO L93 Difference]: Finished difference Result 504 states and 750 transitions. [2024-11-13 13:56:01,973 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 750 transitions. [2024-11-13 13:56:01,979 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2024-11-13 13:56:01,983 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 504 states and 750 transitions. [2024-11-13 13:56:01,983 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2024-11-13 13:56:01,984 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2024-11-13 13:56:01,985 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 750 transitions. [2024-11-13 13:56:01,989 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:01,989 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 750 transitions. [2024-11-13 13:56:01,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 750 transitions. [2024-11-13 13:56:02,012 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 504. [2024-11-13 13:56:02,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 504 states, 504 states have (on average 1.4880952380952381) internal successors, (750), 503 states have internal predecessors, (750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:02,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 750 transitions. [2024-11-13 13:56:02,017 INFO L240 hiAutomatonCegarLoop]: Abstraction has 504 states and 750 transitions. [2024-11-13 13:56:02,017 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:56:02,018 INFO L424 stractBuchiCegarLoop]: Abstraction has 504 states and 750 transitions. [2024-11-13 13:56:02,018 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 13:56:02,018 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 504 states and 750 transitions. [2024-11-13 13:56:02,023 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2024-11-13 13:56:02,023 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:02,024 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:02,028 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:02,030 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:02,030 INFO L745 eck$LassoCheckResult]: Stem: 3332#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 3333#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3438#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3439#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3456#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 3457#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3267#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3268#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3545#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3546#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3512#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3236#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 3237#L586-2 assume !(0 == ~T1_E~0); 3288#L591-1 assume !(0 == ~T2_E~0); 3402#L596-1 assume !(0 == ~T3_E~0); 3403#L601-1 assume !(0 == ~T4_E~0); 3444#L606-1 assume !(0 == ~T5_E~0); 3445#L611-1 assume !(0 == ~E_1~0); 3520#L616-1 assume !(0 == ~E_2~0); 3521#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 3163#L626-1 assume !(0 == ~E_4~0); 3164#L631-1 assume !(0 == ~E_5~0); 3327#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3158#L279 assume 1 == ~m_pc~0; 3159#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3408#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3302#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3303#L720 assume !(0 != activate_threads_~tmp~1#1); 3467#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3334#L298 assume !(1 == ~t1_pc~0); 3105#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3106#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3131#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3132#L728 assume !(0 != activate_threads_~tmp___0~0#1); 3172#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3294#L317 assume 1 == ~t2_pc~0; 3295#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3436#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3443#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3343#L736 assume !(0 != activate_threads_~tmp___1~0#1); 3344#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3509#L336 assume 1 == ~t3_pc~0; 3381#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3382#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3078#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3079#L744 assume !(0 != activate_threads_~tmp___2~0#1); 3475#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3516#L355 assume !(1 == ~t4_pc~0); 3399#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3254#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3202#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3203#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3182#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3183#L374 assume 1 == ~t5_pc~0; 3538#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3318#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3308#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3309#L760 assume !(0 != activate_threads_~tmp___4~0#1); 3427#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3428#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 3557#L649-2 assume !(1 == ~T1_E~0); 3144#L654-1 assume !(1 == ~T2_E~0); 3145#L659-1 assume !(1 == ~T3_E~0); 3342#L664-1 assume !(1 == ~T4_E~0); 3136#L669-1 assume !(1 == ~T5_E~0); 3137#L674-1 assume !(1 == ~E_1~0); 3501#L679-1 assume !(1 == ~E_2~0); 3241#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 3242#L689-1 assume !(1 == ~E_4~0); 3395#L694-1 assume !(1 == ~E_5~0); 3393#L699-1 assume { :end_inline_reset_delta_events } true; 3394#L900-2 [2024-11-13 13:56:02,031 INFO L747 eck$LassoCheckResult]: Loop: 3394#L900-2 assume !false; 3563#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3313#L561-1 assume !false; 3369#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3361#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3107#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3108#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3230#L486 assume !(0 != eval_~tmp~0#1); 3209#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3210#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3532#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3500#L586-5 assume !(0 == ~T1_E~0); 3410#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3258#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3259#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3423#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3459#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3460#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3152#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3103#L626-3 assume !(0 == ~E_4~0); 3104#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3109#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3110#L279-18 assume 1 == ~m_pc~0; 3217#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3219#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3347#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3348#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3522#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3426#L298-18 assume !(1 == ~t1_pc~0); 3076#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 3077#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3266#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3284#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3285#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3404#L317-18 assume 1 == ~t2_pc~0; 3319#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3320#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3434#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3269#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3270#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3525#L336-18 assume 1 == ~t3_pc~0; 3505#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3506#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3461#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3370#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3211#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3212#L355-18 assume !(1 == ~t4_pc~0); 3473#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 3474#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3375#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3376#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3304#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3305#L374-18 assume 1 == ~t5_pc~0; 3515#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3366#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3306#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3307#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 3468#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3469#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3380#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3360#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3221#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3222#L664-3 assume !(1 == ~T4_E~0); 3111#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3112#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3101#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3102#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3061#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3062#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3096#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3097#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3100#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3409#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3392#L919 assume !(0 == start_simulation_~tmp~3#1); 3114#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3491#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3090#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3128#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 3129#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3388#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3526#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3514#L932 assume !(0 != start_simulation_~tmp___0~1#1); 3394#L900-2 [2024-11-13 13:56:02,032 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:02,034 INFO L85 PathProgramCache]: Analyzing trace with hash -2115626582, now seen corresponding path program 1 times [2024-11-13 13:56:02,035 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:02,035 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [104659774] [2024-11-13 13:56:02,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:02,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:02,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:02,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:02,122 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:02,122 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [104659774] [2024-11-13 13:56:02,122 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [104659774] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:02,122 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:02,122 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:02,123 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [203731231] [2024-11-13 13:56:02,123 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:02,123 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:56:02,123 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:02,124 INFO L85 PathProgramCache]: Analyzing trace with hash 575963429, now seen corresponding path program 1 times [2024-11-13 13:56:02,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:02,124 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [579518050] [2024-11-13 13:56:02,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:02,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:02,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:02,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:02,223 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:02,224 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [579518050] [2024-11-13 13:56:02,224 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [579518050] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:02,224 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:02,224 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:02,224 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [161275634] [2024-11-13 13:56:02,224 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:02,225 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:56:02,225 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:02,226 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:56:02,226 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:56:02,226 INFO L87 Difference]: Start difference. First operand 504 states and 750 transitions. cyclomatic complexity: 247 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:02,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:02,246 INFO L93 Difference]: Finished difference Result 504 states and 749 transitions. [2024-11-13 13:56:02,246 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 749 transitions. [2024-11-13 13:56:02,251 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2024-11-13 13:56:02,256 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 504 states and 749 transitions. [2024-11-13 13:56:02,256 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2024-11-13 13:56:02,257 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2024-11-13 13:56:02,258 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 749 transitions. [2024-11-13 13:56:02,259 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:02,260 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 749 transitions. [2024-11-13 13:56:02,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 749 transitions. [2024-11-13 13:56:02,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 504. [2024-11-13 13:56:02,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 504 states, 504 states have (on average 1.4861111111111112) internal successors, (749), 503 states have internal predecessors, (749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:02,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 749 transitions. [2024-11-13 13:56:02,274 INFO L240 hiAutomatonCegarLoop]: Abstraction has 504 states and 749 transitions. [2024-11-13 13:56:02,274 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:56:02,275 INFO L424 stractBuchiCegarLoop]: Abstraction has 504 states and 749 transitions. [2024-11-13 13:56:02,275 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 13:56:02,275 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 504 states and 749 transitions. [2024-11-13 13:56:02,279 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2024-11-13 13:56:02,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:02,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:02,281 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:02,281 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:02,281 INFO L745 eck$LassoCheckResult]: Stem: 4347#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 4348#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4453#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4454#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4471#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 4472#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4282#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4283#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4560#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4561#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4527#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4251#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 4252#L586-2 assume !(0 == ~T1_E~0); 4303#L591-1 assume !(0 == ~T2_E~0); 4417#L596-1 assume !(0 == ~T3_E~0); 4418#L601-1 assume !(0 == ~T4_E~0); 4459#L606-1 assume !(0 == ~T5_E~0); 4460#L611-1 assume !(0 == ~E_1~0); 4535#L616-1 assume !(0 == ~E_2~0); 4536#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 4178#L626-1 assume !(0 == ~E_4~0); 4179#L631-1 assume !(0 == ~E_5~0); 4342#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4173#L279 assume 1 == ~m_pc~0; 4174#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4423#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4317#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4318#L720 assume !(0 != activate_threads_~tmp~1#1); 4482#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4349#L298 assume !(1 == ~t1_pc~0); 4120#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4121#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4146#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4147#L728 assume !(0 != activate_threads_~tmp___0~0#1); 4187#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4309#L317 assume 1 == ~t2_pc~0; 4310#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4451#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4458#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4358#L736 assume !(0 != activate_threads_~tmp___1~0#1); 4359#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4524#L336 assume 1 == ~t3_pc~0; 4396#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4397#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4093#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4094#L744 assume !(0 != activate_threads_~tmp___2~0#1); 4490#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4531#L355 assume !(1 == ~t4_pc~0); 4414#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4269#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4217#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4218#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4197#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4198#L374 assume 1 == ~t5_pc~0; 4553#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4333#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4323#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4324#L760 assume !(0 != activate_threads_~tmp___4~0#1); 4442#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4443#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 4572#L649-2 assume !(1 == ~T1_E~0); 4159#L654-1 assume !(1 == ~T2_E~0); 4160#L659-1 assume !(1 == ~T3_E~0); 4357#L664-1 assume !(1 == ~T4_E~0); 4151#L669-1 assume !(1 == ~T5_E~0); 4152#L674-1 assume !(1 == ~E_1~0); 4516#L679-1 assume !(1 == ~E_2~0); 4256#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4257#L689-1 assume !(1 == ~E_4~0); 4410#L694-1 assume !(1 == ~E_5~0); 4408#L699-1 assume { :end_inline_reset_delta_events } true; 4409#L900-2 [2024-11-13 13:56:02,282 INFO L747 eck$LassoCheckResult]: Loop: 4409#L900-2 assume !false; 4578#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4328#L561-1 assume !false; 4384#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4376#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4122#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4123#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4245#L486 assume !(0 != eval_~tmp~0#1); 4224#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4225#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4547#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4515#L586-5 assume !(0 == ~T1_E~0); 4425#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4273#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4274#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4438#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4474#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4475#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4167#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4118#L626-3 assume !(0 == ~E_4~0); 4119#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4124#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4125#L279-18 assume 1 == ~m_pc~0; 4232#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4234#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4362#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4363#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4537#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4441#L298-18 assume 1 == ~t1_pc~0; 4098#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4092#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4281#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4299#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4300#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4419#L317-18 assume !(1 == ~t2_pc~0); 4336#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 4335#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4449#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4284#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4285#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4540#L336-18 assume 1 == ~t3_pc~0; 4520#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4521#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4476#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4385#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4226#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4227#L355-18 assume 1 == ~t4_pc~0; 4500#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4489#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4390#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4391#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4319#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4320#L374-18 assume 1 == ~t5_pc~0; 4530#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4381#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4321#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4322#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 4483#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4484#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4395#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4375#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4236#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4237#L664-3 assume !(1 == ~T4_E~0); 4126#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4127#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4116#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4117#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4076#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4077#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4111#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4112#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4115#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4424#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4407#L919 assume !(0 == start_simulation_~tmp~3#1); 4129#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4506#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4105#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4143#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 4144#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4403#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4541#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4529#L932 assume !(0 != start_simulation_~tmp___0~1#1); 4409#L900-2 [2024-11-13 13:56:02,282 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:02,282 INFO L85 PathProgramCache]: Analyzing trace with hash -1698229976, now seen corresponding path program 1 times [2024-11-13 13:56:02,283 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:02,283 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203766632] [2024-11-13 13:56:02,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:02,283 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:02,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:02,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:02,330 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:02,330 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1203766632] [2024-11-13 13:56:02,330 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1203766632] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:02,330 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:02,330 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:02,330 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1802094920] [2024-11-13 13:56:02,330 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:02,331 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:56:02,331 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:02,331 INFO L85 PathProgramCache]: Analyzing trace with hash -624153786, now seen corresponding path program 1 times [2024-11-13 13:56:02,331 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:02,331 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1259085312] [2024-11-13 13:56:02,331 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:02,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:02,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:02,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:02,424 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:02,424 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1259085312] [2024-11-13 13:56:02,424 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1259085312] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:02,424 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:02,424 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:02,424 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [10402170] [2024-11-13 13:56:02,424 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:02,425 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:56:02,425 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:02,425 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:56:02,425 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:56:02,426 INFO L87 Difference]: Start difference. First operand 504 states and 749 transitions. cyclomatic complexity: 246 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:02,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:02,446 INFO L93 Difference]: Finished difference Result 504 states and 748 transitions. [2024-11-13 13:56:02,446 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 748 transitions. [2024-11-13 13:56:02,450 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2024-11-13 13:56:02,454 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 504 states and 748 transitions. [2024-11-13 13:56:02,454 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2024-11-13 13:56:02,455 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2024-11-13 13:56:02,455 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 748 transitions. [2024-11-13 13:56:02,456 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:02,457 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 748 transitions. [2024-11-13 13:56:02,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 748 transitions. [2024-11-13 13:56:02,466 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 504. [2024-11-13 13:56:02,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 504 states, 504 states have (on average 1.4841269841269842) internal successors, (748), 503 states have internal predecessors, (748), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:02,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 748 transitions. [2024-11-13 13:56:02,470 INFO L240 hiAutomatonCegarLoop]: Abstraction has 504 states and 748 transitions. [2024-11-13 13:56:02,471 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:56:02,471 INFO L424 stractBuchiCegarLoop]: Abstraction has 504 states and 748 transitions. [2024-11-13 13:56:02,472 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 13:56:02,473 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 504 states and 748 transitions. [2024-11-13 13:56:02,476 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2024-11-13 13:56:02,476 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:02,477 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:02,478 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:02,478 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:02,479 INFO L745 eck$LassoCheckResult]: Stem: 5362#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 5363#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5468#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5469#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5486#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 5487#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5297#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5298#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5575#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5576#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5542#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5266#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 5267#L586-2 assume !(0 == ~T1_E~0); 5318#L591-1 assume !(0 == ~T2_E~0); 5432#L596-1 assume !(0 == ~T3_E~0); 5433#L601-1 assume !(0 == ~T4_E~0); 5474#L606-1 assume !(0 == ~T5_E~0); 5475#L611-1 assume !(0 == ~E_1~0); 5550#L616-1 assume !(0 == ~E_2~0); 5551#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5193#L626-1 assume !(0 == ~E_4~0); 5194#L631-1 assume !(0 == ~E_5~0); 5357#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5188#L279 assume 1 == ~m_pc~0; 5189#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5438#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5332#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5333#L720 assume !(0 != activate_threads_~tmp~1#1); 5497#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5364#L298 assume !(1 == ~t1_pc~0); 5135#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5136#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5161#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5162#L728 assume !(0 != activate_threads_~tmp___0~0#1); 5202#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5324#L317 assume 1 == ~t2_pc~0; 5325#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5466#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5473#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5373#L736 assume !(0 != activate_threads_~tmp___1~0#1); 5374#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5539#L336 assume 1 == ~t3_pc~0; 5411#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5412#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5108#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5109#L744 assume !(0 != activate_threads_~tmp___2~0#1); 5505#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5546#L355 assume !(1 == ~t4_pc~0); 5429#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5284#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5232#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5233#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5212#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5213#L374 assume 1 == ~t5_pc~0; 5568#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5348#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5338#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5339#L760 assume !(0 != activate_threads_~tmp___4~0#1); 5457#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5458#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 5587#L649-2 assume !(1 == ~T1_E~0); 5174#L654-1 assume !(1 == ~T2_E~0); 5175#L659-1 assume !(1 == ~T3_E~0); 5372#L664-1 assume !(1 == ~T4_E~0); 5166#L669-1 assume !(1 == ~T5_E~0); 5167#L674-1 assume !(1 == ~E_1~0); 5531#L679-1 assume !(1 == ~E_2~0); 5271#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5272#L689-1 assume !(1 == ~E_4~0); 5425#L694-1 assume !(1 == ~E_5~0); 5423#L699-1 assume { :end_inline_reset_delta_events } true; 5424#L900-2 [2024-11-13 13:56:02,479 INFO L747 eck$LassoCheckResult]: Loop: 5424#L900-2 assume !false; 5593#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5343#L561-1 assume !false; 5399#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5391#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5137#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5138#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5260#L486 assume !(0 != eval_~tmp~0#1); 5239#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5240#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5562#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5530#L586-5 assume !(0 == ~T1_E~0); 5440#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5288#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5289#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5453#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5489#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5490#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5182#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5133#L626-3 assume !(0 == ~E_4~0); 5134#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5139#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5140#L279-18 assume !(1 == ~m_pc~0); 5248#L279-20 is_master_triggered_~__retres1~0#1 := 0; 5249#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5377#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5378#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5552#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5456#L298-18 assume !(1 == ~t1_pc~0); 5106#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 5107#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5296#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5314#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5315#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5434#L317-18 assume 1 == ~t2_pc~0; 5349#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5350#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5464#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5299#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5300#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5555#L336-18 assume !(1 == ~t3_pc~0); 5537#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 5536#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5491#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5400#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5241#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5242#L355-18 assume 1 == ~t4_pc~0; 5515#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5504#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5405#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5406#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5334#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5335#L374-18 assume 1 == ~t5_pc~0; 5545#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5396#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5336#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5337#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 5498#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5499#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5410#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5390#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5251#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5252#L664-3 assume !(1 == ~T4_E~0); 5141#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5142#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5131#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5132#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5091#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5092#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5126#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5127#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5130#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5439#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 5422#L919 assume !(0 == start_simulation_~tmp~3#1); 5144#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5521#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5120#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5158#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 5159#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5418#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5556#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5544#L932 assume !(0 != start_simulation_~tmp___0~1#1); 5424#L900-2 [2024-11-13 13:56:02,480 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:02,480 INFO L85 PathProgramCache]: Analyzing trace with hash 1917465066, now seen corresponding path program 1 times [2024-11-13 13:56:02,481 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:02,481 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [958187012] [2024-11-13 13:56:02,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:02,481 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:02,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:02,564 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:02,564 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:02,564 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [958187012] [2024-11-13 13:56:02,564 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [958187012] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:02,564 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:02,564 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:56:02,565 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [832588287] [2024-11-13 13:56:02,565 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:02,565 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:56:02,565 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:02,565 INFO L85 PathProgramCache]: Analyzing trace with hash -1721218556, now seen corresponding path program 1 times [2024-11-13 13:56:02,565 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:02,565 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [963696532] [2024-11-13 13:56:02,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:02,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:02,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:02,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:02,667 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:02,667 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [963696532] [2024-11-13 13:56:02,667 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [963696532] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:02,667 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:02,667 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:02,667 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1786005347] [2024-11-13 13:56:02,667 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:02,667 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:56:02,667 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:02,668 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:56:02,668 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:56:02,668 INFO L87 Difference]: Start difference. First operand 504 states and 748 transitions. cyclomatic complexity: 245 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:02,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:02,775 INFO L93 Difference]: Finished difference Result 887 states and 1304 transitions. [2024-11-13 13:56:02,775 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 887 states and 1304 transitions. [2024-11-13 13:56:02,782 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 810 [2024-11-13 13:56:02,786 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 887 states to 887 states and 1304 transitions. [2024-11-13 13:56:02,787 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 887 [2024-11-13 13:56:02,788 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 887 [2024-11-13 13:56:02,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 887 states and 1304 transitions. [2024-11-13 13:56:02,789 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:02,790 INFO L218 hiAutomatonCegarLoop]: Abstraction has 887 states and 1304 transitions. [2024-11-13 13:56:02,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 887 states and 1304 transitions. [2024-11-13 13:56:02,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 887 to 887. [2024-11-13 13:56:02,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 887 states, 887 states have (on average 1.4701240135287486) internal successors, (1304), 886 states have internal predecessors, (1304), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:02,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 887 states to 887 states and 1304 transitions. [2024-11-13 13:56:02,812 INFO L240 hiAutomatonCegarLoop]: Abstraction has 887 states and 1304 transitions. [2024-11-13 13:56:02,813 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:56:02,814 INFO L424 stractBuchiCegarLoop]: Abstraction has 887 states and 1304 transitions. [2024-11-13 13:56:02,818 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 13:56:02,818 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 887 states and 1304 transitions. [2024-11-13 13:56:02,822 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 810 [2024-11-13 13:56:02,823 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:02,823 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:02,824 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:02,824 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:02,825 INFO L745 eck$LassoCheckResult]: Stem: 6762#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 6763#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6868#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6869#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6886#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 6887#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6695#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6696#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6978#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6979#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6944#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6666#L586 assume !(0 == ~M_E~0); 6667#L586-2 assume !(0 == ~T1_E~0); 6717#L591-1 assume !(0 == ~T2_E~0); 6832#L596-1 assume !(0 == ~T3_E~0); 6833#L601-1 assume !(0 == ~T4_E~0); 6874#L606-1 assume !(0 == ~T5_E~0); 6875#L611-1 assume !(0 == ~E_1~0); 6952#L616-1 assume !(0 == ~E_2~0); 6953#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 6591#L626-1 assume !(0 == ~E_4~0); 6592#L631-1 assume !(0 == ~E_5~0); 6757#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6586#L279 assume !(1 == ~m_pc~0); 6588#L279-2 is_master_triggered_~__retres1~0#1 := 0; 6898#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6731#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6732#L720 assume !(0 != activate_threads_~tmp~1#1); 6897#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6764#L298 assume !(1 == ~t1_pc~0); 6533#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6534#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6562#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6563#L728 assume !(0 != activate_threads_~tmp___0~0#1); 6600#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6723#L317 assume 1 == ~t2_pc~0; 6724#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6867#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6873#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6774#L736 assume !(0 != activate_threads_~tmp___1~0#1); 6775#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6941#L336 assume 1 == ~t3_pc~0; 6812#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6813#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6506#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6507#L744 assume !(0 != activate_threads_~tmp___2~0#1); 6906#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6949#L355 assume !(1 == ~t4_pc~0); 6831#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6684#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6630#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6631#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6613#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6614#L374 assume 1 == ~t5_pc~0; 6971#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6751#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6737#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6738#L760 assume !(0 != activate_threads_~tmp___4~0#1); 6856#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6857#L649 assume !(1 == ~M_E~0); 6992#L649-2 assume !(1 == ~T1_E~0); 6572#L654-1 assume !(1 == ~T2_E~0); 6573#L659-1 assume !(1 == ~T3_E~0); 6772#L664-1 assume !(1 == ~T4_E~0); 6564#L669-1 assume !(1 == ~T5_E~0); 6565#L674-1 assume !(1 == ~E_1~0); 6932#L679-1 assume !(1 == ~E_2~0); 6668#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 6669#L689-1 assume !(1 == ~E_4~0); 6826#L694-1 assume !(1 == ~E_5~0); 6823#L699-1 assume { :end_inline_reset_delta_events } true; 6824#L900-2 [2024-11-13 13:56:02,825 INFO L747 eck$LassoCheckResult]: Loop: 6824#L900-2 assume !false; 6999#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6743#L561-1 assume !false; 6801#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6792#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6535#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6536#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6657#L486 assume !(0 != eval_~tmp~0#1); 6637#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6638#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6965#L586-3 assume !(0 == ~M_E~0); 6931#L586-5 assume !(0 == ~T1_E~0); 6839#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6686#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6687#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6852#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6889#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6890#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6580#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6531#L626-3 assume !(0 == ~E_4~0); 6532#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6537#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6538#L279-18 assume !(1 == ~m_pc~0); 6646#L279-20 is_master_triggered_~__retres1~0#1 := 0; 6784#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6777#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6778#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6954#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6855#L298-18 assume !(1 == ~t1_pc~0); 6504#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 6505#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6694#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6712#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6713#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6834#L317-18 assume 1 == ~t2_pc~0; 6747#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6748#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6863#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6697#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6698#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6957#L336-18 assume 1 == ~t3_pc~0; 6936#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6937#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6891#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6800#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6639#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6640#L355-18 assume 1 == ~t4_pc~0; 6916#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6905#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6805#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6806#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6733#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6734#L374-18 assume 1 == ~t5_pc~0; 6947#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6797#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6735#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6736#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 6899#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6900#L649-3 assume !(1 == ~M_E~0); 6810#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6791#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6648#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6649#L664-3 assume !(1 == ~T4_E~0); 6539#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6540#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6529#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6530#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6489#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6490#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6742#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7198#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7190#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7188#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 7184#L919 assume !(0 == start_simulation_~tmp~3#1); 7181#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7070#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7057#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7056#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 7054#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7052#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7050#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 7048#L932 assume !(0 != start_simulation_~tmp___0~1#1); 6824#L900-2 [2024-11-13 13:56:02,825 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:02,825 INFO L85 PathProgramCache]: Analyzing trace with hash -484678139, now seen corresponding path program 1 times [2024-11-13 13:56:02,826 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:02,826 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529988910] [2024-11-13 13:56:02,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:02,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:02,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:02,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:02,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:02,950 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1529988910] [2024-11-13 13:56:02,950 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1529988910] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:02,950 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:02,950 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:02,950 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1382867372] [2024-11-13 13:56:02,951 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:02,951 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:56:02,951 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:02,952 INFO L85 PathProgramCache]: Analyzing trace with hash 377183137, now seen corresponding path program 1 times [2024-11-13 13:56:02,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:02,952 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1135395676] [2024-11-13 13:56:02,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:02,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:02,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:03,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:03,023 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:03,023 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1135395676] [2024-11-13 13:56:03,023 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1135395676] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:03,024 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:03,024 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:03,024 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1820586489] [2024-11-13 13:56:03,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:03,024 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:56:03,024 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:03,025 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:56:03,025 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:56:03,025 INFO L87 Difference]: Start difference. First operand 887 states and 1304 transitions. cyclomatic complexity: 418 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:03,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:03,237 INFO L93 Difference]: Finished difference Result 1620 states and 2381 transitions. [2024-11-13 13:56:03,237 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1620 states and 2381 transitions. [2024-11-13 13:56:03,248 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1532 [2024-11-13 13:56:03,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1620 states to 1620 states and 2381 transitions. [2024-11-13 13:56:03,257 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1620 [2024-11-13 13:56:03,259 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1620 [2024-11-13 13:56:03,259 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1620 states and 2381 transitions. [2024-11-13 13:56:03,262 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:03,262 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1620 states and 2381 transitions. [2024-11-13 13:56:03,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1620 states and 2381 transitions. [2024-11-13 13:56:03,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1620 to 1618. [2024-11-13 13:56:03,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1618 states, 1618 states have (on average 1.4703337453646477) internal successors, (2379), 1617 states have internal predecessors, (2379), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:03,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1618 states to 1618 states and 2379 transitions. [2024-11-13 13:56:03,300 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1618 states and 2379 transitions. [2024-11-13 13:56:03,301 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:56:03,304 INFO L424 stractBuchiCegarLoop]: Abstraction has 1618 states and 2379 transitions. [2024-11-13 13:56:03,304 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 13:56:03,304 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1618 states and 2379 transitions. [2024-11-13 13:56:03,313 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1532 [2024-11-13 13:56:03,314 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:03,314 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:03,316 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:03,316 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:03,317 INFO L745 eck$LassoCheckResult]: Stem: 9285#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 9286#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9403#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9404#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9422#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 9423#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9217#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9218#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9528#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9529#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9491#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9187#L586 assume !(0 == ~M_E~0); 9188#L586-2 assume !(0 == ~T1_E~0); 9241#L591-1 assume !(0 == ~T2_E~0); 9363#L596-1 assume !(0 == ~T3_E~0); 9364#L601-1 assume !(0 == ~T4_E~0); 9408#L606-1 assume !(0 == ~T5_E~0); 9409#L611-1 assume !(0 == ~E_1~0); 9498#L616-1 assume !(0 == ~E_2~0); 9499#L621-1 assume !(0 == ~E_3~0); 9110#L626-1 assume !(0 == ~E_4~0); 9111#L631-1 assume !(0 == ~E_5~0); 9280#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9107#L279 assume !(1 == ~m_pc~0); 9109#L279-2 is_master_triggered_~__retres1~0#1 := 0; 9437#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9255#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9256#L720 assume !(0 != activate_threads_~tmp~1#1); 9436#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9287#L298 assume !(1 == ~t1_pc~0); 9052#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9053#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9078#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9079#L728 assume !(0 != activate_threads_~tmp___0~0#1); 9119#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9247#L317 assume 1 == ~t2_pc~0; 9248#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9401#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9407#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9297#L736 assume !(0 != activate_threads_~tmp___1~0#1); 9298#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9486#L336 assume 1 == ~t3_pc~0; 9337#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9338#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9023#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9024#L744 assume !(0 != activate_threads_~tmp___2~0#1); 9445#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9495#L355 assume !(1 == ~t4_pc~0); 9362#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9205#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9150#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9151#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9132#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9133#L374 assume 1 == ~t5_pc~0; 9519#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9274#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9261#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9262#L760 assume !(0 != activate_threads_~tmp___4~0#1); 9388#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9389#L649 assume !(1 == ~M_E~0); 9559#L649-2 assume !(1 == ~T1_E~0); 9089#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9090#L659-1 assume !(1 == ~T3_E~0); 9295#L664-1 assume !(1 == ~T4_E~0); 9080#L669-1 assume !(1 == ~T5_E~0); 9081#L674-1 assume !(1 == ~E_1~0); 9476#L679-1 assume !(1 == ~E_2~0); 9189#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 9190#L689-1 assume !(1 == ~E_4~0); 9357#L694-1 assume !(1 == ~E_5~0); 9588#L699-1 assume { :end_inline_reset_delta_events } true; 9644#L900-2 [2024-11-13 13:56:03,317 INFO L747 eck$LassoCheckResult]: Loop: 9644#L900-2 assume !false; 9640#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9639#L561-1 assume !false; 9638#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9636#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9631#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9630#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9628#L486 assume !(0 != eval_~tmp~0#1); 9627#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9626#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9625#L586-3 assume !(0 == ~M_E~0); 9624#L586-5 assume !(0 == ~T1_E~0); 9621#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9622#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10582#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10581#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10580#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10579#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10578#L621-3 assume !(0 == ~E_3~0); 10577#L626-3 assume !(0 == ~E_4~0); 10576#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10575#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10574#L279-18 assume !(1 == ~m_pc~0); 10232#L279-20 is_master_triggered_~__retres1~0#1 := 0; 10231#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10230#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10229#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10228#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10227#L298-18 assume 1 == ~t1_pc~0; 10225#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10224#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10223#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10222#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10220#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10219#L317-18 assume !(1 == ~t2_pc~0); 10217#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 9400#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9395#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9396#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10215#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10213#L336-18 assume 1 == ~t3_pc~0; 10199#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10195#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10191#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10187#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10182#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10176#L355-18 assume !(1 == ~t4_pc~0); 10108#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 10106#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10104#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10102#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10100#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10093#L374-18 assume 1 == ~t5_pc~0; 10085#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10083#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10081#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10079#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 10078#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9575#L649-3 assume !(1 == ~M_E~0); 9576#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9911#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9907#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9905#L664-3 assume !(1 == ~T4_E~0); 9902#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9900#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9898#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9896#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9892#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9890#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9887#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9885#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9878#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9876#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 9764#L919 assume !(0 == start_simulation_~tmp~3#1); 9738#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9684#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9679#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9678#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 9677#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9661#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9657#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 9650#L932 assume !(0 != start_simulation_~tmp___0~1#1); 9644#L900-2 [2024-11-13 13:56:03,317 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:03,317 INFO L85 PathProgramCache]: Analyzing trace with hash 1446688901, now seen corresponding path program 1 times [2024-11-13 13:56:03,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:03,318 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [731183611] [2024-11-13 13:56:03,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:03,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:03,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:03,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:03,374 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:03,374 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [731183611] [2024-11-13 13:56:03,374 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [731183611] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:03,374 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:03,374 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:56:03,374 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [474250198] [2024-11-13 13:56:03,374 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:03,375 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:56:03,375 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:03,375 INFO L85 PathProgramCache]: Analyzing trace with hash -111992898, now seen corresponding path program 1 times [2024-11-13 13:56:03,375 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:03,375 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1558672267] [2024-11-13 13:56:03,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:03,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:03,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:03,424 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:03,424 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:03,424 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1558672267] [2024-11-13 13:56:03,426 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1558672267] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:03,426 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:03,426 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:03,426 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1995276595] [2024-11-13 13:56:03,426 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:03,426 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:56:03,426 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:03,427 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:56:03,427 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:56:03,427 INFO L87 Difference]: Start difference. First operand 1618 states and 2379 transitions. cyclomatic complexity: 763 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:03,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:03,519 INFO L93 Difference]: Finished difference Result 3035 states and 4428 transitions. [2024-11-13 13:56:03,519 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3035 states and 4428 transitions. [2024-11-13 13:56:03,538 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2942 [2024-11-13 13:56:03,552 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3035 states to 3035 states and 4428 transitions. [2024-11-13 13:56:03,553 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3035 [2024-11-13 13:56:03,556 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3035 [2024-11-13 13:56:03,556 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3035 states and 4428 transitions. [2024-11-13 13:56:03,561 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:03,561 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3035 states and 4428 transitions. [2024-11-13 13:56:03,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3035 states and 4428 transitions. [2024-11-13 13:56:03,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3035 to 3027. [2024-11-13 13:56:03,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3027 states, 3027 states have (on average 1.4601916088536504) internal successors, (4420), 3026 states have internal predecessors, (4420), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:03,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3027 states to 3027 states and 4420 transitions. [2024-11-13 13:56:03,636 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3027 states and 4420 transitions. [2024-11-13 13:56:03,636 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:56:03,638 INFO L424 stractBuchiCegarLoop]: Abstraction has 3027 states and 4420 transitions. [2024-11-13 13:56:03,638 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 13:56:03,638 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3027 states and 4420 transitions. [2024-11-13 13:56:03,654 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2934 [2024-11-13 13:56:03,655 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:03,655 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:03,656 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:03,656 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:03,656 INFO L745 eck$LassoCheckResult]: Stem: 13947#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 13948#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 14072#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14073#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14092#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 14093#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13881#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13882#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14215#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14216#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14172#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13851#L586 assume !(0 == ~M_E~0); 13852#L586-2 assume !(0 == ~T1_E~0); 13904#L591-1 assume !(0 == ~T2_E~0); 14030#L596-1 assume !(0 == ~T3_E~0); 14031#L601-1 assume !(0 == ~T4_E~0); 14080#L606-1 assume !(0 == ~T5_E~0); 14081#L611-1 assume !(0 == ~E_1~0); 14180#L616-1 assume !(0 == ~E_2~0); 14181#L621-1 assume !(0 == ~E_3~0); 13769#L626-1 assume !(0 == ~E_4~0); 13770#L631-1 assume !(0 == ~E_5~0); 13942#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13766#L279 assume !(1 == ~m_pc~0); 13768#L279-2 is_master_triggered_~__retres1~0#1 := 0; 14107#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13917#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13918#L720 assume !(0 != activate_threads_~tmp~1#1); 14106#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13949#L298 assume !(1 == ~t1_pc~0); 13712#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13713#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13738#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13739#L728 assume !(0 != activate_threads_~tmp___0~0#1); 13779#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13910#L317 assume !(1 == ~t2_pc~0); 13911#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14129#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14077#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13959#L736 assume !(0 != activate_threads_~tmp___1~0#1); 13960#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14166#L336 assume 1 == ~t3_pc~0; 14006#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14007#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13683#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13684#L744 assume !(0 != activate_threads_~tmp___2~0#1); 14116#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14176#L355 assume !(1 == ~t4_pc~0); 14029#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 13870#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13810#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13811#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13792#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13793#L374 assume 1 == ~t5_pc~0; 14204#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13936#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13923#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13924#L760 assume !(0 != activate_threads_~tmp___4~0#1); 14059#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14060#L649 assume !(1 == ~M_E~0); 14239#L649-2 assume !(1 == ~T1_E~0); 13748#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13749#L659-1 assume !(1 == ~T3_E~0); 13957#L664-1 assume !(1 == ~T4_E~0); 13740#L669-1 assume !(1 == ~T5_E~0); 13741#L674-1 assume !(1 == ~E_1~0); 14157#L679-1 assume !(1 == ~E_2~0); 13853#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 13854#L689-1 assume !(1 == ~E_4~0); 14024#L694-1 assume !(1 == ~E_5~0); 14020#L699-1 assume { :end_inline_reset_delta_events } true; 14021#L900-2 [2024-11-13 13:56:03,656 INFO L747 eck$LassoCheckResult]: Loop: 14021#L900-2 assume !false; 15122#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15945#L561-1 assume !false; 15944#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 13979#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 13710#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 13711#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14095#L486 assume !(0 != eval_~tmp~0#1); 15935#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16569#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16568#L586-3 assume !(0 == ~M_E~0); 16567#L586-5 assume !(0 == ~T1_E~0); 16564#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16560#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16556#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16555#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16554#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16553#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16552#L621-3 assume !(0 == ~E_3~0); 16551#L626-3 assume !(0 == ~E_4~0); 16550#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16549#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16548#L279-18 assume !(1 == ~m_pc~0); 16546#L279-20 is_master_triggered_~__retres1~0#1 := 0; 16545#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16544#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16543#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14182#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14058#L298-18 assume !(1 == ~t1_pc~0); 13681#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 13682#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13880#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13900#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13901#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14032#L317-18 assume !(1 == ~t2_pc~0); 14033#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 16688#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16686#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16684#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14187#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14185#L336-18 assume 1 == ~t3_pc~0; 14161#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14162#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14099#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13990#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13820#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13821#L355-18 assume !(1 == ~t4_pc~0); 14114#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 14115#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13994#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13995#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13919#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13920#L374-18 assume !(1 == ~t5_pc~0); 14136#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 13984#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13985#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15408#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 15406#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15404#L649-3 assume !(1 == ~M_E~0); 15400#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15398#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15396#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15394#L664-3 assume !(1 == ~T4_E~0); 15392#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15390#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15388#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15385#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15383#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15381#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15379#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 15374#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 15367#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 15365#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 15334#L919 assume !(0 == start_simulation_~tmp~3#1); 15331#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 15324#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 15319#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 13733#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 13734#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14010#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14186#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 14200#L932 assume !(0 != start_simulation_~tmp___0~1#1); 14021#L900-2 [2024-11-13 13:56:03,657 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:03,657 INFO L85 PathProgramCache]: Analyzing trace with hash -318127708, now seen corresponding path program 1 times [2024-11-13 13:56:03,657 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:03,657 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [581233314] [2024-11-13 13:56:03,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:03,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:03,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:03,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:03,714 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:03,714 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [581233314] [2024-11-13 13:56:03,714 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [581233314] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:03,714 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:03,714 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:56:03,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2146918056] [2024-11-13 13:56:03,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:03,714 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:56:03,715 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:03,715 INFO L85 PathProgramCache]: Analyzing trace with hash -66335876, now seen corresponding path program 1 times [2024-11-13 13:56:03,715 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:03,715 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [932519140] [2024-11-13 13:56:03,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:03,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:03,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:03,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:03,758 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:03,758 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [932519140] [2024-11-13 13:56:03,758 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [932519140] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:03,758 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:03,758 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:03,758 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1977286859] [2024-11-13 13:56:03,758 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:03,759 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:56:03,759 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:03,759 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:56:03,759 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:56:03,760 INFO L87 Difference]: Start difference. First operand 3027 states and 4420 transitions. cyclomatic complexity: 1397 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:03,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:03,862 INFO L93 Difference]: Finished difference Result 5566 states and 8084 transitions. [2024-11-13 13:56:03,862 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5566 states and 8084 transitions. [2024-11-13 13:56:03,898 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5458 [2024-11-13 13:56:03,926 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5566 states to 5566 states and 8084 transitions. [2024-11-13 13:56:03,926 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5566 [2024-11-13 13:56:03,933 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5566 [2024-11-13 13:56:03,933 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5566 states and 8084 transitions. [2024-11-13 13:56:03,942 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:03,942 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5566 states and 8084 transitions. [2024-11-13 13:56:03,948 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5566 states and 8084 transitions. [2024-11-13 13:56:04,025 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5566 to 5550. [2024-11-13 13:56:04,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5550 states, 5550 states have (on average 1.4536936936936937) internal successors, (8068), 5549 states have internal predecessors, (8068), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:04,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5550 states to 5550 states and 8068 transitions. [2024-11-13 13:56:04,054 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5550 states and 8068 transitions. [2024-11-13 13:56:04,054 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:56:04,056 INFO L424 stractBuchiCegarLoop]: Abstraction has 5550 states and 8068 transitions. [2024-11-13 13:56:04,056 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 13:56:04,056 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5550 states and 8068 transitions. [2024-11-13 13:56:04,080 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5442 [2024-11-13 13:56:04,080 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:04,080 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:04,082 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:04,082 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:04,082 INFO L745 eck$LassoCheckResult]: Stem: 22539#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 22540#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 22654#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22655#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22672#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 22673#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22475#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22476#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22782#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22783#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22742#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22443#L586 assume !(0 == ~M_E~0); 22444#L586-2 assume !(0 == ~T1_E~0); 22496#L591-1 assume !(0 == ~T2_E~0); 22611#L596-1 assume !(0 == ~T3_E~0); 22612#L601-1 assume !(0 == ~T4_E~0); 22660#L606-1 assume !(0 == ~T5_E~0); 22661#L611-1 assume !(0 == ~E_1~0); 22752#L616-1 assume !(0 == ~E_2~0); 22753#L621-1 assume !(0 == ~E_3~0); 22369#L626-1 assume !(0 == ~E_4~0); 22370#L631-1 assume !(0 == ~E_5~0); 22534#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22364#L279 assume !(1 == ~m_pc~0); 22366#L279-2 is_master_triggered_~__retres1~0#1 := 0; 22689#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22509#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22510#L720 assume !(0 != activate_threads_~tmp~1#1); 22688#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22541#L298 assume !(1 == ~t1_pc~0); 22310#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22311#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22337#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 22338#L728 assume !(0 != activate_threads_~tmp___0~0#1); 22378#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22502#L317 assume !(1 == ~t2_pc~0); 22503#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22707#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22659#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22550#L736 assume !(0 != activate_threads_~tmp___1~0#1); 22551#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22738#L336 assume !(1 == ~t3_pc~0); 22739#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22810#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22283#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22284#L744 assume !(0 != activate_threads_~tmp___2~0#1); 22697#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22747#L355 assume !(1 == ~t4_pc~0); 22608#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22462#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22408#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22409#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22388#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22389#L374 assume 1 == ~t5_pc~0; 22773#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22525#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22515#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22516#L760 assume !(0 != activate_threads_~tmp___4~0#1); 22643#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22644#L649 assume !(1 == ~M_E~0); 22805#L649-2 assume !(1 == ~T1_E~0); 22349#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22350#L659-1 assume !(1 == ~T3_E~0); 22549#L664-1 assume !(1 == ~T4_E~0); 22341#L669-1 assume !(1 == ~T5_E~0); 22342#L674-1 assume !(1 == ~E_1~0); 22729#L679-1 assume !(1 == ~E_2~0); 22448#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 22449#L689-1 assume !(1 == ~E_4~0); 22604#L694-1 assume !(1 == ~E_5~0); 22602#L699-1 assume { :end_inline_reset_delta_events } true; 22603#L900-2 [2024-11-13 13:56:04,083 INFO L747 eck$LassoCheckResult]: Loop: 22603#L900-2 assume !false; 25634#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25633#L561-1 assume !false; 24951#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 24831#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 24823#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 24821#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24818#L486 assume !(0 != eval_~tmp~0#1); 24819#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25588#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25587#L586-3 assume !(0 == ~M_E~0); 25586#L586-5 assume !(0 == ~T1_E~0); 25585#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25584#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25583#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25582#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25581#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25580#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25579#L621-3 assume !(0 == ~E_3~0); 25578#L626-3 assume !(0 == ~E_4~0); 25577#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25576#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25575#L279-18 assume !(1 == ~m_pc~0); 25573#L279-20 is_master_triggered_~__retres1~0#1 := 0; 25572#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25571#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 25570#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25569#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25568#L298-18 assume 1 == ~t1_pc~0; 25566#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25565#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25564#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 25563#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25562#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25561#L317-18 assume !(1 == ~t2_pc~0); 25560#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 25559#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25558#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25557#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25556#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25555#L336-18 assume !(1 == ~t3_pc~0); 25554#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 25553#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25552#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25551#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25550#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25549#L355-18 assume !(1 == ~t4_pc~0); 25547#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 25546#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25545#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25544#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25543#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25542#L374-18 assume 1 == ~t5_pc~0; 25540#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25539#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25538#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25537#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 25536#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25535#L649-3 assume !(1 == ~M_E~0); 25432#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25534#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24411#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25533#L664-3 assume !(1 == ~T4_E~0); 25532#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25531#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25530#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25529#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24397#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25528#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25527#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 25526#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 25520#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 25519#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 25163#L919 assume !(0 == start_simulation_~tmp~3#1); 25164#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 25668#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 25663#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 25660#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 25656#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25653#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25649#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 25643#L932 assume !(0 != start_simulation_~tmp___0~1#1); 22603#L900-2 [2024-11-13 13:56:04,083 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:04,083 INFO L85 PathProgramCache]: Analyzing trace with hash -375271933, now seen corresponding path program 1 times [2024-11-13 13:56:04,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:04,083 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1843795235] [2024-11-13 13:56:04,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:04,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:04,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:04,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:04,152 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:04,152 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1843795235] [2024-11-13 13:56:04,152 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1843795235] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:04,152 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:04,152 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:56:04,153 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1357691162] [2024-11-13 13:56:04,153 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:04,153 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:56:04,153 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:04,153 INFO L85 PathProgramCache]: Analyzing trace with hash 2027459997, now seen corresponding path program 1 times [2024-11-13 13:56:04,153 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:04,153 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1553522288] [2024-11-13 13:56:04,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:04,153 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:04,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:04,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:04,254 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:04,254 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1553522288] [2024-11-13 13:56:04,254 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1553522288] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:04,254 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:04,254 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:04,254 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [570673206] [2024-11-13 13:56:04,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:04,254 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:56:04,255 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:04,255 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:56:04,255 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:56:04,255 INFO L87 Difference]: Start difference. First operand 5550 states and 8068 transitions. cyclomatic complexity: 2526 Second operand has 5 states, 5 states have (on average 14.2) internal successors, (71), 5 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:04,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:04,501 INFO L93 Difference]: Finished difference Result 5805 states and 8323 transitions. [2024-11-13 13:56:04,502 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5805 states and 8323 transitions. [2024-11-13 13:56:04,531 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5694 [2024-11-13 13:56:04,566 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5805 states to 5805 states and 8323 transitions. [2024-11-13 13:56:04,566 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5805 [2024-11-13 13:56:04,572 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5805 [2024-11-13 13:56:04,572 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5805 states and 8323 transitions. [2024-11-13 13:56:04,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:04,582 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5805 states and 8323 transitions. [2024-11-13 13:56:04,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5805 states and 8323 transitions. [2024-11-13 13:56:04,649 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5805 to 5805. [2024-11-13 13:56:04,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5805 states, 5805 states have (on average 1.4337639965546942) internal successors, (8323), 5804 states have internal predecessors, (8323), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:04,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5805 states to 5805 states and 8323 transitions. [2024-11-13 13:56:04,679 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5805 states and 8323 transitions. [2024-11-13 13:56:04,679 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:56:04,679 INFO L424 stractBuchiCegarLoop]: Abstraction has 5805 states and 8323 transitions. [2024-11-13 13:56:04,680 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 13:56:04,680 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5805 states and 8323 transitions. [2024-11-13 13:56:04,698 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5694 [2024-11-13 13:56:04,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:04,698 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:04,699 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:04,699 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:04,700 INFO L745 eck$LassoCheckResult]: Stem: 33911#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 33912#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 34024#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34025#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34045#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 34046#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33845#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33846#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34160#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34161#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34115#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33816#L586 assume !(0 == ~M_E~0); 33817#L586-2 assume !(0 == ~T1_E~0); 33867#L591-1 assume !(0 == ~T2_E~0); 33988#L596-1 assume !(0 == ~T3_E~0); 33989#L601-1 assume !(0 == ~T4_E~0); 34032#L606-1 assume !(0 == ~T5_E~0); 34033#L611-1 assume !(0 == ~E_1~0); 34128#L616-1 assume !(0 == ~E_2~0); 34129#L621-1 assume !(0 == ~E_3~0); 33735#L626-1 assume !(0 == ~E_4~0); 33736#L631-1 assume !(0 == ~E_5~0); 33906#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33730#L279 assume !(1 == ~m_pc~0); 33732#L279-2 is_master_triggered_~__retres1~0#1 := 0; 34060#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33880#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 33881#L720 assume !(0 != activate_threads_~tmp~1#1); 34059#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33913#L298 assume !(1 == ~t1_pc~0); 33674#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33675#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33700#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 33701#L728 assume !(0 != activate_threads_~tmp___0~0#1); 33744#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33873#L317 assume !(1 == ~t2_pc~0); 33874#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34079#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34029#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 33923#L736 assume !(0 != activate_threads_~tmp___1~0#1); 33924#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34112#L336 assume !(1 == ~t3_pc~0); 34113#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34192#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33647#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33648#L744 assume !(0 != activate_threads_~tmp___2~0#1); 34068#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34122#L355 assume !(1 == ~t4_pc~0); 33987#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33832#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33776#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33777#L752 assume !(0 != activate_threads_~tmp___3~0#1); 33759#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33760#L374 assume 1 == ~t5_pc~0; 34152#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33900#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33886#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33887#L760 assume !(0 != activate_threads_~tmp___4~0#1); 34014#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34015#L649 assume !(1 == ~M_E~0); 34184#L649-2 assume !(1 == ~T1_E~0); 33713#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33714#L659-1 assume !(1 == ~T3_E~0); 34056#L664-1 assume !(1 == ~T4_E~0); 36475#L669-1 assume !(1 == ~T5_E~0); 36473#L674-1 assume !(1 == ~E_1~0); 34120#L679-1 assume !(1 == ~E_2~0); 33818#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 33819#L689-1 assume !(1 == ~E_4~0); 33981#L694-1 assume !(1 == ~E_5~0); 33978#L699-1 assume { :end_inline_reset_delta_events } true; 33979#L900-2 [2024-11-13 13:56:04,700 INFO L747 eck$LassoCheckResult]: Loop: 33979#L900-2 assume !false; 37009#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37007#L561-1 assume !false; 37006#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 37002#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 36994#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 36992#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 36989#L486 assume !(0 != eval_~tmp~0#1); 36990#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37166#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37165#L586-3 assume !(0 == ~M_E~0); 37164#L586-5 assume !(0 == ~T1_E~0); 37163#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37161#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37160#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37159#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37158#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37157#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37155#L621-3 assume !(0 == ~E_3~0); 37154#L626-3 assume !(0 == ~E_4~0); 37153#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37152#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37151#L279-18 assume !(1 == ~m_pc~0); 37149#L279-20 is_master_triggered_~__retres1~0#1 := 0; 37148#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37147#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 37145#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37142#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37140#L298-18 assume 1 == ~t1_pc~0; 37137#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37135#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37133#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 37131#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37129#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37126#L317-18 assume !(1 == ~t2_pc~0); 37124#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 37122#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37120#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 37118#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37116#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37114#L336-18 assume !(1 == ~t3_pc~0); 37112#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 37110#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37108#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 37106#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37104#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37102#L355-18 assume !(1 == ~t4_pc~0); 37098#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 37096#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37094#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 37092#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 37087#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37085#L374-18 assume 1 == ~t5_pc~0; 37082#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37080#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37077#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 37075#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 37073#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37070#L649-3 assume !(1 == ~M_E~0); 37066#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37064#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36577#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37061#L664-3 assume !(1 == ~T4_E~0); 37060#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37059#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37055#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37053#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36570#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37051#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37050#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 37049#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 37041#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 37039#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 37036#L919 assume !(0 == start_simulation_~tmp~3#1); 37037#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 37236#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 37227#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 37222#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 37215#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37209#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37204#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 37200#L932 assume !(0 != start_simulation_~tmp___0~1#1); 33979#L900-2 [2024-11-13 13:56:04,701 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:04,701 INFO L85 PathProgramCache]: Analyzing trace with hash -1192920383, now seen corresponding path program 1 times [2024-11-13 13:56:04,701 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:04,701 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [685461157] [2024-11-13 13:56:04,701 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:04,701 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:04,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:04,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:04,750 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:04,750 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [685461157] [2024-11-13 13:56:04,750 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [685461157] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:04,750 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:04,751 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:56:04,751 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1332144655] [2024-11-13 13:56:04,751 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:04,751 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:56:04,751 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:04,751 INFO L85 PathProgramCache]: Analyzing trace with hash -1992747685, now seen corresponding path program 1 times [2024-11-13 13:56:04,751 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:04,751 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1463707601] [2024-11-13 13:56:04,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:04,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:04,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:04,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:04,794 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:04,794 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1463707601] [2024-11-13 13:56:04,794 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1463707601] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:04,794 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:04,794 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:04,794 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [424456353] [2024-11-13 13:56:04,794 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:04,795 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:56:04,795 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:04,795 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:56:04,795 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:56:04,795 INFO L87 Difference]: Start difference. First operand 5805 states and 8323 transitions. cyclomatic complexity: 2526 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:04,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:04,915 INFO L93 Difference]: Finished difference Result 11422 states and 16248 transitions. [2024-11-13 13:56:04,916 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11422 states and 16248 transitions. [2024-11-13 13:56:04,960 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11256 [2024-11-13 13:56:05,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11422 states to 11422 states and 16248 transitions. [2024-11-13 13:56:05,011 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11422 [2024-11-13 13:56:05,022 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11422 [2024-11-13 13:56:05,023 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11422 states and 16248 transitions. [2024-11-13 13:56:05,041 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:05,041 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11422 states and 16248 transitions. [2024-11-13 13:56:05,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11422 states and 16248 transitions. [2024-11-13 13:56:05,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11422 to 11358. [2024-11-13 13:56:05,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11358 states, 11358 states have (on average 1.4234900510653283) internal successors, (16168), 11357 states have internal predecessors, (16168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:05,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11358 states to 11358 states and 16168 transitions. [2024-11-13 13:56:05,376 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11358 states and 16168 transitions. [2024-11-13 13:56:05,376 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:56:05,376 INFO L424 stractBuchiCegarLoop]: Abstraction has 11358 states and 16168 transitions. [2024-11-13 13:56:05,377 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 13:56:05,377 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11358 states and 16168 transitions. [2024-11-13 13:56:05,414 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11224 [2024-11-13 13:56:05,414 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:05,414 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:05,417 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:05,417 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:05,417 INFO L745 eck$LassoCheckResult]: Stem: 51145#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 51146#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 51273#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 51274#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51294#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 51295#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51075#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 51076#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 51418#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 51419#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 51368#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 51045#L586 assume !(0 == ~M_E~0); 51046#L586-2 assume !(0 == ~T1_E~0); 51100#L591-1 assume !(0 == ~T2_E~0); 51227#L596-1 assume !(0 == ~T3_E~0); 51228#L601-1 assume !(0 == ~T4_E~0); 51281#L606-1 assume !(0 == ~T5_E~0); 51282#L611-1 assume !(0 == ~E_1~0); 51384#L616-1 assume !(0 == ~E_2~0); 51385#L621-1 assume !(0 == ~E_3~0); 50966#L626-1 assume !(0 == ~E_4~0); 50967#L631-1 assume !(0 == ~E_5~0); 51138#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50961#L279 assume !(1 == ~m_pc~0); 50963#L279-2 is_master_triggered_~__retres1~0#1 := 0; 51309#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51113#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 51114#L720 assume !(0 != activate_threads_~tmp~1#1); 51308#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51147#L298 assume !(1 == ~t1_pc~0); 50907#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50908#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50933#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 50934#L728 assume !(0 != activate_threads_~tmp___0~0#1); 50977#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51106#L317 assume !(1 == ~t2_pc~0); 51107#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 51328#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51280#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 51157#L736 assume !(0 != activate_threads_~tmp___1~0#1); 51158#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51365#L336 assume !(1 == ~t3_pc~0); 51366#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 51461#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50880#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 50881#L744 assume !(0 != activate_threads_~tmp___2~0#1); 51317#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51376#L355 assume !(1 == ~t4_pc~0); 51226#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51061#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51007#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 51008#L752 assume !(0 != activate_threads_~tmp___3~0#1); 50989#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50990#L374 assume !(1 == ~t5_pc~0); 51131#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 51132#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51119#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 51120#L760 assume !(0 != activate_threads_~tmp___4~0#1); 51260#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51261#L649 assume !(1 == ~M_E~0); 51453#L649-2 assume !(1 == ~T1_E~0); 50946#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50947#L659-1 assume !(1 == ~T3_E~0); 54449#L664-1 assume !(1 == ~T4_E~0); 54448#L669-1 assume !(1 == ~T5_E~0); 51353#L674-1 assume !(1 == ~E_1~0); 51354#L679-1 assume !(1 == ~E_2~0); 51373#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 51049#L689-1 assume !(1 == ~E_4~0); 51220#L694-1 assume !(1 == ~E_5~0); 51217#L699-1 assume { :end_inline_reset_delta_events } true; 51218#L900-2 [2024-11-13 13:56:05,418 INFO L747 eck$LassoCheckResult]: Loop: 51218#L900-2 assume !false; 54766#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54763#L561-1 assume !false; 54759#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 54755#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 54748#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 54745#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 54741#L486 assume !(0 != eval_~tmp~0#1); 54738#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54736#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54733#L586-3 assume !(0 == ~M_E~0); 54731#L586-5 assume !(0 == ~T1_E~0); 54728#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54725#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54722#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54719#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 54716#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54714#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54710#L621-3 assume !(0 == ~E_3~0); 54707#L626-3 assume !(0 == ~E_4~0); 54699#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54695#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54690#L279-18 assume !(1 == ~m_pc~0); 54684#L279-20 is_master_triggered_~__retres1~0#1 := 0; 54681#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54677#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 54672#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 54668#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54664#L298-18 assume 1 == ~t1_pc~0; 54658#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 54654#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54650#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 54646#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54641#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54637#L317-18 assume !(1 == ~t2_pc~0); 54632#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 54627#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54620#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54616#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54612#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54608#L336-18 assume !(1 == ~t3_pc~0); 54604#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 54600#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54595#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 54589#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54583#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54578#L355-18 assume 1 == ~t4_pc~0; 54573#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54569#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54565#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 54561#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54555#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54550#L374-18 assume !(1 == ~t5_pc~0); 54545#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 54540#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54534#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 54529#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 54523#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54365#L649-3 assume !(1 == ~M_E~0); 54245#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54357#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54074#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54353#L664-3 assume !(1 == ~T4_E~0); 54352#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54350#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54347#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54346#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54061#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54345#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54343#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 54339#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 54332#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 54330#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 54327#L919 assume !(0 == start_simulation_~tmp~3#1); 54328#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 54920#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 54908#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 54904#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 54902#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54895#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54785#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 54784#L932 assume !(0 != start_simulation_~tmp___0~1#1); 51218#L900-2 [2024-11-13 13:56:05,418 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:05,418 INFO L85 PathProgramCache]: Analyzing trace with hash -52568672, now seen corresponding path program 1 times [2024-11-13 13:56:05,418 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:05,418 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1015397348] [2024-11-13 13:56:05,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:05,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:05,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:05,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:05,481 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:05,481 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1015397348] [2024-11-13 13:56:05,481 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1015397348] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:05,481 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:05,481 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:56:05,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [995515099] [2024-11-13 13:56:05,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:05,481 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:56:05,482 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:05,482 INFO L85 PathProgramCache]: Analyzing trace with hash -559834915, now seen corresponding path program 1 times [2024-11-13 13:56:05,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:05,482 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1214171006] [2024-11-13 13:56:05,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:05,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:05,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:05,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:05,536 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:05,536 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1214171006] [2024-11-13 13:56:05,537 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1214171006] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:05,537 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:05,537 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:05,537 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [636698078] [2024-11-13 13:56:05,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:05,537 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:56:05,537 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:05,538 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:56:05,538 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:56:05,538 INFO L87 Difference]: Start difference. First operand 11358 states and 16168 transitions. cyclomatic complexity: 4826 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:05,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:05,603 INFO L93 Difference]: Finished difference Result 11352 states and 16075 transitions. [2024-11-13 13:56:05,604 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11352 states and 16075 transitions. [2024-11-13 13:56:05,645 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11224 [2024-11-13 13:56:05,691 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11352 states to 11352 states and 16075 transitions. [2024-11-13 13:56:05,691 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11352 [2024-11-13 13:56:05,702 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11352 [2024-11-13 13:56:05,702 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11352 states and 16075 transitions. [2024-11-13 13:56:05,717 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:05,717 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11352 states and 16075 transitions. [2024-11-13 13:56:05,729 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11352 states and 16075 transitions. [2024-11-13 13:56:05,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11352 to 5897. [2024-11-13 13:56:05,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5897 states, 5897 states have (on average 1.4132609801594032) internal successors, (8334), 5896 states have internal predecessors, (8334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:05,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5897 states to 5897 states and 8334 transitions. [2024-11-13 13:56:05,841 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5897 states and 8334 transitions. [2024-11-13 13:56:05,841 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:56:05,842 INFO L424 stractBuchiCegarLoop]: Abstraction has 5897 states and 8334 transitions. [2024-11-13 13:56:05,844 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 13:56:05,844 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5897 states and 8334 transitions. [2024-11-13 13:56:05,861 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5796 [2024-11-13 13:56:05,861 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:05,861 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:05,862 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:05,862 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:05,863 INFO L745 eck$LassoCheckResult]: Stem: 73862#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 73863#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 73978#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 73979#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 73995#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 73996#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 73792#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 73793#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 74107#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 74108#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 74069#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 73763#L586 assume !(0 == ~M_E~0); 73764#L586-2 assume !(0 == ~T1_E~0); 73815#L591-1 assume !(0 == ~T2_E~0); 73937#L596-1 assume !(0 == ~T3_E~0); 73938#L601-1 assume !(0 == ~T4_E~0); 73983#L606-1 assume !(0 == ~T5_E~0); 73984#L611-1 assume !(0 == ~E_1~0); 74078#L616-1 assume !(0 == ~E_2~0); 74079#L621-1 assume !(0 == ~E_3~0); 73682#L626-1 assume !(0 == ~E_4~0); 73683#L631-1 assume !(0 == ~E_5~0); 73855#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 73679#L279 assume !(1 == ~m_pc~0); 73681#L279-2 is_master_triggered_~__retres1~0#1 := 0; 74012#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 73828#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 73829#L720 assume !(0 != activate_threads_~tmp~1#1); 74011#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73864#L298 assume !(1 == ~t1_pc~0); 73626#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 73627#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73653#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 73654#L728 assume !(0 != activate_threads_~tmp___0~0#1); 73692#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73821#L317 assume !(1 == ~t2_pc~0); 73822#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 74030#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 73982#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 73874#L736 assume !(0 != activate_threads_~tmp___1~0#1); 73875#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 74063#L336 assume !(1 == ~t3_pc~0); 74064#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 74149#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 73597#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 73598#L744 assume !(0 != activate_threads_~tmp___2~0#1); 74020#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74074#L355 assume !(1 == ~t4_pc~0); 73936#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 74071#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73724#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 73725#L752 assume !(0 != activate_threads_~tmp___3~0#1); 73706#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 73707#L374 assume !(1 == ~t5_pc~0); 73848#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 73849#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 73834#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 73835#L760 assume !(0 != activate_threads_~tmp___4~0#1); 73964#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73965#L649 assume !(1 == ~M_E~0); 74138#L649-2 assume !(1 == ~T1_E~0); 73663#L654-1 assume !(1 == ~T2_E~0); 73664#L659-1 assume !(1 == ~T3_E~0); 73872#L664-1 assume !(1 == ~T4_E~0); 73655#L669-1 assume !(1 == ~T5_E~0); 73656#L674-1 assume !(1 == ~E_1~0); 74052#L679-1 assume !(1 == ~E_2~0); 73765#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 73766#L689-1 assume !(1 == ~E_4~0); 73931#L694-1 assume !(1 == ~E_5~0); 73928#L699-1 assume { :end_inline_reset_delta_events } true; 73929#L900-2 [2024-11-13 13:56:05,863 INFO L747 eck$LassoCheckResult]: Loop: 73929#L900-2 assume !false; 75607#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 75562#L561-1 assume !false; 75604#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 75599#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 75593#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 75592#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 75587#L486 assume !(0 != eval_~tmp~0#1); 75588#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 79261#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 79259#L586-3 assume !(0 == ~M_E~0); 79257#L586-5 assume !(0 == ~T1_E~0); 79254#L591-3 assume !(0 == ~T2_E~0); 79249#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 79248#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 79247#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 79063#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 79062#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 79061#L621-3 assume !(0 == ~E_3~0); 79060#L626-3 assume !(0 == ~E_4~0); 79059#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 79058#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79056#L279-18 assume !(1 == ~m_pc~0); 79053#L279-20 is_master_triggered_~__retres1~0#1 := 0; 79051#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79049#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 79047#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 79045#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 79043#L298-18 assume !(1 == ~t1_pc~0); 79041#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 79038#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 79037#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 79036#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 79031#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75784#L317-18 assume !(1 == ~t2_pc~0); 75781#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 75779#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75777#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 75775#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 75773#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75771#L336-18 assume !(1 == ~t3_pc~0); 75768#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 75766#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75764#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 75762#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 75760#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75753#L355-18 assume !(1 == ~t4_pc~0); 75749#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 75747#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75744#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 75743#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 75740#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75737#L374-18 assume !(1 == ~t5_pc~0); 75735#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 75733#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75731#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 75729#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 75727#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75724#L649-3 assume !(1 == ~M_E~0); 75720#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 75718#L654-3 assume !(1 == ~T2_E~0); 75716#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 75714#L664-3 assume !(1 == ~T4_E~0); 75712#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 75710#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 75708#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 75706#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 75704#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 75702#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 75700#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 75697#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 75690#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 75688#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 75638#L919 assume !(0 == start_simulation_~tmp~3#1); 75636#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 75629#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 75624#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 75622#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 75620#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 75616#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 75614#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 75612#L932 assume !(0 != start_simulation_~tmp___0~1#1); 73929#L900-2 [2024-11-13 13:56:05,863 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:05,864 INFO L85 PathProgramCache]: Analyzing trace with hash -445595682, now seen corresponding path program 1 times [2024-11-13 13:56:05,864 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:05,864 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1393974763] [2024-11-13 13:56:05,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:05,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:05,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:06,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:06,061 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:06,061 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1393974763] [2024-11-13 13:56:06,061 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1393974763] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:06,061 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:06,061 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:06,062 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1734723075] [2024-11-13 13:56:06,062 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:06,062 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:56:06,062 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:06,062 INFO L85 PathProgramCache]: Analyzing trace with hash 180221845, now seen corresponding path program 1 times [2024-11-13 13:56:06,063 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:06,063 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1843544442] [2024-11-13 13:56:06,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:06,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:06,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:06,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:06,113 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:06,113 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1843544442] [2024-11-13 13:56:06,113 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1843544442] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:06,113 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:06,113 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:06,113 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1543812141] [2024-11-13 13:56:06,113 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:06,114 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:56:06,114 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:06,115 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:56:06,115 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:56:06,115 INFO L87 Difference]: Start difference. First operand 5897 states and 8334 transitions. cyclomatic complexity: 2445 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:06,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:06,272 INFO L93 Difference]: Finished difference Result 8753 states and 12285 transitions. [2024-11-13 13:56:06,272 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8753 states and 12285 transitions. [2024-11-13 13:56:06,315 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8640 [2024-11-13 13:56:06,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8753 states to 8753 states and 12285 transitions. [2024-11-13 13:56:06,356 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8753 [2024-11-13 13:56:06,365 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8753 [2024-11-13 13:56:06,366 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8753 states and 12285 transitions. [2024-11-13 13:56:06,377 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:06,377 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8753 states and 12285 transitions. [2024-11-13 13:56:06,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8753 states and 12285 transitions. [2024-11-13 13:56:06,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8753 to 5897. [2024-11-13 13:56:06,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5897 states, 5897 states have (on average 1.400203493301679) internal successors, (8257), 5896 states have internal predecessors, (8257), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:06,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5897 states to 5897 states and 8257 transitions. [2024-11-13 13:56:06,512 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5897 states and 8257 transitions. [2024-11-13 13:56:06,513 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:56:06,513 INFO L424 stractBuchiCegarLoop]: Abstraction has 5897 states and 8257 transitions. [2024-11-13 13:56:06,513 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 13:56:06,513 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5897 states and 8257 transitions. [2024-11-13 13:56:06,536 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5796 [2024-11-13 13:56:06,536 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:06,536 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:06,538 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:06,539 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:06,540 INFO L745 eck$LassoCheckResult]: Stem: 88520#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 88521#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 88641#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 88642#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 88658#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 88659#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 88452#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 88453#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 88776#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 88777#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 88736#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 88422#L586 assume !(0 == ~M_E~0); 88423#L586-2 assume !(0 == ~T1_E~0); 88475#L591-1 assume !(0 == ~T2_E~0); 88598#L596-1 assume !(0 == ~T3_E~0); 88599#L601-1 assume !(0 == ~T4_E~0); 88646#L606-1 assume !(0 == ~T5_E~0); 88647#L611-1 assume !(0 == ~E_1~0); 88745#L616-1 assume !(0 == ~E_2~0); 88746#L621-1 assume !(0 == ~E_3~0); 88343#L626-1 assume !(0 == ~E_4~0); 88344#L631-1 assume !(0 == ~E_5~0); 88513#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88340#L279 assume !(1 == ~m_pc~0); 88342#L279-2 is_master_triggered_~__retres1~0#1 := 0; 88672#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88486#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 88487#L720 assume !(0 != activate_threads_~tmp~1#1); 88671#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88522#L298 assume !(1 == ~t1_pc~0); 88287#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 88288#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88313#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 88314#L728 assume !(0 != activate_threads_~tmp___0~0#1); 88354#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88480#L317 assume !(1 == ~t2_pc~0); 88481#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 88690#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88645#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 88533#L736 assume !(0 != activate_threads_~tmp___1~0#1); 88534#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88729#L336 assume !(1 == ~t3_pc~0); 88730#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 88815#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88258#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 88259#L744 assume !(0 != activate_threads_~tmp___2~0#1); 88680#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88741#L355 assume !(1 == ~t4_pc~0); 88597#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 88738#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88383#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 88384#L752 assume !(0 != activate_threads_~tmp___3~0#1); 88366#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88367#L374 assume !(1 == ~t5_pc~0); 88506#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 88507#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88492#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 88493#L760 assume !(0 != activate_threads_~tmp___4~0#1); 88630#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88631#L649 assume !(1 == ~M_E~0); 88806#L649-2 assume !(1 == ~T1_E~0); 88323#L654-1 assume !(1 == ~T2_E~0); 88324#L659-1 assume !(1 == ~T3_E~0); 88530#L664-1 assume !(1 == ~T4_E~0); 88315#L669-1 assume !(1 == ~T5_E~0); 88316#L674-1 assume !(1 == ~E_1~0); 88719#L679-1 assume !(1 == ~E_2~0); 88424#L684-1 assume !(1 == ~E_3~0); 88425#L689-1 assume !(1 == ~E_4~0); 88592#L694-1 assume !(1 == ~E_5~0); 88589#L699-1 assume { :end_inline_reset_delta_events } true; 88590#L900-2 [2024-11-13 13:56:06,540 INFO L747 eck$LassoCheckResult]: Loop: 88590#L900-2 assume !false; 89776#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 89772#L561-1 assume !false; 89768#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 89714#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 89708#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 89706#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 89704#L486 assume !(0 != eval_~tmp~0#1); 89705#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 90181#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 90179#L586-3 assume !(0 == ~M_E~0); 90177#L586-5 assume !(0 == ~T1_E~0); 90175#L591-3 assume !(0 == ~T2_E~0); 90173#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 90171#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 90168#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 90165#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 90161#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 90158#L621-3 assume !(0 == ~E_3~0); 90153#L626-3 assume !(0 == ~E_4~0); 90149#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 90146#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 90131#L279-18 assume !(1 == ~m_pc~0); 90128#L279-20 is_master_triggered_~__retres1~0#1 := 0; 90125#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 90123#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 90121#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 90119#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 90117#L298-18 assume !(1 == ~t1_pc~0); 90115#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 90112#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 90110#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 90108#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 90106#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 90104#L317-18 assume !(1 == ~t2_pc~0); 90102#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 90100#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 90098#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 90096#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 90094#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 90092#L336-18 assume !(1 == ~t3_pc~0); 90090#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 90087#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 90085#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 90083#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 90082#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 90079#L355-18 assume !(1 == ~t4_pc~0); 90075#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 90073#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 90071#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 90069#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 90066#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 90064#L374-18 assume !(1 == ~t5_pc~0); 90062#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 90061#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 90060#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 90059#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 90057#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 90054#L649-3 assume !(1 == ~M_E~0); 90050#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 90048#L654-3 assume !(1 == ~T2_E~0); 90046#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 90044#L664-3 assume !(1 == ~T4_E~0); 90042#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 90040#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 90039#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 90022#L684-3 assume !(1 == ~E_3~0); 90018#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 90014#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 89995#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 89923#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 89899#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 89870#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 89865#L919 assume !(0 == start_simulation_~tmp~3#1); 89859#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 89818#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 89813#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 89811#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 89809#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 89802#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 89798#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 89790#L932 assume !(0 != start_simulation_~tmp___0~1#1); 88590#L900-2 [2024-11-13 13:56:06,541 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:06,541 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 1 times [2024-11-13 13:56:06,541 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:06,541 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [130644952] [2024-11-13 13:56:06,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:06,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:06,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:06,558 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:56:06,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:06,622 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:56:06,624 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:06,625 INFO L85 PathProgramCache]: Analyzing trace with hash -840846509, now seen corresponding path program 1 times [2024-11-13 13:56:06,625 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:06,625 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1116786446] [2024-11-13 13:56:06,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:06,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:06,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:06,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:06,682 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:06,682 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1116786446] [2024-11-13 13:56:06,682 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1116786446] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:06,682 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:06,682 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:06,682 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1581537063] [2024-11-13 13:56:06,683 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:06,683 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:56:06,683 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:06,683 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:56:06,683 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:56:06,684 INFO L87 Difference]: Start difference. First operand 5897 states and 8257 transitions. cyclomatic complexity: 2368 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:06,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:06,738 INFO L93 Difference]: Finished difference Result 6839 states and 9561 transitions. [2024-11-13 13:56:06,738 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6839 states and 9561 transitions. [2024-11-13 13:56:06,773 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6684 [2024-11-13 13:56:06,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6839 states to 6839 states and 9561 transitions. [2024-11-13 13:56:06,803 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6839 [2024-11-13 13:56:06,809 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6839 [2024-11-13 13:56:06,810 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6839 states and 9561 transitions. [2024-11-13 13:56:06,817 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:06,817 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6839 states and 9561 transitions. [2024-11-13 13:56:06,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6839 states and 9561 transitions. [2024-11-13 13:56:06,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6839 to 6839. [2024-11-13 13:56:06,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6839 states, 6839 states have (on average 1.3980114051761954) internal successors, (9561), 6838 states have internal predecessors, (9561), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:06,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6839 states to 6839 states and 9561 transitions. [2024-11-13 13:56:06,953 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6839 states and 9561 transitions. [2024-11-13 13:56:06,954 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:56:06,954 INFO L424 stractBuchiCegarLoop]: Abstraction has 6839 states and 9561 transitions. [2024-11-13 13:56:06,954 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 13:56:06,954 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6839 states and 9561 transitions. [2024-11-13 13:56:06,975 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6684 [2024-11-13 13:56:06,975 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:06,975 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:06,976 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:06,976 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:06,976 INFO L745 eck$LassoCheckResult]: Stem: 101257#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 101258#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 101372#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 101373#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 101393#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 101394#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 101191#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 101192#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 101514#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 101515#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 101469#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 101161#L586 assume !(0 == ~M_E~0); 101162#L586-2 assume !(0 == ~T1_E~0); 101212#L591-1 assume !(0 == ~T2_E~0); 101334#L596-1 assume !(0 == ~T3_E~0); 101335#L601-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 101381#L606-1 assume !(0 == ~T5_E~0); 101382#L611-1 assume !(0 == ~E_1~0); 101482#L616-1 assume !(0 == ~E_2~0); 101483#L621-1 assume !(0 == ~E_3~0); 101083#L626-1 assume !(0 == ~E_4~0); 101084#L631-1 assume !(0 == ~E_5~0); 101249#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101250#L279 assume !(1 == ~m_pc~0); 101411#L279-2 is_master_triggered_~__retres1~0#1 := 0; 101412#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 101223#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 101224#L720 assume !(0 != activate_threads_~tmp~1#1); 101573#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 101574#L298 assume !(1 == ~t1_pc~0); 101028#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 101029#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 101054#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 101055#L728 assume !(0 != activate_threads_~tmp___0~0#1); 101400#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 101217#L317 assume !(1 == ~t2_pc~0); 101218#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 101567#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 101568#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 101271#L736 assume !(0 != activate_threads_~tmp___1~0#1); 101272#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101463#L336 assume !(1 == ~t3_pc~0); 101464#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 101592#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100999#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 101000#L744 assume !(0 != activate_threads_~tmp___2~0#1); 101474#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101475#L355 assume !(1 == ~t4_pc~0); 101333#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 101471#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 101123#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 101124#L752 assume !(0 != activate_threads_~tmp___3~0#1); 101106#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 101107#L374 assume !(1 == ~t5_pc~0); 101242#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 101243#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 101229#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 101230#L760 assume !(0 != activate_threads_~tmp___4~0#1); 101361#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 101362#L649 assume !(1 == ~M_E~0); 101545#L649-2 assume !(1 == ~T1_E~0); 101064#L654-1 assume !(1 == ~T2_E~0); 101065#L659-1 assume !(1 == ~T3_E~0); 101268#L664-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 101056#L669-1 assume !(1 == ~T5_E~0); 101057#L674-1 assume !(1 == ~E_1~0); 101454#L679-1 assume !(1 == ~E_2~0); 101163#L684-1 assume !(1 == ~E_3~0); 101164#L689-1 assume !(1 == ~E_4~0); 101328#L694-1 assume !(1 == ~E_5~0); 101325#L699-1 assume { :end_inline_reset_delta_events } true; 101326#L900-2 [2024-11-13 13:56:06,977 INFO L747 eck$LassoCheckResult]: Loop: 101326#L900-2 assume !false; 102579#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 102577#L561-1 assume !false; 102575#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 102572#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 102566#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 102565#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 102560#L486 assume !(0 != eval_~tmp~0#1); 102561#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 103475#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 103473#L586-3 assume !(0 == ~M_E~0); 103471#L586-5 assume !(0 == ~T1_E~0); 103469#L591-3 assume !(0 == ~T2_E~0); 103467#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 103463#L601-3 assume !(0 == ~T4_E~0); 103461#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 103459#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 103457#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 103455#L621-3 assume !(0 == ~E_3~0); 103453#L626-3 assume !(0 == ~E_4~0); 103451#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 103448#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103446#L279-18 assume !(1 == ~m_pc~0); 103443#L279-20 is_master_triggered_~__retres1~0#1 := 0; 103441#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103439#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 103437#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 103435#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 103433#L298-18 assume !(1 == ~t1_pc~0); 103431#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 103428#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103426#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 103424#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 103422#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103420#L317-18 assume !(1 == ~t2_pc~0); 103418#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 103416#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 103413#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 102841#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 102835#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102828#L336-18 assume !(1 == ~t3_pc~0); 102821#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 102814#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102806#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 102799#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 102791#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 102785#L355-18 assume !(1 == ~t4_pc~0); 102779#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 102772#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102766#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 102754#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 102750#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 102748#L374-18 assume !(1 == ~t5_pc~0); 102746#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 102731#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 102724#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 102717#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 102710#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102702#L649-3 assume !(1 == ~M_E~0); 102694#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 102689#L654-3 assume !(1 == ~T2_E~0); 102684#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 102678#L664-3 assume !(1 == ~T4_E~0); 102674#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 102670#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 102666#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 102662#L684-3 assume !(1 == ~E_3~0); 102657#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 102652#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 102647#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 102642#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 102633#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 102629#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 102624#L919 assume !(0 == start_simulation_~tmp~3#1); 102621#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 102616#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 102610#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 102606#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 102600#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 102596#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 102592#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 102588#L932 assume !(0 != start_simulation_~tmp___0~1#1); 101326#L900-2 [2024-11-13 13:56:06,977 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:06,977 INFO L85 PathProgramCache]: Analyzing trace with hash 323135776, now seen corresponding path program 1 times [2024-11-13 13:56:06,977 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:06,978 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1834225777] [2024-11-13 13:56:06,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:06,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:06,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:07,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:07,040 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:07,040 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1834225777] [2024-11-13 13:56:07,040 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1834225777] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:07,040 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:07,040 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:07,040 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [608876244] [2024-11-13 13:56:07,040 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:07,040 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:56:07,041 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:07,041 INFO L85 PathProgramCache]: Analyzing trace with hash 113093649, now seen corresponding path program 1 times [2024-11-13 13:56:07,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:07,041 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972316947] [2024-11-13 13:56:07,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:07,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:07,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:07,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:07,147 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:07,147 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1972316947] [2024-11-13 13:56:07,147 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1972316947] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:07,147 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:07,147 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:56:07,147 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1213662499] [2024-11-13 13:56:07,147 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:07,148 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:56:07,148 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:07,148 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:56:07,148 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:56:07,148 INFO L87 Difference]: Start difference. First operand 6839 states and 9561 transitions. cyclomatic complexity: 2730 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:07,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:07,242 INFO L93 Difference]: Finished difference Result 11724 states and 16388 transitions. [2024-11-13 13:56:07,242 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11724 states and 16388 transitions. [2024-11-13 13:56:07,285 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11592 [2024-11-13 13:56:07,325 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11724 states to 11724 states and 16388 transitions. [2024-11-13 13:56:07,325 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11724 [2024-11-13 13:56:07,342 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11724 [2024-11-13 13:56:07,342 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11724 states and 16388 transitions. [2024-11-13 13:56:07,353 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:07,353 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11724 states and 16388 transitions. [2024-11-13 13:56:07,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11724 states and 16388 transitions. [2024-11-13 13:56:07,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11724 to 5897. [2024-11-13 13:56:07,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5897 states, 5897 states have (on average 1.3973206715278956) internal successors, (8240), 5896 states have internal predecessors, (8240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:07,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5897 states to 5897 states and 8240 transitions. [2024-11-13 13:56:07,521 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5897 states and 8240 transitions. [2024-11-13 13:56:07,522 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:56:07,522 INFO L424 stractBuchiCegarLoop]: Abstraction has 5897 states and 8240 transitions. [2024-11-13 13:56:07,522 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 13:56:07,523 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5897 states and 8240 transitions. [2024-11-13 13:56:07,539 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5796 [2024-11-13 13:56:07,539 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:07,539 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:07,540 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:07,541 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:07,541 INFO L745 eck$LassoCheckResult]: Stem: 119830#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 119831#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 119943#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 119944#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 119961#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 119962#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 119767#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 119768#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 120065#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 120066#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 120029#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 119738#L586 assume !(0 == ~M_E~0); 119739#L586-2 assume !(0 == ~T1_E~0); 119788#L591-1 assume !(0 == ~T2_E~0); 119903#L596-1 assume !(0 == ~T3_E~0); 119904#L601-1 assume !(0 == ~T4_E~0); 119949#L606-1 assume !(0 == ~T5_E~0); 119950#L611-1 assume !(0 == ~E_1~0); 120036#L616-1 assume !(0 == ~E_2~0); 120037#L621-1 assume !(0 == ~E_3~0); 119661#L626-1 assume !(0 == ~E_4~0); 119662#L631-1 assume !(0 == ~E_5~0); 119823#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 119656#L279 assume !(1 == ~m_pc~0); 119658#L279-2 is_master_triggered_~__retres1~0#1 := 0; 119975#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119799#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 119800#L720 assume !(0 != activate_threads_~tmp~1#1); 119974#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119832#L298 assume !(1 == ~t1_pc~0); 119604#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 119605#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119631#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 119632#L728 assume !(0 != activate_threads_~tmp___0~0#1); 119670#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119793#L317 assume !(1 == ~t2_pc~0); 119794#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 119993#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 119948#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 119843#L736 assume !(0 != activate_threads_~tmp___1~0#1); 119844#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 120023#L336 assume !(1 == ~t3_pc~0); 120024#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 120091#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119575#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 119576#L744 assume !(0 != activate_threads_~tmp___2~0#1); 119983#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 120032#L355 assume !(1 == ~t4_pc~0); 119902#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 119756#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 119700#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 119701#L752 assume !(0 != activate_threads_~tmp___3~0#1); 119683#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 119684#L374 assume !(1 == ~t5_pc~0); 119816#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 119817#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 119805#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 119806#L760 assume !(0 != activate_threads_~tmp___4~0#1); 119931#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 119932#L649 assume !(1 == ~M_E~0); 120083#L649-2 assume !(1 == ~T1_E~0); 119641#L654-1 assume !(1 == ~T2_E~0); 119642#L659-1 assume !(1 == ~T3_E~0); 119840#L664-1 assume !(1 == ~T4_E~0); 119633#L669-1 assume !(1 == ~T5_E~0); 119634#L674-1 assume !(1 == ~E_1~0); 120014#L679-1 assume !(1 == ~E_2~0); 119740#L684-1 assume !(1 == ~E_3~0); 119741#L689-1 assume !(1 == ~E_4~0); 119896#L694-1 assume !(1 == ~E_5~0); 119893#L699-1 assume { :end_inline_reset_delta_events } true; 119894#L900-2 [2024-11-13 13:56:07,541 INFO L747 eck$LassoCheckResult]: Loop: 119894#L900-2 assume !false; 121957#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 121955#L561-1 assume !false; 121953#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 121950#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 121944#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 121942#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 121939#L486 assume !(0 != eval_~tmp~0#1); 121940#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 122254#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 122252#L586-3 assume !(0 == ~M_E~0); 122249#L586-5 assume !(0 == ~T1_E~0); 122246#L591-3 assume !(0 == ~T2_E~0); 122243#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 122240#L601-3 assume !(0 == ~T4_E~0); 122237#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 122234#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 122231#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 122228#L621-3 assume !(0 == ~E_3~0); 122225#L626-3 assume !(0 == ~E_4~0); 122222#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 122214#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 122211#L279-18 assume !(1 == ~m_pc~0); 122207#L279-20 is_master_triggered_~__retres1~0#1 := 0; 122202#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 122200#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 122197#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 122193#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 122190#L298-18 assume !(1 == ~t1_pc~0); 122187#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 122182#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 122179#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 122176#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 122172#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 122169#L317-18 assume !(1 == ~t2_pc~0); 122166#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 122163#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 122160#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 122157#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 122154#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 122151#L336-18 assume !(1 == ~t3_pc~0); 122148#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 122143#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 122139#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 122135#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 122131#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 122127#L355-18 assume !(1 == ~t4_pc~0); 122123#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 122117#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 122110#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 122104#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 122097#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 122092#L374-18 assume !(1 == ~t5_pc~0); 122087#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 122082#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 122078#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 122074#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 122070#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 122066#L649-3 assume !(1 == ~M_E~0); 122061#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 122058#L654-3 assume !(1 == ~T2_E~0); 122055#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 122051#L664-3 assume !(1 == ~T4_E~0); 122048#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 122045#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 122042#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 122039#L684-3 assume !(1 == ~E_3~0); 122035#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 122031#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 122027#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 122023#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 122015#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 122011#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 122006#L919 assume !(0 == start_simulation_~tmp~3#1); 122003#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 121998#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 121992#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 121989#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 121984#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 121981#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 121977#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 121971#L932 assume !(0 != start_simulation_~tmp___0~1#1); 119894#L900-2 [2024-11-13 13:56:07,542 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:07,542 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 2 times [2024-11-13 13:56:07,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:07,542 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972807321] [2024-11-13 13:56:07,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:07,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:07,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:07,554 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:56:07,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:07,582 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:56:07,583 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:07,583 INFO L85 PathProgramCache]: Analyzing trace with hash 113093649, now seen corresponding path program 2 times [2024-11-13 13:56:07,583 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:07,583 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [454797053] [2024-11-13 13:56:07,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:07,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:07,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:07,648 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:07,648 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:07,649 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [454797053] [2024-11-13 13:56:07,649 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [454797053] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:07,649 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:07,649 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:56:07,649 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [413292218] [2024-11-13 13:56:07,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:07,650 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:56:07,650 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:07,650 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:56:07,650 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:56:07,650 INFO L87 Difference]: Start difference. First operand 5897 states and 8240 transitions. cyclomatic complexity: 2351 Second operand has 5 states, 5 states have (on average 16.4) internal successors, (82), 5 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:07,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:07,745 INFO L93 Difference]: Finished difference Result 6009 states and 8352 transitions. [2024-11-13 13:56:07,746 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6009 states and 8352 transitions. [2024-11-13 13:56:07,767 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5908 [2024-11-13 13:56:07,786 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6009 states to 6009 states and 8352 transitions. [2024-11-13 13:56:07,787 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6009 [2024-11-13 13:56:07,790 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6009 [2024-11-13 13:56:07,791 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6009 states and 8352 transitions. [2024-11-13 13:56:07,795 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:07,795 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6009 states and 8352 transitions. [2024-11-13 13:56:07,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6009 states and 8352 transitions. [2024-11-13 13:56:07,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6009 to 5945. [2024-11-13 13:56:07,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5945 states, 5945 states have (on average 1.3941126997476871) internal successors, (8288), 5944 states have internal predecessors, (8288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:07,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5945 states to 5945 states and 8288 transitions. [2024-11-13 13:56:07,878 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5945 states and 8288 transitions. [2024-11-13 13:56:07,878 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:56:07,879 INFO L424 stractBuchiCegarLoop]: Abstraction has 5945 states and 8288 transitions. [2024-11-13 13:56:07,879 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 13:56:07,879 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5945 states and 8288 transitions. [2024-11-13 13:56:07,895 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5844 [2024-11-13 13:56:07,896 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:07,896 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:07,897 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:07,897 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:07,897 INFO L745 eck$LassoCheckResult]: Stem: 131751#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 131752#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 131883#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 131884#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 131902#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 131903#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 131682#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 131683#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 132031#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 132032#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 131984#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 131648#L586 assume !(0 == ~M_E~0); 131649#L586-2 assume !(0 == ~T1_E~0); 131704#L591-1 assume !(0 == ~T2_E~0); 131838#L596-1 assume !(0 == ~T3_E~0); 131839#L601-1 assume !(0 == ~T4_E~0); 131889#L606-1 assume !(0 == ~T5_E~0); 131890#L611-1 assume !(0 == ~E_1~0); 131997#L616-1 assume !(0 == ~E_2~0); 131998#L621-1 assume !(0 == ~E_3~0); 131573#L626-1 assume !(0 == ~E_4~0); 131574#L631-1 assume !(0 == ~E_5~0); 131744#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 131568#L279 assume !(1 == ~m_pc~0); 131570#L279-2 is_master_triggered_~__retres1~0#1 := 0; 131921#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131715#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 131716#L720 assume !(0 != activate_threads_~tmp~1#1); 131920#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 131753#L298 assume !(1 == ~t1_pc~0); 131516#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 131517#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 131542#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 131543#L728 assume !(0 != activate_threads_~tmp___0~0#1); 131583#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 131709#L317 assume !(1 == ~t2_pc~0); 131710#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 131943#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131888#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 131762#L736 assume !(0 != activate_threads_~tmp___1~0#1); 131763#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 131980#L336 assume !(1 == ~t3_pc~0); 131981#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 132066#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 131489#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 131490#L744 assume !(0 != activate_threads_~tmp___2~0#1); 131929#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 131990#L355 assume !(1 == ~t4_pc~0); 131835#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 131989#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 131613#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 131614#L752 assume !(0 != activate_threads_~tmp___3~0#1); 131596#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 131597#L374 assume !(1 == ~t5_pc~0); 131732#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 131733#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 131721#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 131722#L760 assume !(0 != activate_threads_~tmp___4~0#1); 131871#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131872#L649 assume !(1 == ~M_E~0); 132056#L649-2 assume !(1 == ~T1_E~0); 131554#L654-1 assume !(1 == ~T2_E~0); 131555#L659-1 assume !(1 == ~T3_E~0); 131761#L664-1 assume !(1 == ~T4_E~0); 131546#L669-1 assume !(1 == ~T5_E~0); 131547#L674-1 assume !(1 == ~E_1~0); 131972#L679-1 assume !(1 == ~E_2~0); 131652#L684-1 assume !(1 == ~E_3~0); 131653#L689-1 assume !(1 == ~E_4~0); 131830#L694-1 assume !(1 == ~E_5~0); 131828#L699-1 assume { :end_inline_reset_delta_events } true; 131829#L900-2 [2024-11-13 13:56:07,897 INFO L747 eck$LassoCheckResult]: Loop: 131829#L900-2 assume !false; 135753#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 135752#L561-1 assume !false; 135751#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 135749#L439 assume !(0 == ~m_st~0); 135750#L443 assume !(0 == ~t1_st~0); 135746#L447 assume !(0 == ~t2_st~0); 135747#L451 assume !(0 == ~t3_st~0); 135748#L455 assume !(0 == ~t4_st~0); 135745#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 135743#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 135741#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 135740#L486 assume !(0 != eval_~tmp~0#1); 135739#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 135737#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 135735#L586-3 assume !(0 == ~M_E~0); 135733#L586-5 assume !(0 == ~T1_E~0); 135731#L591-3 assume !(0 == ~T2_E~0); 135729#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 135727#L601-3 assume !(0 == ~T4_E~0); 135725#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 135723#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 135721#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 135719#L621-3 assume !(0 == ~E_3~0); 135717#L626-3 assume !(0 == ~E_4~0); 135715#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 135713#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 135711#L279-18 assume !(1 == ~m_pc~0); 135708#L279-20 is_master_triggered_~__retres1~0#1 := 0; 135705#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 135703#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 135701#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 135699#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 135697#L298-18 assume 1 == ~t1_pc~0; 135694#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 135691#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 135689#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 135687#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 135685#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 135683#L317-18 assume !(1 == ~t2_pc~0); 135681#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 135679#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 135677#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 135675#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 135673#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 135671#L336-18 assume !(1 == ~t3_pc~0); 135669#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 135667#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 135665#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 135663#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 135661#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 135659#L355-18 assume 1 == ~t4_pc~0; 135656#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 135652#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 135648#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 135644#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 135641#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 135639#L374-18 assume !(1 == ~t5_pc~0); 135637#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 135635#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 135633#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 135631#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 135629#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 135627#L649-3 assume !(1 == ~M_E~0); 135621#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 135620#L654-3 assume !(1 == ~T2_E~0); 135619#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 135618#L664-3 assume !(1 == ~T4_E~0); 135616#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 135614#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 135612#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 135610#L684-3 assume !(1 == ~E_3~0); 135607#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 135606#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 135605#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 135604#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 135520#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 135501#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 132269#L919 assume !(0 == start_simulation_~tmp~3#1); 132270#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 135878#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 135872#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 135772#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 135766#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 135764#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 135762#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 135759#L932 assume !(0 != start_simulation_~tmp___0~1#1); 131829#L900-2 [2024-11-13 13:56:07,898 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:07,898 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 3 times [2024-11-13 13:56:07,898 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:07,898 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1135181389] [2024-11-13 13:56:07,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:07,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:07,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:07,911 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:56:07,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:07,934 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:56:07,934 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:07,934 INFO L85 PathProgramCache]: Analyzing trace with hash -1693835950, now seen corresponding path program 1 times [2024-11-13 13:56:07,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:07,935 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [990305350] [2024-11-13 13:56:07,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:07,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:07,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:08,043 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:08,043 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:08,044 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [990305350] [2024-11-13 13:56:08,044 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [990305350] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:08,044 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:08,044 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:56:08,044 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [218414553] [2024-11-13 13:56:08,044 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:08,044 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:56:08,044 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:08,044 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:56:08,044 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:56:08,045 INFO L87 Difference]: Start difference. First operand 5945 states and 8288 transitions. cyclomatic complexity: 2351 Second operand has 5 states, 5 states have (on average 17.4) internal successors, (87), 5 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:08,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:08,239 INFO L93 Difference]: Finished difference Result 6089 states and 8391 transitions. [2024-11-13 13:56:08,239 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6089 states and 8391 transitions. [2024-11-13 13:56:08,260 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5988 [2024-11-13 13:56:08,279 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6089 states to 6089 states and 8391 transitions. [2024-11-13 13:56:08,280 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6089 [2024-11-13 13:56:08,283 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6089 [2024-11-13 13:56:08,283 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6089 states and 8391 transitions. [2024-11-13 13:56:08,287 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:08,287 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6089 states and 8391 transitions. [2024-11-13 13:56:08,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6089 states and 8391 transitions. [2024-11-13 13:56:08,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6089 to 6089. [2024-11-13 13:56:08,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6089 states, 6089 states have (on average 1.3780587945475447) internal successors, (8391), 6088 states have internal predecessors, (8391), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:08,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6089 states to 6089 states and 8391 transitions. [2024-11-13 13:56:08,359 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6089 states and 8391 transitions. [2024-11-13 13:56:08,360 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:56:08,360 INFO L424 stractBuchiCegarLoop]: Abstraction has 6089 states and 8391 transitions. [2024-11-13 13:56:08,360 INFO L331 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-13 13:56:08,360 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6089 states and 8391 transitions. [2024-11-13 13:56:08,377 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5988 [2024-11-13 13:56:08,377 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:08,377 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:08,378 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:08,378 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:08,379 INFO L745 eck$LassoCheckResult]: Stem: 143790#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 143791#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 143918#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 143919#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 143937#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 143938#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 143721#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 143722#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 144059#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 144060#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 144016#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 143692#L586 assume !(0 == ~M_E~0); 143693#L586-2 assume !(0 == ~T1_E~0); 143742#L591-1 assume !(0 == ~T2_E~0); 143874#L596-1 assume !(0 == ~T3_E~0); 143875#L601-1 assume !(0 == ~T4_E~0); 143923#L606-1 assume !(0 == ~T5_E~0); 143924#L611-1 assume !(0 == ~E_1~0); 144027#L616-1 assume !(0 == ~E_2~0); 144028#L621-1 assume !(0 == ~E_3~0); 143615#L626-1 assume !(0 == ~E_4~0); 143616#L631-1 assume !(0 == ~E_5~0); 143783#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 143612#L279 assume !(1 == ~m_pc~0); 143614#L279-2 is_master_triggered_~__retres1~0#1 := 0; 143956#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 143753#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 143754#L720 assume !(0 != activate_threads_~tmp~1#1); 143955#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 143792#L298 assume !(1 == ~t1_pc~0); 143559#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 143560#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 143585#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 143586#L728 assume !(0 != activate_threads_~tmp___0~0#1); 143624#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 143747#L317 assume !(1 == ~t2_pc~0); 143748#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 143976#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 143922#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 143803#L736 assume !(0 != activate_threads_~tmp___1~0#1); 143804#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 144010#L336 assume !(1 == ~t3_pc~0); 144011#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 144105#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 143530#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 143531#L744 assume !(0 != activate_threads_~tmp___2~0#1); 143964#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 144022#L355 assume !(1 == ~t4_pc~0); 143873#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 144019#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 143653#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 143654#L752 assume !(0 != activate_threads_~tmp___3~0#1); 143636#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 143637#L374 assume !(1 == ~t5_pc~0); 143775#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 143776#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 143759#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 143760#L760 assume !(0 != activate_threads_~tmp___4~0#1); 143905#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 143906#L649 assume !(1 == ~M_E~0); 144093#L649-2 assume !(1 == ~T1_E~0); 143595#L654-1 assume !(1 == ~T2_E~0); 143596#L659-1 assume !(1 == ~T3_E~0); 143800#L664-1 assume !(1 == ~T4_E~0); 143587#L669-1 assume !(1 == ~T5_E~0); 143588#L674-1 assume !(1 == ~E_1~0); 144002#L679-1 assume !(1 == ~E_2~0); 143694#L684-1 assume !(1 == ~E_3~0); 143695#L689-1 assume !(1 == ~E_4~0); 143868#L694-1 assume !(1 == ~E_5~0); 143865#L699-1 assume { :end_inline_reset_delta_events } true; 143866#L900-2 [2024-11-13 13:56:08,379 INFO L747 eck$LassoCheckResult]: Loop: 143866#L900-2 assume !false; 149165#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 147581#L561-1 assume !false; 149078#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 149076#L439 assume !(0 == ~m_st~0); 149077#L443 assume !(0 == ~t1_st~0); 149071#L447 assume !(0 == ~t2_st~0); 149072#L451 assume !(0 == ~t3_st~0); 149075#L455 assume !(0 == ~t4_st~0); 149073#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 149074#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 149058#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 149059#L486 assume !(0 != eval_~tmp~0#1); 149401#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 149400#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 149395#L586-3 assume !(0 == ~M_E~0); 149394#L586-5 assume !(0 == ~T1_E~0); 149393#L591-3 assume !(0 == ~T2_E~0); 149392#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 149391#L601-3 assume !(0 == ~T4_E~0); 149390#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 149388#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 149386#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 149384#L621-3 assume !(0 == ~E_3~0); 149382#L626-3 assume !(0 == ~E_4~0); 149380#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 149378#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 149376#L279-18 assume !(1 == ~m_pc~0); 149373#L279-20 is_master_triggered_~__retres1~0#1 := 0; 149371#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 149369#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 149368#L720-18 assume !(0 != activate_threads_~tmp~1#1); 149361#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 149359#L298-18 assume 1 == ~t1_pc~0; 149356#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 149354#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 149353#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 149352#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 149351#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 149350#L317-18 assume !(1 == ~t2_pc~0); 149349#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 149348#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 149347#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 149346#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 149345#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 149344#L336-18 assume !(1 == ~t3_pc~0); 149343#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 149342#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 149341#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 149340#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 149339#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 149338#L355-18 assume !(1 == ~t4_pc~0); 149336#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 149334#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 149332#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 149331#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 149329#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 149328#L374-18 assume !(1 == ~t5_pc~0); 149320#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 149318#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 149316#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 149315#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 149313#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 149311#L649-3 assume !(1 == ~M_E~0); 148577#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 149308#L654-3 assume !(1 == ~T2_E~0); 149306#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 149304#L664-3 assume !(1 == ~T4_E~0); 149302#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 149300#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 149028#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 149027#L684-3 assume !(1 == ~E_3~0); 149026#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 149025#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 149023#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 148667#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 148658#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 148656#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 148653#L919 assume !(0 == start_simulation_~tmp~3#1); 148654#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 149365#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 149360#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 149358#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 149355#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 149168#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 149167#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 149166#L932 assume !(0 != start_simulation_~tmp___0~1#1); 143866#L900-2 [2024-11-13 13:56:08,379 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:08,379 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 4 times [2024-11-13 13:56:08,379 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:08,379 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [647025678] [2024-11-13 13:56:08,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:08,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:08,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:08,392 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:56:08,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:08,410 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:56:08,410 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:08,411 INFO L85 PathProgramCache]: Analyzing trace with hash 1151749101, now seen corresponding path program 1 times [2024-11-13 13:56:08,411 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:08,411 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911854496] [2024-11-13 13:56:08,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:08,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:08,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:08,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:08,456 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:08,456 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1911854496] [2024-11-13 13:56:08,457 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1911854496] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:08,457 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:08,457 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:08,457 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [741860336] [2024-11-13 13:56:08,457 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:08,457 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:56:08,457 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:08,457 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:56:08,457 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:56:08,458 INFO L87 Difference]: Start difference. First operand 6089 states and 8391 transitions. cyclomatic complexity: 2310 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:08,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:08,533 INFO L93 Difference]: Finished difference Result 10621 states and 14463 transitions. [2024-11-13 13:56:08,533 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10621 states and 14463 transitions. [2024-11-13 13:56:08,572 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10496 [2024-11-13 13:56:08,656 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10621 states to 10621 states and 14463 transitions. [2024-11-13 13:56:08,657 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10621 [2024-11-13 13:56:08,661 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10621 [2024-11-13 13:56:08,661 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10621 states and 14463 transitions. [2024-11-13 13:56:08,666 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:08,666 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10621 states and 14463 transitions. [2024-11-13 13:56:08,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10621 states and 14463 transitions. [2024-11-13 13:56:08,743 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10621 to 10297. [2024-11-13 13:56:08,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10297 states, 10297 states have (on average 1.3641837428377197) internal successors, (14047), 10296 states have internal predecessors, (14047), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:08,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10297 states to 10297 states and 14047 transitions. [2024-11-13 13:56:08,780 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10297 states and 14047 transitions. [2024-11-13 13:56:08,780 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:56:08,780 INFO L424 stractBuchiCegarLoop]: Abstraction has 10297 states and 14047 transitions. [2024-11-13 13:56:08,780 INFO L331 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-13 13:56:08,780 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10297 states and 14047 transitions. [2024-11-13 13:56:08,810 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10172 [2024-11-13 13:56:08,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:08,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:08,812 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:08,812 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:08,812 INFO L745 eck$LassoCheckResult]: Stem: 160508#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 160509#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 160625#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 160626#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 160648#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 160649#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 160441#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 160442#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 160776#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 160777#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 160724#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 160410#L586 assume !(0 == ~M_E~0); 160411#L586-2 assume !(0 == ~T1_E~0); 160463#L591-1 assume !(0 == ~T2_E~0); 160583#L596-1 assume !(0 == ~T3_E~0); 160584#L601-1 assume !(0 == ~T4_E~0); 160634#L606-1 assume !(0 == ~T5_E~0); 160635#L611-1 assume !(0 == ~E_1~0); 160743#L616-1 assume !(0 == ~E_2~0); 160744#L621-1 assume !(0 == ~E_3~0); 160333#L626-1 assume !(0 == ~E_4~0); 160334#L631-1 assume !(0 == ~E_5~0); 160501#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 160328#L279 assume !(1 == ~m_pc~0); 160330#L279-2 is_master_triggered_~__retres1~0#1 := 0; 160663#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 160475#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 160476#L720 assume !(0 != activate_threads_~tmp~1#1); 160662#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 160510#L298 assume !(1 == ~t1_pc~0); 160274#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 160275#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 160300#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 160301#L728 assume !(0 != activate_threads_~tmp___0~0#1); 160343#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 160469#L317 assume !(1 == ~t2_pc~0); 160470#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 160683#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 160631#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 160519#L736 assume !(0 != activate_threads_~tmp___1~0#1); 160520#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 160720#L336 assume !(1 == ~t3_pc~0); 160721#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 160815#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 160247#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 160248#L744 assume !(0 != activate_threads_~tmp___2~0#1); 160671#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 160730#L355 assume !(1 == ~t4_pc~0); 160580#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 160728#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 160373#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 160374#L752 assume !(0 != activate_threads_~tmp___3~0#1); 160354#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 160355#L374 assume !(1 == ~t5_pc~0); 160491#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 160492#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 160481#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 160482#L760 assume !(0 != activate_threads_~tmp___4~0#1); 160612#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 160613#L649 assume !(1 == ~M_E~0); 160808#L649-2 assume !(1 == ~T1_E~0); 160312#L654-1 assume !(1 == ~T2_E~0); 160313#L659-1 assume !(1 == ~T3_E~0); 160518#L664-1 assume !(1 == ~T4_E~0); 160304#L669-1 assume !(1 == ~T5_E~0); 160305#L674-1 assume !(1 == ~E_1~0); 160712#L679-1 assume !(1 == ~E_2~0); 160414#L684-1 assume !(1 == ~E_3~0); 160415#L689-1 assume !(1 == ~E_4~0); 160576#L694-1 assume !(1 == ~E_5~0); 160574#L699-1 assume { :end_inline_reset_delta_events } true; 160575#L900-2 [2024-11-13 13:56:08,814 INFO L747 eck$LassoCheckResult]: Loop: 160575#L900-2 assume !false; 167875#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 167873#L561-1 assume !false; 167871#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 167869#L439 assume !(0 == ~m_st~0); 164211#L443 assume !(0 == ~t1_st~0); 164205#L447 assume !(0 == ~t2_st~0); 164199#L451 assume !(0 == ~t3_st~0); 164193#L455 assume !(0 == ~t4_st~0); 164186#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 164179#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 164171#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 164165#L486 assume !(0 != eval_~tmp~0#1); 164049#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 164048#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 164047#L586-3 assume !(0 == ~M_E~0); 164046#L586-5 assume !(0 == ~T1_E~0); 164044#L591-3 assume !(0 == ~T2_E~0); 164042#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 164040#L601-3 assume !(0 == ~T4_E~0); 164039#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 164037#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 164034#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 164032#L621-3 assume !(0 == ~E_3~0); 164030#L626-3 assume !(0 == ~E_4~0); 164028#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 164027#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 164026#L279-18 assume !(1 == ~m_pc~0); 164024#L279-20 is_master_triggered_~__retres1~0#1 := 0; 164023#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 164021#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 164019#L720-18 assume !(0 != activate_threads_~tmp~1#1); 164016#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 164013#L298-18 assume 1 == ~t1_pc~0; 163979#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 163919#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 163912#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 163908#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 163904#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 163897#L317-18 assume !(1 == ~t2_pc~0); 163889#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 163880#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 163871#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 163864#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 163858#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 163850#L336-18 assume !(1 == ~t3_pc~0); 163843#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 163839#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 163838#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 163833#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 163813#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 163759#L355-18 assume 1 == ~t4_pc~0; 163758#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 163751#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 163750#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 163745#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 163743#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 163741#L374-18 assume !(1 == ~t5_pc~0); 163739#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 163737#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 163735#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 163732#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 163730#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 163728#L649-3 assume !(1 == ~M_E~0); 163583#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 163725#L654-3 assume !(1 == ~T2_E~0); 163723#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 163708#L664-3 assume !(1 == ~T4_E~0); 163705#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 163703#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 163701#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 163693#L684-3 assume !(1 == ~E_3~0); 163688#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 163687#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 163686#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 163685#L439-1 assume !(0 == ~m_st~0); 163294#L443-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 163667#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 163663#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 163297#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 163295#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 163292#L279-21 assume 1 == ~m_pc~0; 163289#L280-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 163287#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163284#is_master_triggered_returnLabel#8 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 163273#L720-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 163272#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 163271#L298-21 assume !(1 == ~t1_pc~0); 163268#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 163267#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 163266#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 163265#L728-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 163263#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 163261#L317-21 assume !(1 == ~t2_pc~0); 163260#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 163259#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 163258#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 163257#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 163255#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 163253#L336-21 assume !(1 == ~t3_pc~0); 163251#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 163250#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 163248#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 163245#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 163243#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 163241#L355-21 assume 1 == ~t4_pc~0; 163238#L356-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 163236#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 163234#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 163231#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 163228#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 163226#L374-21 assume !(1 == ~t5_pc~0); 163224#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 163222#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 163220#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 163218#L760-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 163216#L760-23 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 163213#L793 assume 1 == ~M_E~0;~M_E~0 := 2; 163214#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 167934#L798-1 assume !(1 == ~T2_E~0); 167932#L803-1 assume !(1 == ~T3_E~0); 167930#L808-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 167928#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 167926#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 167924#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 167922#L828-1 assume !(1 == ~E_3~0); 167920#L833-1 assume 1 == ~E_4~0;~E_4~0 := 2; 167918#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 167914#L843-1 assume { :end_inline_reset_time_events } true; 163286#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 167910#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 167908#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 167905#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 167903#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 167901#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 167899#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 167897#L932 assume !(0 != start_simulation_~tmp___0~1#1); 160575#L900-2 [2024-11-13 13:56:08,815 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:08,815 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 5 times [2024-11-13 13:56:08,815 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:08,815 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635903011] [2024-11-13 13:56:08,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:08,815 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:08,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:08,831 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:56:08,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:08,855 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:56:08,856 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:08,856 INFO L85 PathProgramCache]: Analyzing trace with hash 40673718, now seen corresponding path program 1 times [2024-11-13 13:56:08,856 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:08,856 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1380956673] [2024-11-13 13:56:08,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:08,856 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:08,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:08,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:08,918 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:08,918 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1380956673] [2024-11-13 13:56:08,918 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1380956673] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:08,918 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:08,919 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:08,919 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1204268544] [2024-11-13 13:56:08,919 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:08,920 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:56:08,920 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:08,920 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:56:08,920 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:56:08,921 INFO L87 Difference]: Start difference. First operand 10297 states and 14047 transitions. cyclomatic complexity: 3758 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:09,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:09,027 INFO L93 Difference]: Finished difference Result 18768 states and 25445 transitions. [2024-11-13 13:56:09,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18768 states and 25445 transitions. [2024-11-13 13:56:09,099 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18596 [2024-11-13 13:56:09,161 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18768 states to 18768 states and 25445 transitions. [2024-11-13 13:56:09,161 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18768 [2024-11-13 13:56:09,173 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18768 [2024-11-13 13:56:09,173 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18768 states and 25445 transitions. [2024-11-13 13:56:09,185 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:09,185 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18768 states and 25445 transitions. [2024-11-13 13:56:09,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18768 states and 25445 transitions. [2024-11-13 13:56:09,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18768 to 18736. [2024-11-13 13:56:09,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18736 states, 18736 states have (on average 1.3563727583262168) internal successors, (25413), 18735 states have internal predecessors, (25413), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:09,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18736 states to 18736 states and 25413 transitions. [2024-11-13 13:56:09,401 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18736 states and 25413 transitions. [2024-11-13 13:56:09,402 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:56:09,402 INFO L424 stractBuchiCegarLoop]: Abstraction has 18736 states and 25413 transitions. [2024-11-13 13:56:09,402 INFO L331 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-13 13:56:09,402 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18736 states and 25413 transitions. [2024-11-13 13:56:09,510 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18564 [2024-11-13 13:56:09,510 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:09,510 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:09,513 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:09,513 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:09,514 INFO L745 eck$LassoCheckResult]: Stem: 189570#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 189571#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 189699#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 189700#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 189720#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 189721#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 189507#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 189508#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 189857#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 189858#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 189803#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 189474#L586 assume !(0 == ~M_E~0); 189475#L586-2 assume !(0 == ~T1_E~0); 189526#L591-1 assume !(0 == ~T2_E~0); 189656#L596-1 assume !(0 == ~T3_E~0); 189657#L601-1 assume !(0 == ~T4_E~0); 189707#L606-1 assume !(0 == ~T5_E~0); 189708#L611-1 assume !(0 == ~E_1~0); 189820#L616-1 assume !(0 == ~E_2~0); 189821#L621-1 assume !(0 == ~E_3~0); 189398#L626-1 assume !(0 == ~E_4~0); 189399#L631-1 assume !(0 == ~E_5~0); 189563#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 189394#L279 assume !(1 == ~m_pc~0); 189395#L279-2 is_master_triggered_~__retres1~0#1 := 0; 189736#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 189537#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 189538#L720 assume !(0 != activate_threads_~tmp~1#1); 189735#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 189572#L298 assume !(1 == ~t1_pc~0); 189343#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 189344#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 189369#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 189370#L728 assume !(0 != activate_threads_~tmp___0~0#1); 189407#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 189531#L317 assume !(1 == ~t2_pc~0); 189532#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 189757#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 189704#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 189581#L736 assume !(0 != activate_threads_~tmp___1~0#1); 189582#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 189798#L336 assume !(1 == ~t3_pc~0); 189799#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 189905#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 189317#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 189318#L744 assume !(0 != activate_threads_~tmp___2~0#1); 189744#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 189808#L355 assume !(1 == ~t4_pc~0); 189653#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 189807#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 189437#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 189438#L752 assume !(0 != activate_threads_~tmp___3~0#1); 189418#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 189419#L374 assume !(1 == ~t5_pc~0); 189552#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 189553#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 189543#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 189544#L760 assume !(0 != activate_threads_~tmp___4~0#1); 189686#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 189687#L649 assume !(1 == ~M_E~0); 189891#L649-2 assume !(1 == ~T1_E~0); 189379#L654-1 assume !(1 == ~T2_E~0); 189380#L659-1 assume !(1 == ~T3_E~0); 189580#L664-1 assume !(1 == ~T4_E~0); 189371#L669-1 assume !(1 == ~T5_E~0); 189372#L674-1 assume !(1 == ~E_1~0); 189790#L679-1 assume !(1 == ~E_2~0); 189478#L684-1 assume !(1 == ~E_3~0); 189479#L689-1 assume !(1 == ~E_4~0); 189649#L694-1 assume !(1 == ~E_5~0); 189647#L699-1 assume { :end_inline_reset_delta_events } true; 189648#L900-2 [2024-11-13 13:56:09,518 INFO L747 eck$LassoCheckResult]: Loop: 189648#L900-2 assume !false; 193586#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 193584#L561-1 assume !false; 193581#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 193578#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 193576#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 193575#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 193574#L486 assume 0 != eval_~tmp~0#1; 193571#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 193569#L494 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 193567#L65 assume 0 == ~m_pc~0; 193566#L92 assume !false; 193565#L77 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 193564#L279-3 assume !(1 == ~m_pc~0); 193563#L279-5 is_master_triggered_~__retres1~0#1 := 0; 193562#L290-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 193561#is_master_triggered_returnLabel#2 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 193560#L720-3 assume !(0 != activate_threads_~tmp~1#1); 193559#L720-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 193558#L298-3 assume 1 == ~t1_pc~0; 193556#L299-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 193555#L309-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 193554#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 193553#L728-3 assume !(0 != activate_threads_~tmp___0~0#1); 193552#L728-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 189924#L317-3 assume !(1 == ~t2_pc~0); 189925#L317-5 is_transmit2_triggered_~__retres1~2#1 := 0; 194022#L328-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 194020#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 194017#L736-3 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 194015#L736-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 194013#L336-3 assume !(1 == ~t3_pc~0); 194011#L336-5 is_transmit3_triggered_~__retres1~3#1 := 0; 194009#L347-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 194007#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 194005#L744-3 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 194003#L744-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 194002#L355-3 assume !(1 == ~t4_pc~0); 194000#L355-5 is_transmit4_triggered_~__retres1~4#1 := 0; 193998#L366-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 193996#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 193995#L752-3 assume !(0 != activate_threads_~tmp___3~0#1); 193990#L752-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 193988#L374-3 assume !(1 == ~t5_pc~0); 193986#L374-5 is_transmit5_triggered_~__retres1~5#1 := 0; 193985#L385-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 193984#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 193983#L760-3 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 193982#L760-5 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true; 193978#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 193972#$Ultimate##223 assume !false; 193969#L85 ~m_pc~0 := 1;~m_st~0 := 2; 193966#master_returnLabel#1 assume { :end_inline_master } true; 193963#L494-2 havoc eval_~tmp_ndt_1~0#1; 192702#L491-1 assume !(0 == ~t1_st~0); 193957#L505-1 assume !(0 == ~t2_st~0); 193958#L519-1 assume !(0 == ~t3_st~0); 195205#L533-1 assume !(0 == ~t4_st~0); 195183#L547-1 assume !(0 == ~t5_st~0); 195178#L561-1 assume !false; 193981#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 193980#L439 assume !(0 == ~m_st~0); 192712#L443 assume !(0 == ~t1_st~0); 193973#L447 assume !(0 == ~t2_st~0); 193974#L451 assume !(0 == ~t3_st~0); 193977#L455 assume !(0 == ~t4_st~0); 193975#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 193976#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 193967#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 193968#L486 assume !(0 != eval_~tmp~0#1); 194410#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 194403#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 194397#L586-3 assume !(0 == ~M_E~0); 194392#L586-5 assume !(0 == ~T1_E~0); 194385#L591-3 assume !(0 == ~T2_E~0); 194378#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 194372#L601-3 assume !(0 == ~T4_E~0); 194366#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 194361#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 194354#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 194347#L621-3 assume !(0 == ~E_3~0); 194339#L626-3 assume !(0 == ~E_4~0); 194330#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 194325#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 194319#L279-18 assume 1 == ~m_pc~0; 194305#L280-6 assume !(1 == ~M_E~0); 194295#L279-20 is_master_triggered_~__retres1~0#1 := 0; 194285#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 194276#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 194268#L720-18 assume !(0 != activate_threads_~tmp~1#1); 194263#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 194259#L298-18 assume !(1 == ~t1_pc~0); 194254#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 194249#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 194245#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 194241#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 194235#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 194230#L317-18 assume !(1 == ~t2_pc~0); 194225#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 194222#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 194219#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 194216#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 194213#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 194210#L336-18 assume !(1 == ~t3_pc~0); 194207#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 194204#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 194201#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 194197#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 194192#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 194187#L355-18 assume !(1 == ~t4_pc~0); 194182#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 194177#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 194173#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 194168#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 194163#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 194159#L374-18 assume !(1 == ~t5_pc~0); 194155#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 194150#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 194142#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 194139#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 194136#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 194132#L649-3 assume !(1 == ~M_E~0); 193226#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 194127#L654-3 assume !(1 == ~T2_E~0); 194123#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 194119#L664-3 assume !(1 == ~T4_E~0); 194114#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 194110#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 194105#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 194099#L684-3 assume !(1 == ~E_3~0); 194095#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 194090#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 194085#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 194082#L439-1 assume !(0 == ~m_st~0); 193350#L443-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 194072#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 194069#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 192860#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 192858#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 192855#L279-21 assume 1 == ~m_pc~0; 192852#L280-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 192850#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 192848#is_master_triggered_returnLabel#8 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 192840#L720-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 192262#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 192257#L298-21 assume !(1 == ~t1_pc~0); 192254#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 192252#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 192251#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 192247#L728-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 192245#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 192243#L317-21 assume !(1 == ~t2_pc~0); 192241#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 192239#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 192236#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 192234#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 192232#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 192229#L336-21 assume !(1 == ~t3_pc~0); 192227#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 192225#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 192223#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 192221#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 192219#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 192217#L355-21 assume 1 == ~t4_pc~0; 192214#L356-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 192212#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 192210#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 192208#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 192205#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 192203#L374-21 assume !(1 == ~t5_pc~0); 192201#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 192199#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 192196#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 192194#L760-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 192192#L760-23 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 192189#L793 assume !(1 == ~M_E~0); 192187#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 192185#L798-1 assume !(1 == ~T2_E~0); 192183#L803-1 assume !(1 == ~T3_E~0); 192181#L808-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 192178#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 192176#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 192174#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 192172#L828-1 assume !(1 == ~E_3~0); 192170#L833-1 assume 1 == ~E_4~0;~E_4~0 := 2; 192168#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 191961#L843-1 assume { :end_inline_reset_time_events } true; 191957#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 191954#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 191951#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 191949#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 191947#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 191945#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 191943#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 191941#L932 assume !(0 != start_simulation_~tmp___0~1#1); 191939#L900-2 assume !false; 191915#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 191910#L561-1 assume !false; 191905#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 191900#L439 assume !(0 == ~m_st~0); 191901#L443 assume !(0 == ~t1_st~0); 192316#L447 assume !(0 == ~t2_st~0); 192314#L451 assume !(0 == ~t3_st~0); 192312#L455 assume !(0 == ~t4_st~0); 192310#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 192308#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 192115#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 192112#L486 assume !(0 != eval_~tmp~0#1); 192110#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 192108#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 192105#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 192103#L586-5 assume !(0 == ~T1_E~0); 192101#L591-3 assume !(0 == ~T2_E~0); 192099#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 192097#L601-3 assume !(0 == ~T4_E~0); 192096#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 192092#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 192090#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 192088#L621-3 assume !(0 == ~E_3~0); 192087#L626-3 assume !(0 == ~E_4~0); 192084#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 192083#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 192078#L279-18 assume 1 == ~m_pc~0; 192072#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 192070#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 192068#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 192066#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 192065#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 192064#L298-18 assume !(1 == ~t1_pc~0); 192062#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 192059#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 192055#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 192053#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 192051#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 192049#L317-18 assume !(1 == ~t2_pc~0); 192047#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 192044#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 192042#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 192040#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 192037#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 192035#L336-18 assume !(1 == ~t3_pc~0); 192033#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 192031#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 192029#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 192027#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 192025#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 192023#L355-18 assume 1 == ~t4_pc~0; 192020#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 192018#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 192016#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 192013#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 192012#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 192010#L374-18 assume !(1 == ~t5_pc~0); 192008#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 192006#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 192005#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 192003#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 192000#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 191997#L649-3 assume !(1 == ~M_E~0); 191995#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 191993#L654-3 assume !(1 == ~T2_E~0); 191991#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 191989#L664-3 assume !(1 == ~T4_E~0); 191986#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 191984#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 191982#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 191980#L684-3 assume !(1 == ~E_3~0); 191978#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 191976#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 191974#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 191971#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 191969#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 191967#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 191959#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 191960#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 193337#L279-21 assume !(1 == ~m_pc~0); 193338#L279-23 is_master_triggered_~__retres1~0#1 := 0; 193734#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 193732#is_master_triggered_returnLabel#8 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 193730#L720-21 assume !(0 != activate_threads_~tmp~1#1); 193728#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 193726#L298-21 assume 1 == ~t1_pc~0; 193722#L299-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 193719#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 193717#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 193715#L728-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 193712#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 193710#L317-21 assume !(1 == ~t2_pc~0); 193708#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 193706#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 193704#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 193702#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 193700#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 193698#L336-21 assume !(1 == ~t3_pc~0); 193697#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 193696#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 193695#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 193694#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 193691#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 193689#L355-21 assume !(1 == ~t4_pc~0); 193686#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 193895#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 193893#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 193678#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 193676#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 193674#L374-21 assume !(1 == ~t5_pc~0); 193672#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 193670#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 193668#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 193666#L760-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 193664#L760-23 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 193661#L793 assume 1 == ~M_E~0;~M_E~0 := 2; 193659#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 193657#L798-1 assume !(1 == ~T2_E~0); 193655#L803-1 assume !(1 == ~T3_E~0); 193653#L808-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 193651#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 193647#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 193645#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 193643#L828-1 assume !(1 == ~E_3~0); 193641#L833-1 assume 1 == ~E_4~0;~E_4~0 := 2; 193638#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 193636#L843-1 assume { :end_inline_reset_time_events } true; 193634#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 193631#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 193629#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 193627#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 193625#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 193623#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 193622#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 193618#L932 assume !(0 != start_simulation_~tmp___0~1#1); 189648#L900-2 [2024-11-13 13:56:09,519 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:09,519 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 6 times [2024-11-13 13:56:09,519 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:09,519 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1031702701] [2024-11-13 13:56:09,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:09,519 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:09,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:09,532 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:56:09,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:09,553 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:56:09,554 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:09,554 INFO L85 PathProgramCache]: Analyzing trace with hash -2065982834, now seen corresponding path program 1 times [2024-11-13 13:56:09,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:09,555 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [319016199] [2024-11-13 13:56:09,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:09,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:09,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:09,672 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 130 trivial. 0 not checked. [2024-11-13 13:56:09,672 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:09,672 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [319016199] [2024-11-13 13:56:09,672 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [319016199] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:09,672 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:09,672 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:09,673 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [144383749] [2024-11-13 13:56:09,673 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:09,673 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:56:09,673 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:09,673 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:56:09,674 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:56:09,674 INFO L87 Difference]: Start difference. First operand 18736 states and 25413 transitions. cyclomatic complexity: 6693 Second operand has 3 states, 3 states have (on average 70.66666666666667) internal successors, (212), 3 states have internal predecessors, (212), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:09,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:09,788 INFO L93 Difference]: Finished difference Result 20869 states and 28038 transitions. [2024-11-13 13:56:09,788 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20869 states and 28038 transitions. [2024-11-13 13:56:09,871 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 20525 [2024-11-13 13:56:09,941 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20869 states to 20869 states and 28038 transitions. [2024-11-13 13:56:09,941 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20869 [2024-11-13 13:56:09,953 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20869 [2024-11-13 13:56:09,953 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20869 states and 28038 transitions. [2024-11-13 13:56:09,966 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:09,966 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20869 states and 28038 transitions. [2024-11-13 13:56:09,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20869 states and 28038 transitions. [2024-11-13 13:56:10,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20869 to 20005. [2024-11-13 13:56:10,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20005 states, 20005 states have (on average 1.3471632091977006) internal successors, (26950), 20004 states have internal predecessors, (26950), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:10,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20005 states to 20005 states and 26950 transitions. [2024-11-13 13:56:10,207 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20005 states and 26950 transitions. [2024-11-13 13:56:10,208 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:56:10,208 INFO L424 stractBuchiCegarLoop]: Abstraction has 20005 states and 26950 transitions. [2024-11-13 13:56:10,208 INFO L331 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-13 13:56:10,208 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20005 states and 26950 transitions. [2024-11-13 13:56:10,266 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 19661 [2024-11-13 13:56:10,267 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:10,267 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:10,268 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:10,268 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:10,268 INFO L745 eck$LassoCheckResult]: Stem: 229193#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 229194#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 229325#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 229326#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 229347#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 229348#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 229127#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 229128#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 229482#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 229483#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 229430#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 229091#L586 assume !(0 == ~M_E~0); 229092#L586-2 assume !(0 == ~T1_E~0); 229148#L591-1 assume !(0 == ~T2_E~0); 229277#L596-1 assume !(0 == ~T3_E~0); 229278#L601-1 assume !(0 == ~T4_E~0); 229333#L606-1 assume !(0 == ~T5_E~0); 229334#L611-1 assume !(0 == ~E_1~0); 229443#L616-1 assume !(0 == ~E_2~0); 229444#L621-1 assume !(0 == ~E_3~0); 229010#L626-1 assume !(0 == ~E_4~0); 229011#L631-1 assume !(0 == ~E_5~0); 229186#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 229006#L279 assume !(1 == ~m_pc~0); 229007#L279-2 is_master_triggered_~__retres1~0#1 := 0; 229364#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 229160#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 229161#L720 assume !(0 != activate_threads_~tmp~1#1); 229363#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 229195#L298 assume !(1 == ~t1_pc~0); 228955#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 228956#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 228981#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 228982#L728 assume !(0 != activate_threads_~tmp___0~0#1); 229020#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 229154#L317 assume !(1 == ~t2_pc~0); 229155#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 229386#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 229330#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 229204#L736 assume !(0 != activate_threads_~tmp___1~0#1); 229205#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 229426#L336 assume !(1 == ~t3_pc~0); 229427#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 229525#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 228929#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 228930#L744 assume !(0 != activate_threads_~tmp___2~0#1); 229372#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 229437#L355 assume !(1 == ~t4_pc~0); 229274#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 229435#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 229052#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 229053#L752 assume !(0 != activate_threads_~tmp___3~0#1); 229032#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 229033#L374 assume !(1 == ~t5_pc~0); 229176#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 229177#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 229166#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 229167#L760 assume !(0 != activate_threads_~tmp___4~0#1); 229313#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 229314#L649 assume !(1 == ~M_E~0); 229514#L649-2 assume !(1 == ~T1_E~0); 228991#L654-1 assume !(1 == ~T2_E~0); 228992#L659-1 assume !(1 == ~T3_E~0); 229203#L664-1 assume !(1 == ~T4_E~0); 228983#L669-1 assume !(1 == ~T5_E~0); 228984#L674-1 assume !(1 == ~E_1~0); 229417#L679-1 assume !(1 == ~E_2~0); 229096#L684-1 assume !(1 == ~E_3~0); 229097#L689-1 assume !(1 == ~E_4~0); 229270#L694-1 assume !(1 == ~E_5~0); 229268#L699-1 assume { :end_inline_reset_delta_events } true; 229269#L900-2 assume !false; 229815#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 229809#L561-1 [2024-11-13 13:56:10,268 INFO L747 eck$LassoCheckResult]: Loop: 229809#L561-1 assume !false; 229803#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 229796#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 229790#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 229784#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 229776#L486 assume 0 != eval_~tmp~0#1; 229769#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 229762#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 229754#L494-2 havoc eval_~tmp_ndt_1~0#1; 229747#L491-1 assume !(0 == ~t1_st~0); 229742#L505-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 229737#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 229731#L522-2 havoc eval_~tmp_ndt_3~0#1; 229726#L519-1 assume !(0 == ~t3_st~0); 229727#L533-1 assume !(0 == ~t4_st~0); 229817#L547-1 assume !(0 == ~t5_st~0); 229809#L561-1 [2024-11-13 13:56:10,269 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:10,269 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547966, now seen corresponding path program 1 times [2024-11-13 13:56:10,269 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:10,269 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1222790979] [2024-11-13 13:56:10,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:10,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:10,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:10,280 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:56:10,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:10,299 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:56:10,299 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:10,299 INFO L85 PathProgramCache]: Analyzing trace with hash -83522811, now seen corresponding path program 1 times [2024-11-13 13:56:10,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:10,299 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1901086811] [2024-11-13 13:56:10,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:10,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:10,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:10,305 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:56:10,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:10,310 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:56:10,311 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:10,311 INFO L85 PathProgramCache]: Analyzing trace with hash 1512901506, now seen corresponding path program 1 times [2024-11-13 13:56:10,311 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:10,311 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2074200427] [2024-11-13 13:56:10,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:10,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:10,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:10,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:10,437 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:10,437 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2074200427] [2024-11-13 13:56:10,437 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2074200427] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:10,437 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:10,437 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:10,438 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1495107248] [2024-11-13 13:56:10,438 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:10,561 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:10,562 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:56:10,562 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:56:10,562 INFO L87 Difference]: Start difference. First operand 20005 states and 26950 transitions. cyclomatic complexity: 6965 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:10,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:10,780 INFO L93 Difference]: Finished difference Result 37868 states and 50649 transitions. [2024-11-13 13:56:10,781 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37868 states and 50649 transitions. [2024-11-13 13:56:10,983 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 37186 [2024-11-13 13:56:11,147 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37868 states to 37868 states and 50649 transitions. [2024-11-13 13:56:11,148 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37868 [2024-11-13 13:56:11,172 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37868 [2024-11-13 13:56:11,173 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37868 states and 50649 transitions. [2024-11-13 13:56:11,202 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:11,202 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37868 states and 50649 transitions. [2024-11-13 13:56:11,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37868 states and 50649 transitions. [2024-11-13 13:56:11,613 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37868 to 35296. [2024-11-13 13:56:11,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35296 states, 35296 states have (on average 1.3423334088848595) internal successors, (47379), 35295 states have internal predecessors, (47379), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:11,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35296 states to 35296 states and 47379 transitions. [2024-11-13 13:56:11,736 INFO L240 hiAutomatonCegarLoop]: Abstraction has 35296 states and 47379 transitions. [2024-11-13 13:56:11,737 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:56:11,737 INFO L424 stractBuchiCegarLoop]: Abstraction has 35296 states and 47379 transitions. [2024-11-13 13:56:11,737 INFO L331 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-13 13:56:11,738 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35296 states and 47379 transitions. [2024-11-13 13:56:11,869 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 34614 [2024-11-13 13:56:11,871 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:11,872 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:11,873 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:11,873 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:11,874 INFO L745 eck$LassoCheckResult]: Stem: 287072#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 287073#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 287206#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 287207#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 287228#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 287229#L401-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 287328#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 294216#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 294215#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 294214#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 294213#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 294212#L586 assume !(0 == ~M_E~0); 294211#L586-2 assume !(0 == ~T1_E~0); 294210#L591-1 assume !(0 == ~T2_E~0); 294209#L596-1 assume !(0 == ~T3_E~0); 294208#L601-1 assume !(0 == ~T4_E~0); 294207#L606-1 assume !(0 == ~T5_E~0); 294206#L611-1 assume !(0 == ~E_1~0); 294205#L616-1 assume !(0 == ~E_2~0); 294204#L621-1 assume !(0 == ~E_3~0); 294203#L626-1 assume !(0 == ~E_4~0); 294202#L631-1 assume !(0 == ~E_5~0); 294201#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 294200#L279 assume !(1 == ~m_pc~0); 294199#L279-2 is_master_triggered_~__retres1~0#1 := 0; 294198#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 287038#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 287039#L720 assume !(0 != activate_threads_~tmp~1#1); 287248#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 287451#L298 assume !(1 == ~t1_pc~0); 294193#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 287430#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 287431#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 286899#L728 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 286900#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 287237#L317 assume !(1 == ~t2_pc~0); 287269#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 287270#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 287210#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 287211#L736 assume !(0 != activate_threads_~tmp___1~0#1); 287404#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 287405#L336 assume !(1 == ~t3_pc~0); 287427#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 287428#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 286810#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 286811#L744 assume !(0 != activate_threads_~tmp___2~0#1); 287319#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 287320#L355 assume !(1 == ~t4_pc~0); 287158#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 287316#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 286931#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 286932#L752 assume !(0 != activate_threads_~tmp___3~0#1); 286914#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 286915#L374 assume !(1 == ~t5_pc~0); 287059#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 287060#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 287044#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 287045#L760 assume !(0 != activate_threads_~tmp___4~0#1); 287195#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 287196#L649 assume !(1 == ~M_E~0); 287456#L649-2 assume !(1 == ~T1_E~0); 287457#L654-1 assume !(1 == ~T2_E~0); 287245#L659-1 assume !(1 == ~T3_E~0); 287246#L664-1 assume !(1 == ~T4_E~0); 286863#L669-1 assume !(1 == ~T5_E~0); 286864#L674-1 assume !(1 == ~E_1~0); 287314#L679-1 assume !(1 == ~E_2~0); 287315#L684-1 assume !(1 == ~E_3~0); 294098#L689-1 assume !(1 == ~E_4~0); 294097#L694-1 assume !(1 == ~E_5~0); 287148#L699-1 assume { :end_inline_reset_delta_events } true; 287149#L900-2 assume !false; 296088#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 296085#L561-1 [2024-11-13 13:56:11,874 INFO L747 eck$LassoCheckResult]: Loop: 296085#L561-1 assume !false; 296082#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 296079#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 296077#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 296076#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 296075#L486 assume 0 != eval_~tmp~0#1; 296072#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 296069#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 296070#L494-2 havoc eval_~tmp_ndt_1~0#1; 296171#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 294120#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 296142#L508-2 havoc eval_~tmp_ndt_2~0#1; 296133#L505-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 296123#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 296116#L522-2 havoc eval_~tmp_ndt_3~0#1; 296106#L519-1 assume !(0 == ~t3_st~0); 296094#L533-1 assume !(0 == ~t4_st~0); 296090#L547-1 assume !(0 == ~t5_st~0); 296085#L561-1 [2024-11-13 13:56:11,874 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:11,875 INFO L85 PathProgramCache]: Analyzing trace with hash -632671874, now seen corresponding path program 1 times [2024-11-13 13:56:11,875 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:11,875 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [170007984] [2024-11-13 13:56:11,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:11,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:11,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:11,917 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:11,917 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:11,917 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [170007984] [2024-11-13 13:56:11,917 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [170007984] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:11,917 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:11,917 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:11,917 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [739088390] [2024-11-13 13:56:11,917 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:11,918 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:56:11,918 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:11,918 INFO L85 PathProgramCache]: Analyzing trace with hash 1526861462, now seen corresponding path program 1 times [2024-11-13 13:56:11,918 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:11,918 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [72345289] [2024-11-13 13:56:11,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:11,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:11,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:11,925 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:56:11,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:11,930 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:56:12,038 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:12,038 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:56:12,039 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:56:12,039 INFO L87 Difference]: Start difference. First operand 35296 states and 47379 transitions. cyclomatic complexity: 12103 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:12,179 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:12,179 INFO L93 Difference]: Finished difference Result 35224 states and 47282 transitions. [2024-11-13 13:56:12,179 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35224 states and 47282 transitions. [2024-11-13 13:56:12,316 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 34614 [2024-11-13 13:56:12,432 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35224 states to 35224 states and 47282 transitions. [2024-11-13 13:56:12,433 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35224 [2024-11-13 13:56:12,453 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35224 [2024-11-13 13:56:12,454 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35224 states and 47282 transitions. [2024-11-13 13:56:12,673 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:12,673 INFO L218 hiAutomatonCegarLoop]: Abstraction has 35224 states and 47282 transitions. [2024-11-13 13:56:12,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35224 states and 47282 transitions. [2024-11-13 13:56:13,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35224 to 35224. [2024-11-13 13:56:13,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35224 states, 35224 states have (on average 1.3423234158528277) internal successors, (47282), 35223 states have internal predecessors, (47282), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:13,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35224 states to 35224 states and 47282 transitions. [2024-11-13 13:56:13,179 INFO L240 hiAutomatonCegarLoop]: Abstraction has 35224 states and 47282 transitions. [2024-11-13 13:56:13,180 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:56:13,180 INFO L424 stractBuchiCegarLoop]: Abstraction has 35224 states and 47282 transitions. [2024-11-13 13:56:13,180 INFO L331 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-13 13:56:13,180 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35224 states and 47282 transitions. [2024-11-13 13:56:13,280 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 34614 [2024-11-13 13:56:13,280 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:13,281 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:13,281 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:13,281 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:13,282 INFO L745 eck$LassoCheckResult]: Stem: 357592#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 357593#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 357712#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 357713#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 357731#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 357732#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 357525#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 357526#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 357848#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 357849#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 357804#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 357493#L586 assume !(0 == ~M_E~0); 357494#L586-2 assume !(0 == ~T1_E~0); 357548#L591-1 assume !(0 == ~T2_E~0); 357671#L596-1 assume !(0 == ~T3_E~0); 357672#L601-1 assume !(0 == ~T4_E~0); 357717#L606-1 assume !(0 == ~T5_E~0); 357718#L611-1 assume !(0 == ~E_1~0); 357812#L616-1 assume !(0 == ~E_2~0); 357813#L621-1 assume !(0 == ~E_3~0); 357415#L626-1 assume !(0 == ~E_4~0); 357416#L631-1 assume !(0 == ~E_5~0); 357587#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 357413#L279 assume !(1 == ~m_pc~0); 357414#L279-2 is_master_triggered_~__retres1~0#1 := 0; 357747#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 357560#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 357561#L720 assume !(0 != activate_threads_~tmp~1#1); 357746#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 357594#L298 assume !(1 == ~t1_pc~0); 357363#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 357364#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 357387#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 357388#L728 assume !(0 != activate_threads_~tmp___0~0#1); 357424#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 357554#L317 assume !(1 == ~t2_pc~0); 357555#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 357768#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 357716#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 357605#L736 assume !(0 != activate_threads_~tmp___1~0#1); 357606#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 357798#L336 assume !(1 == ~t3_pc~0); 357799#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 357884#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 357336#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 357337#L744 assume !(0 != activate_threads_~tmp___2~0#1); 357755#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 357808#L355 assume !(1 == ~t4_pc~0); 357670#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 357805#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 357455#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 357456#L752 assume !(0 != activate_threads_~tmp___3~0#1); 357438#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 357439#L374 assume !(1 == ~t5_pc~0); 357578#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 357579#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 357566#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 357567#L760 assume !(0 != activate_threads_~tmp___4~0#1); 357700#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 357701#L649 assume !(1 == ~M_E~0); 357876#L649-2 assume !(1 == ~T1_E~0); 357397#L654-1 assume !(1 == ~T2_E~0); 357398#L659-1 assume !(1 == ~T3_E~0); 357602#L664-1 assume !(1 == ~T4_E~0); 357389#L669-1 assume !(1 == ~T5_E~0); 357390#L674-1 assume !(1 == ~E_1~0); 357788#L679-1 assume !(1 == ~E_2~0); 357495#L684-1 assume !(1 == ~E_3~0); 357496#L689-1 assume !(1 == ~E_4~0); 357665#L694-1 assume !(1 == ~E_5~0); 357662#L699-1 assume { :end_inline_reset_delta_events } true; 357663#L900-2 assume !false; 373641#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 373639#L561-1 [2024-11-13 13:56:13,282 INFO L747 eck$LassoCheckResult]: Loop: 373639#L561-1 assume !false; 373636#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 373633#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 373631#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 373630#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 373602#L486 assume 0 != eval_~tmp~0#1; 373593#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 373587#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 373582#L494-2 havoc eval_~tmp_ndt_1~0#1; 373359#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 373356#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 373354#L508-2 havoc eval_~tmp_ndt_2~0#1; 373352#L505-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 373349#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 373350#L522-2 havoc eval_~tmp_ndt_3~0#1; 373788#L519-1 assume !(0 == ~t3_st~0); 373647#L533-1 assume !(0 == ~t4_st~0); 373643#L547-1 assume !(0 == ~t5_st~0); 373639#L561-1 [2024-11-13 13:56:13,282 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:13,282 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547966, now seen corresponding path program 2 times [2024-11-13 13:56:13,283 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:13,283 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [665162319] [2024-11-13 13:56:13,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:13,283 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:13,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:13,296 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:56:13,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:13,314 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:56:13,315 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:13,315 INFO L85 PathProgramCache]: Analyzing trace with hash 1526861462, now seen corresponding path program 2 times [2024-11-13 13:56:13,315 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:13,315 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [480913559] [2024-11-13 13:56:13,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:13,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:13,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:13,320 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:56:13,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:13,324 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:56:13,325 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:13,325 INFO L85 PathProgramCache]: Analyzing trace with hash -1907661869, now seen corresponding path program 1 times [2024-11-13 13:56:13,325 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:13,326 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [911938967] [2024-11-13 13:56:13,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:13,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:13,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:13,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:13,379 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:13,379 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [911938967] [2024-11-13 13:56:13,379 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [911938967] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:13,379 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:13,380 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:13,380 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2141953939] [2024-11-13 13:56:13,380 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:13,480 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:13,480 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:56:13,480 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:56:13,480 INFO L87 Difference]: Start difference. First operand 35224 states and 47282 transitions. cyclomatic complexity: 12078 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:13,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:13,636 INFO L93 Difference]: Finished difference Result 41005 states and 54635 transitions. [2024-11-13 13:56:13,636 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41005 states and 54635 transitions. [2024-11-13 13:56:13,983 INFO L131 ngComponentsAnalysis]: Automaton has 22 accepting balls. 39793 [2024-11-13 13:56:14,209 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41005 states to 41005 states and 54635 transitions. [2024-11-13 13:56:14,210 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41005 [2024-11-13 13:56:14,232 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41005 [2024-11-13 13:56:14,233 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41005 states and 54635 transitions. [2024-11-13 13:56:14,259 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:14,259 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41005 states and 54635 transitions. [2024-11-13 13:56:14,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41005 states and 54635 transitions. [2024-11-13 13:56:14,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41005 to 39447. [2024-11-13 13:56:14,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39447 states, 39447 states have (on average 1.3358937308287069) internal successors, (52697), 39446 states have internal predecessors, (52697), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:14,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39447 states to 39447 states and 52697 transitions. [2024-11-13 13:56:14,819 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39447 states and 52697 transitions. [2024-11-13 13:56:14,820 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:56:14,820 INFO L424 stractBuchiCegarLoop]: Abstraction has 39447 states and 52697 transitions. [2024-11-13 13:56:14,821 INFO L331 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-13 13:56:14,821 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39447 states and 52697 transitions. [2024-11-13 13:56:15,101 INFO L131 ngComponentsAnalysis]: Automaton has 22 accepting balls. 38235 [2024-11-13 13:56:15,101 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:15,101 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:15,102 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:15,102 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:15,103 INFO L745 eck$LassoCheckResult]: Stem: 433836#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 433837#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 433958#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 433959#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 433980#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 433981#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 433767#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 433768#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 434114#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 434115#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 434066#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 433733#L586 assume !(0 == ~M_E~0); 433734#L586-2 assume !(0 == ~T1_E~0); 433790#L591-1 assume !(0 == ~T2_E~0); 433916#L596-1 assume !(0 == ~T3_E~0); 433917#L601-1 assume !(0 == ~T4_E~0); 433965#L606-1 assume !(0 == ~T5_E~0); 433966#L611-1 assume !(0 == ~E_1~0); 434075#L616-1 assume !(0 == ~E_2~0); 434076#L621-1 assume !(0 == ~E_3~0); 433652#L626-1 assume !(0 == ~E_4~0); 433653#L631-1 assume !(0 == ~E_5~0); 433829#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 433650#L279 assume !(1 == ~m_pc~0); 433651#L279-2 is_master_triggered_~__retres1~0#1 := 0; 434000#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 433801#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 433802#L720 assume !(0 != activate_threads_~tmp~1#1); 433999#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 433838#L298 assume !(1 == ~t1_pc~0); 433600#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 433601#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 433624#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 433625#L728 assume !(0 != activate_threads_~tmp___0~0#1); 433662#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 433795#L317 assume !(1 == ~t2_pc~0); 433796#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 434022#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 433964#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 433849#L736 assume !(0 != activate_threads_~tmp___1~0#1); 433850#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 434059#L336 assume !(1 == ~t3_pc~0); 434060#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 434155#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 433573#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 433574#L744 assume !(0 != activate_threads_~tmp___2~0#1); 434009#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 434071#L355 assume !(1 == ~t4_pc~0); 433915#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 434068#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 433694#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 433695#L752 assume !(0 != activate_threads_~tmp___3~0#1); 433675#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 433676#L374 assume !(1 == ~t5_pc~0); 433822#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 433823#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 433807#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 433808#L760 assume !(0 != activate_threads_~tmp___4~0#1); 433946#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 433947#L649 assume !(1 == ~M_E~0); 434145#L649-2 assume !(1 == ~T1_E~0); 433634#L654-1 assume !(1 == ~T2_E~0); 433635#L659-1 assume !(1 == ~T3_E~0); 433846#L664-1 assume !(1 == ~T4_E~0); 433626#L669-1 assume !(1 == ~T5_E~0); 433627#L674-1 assume !(1 == ~E_1~0); 434049#L679-1 assume !(1 == ~E_2~0); 433735#L684-1 assume !(1 == ~E_3~0); 433736#L689-1 assume !(1 == ~E_4~0); 433910#L694-1 assume !(1 == ~E_5~0); 433907#L699-1 assume { :end_inline_reset_delta_events } true; 433908#L900-2 assume !false; 442673#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 442671#L561-1 [2024-11-13 13:56:15,103 INFO L747 eck$LassoCheckResult]: Loop: 442671#L561-1 assume !false; 442668#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 442666#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 442661#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 442660#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 442658#L486 assume 0 != eval_~tmp~0#1; 442652#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 442646#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 442643#L494-2 havoc eval_~tmp_ndt_1~0#1; 442007#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 441999#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 441995#L508-2 havoc eval_~tmp_ndt_2~0#1; 441990#L505-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 441985#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 441986#L522-2 havoc eval_~tmp_ndt_3~0#1; 442946#L519-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 442941#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 442939#L536-2 havoc eval_~tmp_ndt_4~0#1; 442682#L533-1 assume !(0 == ~t4_st~0); 442675#L547-1 assume !(0 == ~t5_st~0); 442671#L561-1 [2024-11-13 13:56:15,103 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:15,103 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547966, now seen corresponding path program 3 times [2024-11-13 13:56:15,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:15,104 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1627044430] [2024-11-13 13:56:15,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:15,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:15,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:15,115 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:56:15,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:15,130 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:56:15,131 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:15,131 INFO L85 PathProgramCache]: Analyzing trace with hash -1734103385, now seen corresponding path program 1 times [2024-11-13 13:56:15,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:15,131 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1154400421] [2024-11-13 13:56:15,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:15,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:15,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:15,135 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:56:15,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:15,139 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:56:15,140 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:15,140 INFO L85 PathProgramCache]: Analyzing trace with hash 518826148, now seen corresponding path program 1 times [2024-11-13 13:56:15,140 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:15,140 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1386706651] [2024-11-13 13:56:15,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:15,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:15,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:15,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:15,192 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:15,192 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1386706651] [2024-11-13 13:56:15,192 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1386706651] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:15,192 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:15,192 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:56:15,192 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1898581893] [2024-11-13 13:56:15,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:15,302 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:15,302 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:56:15,302 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:56:15,303 INFO L87 Difference]: Start difference. First operand 39447 states and 52697 transitions. cyclomatic complexity: 13272 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:15,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:15,697 INFO L93 Difference]: Finished difference Result 69500 states and 92582 transitions. [2024-11-13 13:56:15,698 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69500 states and 92582 transitions. [2024-11-13 13:56:15,943 INFO L131 ngComponentsAnalysis]: Automaton has 22 accepting balls. 67154 [2024-11-13 13:56:16,230 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69500 states to 69500 states and 92582 transitions. [2024-11-13 13:56:16,231 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69500 [2024-11-13 13:56:16,260 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69500 [2024-11-13 13:56:16,261 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69500 states and 92582 transitions. [2024-11-13 13:56:16,292 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:16,293 INFO L218 hiAutomatonCegarLoop]: Abstraction has 69500 states and 92582 transitions. [2024-11-13 13:56:16,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69500 states and 92582 transitions. [2024-11-13 13:56:16,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69500 to 67526. [2024-11-13 13:56:17,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67526 states, 67526 states have (on average 1.336255664484791) internal successors, (90232), 67525 states have internal predecessors, (90232), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:17,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67526 states to 67526 states and 90232 transitions. [2024-11-13 13:56:17,197 INFO L240 hiAutomatonCegarLoop]: Abstraction has 67526 states and 90232 transitions. [2024-11-13 13:56:17,198 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:56:17,198 INFO L424 stractBuchiCegarLoop]: Abstraction has 67526 states and 90232 transitions. [2024-11-13 13:56:17,198 INFO L331 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-13 13:56:17,198 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67526 states and 90232 transitions. [2024-11-13 13:56:17,446 INFO L131 ngComponentsAnalysis]: Automaton has 22 accepting balls. 65180 [2024-11-13 13:56:17,446 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:17,446 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:17,447 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:17,447 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:17,447 INFO L745 eck$LassoCheckResult]: Stem: 542790#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 542791#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 542923#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 542924#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 542943#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 542944#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 542720#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 542721#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 543089#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 543090#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 543030#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 542687#L586 assume !(0 == ~M_E~0); 542688#L586-2 assume !(0 == ~T1_E~0); 542744#L591-1 assume !(0 == ~T2_E~0); 542878#L596-1 assume !(0 == ~T3_E~0); 542879#L601-1 assume !(0 == ~T4_E~0); 542928#L606-1 assume !(0 == ~T5_E~0); 542929#L611-1 assume !(0 == ~E_1~0); 543042#L616-1 assume !(0 == ~E_2~0); 543043#L621-1 assume !(0 == ~E_3~0); 542606#L626-1 assume !(0 == ~E_4~0); 542607#L631-1 assume !(0 == ~E_5~0); 542783#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 542604#L279 assume !(1 == ~m_pc~0); 542605#L279-2 is_master_triggered_~__retres1~0#1 := 0; 542962#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 542755#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 542756#L720 assume !(0 != activate_threads_~tmp~1#1); 542961#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 542792#L298 assume !(1 == ~t1_pc~0); 542554#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 542555#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 542578#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 542579#L728 assume !(0 != activate_threads_~tmp___0~0#1); 542616#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 542749#L317 assume !(1 == ~t2_pc~0); 542750#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 542983#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 542927#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 542803#L736 assume !(0 != activate_threads_~tmp___1~0#1); 542804#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 543024#L336 assume !(1 == ~t3_pc~0); 543025#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 543152#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 542528#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 542529#L744 assume !(0 != activate_threads_~tmp___2~0#1); 542971#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 543036#L355 assume !(1 == ~t4_pc~0); 542877#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 543033#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 542647#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 542648#L752 assume !(0 != activate_threads_~tmp___3~0#1); 542629#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 542630#L374 assume !(1 == ~t5_pc~0); 542776#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 542777#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 542761#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 542762#L760 assume !(0 != activate_threads_~tmp___4~0#1); 542910#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 542911#L649 assume !(1 == ~M_E~0); 543136#L649-2 assume !(1 == ~T1_E~0); 542588#L654-1 assume !(1 == ~T2_E~0); 542589#L659-1 assume !(1 == ~T3_E~0); 542800#L664-1 assume !(1 == ~T4_E~0); 542580#L669-1 assume !(1 == ~T5_E~0); 542581#L674-1 assume !(1 == ~E_1~0); 543011#L679-1 assume !(1 == ~E_2~0); 542689#L684-1 assume !(1 == ~E_3~0); 542690#L689-1 assume !(1 == ~E_4~0); 542872#L694-1 assume !(1 == ~E_5~0); 542868#L699-1 assume { :end_inline_reset_delta_events } true; 542869#L900-2 assume !false; 579417#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 574874#L561-1 [2024-11-13 13:56:17,447 INFO L747 eck$LassoCheckResult]: Loop: 574874#L561-1 assume !false; 579413#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 579411#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 579410#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 579409#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 579406#L486 assume 0 != eval_~tmp~0#1; 579403#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 579400#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 579398#L494-2 havoc eval_~tmp_ndt_1~0#1; 579396#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 579298#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 579394#L508-2 havoc eval_~tmp_ndt_2~0#1; 579882#L505-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 579879#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 579880#L522-2 havoc eval_~tmp_ndt_3~0#1; 587971#L519-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 587967#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 587965#L536-2 havoc eval_~tmp_ndt_4~0#1; 574881#L533-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 574878#L550 assume !(0 != eval_~tmp_ndt_5~0#1); 574876#L550-2 havoc eval_~tmp_ndt_5~0#1; 574873#L547-1 assume !(0 == ~t5_st~0); 574874#L561-1 [2024-11-13 13:56:17,448 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:17,449 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547966, now seen corresponding path program 4 times [2024-11-13 13:56:17,449 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:17,449 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [17103761] [2024-11-13 13:56:17,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:17,449 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:17,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:17,474 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:56:17,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:17,497 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:56:17,497 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:17,497 INFO L85 PathProgramCache]: Analyzing trace with hash -31321770, now seen corresponding path program 1 times [2024-11-13 13:56:17,497 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:17,498 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [767072826] [2024-11-13 13:56:17,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:17,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:17,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:17,504 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:56:17,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:17,509 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:56:17,510 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:17,510 INFO L85 PathProgramCache]: Analyzing trace with hash 370442259, now seen corresponding path program 1 times [2024-11-13 13:56:17,510 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:17,510 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [707871828] [2024-11-13 13:56:17,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:17,510 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:17,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:56:17,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:56:17,807 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:56:17,807 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [707871828] [2024-11-13 13:56:17,808 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [707871828] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:56:17,808 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:56:17,808 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:56:17,808 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1602889707] [2024-11-13 13:56:17,808 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:56:17,913 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:56:17,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:56:17,914 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:56:17,914 INFO L87 Difference]: Start difference. First operand 67526 states and 90232 transitions. cyclomatic complexity: 22728 Second operand has 3 states, 2 states have (on average 47.5) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:18,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:56:18,168 INFO L93 Difference]: Finished difference Result 79878 states and 106415 transitions. [2024-11-13 13:56:18,169 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79878 states and 106415 transitions. [2024-11-13 13:56:18,531 INFO L131 ngComponentsAnalysis]: Automaton has 23 accepting balls. 75556 [2024-11-13 13:56:19,069 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79878 states to 79878 states and 106415 transitions. [2024-11-13 13:56:19,070 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 79878 [2024-11-13 13:56:19,102 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 79878 [2024-11-13 13:56:19,102 INFO L73 IsDeterministic]: Start isDeterministic. Operand 79878 states and 106415 transitions. [2024-11-13 13:56:19,155 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:56:19,155 INFO L218 hiAutomatonCegarLoop]: Abstraction has 79878 states and 106415 transitions. [2024-11-13 13:56:19,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79878 states and 106415 transitions. [2024-11-13 13:56:19,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79878 to 79878. [2024-11-13 13:56:19,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 79878 states, 79878 states have (on average 1.332219134179624) internal successors, (106415), 79877 states have internal predecessors, (106415), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:56:20,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79878 states to 79878 states and 106415 transitions. [2024-11-13 13:56:20,138 INFO L240 hiAutomatonCegarLoop]: Abstraction has 79878 states and 106415 transitions. [2024-11-13 13:56:20,139 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:56:20,139 INFO L424 stractBuchiCegarLoop]: Abstraction has 79878 states and 106415 transitions. [2024-11-13 13:56:20,139 INFO L331 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-13 13:56:20,139 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 79878 states and 106415 transitions. [2024-11-13 13:56:20,370 INFO L131 ngComponentsAnalysis]: Automaton has 23 accepting balls. 75556 [2024-11-13 13:56:20,370 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:56:20,371 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:56:20,371 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:20,371 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:56:20,372 INFO L745 eck$LassoCheckResult]: Stem: 690194#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 690195#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 690321#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 690322#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 690343#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 690344#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 690127#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 690128#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 690480#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 690481#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 690424#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 690096#L586 assume !(0 == ~M_E~0); 690097#L586-2 assume !(0 == ~T1_E~0); 690149#L591-1 assume !(0 == ~T2_E~0); 690276#L596-1 assume !(0 == ~T3_E~0); 690277#L601-1 assume !(0 == ~T4_E~0); 690328#L606-1 assume !(0 == ~T5_E~0); 690329#L611-1 assume !(0 == ~E_1~0); 690436#L616-1 assume !(0 == ~E_2~0); 690437#L621-1 assume !(0 == ~E_3~0); 690019#L626-1 assume !(0 == ~E_4~0); 690020#L631-1 assume !(0 == ~E_5~0); 690187#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 690017#L279 assume !(1 == ~m_pc~0); 690018#L279-2 is_master_triggered_~__retres1~0#1 := 0; 690361#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 690160#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 690161#L720 assume !(0 != activate_threads_~tmp~1#1); 690360#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 690196#L298 assume !(1 == ~t1_pc~0); 689966#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 689967#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 689990#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 689991#L728 assume !(0 != activate_threads_~tmp___0~0#1); 690028#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 690154#L317 assume !(1 == ~t2_pc~0); 690155#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 690381#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 690327#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 690207#L736 assume !(0 != activate_threads_~tmp___1~0#1); 690208#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 690418#L336 assume !(1 == ~t3_pc~0); 690419#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 690526#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 689940#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 689941#L744 assume !(0 != activate_threads_~tmp___2~0#1); 690369#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 690431#L355 assume !(1 == ~t4_pc~0); 690275#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 690428#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 690057#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 690058#L752 assume !(0 != activate_threads_~tmp___3~0#1); 690040#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 690041#L374 assume !(1 == ~t5_pc~0); 690180#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 690181#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 690167#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 690168#L760 assume !(0 != activate_threads_~tmp___4~0#1); 690309#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 690310#L649 assume !(1 == ~M_E~0); 690516#L649-2 assume !(1 == ~T1_E~0); 690000#L654-1 assume !(1 == ~T2_E~0); 690001#L659-1 assume !(1 == ~T3_E~0); 690204#L664-1 assume !(1 == ~T4_E~0); 689992#L669-1 assume !(1 == ~T5_E~0); 689993#L674-1 assume !(1 == ~E_1~0); 690408#L679-1 assume !(1 == ~E_2~0); 690098#L684-1 assume !(1 == ~E_3~0); 690099#L689-1 assume !(1 == ~E_4~0); 690270#L694-1 assume !(1 == ~E_5~0); 690266#L699-1 assume { :end_inline_reset_delta_events } true; 690267#L900-2 assume !false; 745302#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 745299#L561-1 [2024-11-13 13:56:20,372 INFO L747 eck$LassoCheckResult]: Loop: 745299#L561-1 assume !false; 745297#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 745294#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 745292#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 745290#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 745288#L486 assume 0 != eval_~tmp~0#1; 745285#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 745282#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 745280#L494-2 havoc eval_~tmp_ndt_1~0#1; 745277#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 744752#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 745275#L508-2 havoc eval_~tmp_ndt_2~0#1; 753643#L505-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 753640#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 753641#L522-2 havoc eval_~tmp_ndt_3~0#1; 767847#L519-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 690244#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 690245#L536-2 havoc eval_~tmp_ndt_4~0#1; 765992#L533-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 765989#L550 assume !(0 != eval_~tmp_ndt_5~0#1); 765988#L550-2 havoc eval_~tmp_ndt_5~0#1; 765987#L547-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 725886#L564 assume !(0 != eval_~tmp_ndt_6~0#1); 725887#L564-2 havoc eval_~tmp_ndt_6~0#1; 745299#L561-1 [2024-11-13 13:56:20,372 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:20,373 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547966, now seen corresponding path program 5 times [2024-11-13 13:56:20,373 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:20,373 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [626441197] [2024-11-13 13:56:20,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:20,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:20,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:20,389 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:56:20,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:20,406 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:56:20,407 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:20,407 INFO L85 PathProgramCache]: Analyzing trace with hash -35447474, now seen corresponding path program 1 times [2024-11-13 13:56:20,407 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:20,407 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445304433] [2024-11-13 13:56:20,407 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:20,408 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:20,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:20,412 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:56:20,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:20,416 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:56:20,416 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:56:20,416 INFO L85 PathProgramCache]: Analyzing trace with hash -487272245, now seen corresponding path program 1 times [2024-11-13 13:56:20,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:56:20,416 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [78143244] [2024-11-13 13:56:20,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:56:20,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:56:20,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:20,428 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:56:20,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:20,447 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:56:22,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:22,565 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:56:22,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:56:22,915 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.11 01:56:22 BoogieIcfgContainer [2024-11-13 13:56:22,918 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-13 13:56:22,919 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-13 13:56:22,919 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-13 13:56:22,919 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-13 13:56:22,920 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:56:00" (3/4) ... [2024-11-13 13:56:22,922 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-13 13:56:23,047 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8f323f9-944e-4f13-9133-164c2e8ea6f8/bin/uautomizer-verify-qhAvR1uOyd/witness.graphml [2024-11-13 13:56:23,047 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-13 13:56:23,048 INFO L158 Benchmark]: Toolchain (without parser) took 24820.05ms. Allocated memory was 117.4MB in the beginning and 9.6GB in the end (delta: 9.5GB). Free memory was 94.2MB in the beginning and 8.4GB in the end (delta: -8.3GB). Peak memory consumption was 1.2GB. Max. memory is 16.1GB. [2024-11-13 13:56:23,051 INFO L158 Benchmark]: CDTParser took 0.45ms. Allocated memory is still 167.8MB. Free memory is still 104.2MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 13:56:23,051 INFO L158 Benchmark]: CACSL2BoogieTranslator took 426.73ms. Allocated memory is still 117.4MB. Free memory was 94.2MB in the beginning and 78.3MB in the end (delta: 15.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-13 13:56:23,051 INFO L158 Benchmark]: Boogie Procedure Inliner took 104.23ms. Allocated memory is still 117.4MB. Free memory was 78.3MB in the beginning and 74.1MB in the end (delta: 4.2MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 13:56:23,052 INFO L158 Benchmark]: Boogie Preprocessor took 140.54ms. Allocated memory is still 117.4MB. Free memory was 74.1MB in the beginning and 68.6MB in the end (delta: 5.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 13:56:23,052 INFO L158 Benchmark]: RCFGBuilder took 1701.91ms. Allocated memory is still 117.4MB. Free memory was 68.6MB in the beginning and 53.0MB in the end (delta: 15.6MB). Peak memory consumption was 41.0MB. Max. memory is 16.1GB. [2024-11-13 13:56:23,052 INFO L158 Benchmark]: BuchiAutomizer took 22312.29ms. Allocated memory was 117.4MB in the beginning and 9.6GB in the end (delta: 9.5GB). Free memory was 53.0MB in the beginning and 8.4GB in the end (delta: -8.3GB). Peak memory consumption was 1.1GB. Max. memory is 16.1GB. [2024-11-13 13:56:23,052 INFO L158 Benchmark]: Witness Printer took 128.38ms. Allocated memory is still 9.6GB. Free memory was 8.4GB in the beginning and 8.4GB in the end (delta: 12.6MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-13 13:56:23,054 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.45ms. Allocated memory is still 167.8MB. Free memory is still 104.2MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 426.73ms. Allocated memory is still 117.4MB. Free memory was 94.2MB in the beginning and 78.3MB in the end (delta: 15.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 104.23ms. Allocated memory is still 117.4MB. Free memory was 78.3MB in the beginning and 74.1MB in the end (delta: 4.2MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 140.54ms. Allocated memory is still 117.4MB. Free memory was 74.1MB in the beginning and 68.6MB in the end (delta: 5.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 1701.91ms. Allocated memory is still 117.4MB. Free memory was 68.6MB in the beginning and 53.0MB in the end (delta: 15.6MB). Peak memory consumption was 41.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 22312.29ms. Allocated memory was 117.4MB in the beginning and 9.6GB in the end (delta: 9.5GB). Free memory was 53.0MB in the beginning and 8.4GB in the end (delta: -8.3GB). Peak memory consumption was 1.1GB. Max. memory is 16.1GB. * Witness Printer took 128.38ms. Allocated memory is still 9.6GB. Free memory was 8.4GB in the beginning and 8.4GB in the end (delta: 12.6MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 25 terminating modules (25 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.25 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 79878 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 21.9s and 26 iterations. TraceHistogramMax:3. Analysis of lassos took 6.9s. Construction of modules took 1.0s. Büchi inclusion checks took 12.3s. Highest rank in rank-based complementation 0. Minimization of det autom 25. Minimization of nondet autom 0. Automata minimization 5.6s AutomataMinimizationTime, 25 MinimizatonAttempts, 21616 StatesRemovedByMinimization, 14 NontrivialMinimizations. Non-live state removal took 3.7s Buchi closure took 0.2s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 16139 SdHoareTripleChecker+Valid, 1.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 16139 mSDsluCounter, 35179 SdHoareTripleChecker+Invalid, 1.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 15524 mSDsCounter, 275 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 731 IncrementalHoareTripleChecker+Invalid, 1006 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 275 mSolverCounterUnsat, 19655 mSDtfsCounter, 731 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI6 SFLT0 conc4 concLT0 SILN1 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 481]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int m_st ; [L32] int t1_st ; [L33] int t2_st ; [L34] int t3_st ; [L35] int t4_st ; [L36] int t5_st ; [L37] int m_i ; [L38] int t1_i ; [L39] int t2_i ; [L40] int t3_i ; [L41] int t4_i ; [L42] int t5_i ; [L43] int M_E = 2; [L44] int T1_E = 2; [L45] int T2_E = 2; [L46] int T3_E = 2; [L47] int T4_E = 2; [L48] int T5_E = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0] [L945] int __retres1 ; [L949] CALL init_model() [L856] m_i = 1 [L857] t1_i = 1 [L858] t2_i = 1 [L859] t3_i = 1 [L860] t4_i = 1 [L861] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L949] RET init_model() [L950] CALL start_simulation() [L886] int kernel_st ; [L887] int tmp ; [L888] int tmp___0 ; [L892] kernel_st = 0 [L893] FCALL update_channels() [L894] CALL init_threads() [L401] COND TRUE m_i == 1 [L402] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L406] COND TRUE t1_i == 1 [L407] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L411] COND TRUE t2_i == 1 [L412] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L416] COND TRUE t3_i == 1 [L417] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L421] COND TRUE t4_i == 1 [L422] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L426] COND TRUE t5_i == 1 [L427] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L894] RET init_threads() [L895] CALL fire_delta_events() [L586] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L591] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L596] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L601] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L606] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L611] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L616] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L621] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L626] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L631] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L636] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L895] RET fire_delta_events() [L896] CALL activate_threads() [L709] int tmp ; [L710] int tmp___0 ; [L711] int tmp___1 ; [L712] int tmp___2 ; [L713] int tmp___3 ; [L714] int tmp___4 ; [L718] CALL, EXPR is_master_triggered() [L276] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L279] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L289] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L291] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L718] RET, EXPR is_master_triggered() [L718] tmp = is_master_triggered() [L720] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L726] CALL, EXPR is_transmit1_triggered() [L295] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L298] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L308] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L310] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L726] RET, EXPR is_transmit1_triggered() [L726] tmp___0 = is_transmit1_triggered() [L728] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L734] CALL, EXPR is_transmit2_triggered() [L314] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L317] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L327] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L329] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L734] RET, EXPR is_transmit2_triggered() [L734] tmp___1 = is_transmit2_triggered() [L736] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L742] CALL, EXPR is_transmit3_triggered() [L333] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L336] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L346] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L348] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L742] RET, EXPR is_transmit3_triggered() [L742] tmp___2 = is_transmit3_triggered() [L744] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L750] CALL, EXPR is_transmit4_triggered() [L352] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L355] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L365] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L367] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L750] RET, EXPR is_transmit4_triggered() [L750] tmp___3 = is_transmit4_triggered() [L752] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L758] CALL, EXPR is_transmit5_triggered() [L371] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L374] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L384] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L386] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L758] RET, EXPR is_transmit5_triggered() [L758] tmp___4 = is_transmit5_triggered() [L760] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L896] RET activate_threads() [L897] CALL reset_delta_events() [L649] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L654] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L659] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L664] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L669] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L674] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L679] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L684] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L689] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L694] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L699] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L897] RET reset_delta_events() [L900] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L903] kernel_st = 1 [L904] CALL eval() [L477] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] Loop: [L481] COND TRUE 1 [L484] CALL, EXPR exists_runnable_thread() [L436] int __retres1 ; [L439] COND TRUE m_st == 0 [L440] __retres1 = 1 [L472] return (__retres1); [L484] RET, EXPR exists_runnable_thread() [L484] tmp = exists_runnable_thread() [L486] COND TRUE \read(tmp) [L491] COND TRUE m_st == 0 [L492] int tmp_ndt_1; [L493] tmp_ndt_1 = __VERIFIER_nondet_int() [L494] COND FALSE !(\read(tmp_ndt_1)) [L505] COND TRUE t1_st == 0 [L506] int tmp_ndt_2; [L507] tmp_ndt_2 = __VERIFIER_nondet_int() [L508] COND FALSE !(\read(tmp_ndt_2)) [L519] COND TRUE t2_st == 0 [L520] int tmp_ndt_3; [L521] tmp_ndt_3 = __VERIFIER_nondet_int() [L522] COND FALSE !(\read(tmp_ndt_3)) [L533] COND TRUE t3_st == 0 [L534] int tmp_ndt_4; [L535] tmp_ndt_4 = __VERIFIER_nondet_int() [L536] COND FALSE !(\read(tmp_ndt_4)) [L547] COND TRUE t4_st == 0 [L548] int tmp_ndt_5; [L549] tmp_ndt_5 = __VERIFIER_nondet_int() [L550] COND FALSE !(\read(tmp_ndt_5)) [L561] COND TRUE t5_st == 0 [L562] int tmp_ndt_6; [L563] tmp_ndt_6 = __VERIFIER_nondet_int() [L564] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 481]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int m_st ; [L32] int t1_st ; [L33] int t2_st ; [L34] int t3_st ; [L35] int t4_st ; [L36] int t5_st ; [L37] int m_i ; [L38] int t1_i ; [L39] int t2_i ; [L40] int t3_i ; [L41] int t4_i ; [L42] int t5_i ; [L43] int M_E = 2; [L44] int T1_E = 2; [L45] int T2_E = 2; [L46] int T3_E = 2; [L47] int T4_E = 2; [L48] int T5_E = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0] [L945] int __retres1 ; [L949] CALL init_model() [L856] m_i = 1 [L857] t1_i = 1 [L858] t2_i = 1 [L859] t3_i = 1 [L860] t4_i = 1 [L861] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L949] RET init_model() [L950] CALL start_simulation() [L886] int kernel_st ; [L887] int tmp ; [L888] int tmp___0 ; [L892] kernel_st = 0 [L893] FCALL update_channels() [L894] CALL init_threads() [L401] COND TRUE m_i == 1 [L402] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L406] COND TRUE t1_i == 1 [L407] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L411] COND TRUE t2_i == 1 [L412] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L416] COND TRUE t3_i == 1 [L417] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L421] COND TRUE t4_i == 1 [L422] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L426] COND TRUE t5_i == 1 [L427] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L894] RET init_threads() [L895] CALL fire_delta_events() [L586] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L591] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L596] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L601] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L606] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L611] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L616] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L621] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L626] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L631] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L636] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L895] RET fire_delta_events() [L896] CALL activate_threads() [L709] int tmp ; [L710] int tmp___0 ; [L711] int tmp___1 ; [L712] int tmp___2 ; [L713] int tmp___3 ; [L714] int tmp___4 ; [L718] CALL, EXPR is_master_triggered() [L276] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L279] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L289] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L291] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L718] RET, EXPR is_master_triggered() [L718] tmp = is_master_triggered() [L720] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L726] CALL, EXPR is_transmit1_triggered() [L295] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L298] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L308] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L310] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L726] RET, EXPR is_transmit1_triggered() [L726] tmp___0 = is_transmit1_triggered() [L728] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L734] CALL, EXPR is_transmit2_triggered() [L314] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L317] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L327] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L329] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L734] RET, EXPR is_transmit2_triggered() [L734] tmp___1 = is_transmit2_triggered() [L736] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L742] CALL, EXPR is_transmit3_triggered() [L333] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L336] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L346] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L348] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L742] RET, EXPR is_transmit3_triggered() [L742] tmp___2 = is_transmit3_triggered() [L744] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L750] CALL, EXPR is_transmit4_triggered() [L352] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L355] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L365] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L367] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L750] RET, EXPR is_transmit4_triggered() [L750] tmp___3 = is_transmit4_triggered() [L752] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L758] CALL, EXPR is_transmit5_triggered() [L371] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L374] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L384] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L386] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L758] RET, EXPR is_transmit5_triggered() [L758] tmp___4 = is_transmit5_triggered() [L760] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L896] RET activate_threads() [L897] CALL reset_delta_events() [L649] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L654] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L659] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L664] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L669] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L674] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L679] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L684] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L689] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L694] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L699] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L897] RET reset_delta_events() [L900] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L903] kernel_st = 1 [L904] CALL eval() [L477] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] Loop: [L481] COND TRUE 1 [L484] CALL, EXPR exists_runnable_thread() [L436] int __retres1 ; [L439] COND TRUE m_st == 0 [L440] __retres1 = 1 [L472] return (__retres1); [L484] RET, EXPR exists_runnable_thread() [L484] tmp = exists_runnable_thread() [L486] COND TRUE \read(tmp) [L491] COND TRUE m_st == 0 [L492] int tmp_ndt_1; [L493] tmp_ndt_1 = __VERIFIER_nondet_int() [L494] COND FALSE !(\read(tmp_ndt_1)) [L505] COND TRUE t1_st == 0 [L506] int tmp_ndt_2; [L507] tmp_ndt_2 = __VERIFIER_nondet_int() [L508] COND FALSE !(\read(tmp_ndt_2)) [L519] COND TRUE t2_st == 0 [L520] int tmp_ndt_3; [L521] tmp_ndt_3 = __VERIFIER_nondet_int() [L522] COND FALSE !(\read(tmp_ndt_3)) [L533] COND TRUE t3_st == 0 [L534] int tmp_ndt_4; [L535] tmp_ndt_4 = __VERIFIER_nondet_int() [L536] COND FALSE !(\read(tmp_ndt_4)) [L547] COND TRUE t4_st == 0 [L548] int tmp_ndt_5; [L549] tmp_ndt_5 = __VERIFIER_nondet_int() [L550] COND FALSE !(\read(tmp_ndt_5)) [L561] COND TRUE t5_st == 0 [L562] int tmp_ndt_6; [L563] tmp_ndt_6 = __VERIFIER_nondet_int() [L564] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-13 13:56:23,096 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8f323f9-944e-4f13-9133-164c2e8ea6f8/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)