./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.08.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.08.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d0fbb3eaba725aed5c3b8bf09c66f0f1daed4feeee0b9a3792dc033de334e501 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 13:53:28,411 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 13:53:28,478 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 13:53:28,484 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 13:53:28,484 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 13:53:28,509 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 13:53:28,510 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 13:53:28,510 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 13:53:28,511 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 13:53:28,511 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 13:53:28,511 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 13:53:28,511 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 13:53:28,511 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 13:53:28,512 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 13:53:28,512 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 13:53:28,512 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 13:53:28,512 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 13:53:28,512 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 13:53:28,512 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 13:53:28,512 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 13:53:28,512 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 13:53:28,512 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 13:53:28,513 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 13:53:28,513 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 13:53:28,513 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 13:53:28,513 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 13:53:28,513 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 13:53:28,513 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 13:53:28,513 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 13:53:28,513 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 13:53:28,513 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 13:53:28,513 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 13:53:28,514 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 13:53:28,514 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 13:53:28,514 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 13:53:28,514 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 13:53:28,514 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 13:53:28,514 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 13:53:28,515 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 13:53:28,515 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d0fbb3eaba725aed5c3b8bf09c66f0f1daed4feeee0b9a3792dc033de334e501 [2024-11-13 13:53:28,855 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 13:53:28,869 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 13:53:28,871 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 13:53:28,873 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 13:53:28,874 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 13:53:28,876 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/transmitter.08.cil.c Unable to find full path for "g++" [2024-11-13 13:53:30,922 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 13:53:31,321 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 13:53:31,322 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/sv-benchmarks/c/systemc/transmitter.08.cil.c [2024-11-13 13:53:31,335 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/data/b1ab8d102/1c84dcc08191490e9ded646e51ef05eb/FLAGf81338880 [2024-11-13 13:53:31,528 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/data/b1ab8d102/1c84dcc08191490e9ded646e51ef05eb [2024-11-13 13:53:31,534 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 13:53:31,536 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 13:53:31,537 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 13:53:31,537 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 13:53:31,543 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 13:53:31,545 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 01:53:31" (1/1) ... [2024-11-13 13:53:31,546 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2879309d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:53:31, skipping insertion in model container [2024-11-13 13:53:31,546 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 01:53:31" (1/1) ... [2024-11-13 13:53:31,605 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 13:53:31,902 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 13:53:31,917 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 13:53:32,044 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 13:53:32,083 INFO L204 MainTranslator]: Completed translation [2024-11-13 13:53:32,084 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:53:32 WrapperNode [2024-11-13 13:53:32,084 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 13:53:32,085 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 13:53:32,085 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 13:53:32,086 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 13:53:32,093 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:53:32" (1/1) ... [2024-11-13 13:53:32,110 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:53:32" (1/1) ... [2024-11-13 13:53:32,220 INFO L138 Inliner]: procedures = 44, calls = 55, calls flagged for inlining = 50, calls inlined = 147, statements flattened = 2204 [2024-11-13 13:53:32,221 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 13:53:32,222 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 13:53:32,222 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 13:53:32,222 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 13:53:32,234 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:53:32" (1/1) ... [2024-11-13 13:53:32,234 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:53:32" (1/1) ... [2024-11-13 13:53:32,249 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:53:32" (1/1) ... [2024-11-13 13:53:32,286 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 13:53:32,287 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:53:32" (1/1) ... [2024-11-13 13:53:32,287 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:53:32" (1/1) ... [2024-11-13 13:53:32,329 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:53:32" (1/1) ... [2024-11-13 13:53:32,353 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:53:32" (1/1) ... [2024-11-13 13:53:32,357 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:53:32" (1/1) ... [2024-11-13 13:53:32,362 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:53:32" (1/1) ... [2024-11-13 13:53:32,374 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 13:53:32,374 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 13:53:32,375 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 13:53:32,375 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 13:53:32,380 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:53:32" (1/1) ... [2024-11-13 13:53:32,386 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:53:32,406 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:53:32,430 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:53:32,444 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 13:53:32,470 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 13:53:32,470 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 13:53:32,470 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 13:53:32,470 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 13:53:32,580 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 13:53:32,582 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 13:53:34,816 INFO L? ?]: Removed 438 outVars from TransFormulas that were not future-live. [2024-11-13 13:53:34,817 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 13:53:34,857 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 13:53:34,857 INFO L316 CfgBuilder]: Removed 12 assume(true) statements. [2024-11-13 13:53:34,858 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:53:34 BoogieIcfgContainer [2024-11-13 13:53:34,858 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 13:53:34,859 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 13:53:34,859 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 13:53:34,864 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 13:53:34,865 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:53:34,865 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 01:53:31" (1/3) ... [2024-11-13 13:53:34,866 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1010977a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 01:53:34, skipping insertion in model container [2024-11-13 13:53:34,866 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:53:34,866 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:53:32" (2/3) ... [2024-11-13 13:53:34,867 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1010977a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 01:53:34, skipping insertion in model container [2024-11-13 13:53:34,867 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:53:34,867 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:53:34" (3/3) ... [2024-11-13 13:53:34,868 INFO L333 chiAutomizerObserver]: Analyzing ICFG transmitter.08.cil.c [2024-11-13 13:53:34,945 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 13:53:34,946 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 13:53:34,946 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 13:53:34,946 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 13:53:34,946 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 13:53:34,946 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 13:53:34,946 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 13:53:34,946 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 13:53:34,956 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 941 states, 940 states have (on average 1.5127659574468084) internal successors, (1422), 940 states have internal predecessors, (1422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:35,010 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 824 [2024-11-13 13:53:35,010 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:35,011 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:35,022 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:35,022 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:35,022 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 13:53:35,025 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 941 states, 940 states have (on average 1.5127659574468084) internal successors, (1422), 940 states have internal predecessors, (1422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:35,044 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 824 [2024-11-13 13:53:35,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:35,044 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:35,048 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:35,048 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:35,058 INFO L745 eck$LassoCheckResult]: Stem: 126#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 859#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 683#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 855#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 685#L581true assume !(1 == ~m_i~0);~m_st~0 := 2; 193#L581-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 827#L586-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 676#L591-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 652#L596-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 239#L601-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 686#L606-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 413#L611-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 771#L616-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 295#L621-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 713#L838true assume !(0 == ~M_E~0); 422#L838-2true assume !(0 == ~T1_E~0); 25#L843-1true assume !(0 == ~T2_E~0); 83#L848-1true assume !(0 == ~T3_E~0); 435#L853-1true assume !(0 == ~T4_E~0); 287#L858-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 2#L863-1true assume !(0 == ~T6_E~0); 764#L868-1true assume !(0 == ~T7_E~0); 884#L873-1true assume !(0 == ~T8_E~0); 758#L878-1true assume !(0 == ~E_1~0); 722#L883-1true assume !(0 == ~E_2~0); 797#L888-1true assume !(0 == ~E_3~0); 390#L893-1true assume !(0 == ~E_4~0); 798#L898-1true assume 0 == ~E_5~0;~E_5~0 := 1; 928#L903-1true assume !(0 == ~E_6~0); 719#L908-1true assume !(0 == ~E_7~0); 506#L913-1true assume !(0 == ~E_8~0); 30#L918-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 525#L402true assume !(1 == ~m_pc~0); 271#L402-2true is_master_triggered_~__retres1~0#1 := 0; 96#L413true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 575#is_master_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 243#L1035true assume !(0 != activate_threads_~tmp~1#1); 279#L1035-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 710#L421true assume 1 == ~t1_pc~0; 826#L422true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 900#L432true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 315#L1043true assume !(0 != activate_threads_~tmp___0~0#1); 787#L1043-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 912#L440true assume 1 == ~t2_pc~0; 18#L441true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 101#L451true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 209#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 833#L1051true assume !(0 != activate_threads_~tmp___1~0#1); 527#L1051-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 213#L459true assume !(1 == ~t3_pc~0); 702#L459-2true is_transmit3_triggered_~__retres1~3#1 := 0; 782#L470true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 93#L1059true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 934#L1059-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 98#L478true assume 1 == ~t4_pc~0; 394#L479true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 674#L489true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 198#L1067true assume !(0 != activate_threads_~tmp___3~0#1); 50#L1067-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 432#L497true assume !(1 == ~t5_pc~0); 361#L497-2true is_transmit5_triggered_~__retres1~5#1 := 0; 458#L508true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 577#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 788#L1075true assume !(0 != activate_threads_~tmp___4~0#1); 696#L1075-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 891#L516true assume 1 == ~t6_pc~0; 892#L517true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 412#L527true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 199#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 123#L1083true assume !(0 != activate_threads_~tmp___5~0#1); 472#L1083-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 406#L535true assume !(1 == ~t7_pc~0); 802#L535-2true is_transmit7_triggered_~__retres1~7#1 := 0; 470#L546true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 870#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 500#L1091true assume !(0 != activate_threads_~tmp___6~0#1); 493#L1091-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 687#L554true assume 1 == ~t8_pc~0; 438#L555true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 828#L565true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 518#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 171#L1099true assume !(0 != activate_threads_~tmp___7~0#1); 501#L1099-2true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7#L931true assume !(1 == ~M_E~0); 743#L931-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 824#L936-1true assume !(1 == ~T2_E~0); 909#L941-1true assume !(1 == ~T3_E~0); 280#L946-1true assume !(1 == ~T4_E~0); 707#L951-1true assume !(1 == ~T5_E~0); 131#L956-1true assume !(1 == ~T6_E~0); 893#L961-1true assume !(1 == ~T7_E~0); 391#L966-1true assume !(1 == ~T8_E~0); 495#L971-1true assume 1 == ~E_1~0;~E_1~0 := 2; 845#L976-1true assume !(1 == ~E_2~0); 463#L981-1true assume !(1 == ~E_3~0); 283#L986-1true assume !(1 == ~E_4~0); 146#L991-1true assume !(1 == ~E_5~0); 874#L996-1true assume !(1 == ~E_6~0); 776#L1001-1true assume !(1 == ~E_7~0); 431#L1006-1true assume !(1 == ~E_8~0); 708#L1011-1true assume { :end_inline_reset_delta_events } true; 36#L1272-2true [2024-11-13 13:53:35,062 INFO L747 eck$LassoCheckResult]: Loop: 36#L1272-2true assume !false; 427#L1273true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 837#L813-1true assume !true; 524#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 316#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 657#L838-3true assume 0 == ~M_E~0;~M_E~0 := 1; 478#L838-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 808#L843-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 350#L848-3true assume !(0 == ~T3_E~0); 392#L853-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 585#L858-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 452#L863-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 442#L868-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 461#L873-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 160#L878-3true assume 0 == ~E_1~0;~E_1~0 := 1; 19#L883-3true assume 0 == ~E_2~0;~E_2~0 := 1; 671#L888-3true assume !(0 == ~E_3~0); 20#L893-3true assume 0 == ~E_4~0;~E_4~0 := 1; 298#L898-3true assume 0 == ~E_5~0;~E_5~0 := 1; 606#L903-3true assume 0 == ~E_6~0;~E_6~0 := 1; 796#L908-3true assume 0 == ~E_7~0;~E_7~0 := 1; 303#L913-3true assume 0 == ~E_8~0;~E_8~0 := 1; 38#L918-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 902#L402-27true assume 1 == ~m_pc~0; 14#L403-9true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 850#L413-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 471#is_master_triggered_returnLabel#10true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 748#L1035-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 640#L1035-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 673#L421-27true assume 1 == ~t1_pc~0; 504#L422-9true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 832#L432-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 374#is_transmit1_triggered_returnLabel#10true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 777#L1043-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 898#L1043-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 407#L440-27true assume 1 == ~t2_pc~0; 880#L441-9true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 940#L451-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 446#is_transmit2_triggered_returnLabel#10true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 330#L1051-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 420#L1051-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 148#L459-27true assume !(1 == ~t3_pc~0); 662#L459-29true is_transmit3_triggered_~__retres1~3#1 := 0; 847#L470-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 312#is_transmit3_triggered_returnLabel#10true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 405#L1059-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 762#L1059-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 895#L478-27true assume !(1 == ~t4_pc~0); 141#L478-29true is_transmit4_triggered_~__retres1~4#1 := 0; 414#L489-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 252#is_transmit4_triggered_returnLabel#10true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 555#L1067-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 763#L1067-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 607#L497-27true assume 1 == ~t5_pc~0; 840#L498-9true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 166#L508-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 602#is_transmit5_triggered_returnLabel#10true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 134#L1075-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 678#L1075-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 300#L516-27true assume !(1 == ~t6_pc~0); 418#L516-29true is_transmit6_triggered_~__retres1~6#1 := 0; 203#L527-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 752#is_transmit6_triggered_returnLabel#10true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 424#L1083-27true assume !(0 != activate_threads_~tmp___5~0#1); 774#L1083-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 254#L535-27true assume !(1 == ~t7_pc~0); 534#L535-29true is_transmit7_triggered_~__retres1~7#1 := 0; 937#L546-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 180#is_transmit7_triggered_returnLabel#10true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 842#L1091-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 225#L1091-29true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 786#L554-27true assume !(1 == ~t8_pc~0); 26#L554-29true is_transmit8_triggered_~__retres1~8#1 := 0; 100#L565-9true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 550#is_transmit8_triggered_returnLabel#10true activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 335#L1099-27true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 158#L1099-29true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 529#L931-3true assume 1 == ~M_E~0;~M_E~0 := 2; 91#L931-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 223#L936-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 311#L941-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 531#L946-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 168#L951-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 513#L956-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 371#L961-3true assume !(1 == ~T7_E~0); 232#L966-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 726#L971-3true assume 1 == ~E_1~0;~E_1~0 := 2; 411#L976-3true assume 1 == ~E_2~0;~E_2~0 := 2; 35#L981-3true assume 1 == ~E_3~0;~E_3~0 := 2; 159#L986-3true assume 1 == ~E_4~0;~E_4~0 := 2; 29#L991-3true assume 1 == ~E_5~0;~E_5~0 := 2; 482#L996-3true assume 1 == ~E_6~0;~E_6~0 := 2; 611#L1001-3true assume !(1 == ~E_7~0); 215#L1006-3true assume 1 == ~E_8~0;~E_8~0 := 2; 516#L1011-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 48#L634-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 314#L681-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 183#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 792#L1291true assume !(0 == start_simulation_~tmp~3#1); 759#L1291-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 293#L634-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4#L681-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 31#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 730#L1246true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 267#L1253true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 329#stop_simulation_returnLabel#1true start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 556#L1304true assume !(0 != start_simulation_~tmp___0~1#1); 36#L1272-2true [2024-11-13 13:53:35,068 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:35,069 INFO L85 PathProgramCache]: Analyzing trace with hash -1897256038, now seen corresponding path program 1 times [2024-11-13 13:53:35,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:35,083 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [177150742] [2024-11-13 13:53:35,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:35,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:35,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:35,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:35,436 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:35,437 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [177150742] [2024-11-13 13:53:35,437 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [177150742] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:35,438 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:35,438 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:35,439 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [304965043] [2024-11-13 13:53:35,440 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:35,443 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:35,444 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:35,444 INFO L85 PathProgramCache]: Analyzing trace with hash -118542582, now seen corresponding path program 1 times [2024-11-13 13:53:35,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:35,445 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [925858027] [2024-11-13 13:53:35,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:35,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:35,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:35,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:35,515 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:35,515 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [925858027] [2024-11-13 13:53:35,516 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [925858027] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:35,517 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:35,517 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:53:35,517 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2107165624] [2024-11-13 13:53:35,517 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:35,518 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:35,520 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:35,551 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:53:35,552 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:53:35,557 INFO L87 Difference]: Start difference. First operand has 941 states, 940 states have (on average 1.5127659574468084) internal successors, (1422), 940 states have internal predecessors, (1422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:35,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:35,667 INFO L93 Difference]: Finished difference Result 939 states and 1394 transitions. [2024-11-13 13:53:35,673 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 939 states and 1394 transitions. [2024-11-13 13:53:35,694 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-11-13 13:53:35,715 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 939 states to 933 states and 1388 transitions. [2024-11-13 13:53:35,716 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-11-13 13:53:35,720 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-11-13 13:53:35,721 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1388 transitions. [2024-11-13 13:53:35,730 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:35,730 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1388 transitions. [2024-11-13 13:53:35,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1388 transitions. [2024-11-13 13:53:35,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-11-13 13:53:35,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.487674169346195) internal successors, (1388), 932 states have internal predecessors, (1388), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:35,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1388 transitions. [2024-11-13 13:53:35,832 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1388 transitions. [2024-11-13 13:53:35,833 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:53:35,837 INFO L424 stractBuchiCegarLoop]: Abstraction has 933 states and 1388 transitions. [2024-11-13 13:53:35,841 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 13:53:35,841 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1388 transitions. [2024-11-13 13:53:35,852 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-11-13 13:53:35,853 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:35,854 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:35,860 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:35,860 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:35,861 INFO L745 eck$LassoCheckResult]: Stem: 2139#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2766#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2767#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2768#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 2258#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2259#L586-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2764#L591-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2760#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2330#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2331#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2565#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2566#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2414#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2415#L838 assume !(0 == ~M_E~0); 2573#L838-2 assume !(0 == ~T1_E~0); 1938#L843-1 assume !(0 == ~T2_E~0); 1939#L848-1 assume !(0 == ~T3_E~0); 2059#L853-1 assume !(0 == ~T4_E~0); 2401#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1889#L863-1 assume !(0 == ~T6_E~0); 1890#L868-1 assume !(0 == ~T7_E~0); 2796#L873-1 assume !(0 == ~T8_E~0); 2794#L878-1 assume !(0 == ~E_1~0); 2785#L883-1 assume !(0 == ~E_2~0); 2786#L888-1 assume !(0 == ~E_3~0); 2534#L893-1 assume !(0 == ~E_4~0); 2535#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2806#L903-1 assume !(0 == ~E_6~0); 2783#L908-1 assume !(0 == ~E_7~0); 2664#L913-1 assume !(0 == ~E_8~0); 1950#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1951#L402 assume !(1 == ~m_pc~0); 2162#L402-2 is_master_triggered_~__retres1~0#1 := 0; 2083#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2084#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2336#L1035 assume !(0 != activate_threads_~tmp~1#1); 2337#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2389#L421 assume 1 == ~t1_pc~0; 2779#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2797#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1953#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1954#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 2443#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2804#L440 assume 1 == ~t2_pc~0; 1922#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1923#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2093#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2284#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 2679#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2287#L459 assume !(1 == ~t3_pc~0); 2288#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2777#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1911#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1912#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2078#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2087#L478 assume 1 == ~t4_pc~0; 2088#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2539#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2031#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2032#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1992#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1993#L497 assume !(1 == ~t5_pc~0); 2042#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2043#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2610#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2716#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 2773#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2774#L516 assume 1 == ~t6_pc~0; 2820#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2564#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2267#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2133#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 2134#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2553#L535 assume !(1 == ~t7_pc~0); 2554#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2624#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2625#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2656#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 2646#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2647#L554 assume 1 == ~t8_pc~0; 2589#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1914#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2672#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2221#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 2222#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1900#L931 assume !(1 == ~M_E~0); 1901#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2792#L936-1 assume !(1 == ~T2_E~0); 2811#L941-1 assume !(1 == ~T3_E~0); 2390#L946-1 assume !(1 == ~T4_E~0); 2391#L951-1 assume !(1 == ~T5_E~0); 2148#L956-1 assume !(1 == ~T6_E~0); 2149#L961-1 assume !(1 == ~T7_E~0); 2536#L966-1 assume !(1 == ~T8_E~0); 2537#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2649#L976-1 assume !(1 == ~E_2~0); 2614#L981-1 assume !(1 == ~E_3~0); 2394#L986-1 assume !(1 == ~E_4~0); 2175#L991-1 assume !(1 == ~E_5~0); 2176#L996-1 assume !(1 == ~E_6~0); 2801#L1001-1 assume !(1 == ~E_7~0); 2584#L1006-1 assume !(1 == ~E_8~0); 2585#L1011-1 assume { :end_inline_reset_delta_events } true; 1961#L1272-2 [2024-11-13 13:53:35,862 INFO L747 eck$LassoCheckResult]: Loop: 1961#L1272-2 assume !false; 1962#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2198#L813-1 assume !false; 2734#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2735#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1965#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2303#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2304#L696 assume !(0 != eval_~tmp~0#1); 2677#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2444#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2445#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2633#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2634#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2487#L848-3 assume !(0 == ~T3_E~0); 2488#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2538#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2603#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2593#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2594#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2202#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1925#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1926#L888-3 assume !(0 == ~E_3~0); 1927#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1928#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2420#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2736#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2428#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1966#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1967#L402-27 assume 1 == ~m_pc~0; 1915#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1916#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2626#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2627#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2753#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2754#L421-27 assume !(1 == ~t1_pc~0); 2192#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2193#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2512#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2513#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2802#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2556#L440-27 assume 1 == ~t2_pc~0; 2557#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2731#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2598#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2463#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2464#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2178#L459-27 assume !(1 == ~t3_pc~0); 2179#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 2619#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2440#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2441#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2552#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2795#L478-27 assume !(1 == ~t4_pc~0); 2167#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 2168#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2351#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2352#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2701#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2737#L497-27 assume 1 == ~t5_pc~0; 2738#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2211#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2212#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2154#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2155#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2422#L516-27 assume !(1 == ~t6_pc~0); 2423#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2275#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2276#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2575#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 2576#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2355#L535-27 assume 1 == ~t7_pc~0; 2356#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2685#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2235#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2236#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2306#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2307#L554-27 assume !(1 == ~t8_pc~0); 1940#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1941#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2092#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2472#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2199#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2200#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2074#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2075#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2305#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2439#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2215#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2216#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2510#L961-3 assume !(1 == ~T7_E~0); 2315#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2316#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2563#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1959#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1960#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1948#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1949#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2639#L1001-3 assume !(1 == ~E_7~0); 2292#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2293#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1987#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1988#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2241#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2242#L1291 assume !(0 == start_simulation_~tmp~3#1); 2507#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2410#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1893#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1894#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1952#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2376#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2377#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2462#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1961#L1272-2 [2024-11-13 13:53:35,864 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:35,864 INFO L85 PathProgramCache]: Analyzing trace with hash 500214492, now seen corresponding path program 1 times [2024-11-13 13:53:35,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:35,865 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2051643113] [2024-11-13 13:53:35,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:35,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:35,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:36,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:36,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:36,033 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2051643113] [2024-11-13 13:53:36,033 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2051643113] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:36,033 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:36,035 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:36,036 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1298329164] [2024-11-13 13:53:36,036 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:36,036 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:36,037 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:36,037 INFO L85 PathProgramCache]: Analyzing trace with hash 1780923630, now seen corresponding path program 1 times [2024-11-13 13:53:36,037 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:36,037 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1006209909] [2024-11-13 13:53:36,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:36,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:36,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:36,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:36,238 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:36,238 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1006209909] [2024-11-13 13:53:36,239 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1006209909] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:36,239 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:36,239 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:36,239 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1790883691] [2024-11-13 13:53:36,239 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:36,239 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:36,240 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:36,240 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:53:36,240 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:53:36,242 INFO L87 Difference]: Start difference. First operand 933 states and 1388 transitions. cyclomatic complexity: 456 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:36,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:36,291 INFO L93 Difference]: Finished difference Result 933 states and 1387 transitions. [2024-11-13 13:53:36,291 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1387 transitions. [2024-11-13 13:53:36,301 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-11-13 13:53:36,310 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1387 transitions. [2024-11-13 13:53:36,311 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-11-13 13:53:36,313 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-11-13 13:53:36,314 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1387 transitions. [2024-11-13 13:53:36,318 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:36,319 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1387 transitions. [2024-11-13 13:53:36,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1387 transitions. [2024-11-13 13:53:36,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-11-13 13:53:36,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4866023579849947) internal successors, (1387), 932 states have internal predecessors, (1387), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:36,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1387 transitions. [2024-11-13 13:53:36,360 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1387 transitions. [2024-11-13 13:53:36,361 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:53:36,361 INFO L424 stractBuchiCegarLoop]: Abstraction has 933 states and 1387 transitions. [2024-11-13 13:53:36,362 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 13:53:36,362 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1387 transitions. [2024-11-13 13:53:36,372 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-11-13 13:53:36,373 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:36,373 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:36,378 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:36,378 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:36,381 INFO L745 eck$LassoCheckResult]: Stem: 4012#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 4013#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4639#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4640#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4641#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 4131#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4132#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4637#L591-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4633#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4203#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4204#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4438#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4439#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4287#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4288#L838 assume !(0 == ~M_E~0); 4446#L838-2 assume !(0 == ~T1_E~0); 3811#L843-1 assume !(0 == ~T2_E~0); 3812#L848-1 assume !(0 == ~T3_E~0); 3932#L853-1 assume !(0 == ~T4_E~0); 4274#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3762#L863-1 assume !(0 == ~T6_E~0); 3763#L868-1 assume !(0 == ~T7_E~0); 4669#L873-1 assume !(0 == ~T8_E~0); 4667#L878-1 assume !(0 == ~E_1~0); 4658#L883-1 assume !(0 == ~E_2~0); 4659#L888-1 assume !(0 == ~E_3~0); 4407#L893-1 assume !(0 == ~E_4~0); 4408#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4679#L903-1 assume !(0 == ~E_6~0); 4656#L908-1 assume !(0 == ~E_7~0); 4537#L913-1 assume !(0 == ~E_8~0); 3823#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3824#L402 assume !(1 == ~m_pc~0); 4035#L402-2 is_master_triggered_~__retres1~0#1 := 0; 3956#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3957#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4209#L1035 assume !(0 != activate_threads_~tmp~1#1); 4210#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4262#L421 assume 1 == ~t1_pc~0; 4652#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4670#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3826#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3827#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 4316#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4677#L440 assume 1 == ~t2_pc~0; 3795#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3796#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3966#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4157#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 4552#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4160#L459 assume !(1 == ~t3_pc~0); 4161#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4650#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3784#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3785#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3951#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3960#L478 assume 1 == ~t4_pc~0; 3961#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4412#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3904#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3905#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 3865#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3866#L497 assume !(1 == ~t5_pc~0); 3915#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3916#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4483#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4589#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 4646#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4647#L516 assume 1 == ~t6_pc~0; 4693#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4437#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4140#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4006#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 4007#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4426#L535 assume !(1 == ~t7_pc~0); 4427#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4497#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4498#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4529#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 4519#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4520#L554 assume 1 == ~t8_pc~0; 4462#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3787#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4545#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4094#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 4095#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3773#L931 assume !(1 == ~M_E~0); 3774#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4665#L936-1 assume !(1 == ~T2_E~0); 4684#L941-1 assume !(1 == ~T3_E~0); 4263#L946-1 assume !(1 == ~T4_E~0); 4264#L951-1 assume !(1 == ~T5_E~0); 4021#L956-1 assume !(1 == ~T6_E~0); 4022#L961-1 assume !(1 == ~T7_E~0); 4409#L966-1 assume !(1 == ~T8_E~0); 4410#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4522#L976-1 assume !(1 == ~E_2~0); 4487#L981-1 assume !(1 == ~E_3~0); 4267#L986-1 assume !(1 == ~E_4~0); 4048#L991-1 assume !(1 == ~E_5~0); 4049#L996-1 assume !(1 == ~E_6~0); 4674#L1001-1 assume !(1 == ~E_7~0); 4457#L1006-1 assume !(1 == ~E_8~0); 4458#L1011-1 assume { :end_inline_reset_delta_events } true; 3834#L1272-2 [2024-11-13 13:53:36,382 INFO L747 eck$LassoCheckResult]: Loop: 3834#L1272-2 assume !false; 3835#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4071#L813-1 assume !false; 4607#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4608#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3838#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4176#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4177#L696 assume !(0 != eval_~tmp~0#1); 4550#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4317#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4318#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4506#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4507#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4360#L848-3 assume !(0 == ~T3_E~0); 4361#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4411#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4476#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4466#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4467#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4075#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3798#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3799#L888-3 assume !(0 == ~E_3~0); 3800#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3801#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4293#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4609#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4301#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3839#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3840#L402-27 assume 1 == ~m_pc~0; 3788#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3789#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4499#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4500#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4626#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4627#L421-27 assume !(1 == ~t1_pc~0); 4065#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 4066#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4385#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4386#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4675#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4429#L440-27 assume 1 == ~t2_pc~0; 4430#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4604#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4471#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4336#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4337#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4051#L459-27 assume !(1 == ~t3_pc~0); 4052#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 4492#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4313#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4314#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4425#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4668#L478-27 assume !(1 == ~t4_pc~0); 4040#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 4041#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4224#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4225#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4574#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4610#L497-27 assume 1 == ~t5_pc~0; 4611#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4084#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4085#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4027#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4028#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4295#L516-27 assume !(1 == ~t6_pc~0); 4296#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 4148#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4149#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4448#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 4449#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4228#L535-27 assume 1 == ~t7_pc~0; 4229#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4558#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4108#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4109#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4179#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4180#L554-27 assume !(1 == ~t8_pc~0); 3813#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 3814#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3965#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4345#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4072#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4073#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3947#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3948#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4178#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4312#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4088#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4089#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4383#L961-3 assume !(1 == ~T7_E~0); 4188#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4189#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4436#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3832#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3833#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3821#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3822#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4512#L1001-3 assume !(1 == ~E_7~0); 4165#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4166#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3860#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3861#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4114#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 4115#L1291 assume !(0 == start_simulation_~tmp~3#1); 4380#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4283#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3766#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3767#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 3825#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4249#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4250#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 4335#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 3834#L1272-2 [2024-11-13 13:53:36,382 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:36,383 INFO L85 PathProgramCache]: Analyzing trace with hash -1888349538, now seen corresponding path program 1 times [2024-11-13 13:53:36,383 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:36,383 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1372061262] [2024-11-13 13:53:36,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:36,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:36,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:36,522 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:36,522 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:36,522 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1372061262] [2024-11-13 13:53:36,522 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1372061262] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:36,522 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:36,522 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:36,522 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1071931048] [2024-11-13 13:53:36,522 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:36,523 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:36,523 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:36,523 INFO L85 PathProgramCache]: Analyzing trace with hash 1780923630, now seen corresponding path program 2 times [2024-11-13 13:53:36,523 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:36,523 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1102363836] [2024-11-13 13:53:36,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:36,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:36,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:36,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:36,695 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:36,695 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1102363836] [2024-11-13 13:53:36,695 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1102363836] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:36,696 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:36,696 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:36,696 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1751755619] [2024-11-13 13:53:36,696 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:36,696 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:36,697 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:36,697 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:53:36,697 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:53:36,698 INFO L87 Difference]: Start difference. First operand 933 states and 1387 transitions. cyclomatic complexity: 455 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:36,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:36,735 INFO L93 Difference]: Finished difference Result 933 states and 1386 transitions. [2024-11-13 13:53:36,735 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1386 transitions. [2024-11-13 13:53:36,742 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-11-13 13:53:36,750 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1386 transitions. [2024-11-13 13:53:36,752 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-11-13 13:53:36,755 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-11-13 13:53:36,756 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1386 transitions. [2024-11-13 13:53:36,758 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:36,761 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1386 transitions. [2024-11-13 13:53:36,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1386 transitions. [2024-11-13 13:53:36,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-11-13 13:53:36,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4855305466237942) internal successors, (1386), 932 states have internal predecessors, (1386), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:36,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1386 transitions. [2024-11-13 13:53:36,795 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1386 transitions. [2024-11-13 13:53:36,795 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:53:36,796 INFO L424 stractBuchiCegarLoop]: Abstraction has 933 states and 1386 transitions. [2024-11-13 13:53:36,796 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 13:53:36,796 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1386 transitions. [2024-11-13 13:53:36,804 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-11-13 13:53:36,804 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:36,804 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:36,806 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:36,810 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:36,811 INFO L745 eck$LassoCheckResult]: Stem: 5885#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 5886#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6512#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6513#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6514#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 6004#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6005#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6510#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6506#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6076#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6077#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6311#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6312#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6160#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6161#L838 assume !(0 == ~M_E~0); 6319#L838-2 assume !(0 == ~T1_E~0); 5684#L843-1 assume !(0 == ~T2_E~0); 5685#L848-1 assume !(0 == ~T3_E~0); 5805#L853-1 assume !(0 == ~T4_E~0); 6147#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5635#L863-1 assume !(0 == ~T6_E~0); 5636#L868-1 assume !(0 == ~T7_E~0); 6542#L873-1 assume !(0 == ~T8_E~0); 6540#L878-1 assume !(0 == ~E_1~0); 6531#L883-1 assume !(0 == ~E_2~0); 6532#L888-1 assume !(0 == ~E_3~0); 6280#L893-1 assume !(0 == ~E_4~0); 6281#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6552#L903-1 assume !(0 == ~E_6~0); 6529#L908-1 assume !(0 == ~E_7~0); 6410#L913-1 assume !(0 == ~E_8~0); 5696#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5697#L402 assume !(1 == ~m_pc~0); 5908#L402-2 is_master_triggered_~__retres1~0#1 := 0; 5829#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5830#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6082#L1035 assume !(0 != activate_threads_~tmp~1#1); 6083#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6135#L421 assume 1 == ~t1_pc~0; 6525#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6543#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5699#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5700#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 6189#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6550#L440 assume 1 == ~t2_pc~0; 5668#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5669#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5839#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6030#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 6425#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6033#L459 assume !(1 == ~t3_pc~0); 6034#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6523#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5657#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5658#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5824#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5833#L478 assume 1 == ~t4_pc~0; 5834#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6285#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5777#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5778#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 5738#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5739#L497 assume !(1 == ~t5_pc~0); 5788#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5789#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6356#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6462#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 6519#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6520#L516 assume 1 == ~t6_pc~0; 6566#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6310#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6013#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5879#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 5880#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6299#L535 assume !(1 == ~t7_pc~0); 6300#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6370#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6371#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6402#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 6392#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6393#L554 assume 1 == ~t8_pc~0; 6335#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5660#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6418#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5967#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 5968#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5646#L931 assume !(1 == ~M_E~0); 5647#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6538#L936-1 assume !(1 == ~T2_E~0); 6557#L941-1 assume !(1 == ~T3_E~0); 6136#L946-1 assume !(1 == ~T4_E~0); 6137#L951-1 assume !(1 == ~T5_E~0); 5894#L956-1 assume !(1 == ~T6_E~0); 5895#L961-1 assume !(1 == ~T7_E~0); 6282#L966-1 assume !(1 == ~T8_E~0); 6283#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6395#L976-1 assume !(1 == ~E_2~0); 6360#L981-1 assume !(1 == ~E_3~0); 6140#L986-1 assume !(1 == ~E_4~0); 5921#L991-1 assume !(1 == ~E_5~0); 5922#L996-1 assume !(1 == ~E_6~0); 6547#L1001-1 assume !(1 == ~E_7~0); 6330#L1006-1 assume !(1 == ~E_8~0); 6331#L1011-1 assume { :end_inline_reset_delta_events } true; 5707#L1272-2 [2024-11-13 13:53:36,811 INFO L747 eck$LassoCheckResult]: Loop: 5707#L1272-2 assume !false; 5708#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5944#L813-1 assume !false; 6480#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6481#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5711#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6049#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6050#L696 assume !(0 != eval_~tmp~0#1); 6423#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6190#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6191#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6379#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6380#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6233#L848-3 assume !(0 == ~T3_E~0); 6234#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6284#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6349#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6339#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6340#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5948#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5671#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5672#L888-3 assume !(0 == ~E_3~0); 5673#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5674#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6166#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6482#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6174#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5712#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5713#L402-27 assume 1 == ~m_pc~0; 5661#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5662#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6372#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6373#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6499#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6500#L421-27 assume !(1 == ~t1_pc~0); 5938#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 5939#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6258#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6259#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6548#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6302#L440-27 assume !(1 == ~t2_pc~0); 6304#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 6477#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6344#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6209#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6210#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5924#L459-27 assume !(1 == ~t3_pc~0); 5925#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 6365#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6186#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6187#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6298#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6541#L478-27 assume 1 == ~t4_pc~0; 6560#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5914#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6097#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6098#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6447#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6483#L497-27 assume 1 == ~t5_pc~0; 6484#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5957#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5958#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5900#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5901#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6168#L516-27 assume !(1 == ~t6_pc~0); 6169#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 6021#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6022#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6321#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 6322#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6101#L535-27 assume 1 == ~t7_pc~0; 6102#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6431#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5981#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5982#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6052#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6053#L554-27 assume !(1 == ~t8_pc~0); 5686#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 5687#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5838#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6218#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5945#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5946#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5820#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5821#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6051#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6185#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5961#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5962#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6256#L961-3 assume !(1 == ~T7_E~0); 6061#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6062#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6309#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5705#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5706#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5694#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5695#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6385#L1001-3 assume !(1 == ~E_7~0); 6038#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6039#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 5733#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5734#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 5987#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5988#L1291 assume !(0 == start_simulation_~tmp~3#1); 6253#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6156#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5639#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 5640#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 5698#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6122#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6123#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 6208#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 5707#L1272-2 [2024-11-13 13:53:36,811 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:36,812 INFO L85 PathProgramCache]: Analyzing trace with hash 805546652, now seen corresponding path program 1 times [2024-11-13 13:53:36,812 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:36,812 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1953425769] [2024-11-13 13:53:36,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:36,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:36,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:36,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:36,879 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:36,879 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1953425769] [2024-11-13 13:53:36,880 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1953425769] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:36,880 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:36,880 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:36,880 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [881711487] [2024-11-13 13:53:36,880 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:36,880 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:36,881 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:36,881 INFO L85 PathProgramCache]: Analyzing trace with hash -1092974994, now seen corresponding path program 1 times [2024-11-13 13:53:36,881 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:36,882 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899595686] [2024-11-13 13:53:36,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:36,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:36,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:36,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:36,993 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:36,993 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [899595686] [2024-11-13 13:53:36,993 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [899595686] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:36,994 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:36,994 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:36,994 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [509383302] [2024-11-13 13:53:36,994 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:36,994 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:36,995 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:36,995 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:53:36,995 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:53:36,995 INFO L87 Difference]: Start difference. First operand 933 states and 1386 transitions. cyclomatic complexity: 454 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:37,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:37,028 INFO L93 Difference]: Finished difference Result 933 states and 1385 transitions. [2024-11-13 13:53:37,028 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1385 transitions. [2024-11-13 13:53:37,035 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-11-13 13:53:37,041 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1385 transitions. [2024-11-13 13:53:37,041 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-11-13 13:53:37,042 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-11-13 13:53:37,042 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1385 transitions. [2024-11-13 13:53:37,044 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:37,044 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1385 transitions. [2024-11-13 13:53:37,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1385 transitions. [2024-11-13 13:53:37,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-11-13 13:53:37,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4844587352625938) internal successors, (1385), 932 states have internal predecessors, (1385), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:37,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1385 transitions. [2024-11-13 13:53:37,069 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1385 transitions. [2024-11-13 13:53:37,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:53:37,070 INFO L424 stractBuchiCegarLoop]: Abstraction has 933 states and 1385 transitions. [2024-11-13 13:53:37,070 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 13:53:37,070 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1385 transitions. [2024-11-13 13:53:37,076 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-11-13 13:53:37,076 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:37,077 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:37,078 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:37,082 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:37,082 INFO L745 eck$LassoCheckResult]: Stem: 7758#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 7759#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 8385#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8386#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8387#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 7877#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7878#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8383#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8379#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7949#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7950#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8184#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8185#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8033#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8034#L838 assume !(0 == ~M_E~0); 8192#L838-2 assume !(0 == ~T1_E~0); 7557#L843-1 assume !(0 == ~T2_E~0); 7558#L848-1 assume !(0 == ~T3_E~0); 7678#L853-1 assume !(0 == ~T4_E~0); 8020#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7508#L863-1 assume !(0 == ~T6_E~0); 7509#L868-1 assume !(0 == ~T7_E~0); 8415#L873-1 assume !(0 == ~T8_E~0); 8413#L878-1 assume !(0 == ~E_1~0); 8404#L883-1 assume !(0 == ~E_2~0); 8405#L888-1 assume !(0 == ~E_3~0); 8153#L893-1 assume !(0 == ~E_4~0); 8154#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 8425#L903-1 assume !(0 == ~E_6~0); 8402#L908-1 assume !(0 == ~E_7~0); 8283#L913-1 assume !(0 == ~E_8~0); 7569#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7570#L402 assume !(1 == ~m_pc~0); 7781#L402-2 is_master_triggered_~__retres1~0#1 := 0; 7702#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7703#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7955#L1035 assume !(0 != activate_threads_~tmp~1#1); 7956#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8008#L421 assume 1 == ~t1_pc~0; 8398#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8416#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7572#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7573#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 8062#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8423#L440 assume 1 == ~t2_pc~0; 7541#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7542#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7712#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7903#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 8298#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7906#L459 assume !(1 == ~t3_pc~0); 7907#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8396#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7530#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7531#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7697#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7706#L478 assume 1 == ~t4_pc~0; 7707#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8158#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7650#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7651#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 7611#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7612#L497 assume !(1 == ~t5_pc~0); 7661#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7662#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8229#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8335#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 8392#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8393#L516 assume 1 == ~t6_pc~0; 8439#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8183#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7886#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7752#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 7753#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8172#L535 assume !(1 == ~t7_pc~0); 8173#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8243#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8244#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8275#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 8265#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8266#L554 assume 1 == ~t8_pc~0; 8208#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7533#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8291#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7840#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 7841#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7519#L931 assume !(1 == ~M_E~0); 7520#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8411#L936-1 assume !(1 == ~T2_E~0); 8430#L941-1 assume !(1 == ~T3_E~0); 8009#L946-1 assume !(1 == ~T4_E~0); 8010#L951-1 assume !(1 == ~T5_E~0); 7767#L956-1 assume !(1 == ~T6_E~0); 7768#L961-1 assume !(1 == ~T7_E~0); 8155#L966-1 assume !(1 == ~T8_E~0); 8156#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 8268#L976-1 assume !(1 == ~E_2~0); 8233#L981-1 assume !(1 == ~E_3~0); 8013#L986-1 assume !(1 == ~E_4~0); 7794#L991-1 assume !(1 == ~E_5~0); 7795#L996-1 assume !(1 == ~E_6~0); 8420#L1001-1 assume !(1 == ~E_7~0); 8203#L1006-1 assume !(1 == ~E_8~0); 8204#L1011-1 assume { :end_inline_reset_delta_events } true; 7580#L1272-2 [2024-11-13 13:53:37,083 INFO L747 eck$LassoCheckResult]: Loop: 7580#L1272-2 assume !false; 7581#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7817#L813-1 assume !false; 8353#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8354#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7584#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7922#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7923#L696 assume !(0 != eval_~tmp~0#1); 8296#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8063#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8064#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8252#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8253#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8106#L848-3 assume !(0 == ~T3_E~0); 8107#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8157#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8222#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8212#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8213#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7821#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7544#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7545#L888-3 assume !(0 == ~E_3~0); 7546#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7547#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8039#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8355#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8047#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7585#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7586#L402-27 assume !(1 == ~m_pc~0); 7536#L402-29 is_master_triggered_~__retres1~0#1 := 0; 7535#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8245#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8246#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8372#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8373#L421-27 assume !(1 == ~t1_pc~0); 7811#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 7812#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8131#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8132#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8421#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8175#L440-27 assume 1 == ~t2_pc~0; 8176#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8350#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8217#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8082#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8083#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7797#L459-27 assume !(1 == ~t3_pc~0); 7798#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 8238#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8059#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8060#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8171#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8414#L478-27 assume 1 == ~t4_pc~0; 8433#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7787#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7970#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7971#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8320#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8356#L497-27 assume 1 == ~t5_pc~0; 8357#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7830#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7831#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7773#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7774#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8041#L516-27 assume !(1 == ~t6_pc~0); 8042#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 7894#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7895#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8194#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 8195#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7974#L535-27 assume 1 == ~t7_pc~0; 7975#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8304#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7854#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7855#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7925#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7926#L554-27 assume 1 == ~t8_pc~0; 8128#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7560#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7711#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8091#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7818#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7819#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7693#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7694#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7924#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8058#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7834#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7835#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8129#L961-3 assume !(1 == ~T7_E~0); 7934#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7935#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8182#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7578#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7579#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7567#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7568#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8258#L1001-3 assume !(1 == ~E_7~0); 7911#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7912#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 7606#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7607#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7860#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 7861#L1291 assume !(0 == start_simulation_~tmp~3#1); 8126#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8029#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7512#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7513#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 7571#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7995#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7996#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8081#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 7580#L1272-2 [2024-11-13 13:53:37,083 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:37,084 INFO L85 PathProgramCache]: Analyzing trace with hash 1862277854, now seen corresponding path program 1 times [2024-11-13 13:53:37,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:37,084 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1064109397] [2024-11-13 13:53:37,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:37,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:37,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:37,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:37,159 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:37,159 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1064109397] [2024-11-13 13:53:37,159 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1064109397] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:37,159 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:37,159 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:37,159 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1716034354] [2024-11-13 13:53:37,159 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:37,160 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:37,160 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:37,160 INFO L85 PathProgramCache]: Analyzing trace with hash 702351055, now seen corresponding path program 1 times [2024-11-13 13:53:37,160 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:37,161 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1116414417] [2024-11-13 13:53:37,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:37,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:37,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:37,243 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:37,244 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:37,244 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1116414417] [2024-11-13 13:53:37,244 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1116414417] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:37,244 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:37,245 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:37,245 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [855808163] [2024-11-13 13:53:37,245 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:37,245 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:37,245 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:37,246 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:53:37,246 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:53:37,246 INFO L87 Difference]: Start difference. First operand 933 states and 1385 transitions. cyclomatic complexity: 453 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:37,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:37,286 INFO L93 Difference]: Finished difference Result 933 states and 1384 transitions. [2024-11-13 13:53:37,286 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1384 transitions. [2024-11-13 13:53:37,293 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-11-13 13:53:37,299 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1384 transitions. [2024-11-13 13:53:37,300 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-11-13 13:53:37,301 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-11-13 13:53:37,301 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1384 transitions. [2024-11-13 13:53:37,303 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:37,303 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1384 transitions. [2024-11-13 13:53:37,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1384 transitions. [2024-11-13 13:53:37,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-11-13 13:53:37,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4833869239013933) internal successors, (1384), 932 states have internal predecessors, (1384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:37,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1384 transitions. [2024-11-13 13:53:37,324 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1384 transitions. [2024-11-13 13:53:37,325 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:53:37,325 INFO L424 stractBuchiCegarLoop]: Abstraction has 933 states and 1384 transitions. [2024-11-13 13:53:37,326 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 13:53:37,327 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1384 transitions. [2024-11-13 13:53:37,333 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-11-13 13:53:37,333 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:37,333 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:37,335 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:37,335 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:37,336 INFO L745 eck$LassoCheckResult]: Stem: 9631#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 9632#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10258#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10259#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10260#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 9750#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9751#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10256#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10252#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9822#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9823#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10057#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10058#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9906#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9907#L838 assume !(0 == ~M_E~0); 10065#L838-2 assume !(0 == ~T1_E~0); 9430#L843-1 assume !(0 == ~T2_E~0); 9431#L848-1 assume !(0 == ~T3_E~0); 9551#L853-1 assume !(0 == ~T4_E~0); 9893#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9381#L863-1 assume !(0 == ~T6_E~0); 9382#L868-1 assume !(0 == ~T7_E~0); 10288#L873-1 assume !(0 == ~T8_E~0); 10286#L878-1 assume !(0 == ~E_1~0); 10277#L883-1 assume !(0 == ~E_2~0); 10278#L888-1 assume !(0 == ~E_3~0); 10026#L893-1 assume !(0 == ~E_4~0); 10027#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 10298#L903-1 assume !(0 == ~E_6~0); 10275#L908-1 assume !(0 == ~E_7~0); 10156#L913-1 assume !(0 == ~E_8~0); 9442#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9443#L402 assume !(1 == ~m_pc~0); 9654#L402-2 is_master_triggered_~__retres1~0#1 := 0; 9575#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9576#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9828#L1035 assume !(0 != activate_threads_~tmp~1#1); 9829#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9881#L421 assume 1 == ~t1_pc~0; 10271#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10289#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9445#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9446#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 9935#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10296#L440 assume 1 == ~t2_pc~0; 9414#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9415#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9585#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9776#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 10171#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9779#L459 assume !(1 == ~t3_pc~0); 9780#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10269#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9403#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9404#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9570#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9579#L478 assume 1 == ~t4_pc~0; 9580#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10031#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9523#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9524#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 9484#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9485#L497 assume !(1 == ~t5_pc~0); 9534#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9535#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10102#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10208#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 10265#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10266#L516 assume 1 == ~t6_pc~0; 10312#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10056#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9759#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9625#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 9626#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10045#L535 assume !(1 == ~t7_pc~0); 10046#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10116#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10117#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10148#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 10138#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10139#L554 assume 1 == ~t8_pc~0; 10081#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9406#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10164#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9713#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 9714#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9392#L931 assume !(1 == ~M_E~0); 9393#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10284#L936-1 assume !(1 == ~T2_E~0); 10303#L941-1 assume !(1 == ~T3_E~0); 9882#L946-1 assume !(1 == ~T4_E~0); 9883#L951-1 assume !(1 == ~T5_E~0); 9640#L956-1 assume !(1 == ~T6_E~0); 9641#L961-1 assume !(1 == ~T7_E~0); 10028#L966-1 assume !(1 == ~T8_E~0); 10029#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 10141#L976-1 assume !(1 == ~E_2~0); 10106#L981-1 assume !(1 == ~E_3~0); 9886#L986-1 assume !(1 == ~E_4~0); 9667#L991-1 assume !(1 == ~E_5~0); 9668#L996-1 assume !(1 == ~E_6~0); 10293#L1001-1 assume !(1 == ~E_7~0); 10076#L1006-1 assume !(1 == ~E_8~0); 10077#L1011-1 assume { :end_inline_reset_delta_events } true; 9453#L1272-2 [2024-11-13 13:53:37,336 INFO L747 eck$LassoCheckResult]: Loop: 9453#L1272-2 assume !false; 9454#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9690#L813-1 assume !false; 10226#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10227#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9457#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9795#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9796#L696 assume !(0 != eval_~tmp~0#1); 10169#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9936#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9937#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10125#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10126#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9979#L848-3 assume !(0 == ~T3_E~0); 9980#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10030#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10095#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10085#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10086#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9694#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9417#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9418#L888-3 assume !(0 == ~E_3~0); 9419#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9420#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9912#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10228#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9920#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9458#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9459#L402-27 assume !(1 == ~m_pc~0); 9409#L402-29 is_master_triggered_~__retres1~0#1 := 0; 9408#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10118#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10119#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10245#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10246#L421-27 assume !(1 == ~t1_pc~0); 9684#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 9685#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10004#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10005#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10294#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10048#L440-27 assume 1 == ~t2_pc~0; 10049#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10223#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10090#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9955#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9956#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9670#L459-27 assume !(1 == ~t3_pc~0); 9671#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 10111#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9932#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9933#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10044#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10287#L478-27 assume 1 == ~t4_pc~0; 10306#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9660#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9843#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9844#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10193#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10229#L497-27 assume 1 == ~t5_pc~0; 10230#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9703#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9704#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9646#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9647#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9914#L516-27 assume !(1 == ~t6_pc~0); 9915#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 9767#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9768#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10067#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 10068#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9847#L535-27 assume 1 == ~t7_pc~0; 9848#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10177#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9727#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9728#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9798#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9799#L554-27 assume 1 == ~t8_pc~0; 10001#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9433#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9584#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9964#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9691#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9692#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9566#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9567#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9797#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9931#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9707#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9708#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10002#L961-3 assume !(1 == ~T7_E~0); 9807#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9808#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10055#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9451#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9452#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9440#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9441#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10131#L1001-3 assume !(1 == ~E_7~0); 9784#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9785#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 9479#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9480#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9733#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 9734#L1291 assume !(0 == start_simulation_~tmp~3#1); 9999#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 9902#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9385#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9386#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 9444#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9868#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9869#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 9954#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 9453#L1272-2 [2024-11-13 13:53:37,336 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:37,336 INFO L85 PathProgramCache]: Analyzing trace with hash 510892636, now seen corresponding path program 1 times [2024-11-13 13:53:37,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:37,336 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [386109193] [2024-11-13 13:53:37,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:37,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:37,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:37,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:37,407 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:37,407 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [386109193] [2024-11-13 13:53:37,407 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [386109193] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:37,407 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:37,408 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:37,408 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [963686069] [2024-11-13 13:53:37,408 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:37,408 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:37,409 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:37,409 INFO L85 PathProgramCache]: Analyzing trace with hash 702351055, now seen corresponding path program 2 times [2024-11-13 13:53:37,409 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:37,409 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1624402388] [2024-11-13 13:53:37,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:37,409 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:37,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:37,489 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:37,490 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:37,490 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1624402388] [2024-11-13 13:53:37,490 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1624402388] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:37,490 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:37,490 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:37,490 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [917226359] [2024-11-13 13:53:37,490 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:37,491 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:37,491 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:37,492 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:53:37,492 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:53:37,492 INFO L87 Difference]: Start difference. First operand 933 states and 1384 transitions. cyclomatic complexity: 452 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:37,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:37,517 INFO L93 Difference]: Finished difference Result 933 states and 1383 transitions. [2024-11-13 13:53:37,517 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1383 transitions. [2024-11-13 13:53:37,524 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-11-13 13:53:37,529 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1383 transitions. [2024-11-13 13:53:37,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-11-13 13:53:37,531 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-11-13 13:53:37,531 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1383 transitions. [2024-11-13 13:53:37,532 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:37,533 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1383 transitions. [2024-11-13 13:53:37,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1383 transitions. [2024-11-13 13:53:37,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-11-13 13:53:37,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.482315112540193) internal successors, (1383), 932 states have internal predecessors, (1383), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:37,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1383 transitions. [2024-11-13 13:53:37,552 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1383 transitions. [2024-11-13 13:53:37,552 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:53:37,553 INFO L424 stractBuchiCegarLoop]: Abstraction has 933 states and 1383 transitions. [2024-11-13 13:53:37,553 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 13:53:37,553 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1383 transitions. [2024-11-13 13:53:37,560 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-11-13 13:53:37,560 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:37,560 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:37,562 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:37,562 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:37,563 INFO L745 eck$LassoCheckResult]: Stem: 11504#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 11505#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 12131#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12132#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12133#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 11623#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11624#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12129#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12125#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11695#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11696#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11930#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11931#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11779#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11780#L838 assume !(0 == ~M_E~0); 11938#L838-2 assume !(0 == ~T1_E~0); 11303#L843-1 assume !(0 == ~T2_E~0); 11304#L848-1 assume !(0 == ~T3_E~0); 11424#L853-1 assume !(0 == ~T4_E~0); 11766#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11254#L863-1 assume !(0 == ~T6_E~0); 11255#L868-1 assume !(0 == ~T7_E~0); 12161#L873-1 assume !(0 == ~T8_E~0); 12159#L878-1 assume !(0 == ~E_1~0); 12150#L883-1 assume !(0 == ~E_2~0); 12151#L888-1 assume !(0 == ~E_3~0); 11899#L893-1 assume !(0 == ~E_4~0); 11900#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 12171#L903-1 assume !(0 == ~E_6~0); 12148#L908-1 assume !(0 == ~E_7~0); 12029#L913-1 assume !(0 == ~E_8~0); 11315#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11316#L402 assume !(1 == ~m_pc~0); 11527#L402-2 is_master_triggered_~__retres1~0#1 := 0; 11448#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11449#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11701#L1035 assume !(0 != activate_threads_~tmp~1#1); 11702#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11754#L421 assume 1 == ~t1_pc~0; 12144#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12162#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11318#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11319#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 11808#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12169#L440 assume 1 == ~t2_pc~0; 11287#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11288#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11458#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11649#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 12044#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11652#L459 assume !(1 == ~t3_pc~0); 11653#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12142#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11276#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11277#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11443#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11452#L478 assume 1 == ~t4_pc~0; 11453#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11904#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11396#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11397#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 11357#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11358#L497 assume !(1 == ~t5_pc~0); 11407#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11408#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11975#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12081#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 12138#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12139#L516 assume 1 == ~t6_pc~0; 12185#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11929#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11632#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11498#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 11499#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11918#L535 assume !(1 == ~t7_pc~0); 11919#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11989#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11990#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12021#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 12011#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12012#L554 assume 1 == ~t8_pc~0; 11954#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11279#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12037#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11586#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 11587#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11265#L931 assume !(1 == ~M_E~0); 11266#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12157#L936-1 assume !(1 == ~T2_E~0); 12176#L941-1 assume !(1 == ~T3_E~0); 11755#L946-1 assume !(1 == ~T4_E~0); 11756#L951-1 assume !(1 == ~T5_E~0); 11513#L956-1 assume !(1 == ~T6_E~0); 11514#L961-1 assume !(1 == ~T7_E~0); 11901#L966-1 assume !(1 == ~T8_E~0); 11902#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12014#L976-1 assume !(1 == ~E_2~0); 11979#L981-1 assume !(1 == ~E_3~0); 11759#L986-1 assume !(1 == ~E_4~0); 11540#L991-1 assume !(1 == ~E_5~0); 11541#L996-1 assume !(1 == ~E_6~0); 12166#L1001-1 assume !(1 == ~E_7~0); 11949#L1006-1 assume !(1 == ~E_8~0); 11950#L1011-1 assume { :end_inline_reset_delta_events } true; 11326#L1272-2 [2024-11-13 13:53:37,564 INFO L747 eck$LassoCheckResult]: Loop: 11326#L1272-2 assume !false; 11327#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11563#L813-1 assume !false; 12099#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12100#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11330#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11668#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11669#L696 assume !(0 != eval_~tmp~0#1); 12042#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11809#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11810#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11998#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11999#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11852#L848-3 assume !(0 == ~T3_E~0); 11853#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11903#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11968#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11958#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11959#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11567#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11290#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11291#L888-3 assume !(0 == ~E_3~0); 11292#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11293#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11785#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12101#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11793#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 11331#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11332#L402-27 assume 1 == ~m_pc~0; 11280#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11281#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11991#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11992#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12118#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12119#L421-27 assume !(1 == ~t1_pc~0); 11557#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 11558#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11877#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11878#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12167#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11921#L440-27 assume 1 == ~t2_pc~0; 11922#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12096#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11963#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11828#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11829#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11543#L459-27 assume !(1 == ~t3_pc~0); 11544#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 11984#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11805#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11806#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11917#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12160#L478-27 assume 1 == ~t4_pc~0; 12179#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11533#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11716#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11717#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12066#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12102#L497-27 assume 1 == ~t5_pc~0; 12103#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11576#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11577#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11519#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11520#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11787#L516-27 assume !(1 == ~t6_pc~0); 11788#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 11640#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11641#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11940#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 11941#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11720#L535-27 assume 1 == ~t7_pc~0; 11721#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12050#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11600#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11601#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11671#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11672#L554-27 assume 1 == ~t8_pc~0; 11874#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11306#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11457#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11837#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11564#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11565#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11439#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11440#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11670#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11804#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11580#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11581#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11875#L961-3 assume !(1 == ~T7_E~0); 11680#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11681#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11928#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11324#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11325#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11313#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11314#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12004#L1001-3 assume !(1 == ~E_7~0); 11657#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11658#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 11352#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11353#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11606#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 11607#L1291 assume !(0 == start_simulation_~tmp~3#1); 11872#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 11775#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11258#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11259#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 11317#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11741#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11742#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 11827#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 11326#L1272-2 [2024-11-13 13:53:37,564 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:37,564 INFO L85 PathProgramCache]: Analyzing trace with hash 2129867550, now seen corresponding path program 1 times [2024-11-13 13:53:37,565 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:37,565 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1497238214] [2024-11-13 13:53:37,565 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:37,565 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:37,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:37,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:37,618 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:37,618 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1497238214] [2024-11-13 13:53:37,618 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1497238214] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:37,618 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:37,618 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:37,619 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2069042504] [2024-11-13 13:53:37,619 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:37,619 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:37,619 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:37,619 INFO L85 PathProgramCache]: Analyzing trace with hash 1157257136, now seen corresponding path program 1 times [2024-11-13 13:53:37,619 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:37,619 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1001260149] [2024-11-13 13:53:37,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:37,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:37,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:37,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:37,688 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:37,688 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1001260149] [2024-11-13 13:53:37,688 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1001260149] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:37,688 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:37,688 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:37,688 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [256888521] [2024-11-13 13:53:37,688 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:37,688 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:37,689 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:37,689 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:53:37,689 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:53:37,689 INFO L87 Difference]: Start difference. First operand 933 states and 1383 transitions. cyclomatic complexity: 451 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:37,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:37,745 INFO L93 Difference]: Finished difference Result 933 states and 1382 transitions. [2024-11-13 13:53:37,745 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1382 transitions. [2024-11-13 13:53:37,752 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-11-13 13:53:37,757 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1382 transitions. [2024-11-13 13:53:37,757 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-11-13 13:53:37,758 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-11-13 13:53:37,758 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1382 transitions. [2024-11-13 13:53:37,760 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:37,760 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1382 transitions. [2024-11-13 13:53:37,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1382 transitions. [2024-11-13 13:53:37,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-11-13 13:53:37,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4812433011789925) internal successors, (1382), 932 states have internal predecessors, (1382), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:37,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1382 transitions. [2024-11-13 13:53:37,778 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1382 transitions. [2024-11-13 13:53:37,779 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:53:37,780 INFO L424 stractBuchiCegarLoop]: Abstraction has 933 states and 1382 transitions. [2024-11-13 13:53:37,780 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 13:53:37,780 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1382 transitions. [2024-11-13 13:53:37,786 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-11-13 13:53:37,786 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:37,786 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:37,788 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:37,788 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:37,788 INFO L745 eck$LassoCheckResult]: Stem: 13377#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 13378#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 14004#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14005#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14006#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 13496#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13497#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14002#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13998#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13568#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13569#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13803#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13804#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13652#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13653#L838 assume !(0 == ~M_E~0); 13812#L838-2 assume !(0 == ~T1_E~0); 13176#L843-1 assume !(0 == ~T2_E~0); 13177#L848-1 assume !(0 == ~T3_E~0); 13297#L853-1 assume !(0 == ~T4_E~0); 13641#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13129#L863-1 assume !(0 == ~T6_E~0); 13130#L868-1 assume !(0 == ~T7_E~0); 14034#L873-1 assume !(0 == ~T8_E~0); 14032#L878-1 assume !(0 == ~E_1~0); 14023#L883-1 assume !(0 == ~E_2~0); 14024#L888-1 assume !(0 == ~E_3~0); 13775#L893-1 assume !(0 == ~E_4~0); 13776#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 14044#L903-1 assume !(0 == ~E_6~0); 14021#L908-1 assume !(0 == ~E_7~0); 13903#L913-1 assume !(0 == ~E_8~0); 13189#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13190#L402 assume !(1 == ~m_pc~0); 13404#L402-2 is_master_triggered_~__retres1~0#1 := 0; 13321#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13322#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13574#L1035 assume !(0 != activate_threads_~tmp~1#1); 13575#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13629#L421 assume 1 == ~t1_pc~0; 14017#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14038#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13191#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13192#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 13683#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14042#L440 assume 1 == ~t2_pc~0; 13160#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13161#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13331#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13522#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 13917#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13529#L459 assume !(1 == ~t3_pc~0); 13530#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 14015#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13149#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13150#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13316#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13325#L478 assume 1 == ~t4_pc~0; 13326#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13777#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13269#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13270#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 13232#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13233#L497 assume !(1 == ~t5_pc~0); 13280#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13281#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13848#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13954#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 14011#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14012#L516 assume 1 == ~t6_pc~0; 14058#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13802#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13505#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13371#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 13372#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13791#L535 assume !(1 == ~t7_pc~0); 13792#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13862#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13863#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13894#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 13885#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13886#L554 assume 1 == ~t8_pc~0; 13827#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13152#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13911#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13462#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 13463#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13138#L931 assume !(1 == ~M_E~0); 13139#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14030#L936-1 assume !(1 == ~T2_E~0); 14049#L941-1 assume !(1 == ~T3_E~0); 13627#L946-1 assume !(1 == ~T4_E~0); 13628#L951-1 assume !(1 == ~T5_E~0); 13386#L956-1 assume !(1 == ~T6_E~0); 13387#L961-1 assume !(1 == ~T7_E~0); 13772#L966-1 assume !(1 == ~T8_E~0); 13773#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 13887#L976-1 assume !(1 == ~E_2~0); 13852#L981-1 assume !(1 == ~E_3~0); 13632#L986-1 assume !(1 == ~E_4~0); 13413#L991-1 assume !(1 == ~E_5~0); 13414#L996-1 assume !(1 == ~E_6~0); 14039#L1001-1 assume !(1 == ~E_7~0); 13822#L1006-1 assume !(1 == ~E_8~0); 13823#L1011-1 assume { :end_inline_reset_delta_events } true; 13199#L1272-2 [2024-11-13 13:53:37,789 INFO L747 eck$LassoCheckResult]: Loop: 13199#L1272-2 assume !false; 13200#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13436#L813-1 assume !false; 13972#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13973#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13203#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13541#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13542#L696 assume !(0 != eval_~tmp~0#1); 13915#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13681#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13682#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13871#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13872#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13725#L848-3 assume !(0 == ~T3_E~0); 13726#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13774#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13841#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13831#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13832#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13440#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13163#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13164#L888-3 assume !(0 == ~E_3~0); 13165#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13166#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13658#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13974#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13666#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13204#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13205#L402-27 assume 1 == ~m_pc~0; 13153#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13154#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13864#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13865#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13991#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13992#L421-27 assume !(1 == ~t1_pc~0); 13430#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 13431#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13750#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13751#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14040#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13794#L440-27 assume 1 == ~t2_pc~0; 13795#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13968#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13836#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13701#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13702#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13416#L459-27 assume !(1 == ~t3_pc~0); 13417#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 13857#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13678#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13679#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13790#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14033#L478-27 assume 1 == ~t4_pc~0; 14052#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13406#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13589#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13590#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13939#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13975#L497-27 assume 1 == ~t5_pc~0; 13976#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13449#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13450#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13392#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13393#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13660#L516-27 assume !(1 == ~t6_pc~0); 13661#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 13513#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13514#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13813#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 13814#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13593#L535-27 assume 1 == ~t7_pc~0; 13594#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13923#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13473#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13474#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13544#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13545#L554-27 assume 1 == ~t8_pc~0; 13747#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13179#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13330#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13710#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13437#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13438#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13312#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13313#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13543#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13677#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13453#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13454#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13748#L961-3 assume !(1 == ~T7_E~0); 13553#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13554#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13801#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13197#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13198#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13186#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13187#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13877#L1001-3 assume !(1 == ~E_7~0); 13527#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13528#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13225#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13226#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13479#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 13480#L1291 assume !(0 == start_simulation_~tmp~3#1); 13745#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13648#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13131#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13132#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 13188#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13614#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13615#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 13700#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 13199#L1272-2 [2024-11-13 13:53:37,789 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:37,789 INFO L85 PathProgramCache]: Analyzing trace with hash -1281590756, now seen corresponding path program 1 times [2024-11-13 13:53:37,790 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:37,790 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [243076825] [2024-11-13 13:53:37,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:37,790 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:37,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:37,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:37,835 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:37,835 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [243076825] [2024-11-13 13:53:37,835 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [243076825] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:37,835 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:37,836 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:37,836 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [45176716] [2024-11-13 13:53:37,836 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:37,836 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:37,836 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:37,836 INFO L85 PathProgramCache]: Analyzing trace with hash 1157257136, now seen corresponding path program 2 times [2024-11-13 13:53:37,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:37,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1467749018] [2024-11-13 13:53:37,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:37,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:37,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:37,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:37,897 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:37,897 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1467749018] [2024-11-13 13:53:37,899 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1467749018] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:37,899 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:37,899 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:37,899 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1297106921] [2024-11-13 13:53:37,899 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:37,900 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:37,900 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:37,900 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:53:37,900 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:53:37,900 INFO L87 Difference]: Start difference. First operand 933 states and 1382 transitions. cyclomatic complexity: 450 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:37,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:37,925 INFO L93 Difference]: Finished difference Result 933 states and 1381 transitions. [2024-11-13 13:53:37,925 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1381 transitions. [2024-11-13 13:53:37,932 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-11-13 13:53:37,937 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1381 transitions. [2024-11-13 13:53:37,938 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-11-13 13:53:37,939 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-11-13 13:53:37,939 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1381 transitions. [2024-11-13 13:53:37,940 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:37,940 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1381 transitions. [2024-11-13 13:53:37,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1381 transitions. [2024-11-13 13:53:37,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-11-13 13:53:37,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.480171489817792) internal successors, (1381), 932 states have internal predecessors, (1381), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:37,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1381 transitions. [2024-11-13 13:53:37,960 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1381 transitions. [2024-11-13 13:53:37,960 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:53:37,962 INFO L424 stractBuchiCegarLoop]: Abstraction has 933 states and 1381 transitions. [2024-11-13 13:53:37,963 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 13:53:37,963 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1381 transitions. [2024-11-13 13:53:37,968 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-11-13 13:53:37,969 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:37,969 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:37,971 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:37,974 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:37,974 INFO L745 eck$LassoCheckResult]: Stem: 15250#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 15251#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 15877#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15878#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15879#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 15369#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15370#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15875#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15871#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15441#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15442#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15676#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 15677#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 15525#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15526#L838 assume !(0 == ~M_E~0); 15685#L838-2 assume !(0 == ~T1_E~0); 15049#L843-1 assume !(0 == ~T2_E~0); 15050#L848-1 assume !(0 == ~T3_E~0); 15170#L853-1 assume !(0 == ~T4_E~0); 15514#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15002#L863-1 assume !(0 == ~T6_E~0); 15003#L868-1 assume !(0 == ~T7_E~0); 15907#L873-1 assume !(0 == ~T8_E~0); 15905#L878-1 assume !(0 == ~E_1~0); 15896#L883-1 assume !(0 == ~E_2~0); 15897#L888-1 assume !(0 == ~E_3~0); 15645#L893-1 assume !(0 == ~E_4~0); 15646#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 15917#L903-1 assume !(0 == ~E_6~0); 15894#L908-1 assume !(0 == ~E_7~0); 15776#L913-1 assume !(0 == ~E_8~0); 15062#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15063#L402 assume !(1 == ~m_pc~0); 15277#L402-2 is_master_triggered_~__retres1~0#1 := 0; 15194#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15195#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15447#L1035 assume !(0 != activate_threads_~tmp~1#1); 15448#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15500#L421 assume 1 == ~t1_pc~0; 15890#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15911#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15064#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15065#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 15554#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15915#L440 assume 1 == ~t2_pc~0; 15033#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15034#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15204#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15395#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 15790#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15402#L459 assume !(1 == ~t3_pc~0); 15403#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15888#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15022#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15023#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15189#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15198#L478 assume 1 == ~t4_pc~0; 15199#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15650#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15142#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15143#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 15105#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15106#L497 assume !(1 == ~t5_pc~0); 15153#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15154#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15721#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15827#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 15884#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15885#L516 assume 1 == ~t6_pc~0; 15931#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15675#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15378#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15244#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 15245#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15664#L535 assume !(1 == ~t7_pc~0); 15665#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15735#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15736#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15767#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 15758#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15759#L554 assume 1 == ~t8_pc~0; 15700#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15025#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15783#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15335#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 15336#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15011#L931 assume !(1 == ~M_E~0); 15012#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15903#L936-1 assume !(1 == ~T2_E~0); 15922#L941-1 assume !(1 == ~T3_E~0); 15501#L946-1 assume !(1 == ~T4_E~0); 15502#L951-1 assume !(1 == ~T5_E~0); 15259#L956-1 assume !(1 == ~T6_E~0); 15260#L961-1 assume !(1 == ~T7_E~0); 15647#L966-1 assume !(1 == ~T8_E~0); 15648#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 15761#L976-1 assume !(1 == ~E_2~0); 15725#L981-1 assume !(1 == ~E_3~0); 15505#L986-1 assume !(1 == ~E_4~0); 15286#L991-1 assume !(1 == ~E_5~0); 15287#L996-1 assume !(1 == ~E_6~0); 15912#L1001-1 assume !(1 == ~E_7~0); 15695#L1006-1 assume !(1 == ~E_8~0); 15696#L1011-1 assume { :end_inline_reset_delta_events } true; 15072#L1272-2 [2024-11-13 13:53:37,974 INFO L747 eck$LassoCheckResult]: Loop: 15072#L1272-2 assume !false; 15073#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15311#L813-1 assume !false; 15845#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15846#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 15076#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15414#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15415#L696 assume !(0 != eval_~tmp~0#1); 15788#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15555#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15556#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15744#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15745#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15599#L848-3 assume !(0 == ~T3_E~0); 15600#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15649#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15714#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15705#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15706#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15315#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15038#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15039#L888-3 assume !(0 == ~E_3~0); 15036#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15037#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15531#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15847#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15539#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15077#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15078#L402-27 assume 1 == ~m_pc~0; 15026#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15027#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15737#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15738#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15864#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15865#L421-27 assume !(1 == ~t1_pc~0); 15303#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 15304#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15623#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15624#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15913#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15667#L440-27 assume 1 == ~t2_pc~0; 15668#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15841#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15709#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15574#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15575#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15289#L459-27 assume !(1 == ~t3_pc~0); 15290#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 15730#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15551#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15552#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15663#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15906#L478-27 assume 1 == ~t4_pc~0; 15925#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15279#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15462#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15463#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15812#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15848#L497-27 assume !(1 == ~t5_pc~0); 15456#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 15322#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15323#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15265#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15266#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15532#L516-27 assume !(1 == ~t6_pc~0); 15533#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 15383#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15384#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15686#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 15687#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15466#L535-27 assume 1 == ~t7_pc~0; 15467#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15796#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15346#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15347#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15417#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15418#L554-27 assume 1 == ~t8_pc~0; 15620#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15052#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15203#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15580#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15308#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15309#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15185#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15186#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15416#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15550#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15326#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15327#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15621#L961-3 assume !(1 == ~T7_E~0); 15426#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15427#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15674#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15070#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15071#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15059#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15060#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15750#L1001-3 assume !(1 == ~E_7~0); 15400#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15401#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15098#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 15099#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15348#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 15349#L1291 assume !(0 == start_simulation_~tmp~3#1); 15618#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15521#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 15004#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15005#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 15061#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15487#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15488#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 15573#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 15072#L1272-2 [2024-11-13 13:53:37,975 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:37,975 INFO L85 PathProgramCache]: Analyzing trace with hash -1253090466, now seen corresponding path program 1 times [2024-11-13 13:53:37,975 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:37,975 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [885258048] [2024-11-13 13:53:37,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:37,975 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:37,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:38,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:38,045 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:38,045 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [885258048] [2024-11-13 13:53:38,045 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [885258048] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:38,045 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:38,046 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:53:38,046 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1462660278] [2024-11-13 13:53:38,046 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:38,046 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:38,046 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:38,047 INFO L85 PathProgramCache]: Analyzing trace with hash 1260058383, now seen corresponding path program 1 times [2024-11-13 13:53:38,047 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:38,047 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2134980488] [2024-11-13 13:53:38,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:38,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:38,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:38,126 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:38,126 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:38,126 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2134980488] [2024-11-13 13:53:38,126 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2134980488] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:38,126 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:38,126 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:38,126 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [368891740] [2024-11-13 13:53:38,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:38,126 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:38,126 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:38,127 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:53:38,127 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:53:38,127 INFO L87 Difference]: Start difference. First operand 933 states and 1381 transitions. cyclomatic complexity: 449 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:38,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:38,173 INFO L93 Difference]: Finished difference Result 933 states and 1376 transitions. [2024-11-13 13:53:38,174 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1376 transitions. [2024-11-13 13:53:38,181 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-11-13 13:53:38,187 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1376 transitions. [2024-11-13 13:53:38,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2024-11-13 13:53:38,189 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2024-11-13 13:53:38,189 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1376 transitions. [2024-11-13 13:53:38,191 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:38,191 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1376 transitions. [2024-11-13 13:53:38,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1376 transitions. [2024-11-13 13:53:38,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2024-11-13 13:53:38,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.47481243301179) internal successors, (1376), 932 states have internal predecessors, (1376), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:38,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1376 transitions. [2024-11-13 13:53:38,212 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1376 transitions. [2024-11-13 13:53:38,213 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:53:38,214 INFO L424 stractBuchiCegarLoop]: Abstraction has 933 states and 1376 transitions. [2024-11-13 13:53:38,215 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 13:53:38,215 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1376 transitions. [2024-11-13 13:53:38,223 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2024-11-13 13:53:38,224 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:38,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:38,227 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:38,227 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:38,227 INFO L745 eck$LassoCheckResult]: Stem: 17123#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 17124#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 17750#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17751#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17752#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 17242#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17243#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17748#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17744#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17314#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17315#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17549#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17550#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 17398#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17399#L838 assume !(0 == ~M_E~0); 17558#L838-2 assume !(0 == ~T1_E~0); 16922#L843-1 assume !(0 == ~T2_E~0); 16923#L848-1 assume !(0 == ~T3_E~0); 17043#L853-1 assume !(0 == ~T4_E~0); 17387#L858-1 assume !(0 == ~T5_E~0); 16873#L863-1 assume !(0 == ~T6_E~0); 16874#L868-1 assume !(0 == ~T7_E~0); 17780#L873-1 assume !(0 == ~T8_E~0); 17778#L878-1 assume !(0 == ~E_1~0); 17769#L883-1 assume !(0 == ~E_2~0); 17770#L888-1 assume !(0 == ~E_3~0); 17518#L893-1 assume !(0 == ~E_4~0); 17519#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 17790#L903-1 assume !(0 == ~E_6~0); 17767#L908-1 assume !(0 == ~E_7~0); 17648#L913-1 assume !(0 == ~E_8~0); 16935#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16936#L402 assume !(1 == ~m_pc~0); 17148#L402-2 is_master_triggered_~__retres1~0#1 := 0; 17067#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17068#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17320#L1035 assume !(0 != activate_threads_~tmp~1#1); 17321#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17373#L421 assume 1 == ~t1_pc~0; 17763#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17784#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16937#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16938#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 17427#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17788#L440 assume 1 == ~t2_pc~0; 16906#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16907#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17077#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17268#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 17663#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17275#L459 assume !(1 == ~t3_pc~0); 17276#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17761#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16895#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16896#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17062#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17071#L478 assume 1 == ~t4_pc~0; 17072#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17523#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17015#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17016#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 16978#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16979#L497 assume !(1 == ~t5_pc~0); 17026#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17027#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17594#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17700#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 17757#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17758#L516 assume 1 == ~t6_pc~0; 17804#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17548#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17251#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17117#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 17118#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17537#L535 assume !(1 == ~t7_pc~0); 17538#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 17608#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17609#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17640#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 17630#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17631#L554 assume 1 == ~t8_pc~0; 17573#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16898#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17656#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17208#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 17209#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16884#L931 assume !(1 == ~M_E~0); 16885#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17776#L936-1 assume !(1 == ~T2_E~0); 17795#L941-1 assume !(1 == ~T3_E~0); 17374#L946-1 assume !(1 == ~T4_E~0); 17375#L951-1 assume !(1 == ~T5_E~0); 17132#L956-1 assume !(1 == ~T6_E~0); 17133#L961-1 assume !(1 == ~T7_E~0); 17520#L966-1 assume !(1 == ~T8_E~0); 17521#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 17633#L976-1 assume !(1 == ~E_2~0); 17598#L981-1 assume !(1 == ~E_3~0); 17378#L986-1 assume !(1 == ~E_4~0); 17159#L991-1 assume !(1 == ~E_5~0); 17160#L996-1 assume !(1 == ~E_6~0); 17785#L1001-1 assume !(1 == ~E_7~0); 17568#L1006-1 assume !(1 == ~E_8~0); 17569#L1011-1 assume { :end_inline_reset_delta_events } true; 16945#L1272-2 [2024-11-13 13:53:38,227 INFO L747 eck$LassoCheckResult]: Loop: 16945#L1272-2 assume !false; 16946#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17184#L813-1 assume !false; 17718#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 17719#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16949#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 17287#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17288#L696 assume !(0 != eval_~tmp~0#1); 17661#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17428#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17429#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17617#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17618#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17471#L848-3 assume !(0 == ~T3_E~0); 17472#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17522#L858-3 assume !(0 == ~T5_E~0); 17587#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17578#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17579#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17188#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16909#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16910#L888-3 assume !(0 == ~E_3~0); 16911#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16912#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17404#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17722#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17412#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16950#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16951#L402-27 assume 1 == ~m_pc~0; 16899#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16900#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17610#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17611#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17737#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17738#L421-27 assume !(1 == ~t1_pc~0); 17176#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 17177#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17496#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17497#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17786#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17540#L440-27 assume 1 == ~t2_pc~0; 17541#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17714#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17582#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17447#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17448#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17162#L459-27 assume !(1 == ~t3_pc~0); 17163#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 17603#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17424#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17425#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17536#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17779#L478-27 assume 1 == ~t4_pc~0; 17798#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17152#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17335#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17336#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17685#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17720#L497-27 assume 1 == ~t5_pc~0; 17721#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17195#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17196#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17138#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17139#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17405#L516-27 assume !(1 == ~t6_pc~0); 17406#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 17252#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17253#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17559#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 17560#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17339#L535-27 assume 1 == ~t7_pc~0; 17340#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17667#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17219#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17220#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17290#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17291#L554-27 assume 1 == ~t8_pc~0; 17493#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16925#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17076#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17453#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17181#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17182#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17058#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17059#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17289#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17423#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17199#L951-3 assume !(1 == ~T5_E~0); 17200#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17494#L961-3 assume !(1 == ~T7_E~0); 17299#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17300#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17547#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16943#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16944#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16932#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16933#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17623#L1001-3 assume !(1 == ~E_7~0); 17273#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17274#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16971#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16972#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 17221#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 17222#L1291 assume !(0 == start_simulation_~tmp~3#1); 17491#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 17392#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16877#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16878#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 16934#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17359#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17360#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 17446#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 16945#L1272-2 [2024-11-13 13:53:38,228 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:38,228 INFO L85 PathProgramCache]: Analyzing trace with hash 623392352, now seen corresponding path program 1 times [2024-11-13 13:53:38,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:38,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1562541964] [2024-11-13 13:53:38,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:38,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:38,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:38,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:38,349 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:38,349 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1562541964] [2024-11-13 13:53:38,349 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1562541964] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:38,349 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:38,350 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:38,350 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [795153669] [2024-11-13 13:53:38,350 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:38,350 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:38,350 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:38,351 INFO L85 PathProgramCache]: Analyzing trace with hash -1396090444, now seen corresponding path program 1 times [2024-11-13 13:53:38,351 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:38,351 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [503481705] [2024-11-13 13:53:38,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:38,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:38,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:38,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:38,422 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:38,422 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [503481705] [2024-11-13 13:53:38,423 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [503481705] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:38,423 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:38,423 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:38,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1719350562] [2024-11-13 13:53:38,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:38,423 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:38,423 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:38,424 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:53:38,425 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:53:38,425 INFO L87 Difference]: Start difference. First operand 933 states and 1376 transitions. cyclomatic complexity: 444 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:38,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:38,654 INFO L93 Difference]: Finished difference Result 1704 states and 2511 transitions. [2024-11-13 13:53:38,654 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1704 states and 2511 transitions. [2024-11-13 13:53:38,665 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1575 [2024-11-13 13:53:38,675 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1704 states to 1704 states and 2511 transitions. [2024-11-13 13:53:38,675 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1704 [2024-11-13 13:53:38,677 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1704 [2024-11-13 13:53:38,677 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1704 states and 2511 transitions. [2024-11-13 13:53:38,680 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:38,680 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1704 states and 2511 transitions. [2024-11-13 13:53:38,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1704 states and 2511 transitions. [2024-11-13 13:53:38,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1704 to 1703. [2024-11-13 13:53:38,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1703 states, 1703 states have (on average 1.473869641808573) internal successors, (2510), 1702 states have internal predecessors, (2510), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:38,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1703 states to 1703 states and 2510 transitions. [2024-11-13 13:53:38,726 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1703 states and 2510 transitions. [2024-11-13 13:53:38,727 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:53:38,727 INFO L424 stractBuchiCegarLoop]: Abstraction has 1703 states and 2510 transitions. [2024-11-13 13:53:38,727 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 13:53:38,728 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1703 states and 2510 transitions. [2024-11-13 13:53:38,737 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1575 [2024-11-13 13:53:38,738 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:38,738 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:38,739 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:38,740 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:38,740 INFO L745 eck$LassoCheckResult]: Stem: 19771#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 19772#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 20464#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20465#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20466#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 19892#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19893#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20462#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20449#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19972#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19973#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20222#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20223#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 20061#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20062#L838 assume !(0 == ~M_E~0); 20230#L838-2 assume !(0 == ~T1_E~0); 19569#L843-1 assume !(0 == ~T2_E~0); 19570#L848-1 assume !(0 == ~T3_E~0); 19691#L853-1 assume !(0 == ~T4_E~0); 20048#L858-1 assume !(0 == ~T5_E~0); 19520#L863-1 assume !(0 == ~T6_E~0); 19521#L868-1 assume !(0 == ~T7_E~0); 20510#L873-1 assume !(0 == ~T8_E~0); 20506#L878-1 assume !(0 == ~E_1~0); 20491#L883-1 assume !(0 == ~E_2~0); 20492#L888-1 assume !(0 == ~E_3~0); 20190#L893-1 assume !(0 == ~E_4~0); 20191#L898-1 assume !(0 == ~E_5~0); 20523#L903-1 assume !(0 == ~E_6~0); 20489#L908-1 assume !(0 == ~E_7~0); 20326#L913-1 assume !(0 == ~E_8~0); 19582#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19583#L402 assume !(1 == ~m_pc~0); 19794#L402-2 is_master_triggered_~__retres1~0#1 := 0; 19715#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19716#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19978#L1035 assume !(0 != activate_threads_~tmp~1#1); 19979#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20033#L421 assume 1 == ~t1_pc~0; 20484#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20511#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19585#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19586#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 20092#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20520#L440 assume 1 == ~t2_pc~0; 19553#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19554#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19725#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19921#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 20351#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19925#L459 assume !(1 == ~t3_pc~0); 19926#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20480#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19542#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19543#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19710#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19719#L478 assume 1 == ~t4_pc~0; 19720#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20195#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19663#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19664#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 19624#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19625#L497 assume !(1 == ~t5_pc~0); 19674#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 19675#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20269#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20395#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 20474#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20475#L516 assume 1 == ~t6_pc~0; 20552#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20221#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19902#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19765#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 19766#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20210#L535 assume !(1 == ~t7_pc~0); 20211#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20284#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20285#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20318#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 20307#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20308#L554 assume 1 == ~t8_pc~0; 20247#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19545#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20336#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19854#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 19855#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19531#L931 assume !(1 == ~M_E~0); 19532#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20500#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20534#L941-1 assume !(1 == ~T3_E~0); 20034#L946-1 assume !(1 == ~T4_E~0); 20035#L951-1 assume !(1 == ~T5_E~0); 19780#L956-1 assume !(1 == ~T6_E~0); 19781#L961-1 assume !(1 == ~T7_E~0); 20192#L966-1 assume !(1 == ~T8_E~0); 20193#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 20310#L976-1 assume !(1 == ~E_2~0); 20274#L981-1 assume !(1 == ~E_3~0); 20040#L986-1 assume !(1 == ~E_4~0); 20041#L991-1 assume !(1 == ~E_5~0); 19808#L996-1 assume !(1 == ~E_6~0); 20515#L1001-1 assume !(1 == ~E_7~0); 20241#L1006-1 assume !(1 == ~E_8~0); 20242#L1011-1 assume { :end_inline_reset_delta_events } true; 20580#L1272-2 [2024-11-13 13:53:38,740 INFO L747 eck$LassoCheckResult]: Loop: 20580#L1272-2 assume !false; 20576#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20537#L813-1 assume !false; 20538#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20568#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 20187#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19941#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19942#L696 assume !(0 != eval_~tmp~0#1); 20346#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20347#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20454#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20455#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20562#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20137#L848-3 assume !(0 == ~T3_E~0); 20138#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20194#L858-3 assume !(0 == ~T5_E~0); 20261#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20251#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20252#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19835#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19556#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19557#L888-3 assume !(0 == ~E_3~0); 19558#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19559#L898-3 assume !(0 == ~E_5~0); 20067#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20416#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20075#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19598#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19599#L402-27 assume 1 == ~m_pc~0; 19546#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19547#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20286#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20287#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20439#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20440#L421-27 assume !(1 == ~t1_pc~0); 19825#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 19826#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20165#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20166#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20516#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20213#L440-27 assume 1 == ~t2_pc~0; 20214#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20411#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20256#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20113#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20114#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19811#L459-27 assume !(1 == ~t3_pc~0); 19812#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 20279#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20087#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20088#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20209#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20509#L478-27 assume !(1 == ~t4_pc~0); 19799#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 19800#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19993#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19994#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20377#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20417#L497-27 assume 1 == ~t5_pc~0; 20418#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19844#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19845#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19786#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19787#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20069#L516-27 assume !(1 == ~t6_pc~0); 20070#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 19910#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19911#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20505#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 21127#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21125#L535-27 assume 1 == ~t7_pc~0; 21121#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21120#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21119#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21118#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21117#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21116#L554-27 assume 1 == ~t8_pc~0; 21114#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21113#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21112#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21050#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21049#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21048#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21047#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21046#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19944#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21045#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21044#L951-3 assume !(1 == ~T5_E~0); 21043#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21042#L961-3 assume !(1 == ~T7_E~0); 21041#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21040#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21039#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21038#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21037#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21036#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19580#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21035#L1001-3 assume !(1 == ~E_7~0); 21034#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21033#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19619#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19620#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20091#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 20646#L1291 assume !(0 == start_simulation_~tmp~3#1); 20507#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20508#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 20592#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20591#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 20589#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20587#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20586#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 20584#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 20580#L1272-2 [2024-11-13 13:53:38,740 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:38,741 INFO L85 PathProgramCache]: Analyzing trace with hash 1671526308, now seen corresponding path program 1 times [2024-11-13 13:53:38,741 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:38,741 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1033448778] [2024-11-13 13:53:38,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:38,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:38,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:38,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:38,853 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:38,853 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1033448778] [2024-11-13 13:53:38,853 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1033448778] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:38,853 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:38,854 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:53:38,854 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [641313435] [2024-11-13 13:53:38,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:38,854 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:38,855 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:38,855 INFO L85 PathProgramCache]: Analyzing trace with hash 221659093, now seen corresponding path program 1 times [2024-11-13 13:53:38,855 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:38,855 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2071625836] [2024-11-13 13:53:38,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:38,855 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:38,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:38,913 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:38,913 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:38,913 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2071625836] [2024-11-13 13:53:38,913 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2071625836] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:38,913 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:38,913 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:38,914 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2109460737] [2024-11-13 13:53:38,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:38,914 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:38,914 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:38,914 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:53:38,914 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:53:38,915 INFO L87 Difference]: Start difference. First operand 1703 states and 2510 transitions. cyclomatic complexity: 809 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:39,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:39,036 INFO L93 Difference]: Finished difference Result 3128 states and 4579 transitions. [2024-11-13 13:53:39,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3128 states and 4579 transitions. [2024-11-13 13:53:39,058 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2997 [2024-11-13 13:53:39,077 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3128 states to 3128 states and 4579 transitions. [2024-11-13 13:53:39,077 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3128 [2024-11-13 13:53:39,080 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3128 [2024-11-13 13:53:39,081 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3128 states and 4579 transitions. [2024-11-13 13:53:39,086 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:39,086 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3128 states and 4579 transitions. [2024-11-13 13:53:39,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3128 states and 4579 transitions. [2024-11-13 13:53:39,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3128 to 3124. [2024-11-13 13:53:39,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3124 states, 3124 states have (on average 1.4644686299615877) internal successors, (4575), 3123 states have internal predecessors, (4575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:39,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3124 states to 3124 states and 4575 transitions. [2024-11-13 13:53:39,164 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3124 states and 4575 transitions. [2024-11-13 13:53:39,164 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:53:39,165 INFO L424 stractBuchiCegarLoop]: Abstraction has 3124 states and 4575 transitions. [2024-11-13 13:53:39,165 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 13:53:39,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3124 states and 4575 transitions. [2024-11-13 13:53:39,182 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2993 [2024-11-13 13:53:39,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:39,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:39,185 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:39,185 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:39,186 INFO L745 eck$LassoCheckResult]: Stem: 24609#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 24610#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 25268#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25269#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25271#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 24730#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24731#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25265#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25261#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24805#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24806#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25043#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25044#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24890#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24891#L838 assume !(0 == ~M_E~0); 25051#L838-2 assume !(0 == ~T1_E~0); 24407#L843-1 assume !(0 == ~T2_E~0); 24408#L848-1 assume !(0 == ~T3_E~0); 24528#L853-1 assume !(0 == ~T4_E~0); 24877#L858-1 assume !(0 == ~T5_E~0); 24358#L863-1 assume !(0 == ~T6_E~0); 24359#L868-1 assume !(0 == ~T7_E~0); 25314#L873-1 assume !(0 == ~T8_E~0); 25312#L878-1 assume !(0 == ~E_1~0); 25291#L883-1 assume !(0 == ~E_2~0); 25292#L888-1 assume !(0 == ~E_3~0); 25011#L893-1 assume !(0 == ~E_4~0); 25012#L898-1 assume !(0 == ~E_5~0); 25326#L903-1 assume !(0 == ~E_6~0); 25289#L908-1 assume !(0 == ~E_7~0); 25149#L913-1 assume !(0 == ~E_8~0); 24420#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24421#L402 assume !(1 == ~m_pc~0); 24632#L402-2 is_master_triggered_~__retres1~0#1 := 0; 24552#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24553#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 24811#L1035 assume !(0 != activate_threads_~tmp~1#1); 24812#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24864#L421 assume !(1 == ~t1_pc~0); 25286#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25315#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24423#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 24424#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 24919#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25324#L440 assume 1 == ~t2_pc~0; 24391#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24392#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24562#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24755#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 25167#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24758#L459 assume !(1 == ~t3_pc~0); 24759#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25282#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24380#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24381#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24547#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24556#L478 assume 1 == ~t4_pc~0; 24557#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25016#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24500#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24501#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 24461#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24462#L497 assume !(1 == ~t5_pc~0); 24511#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 24512#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25090#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25209#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 25277#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25278#L516 assume 1 == ~t6_pc~0; 25342#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25042#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24739#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24603#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 24604#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25031#L535 assume !(1 == ~t7_pc~0); 25032#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 25106#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25107#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25140#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 25130#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25131#L554 assume 1 == ~t8_pc~0; 25068#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24383#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25160#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24692#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 24693#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24369#L931 assume !(1 == ~M_E~0); 24370#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25305#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25331#L941-1 assume !(1 == ~T3_E~0); 24865#L946-1 assume !(1 == ~T4_E~0); 24866#L951-1 assume !(1 == ~T5_E~0); 24618#L956-1 assume !(1 == ~T6_E~0); 24619#L961-1 assume !(1 == ~T7_E~0); 25013#L966-1 assume !(1 == ~T8_E~0); 25014#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 25133#L976-1 assume !(1 == ~E_2~0); 25094#L981-1 assume !(1 == ~E_3~0); 24869#L986-1 assume !(1 == ~E_4~0); 24870#L991-1 assume !(1 == ~E_5~0); 24646#L996-1 assume !(1 == ~E_6~0); 26797#L1001-1 assume !(1 == ~E_7~0); 26795#L1006-1 assume !(1 == ~E_8~0); 26793#L1011-1 assume { :end_inline_reset_delta_events } true; 26790#L1272-2 [2024-11-13 13:53:39,187 INFO L747 eck$LassoCheckResult]: Loop: 26790#L1272-2 assume !false; 26788#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26785#L813-1 assume !false; 26782#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 26746#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 26741#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 26740#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26737#L696 assume !(0 != eval_~tmp~0#1); 25165#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24920#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24921#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25115#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25116#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24963#L848-3 assume !(0 == ~T3_E~0); 24964#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25015#L858-3 assume !(0 == ~T5_E~0); 25083#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25072#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25073#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24672#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24394#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24395#L888-3 assume !(0 == ~E_3~0); 24396#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24397#L898-3 assume !(0 == ~E_5~0); 24896#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25235#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24904#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24436#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24437#L402-27 assume 1 == ~m_pc~0; 24384#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24385#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25108#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25109#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25254#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25255#L421-27 assume !(1 == ~t1_pc~0); 24662#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 24663#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24988#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 24989#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25321#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25034#L440-27 assume 1 == ~t2_pc~0; 25035#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25230#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25077#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24939#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24940#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24650#L459-27 assume !(1 == ~t3_pc~0); 24651#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 26935#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26934#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26931#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26929#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26928#L478-27 assume 1 == ~t4_pc~0; 26926#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26925#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26923#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26921#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26920#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26919#L497-27 assume !(1 == ~t5_pc~0); 26917#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 26916#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26915#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26912#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26910#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26908#L516-27 assume 1 == ~t6_pc~0; 26905#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26903#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26902#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26901#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 26900#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26899#L535-27 assume !(1 == ~t7_pc~0); 26896#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 26893#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26891#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26890#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26889#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26888#L554-27 assume 1 == ~t8_pc~0; 26886#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26885#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26884#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26883#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26882#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26881#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26880#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26879#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24777#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26878#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26877#L951-3 assume !(1 == ~T5_E~0); 26876#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26875#L961-3 assume !(1 == ~T7_E~0); 26874#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26873#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26872#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26871#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26870#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26869#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24418#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26868#L1001-3 assume !(1 == ~E_7~0); 26867#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 26866#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 26865#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 26854#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 26853#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 26850#L1291 assume !(0 == start_simulation_~tmp~3#1); 26845#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 26841#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 26832#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 26831#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 26830#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26829#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26828#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 26792#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 26790#L1272-2 [2024-11-13 13:53:39,187 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:39,188 INFO L85 PathProgramCache]: Analyzing trace with hash 493551747, now seen corresponding path program 1 times [2024-11-13 13:53:39,188 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:39,188 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1932128135] [2024-11-13 13:53:39,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:39,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:39,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:39,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:39,261 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:39,261 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1932128135] [2024-11-13 13:53:39,261 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1932128135] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:39,261 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:39,261 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:53:39,262 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1761902238] [2024-11-13 13:53:39,262 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:39,262 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:39,263 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:39,263 INFO L85 PathProgramCache]: Analyzing trace with hash -1357404587, now seen corresponding path program 1 times [2024-11-13 13:53:39,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:39,263 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2033910390] [2024-11-13 13:53:39,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:39,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:39,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:39,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:39,330 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:39,330 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2033910390] [2024-11-13 13:53:39,330 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2033910390] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:39,330 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:39,330 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:39,330 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [415098864] [2024-11-13 13:53:39,331 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:39,331 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:39,331 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:39,331 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:53:39,331 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:53:39,332 INFO L87 Difference]: Start difference. First operand 3124 states and 4575 transitions. cyclomatic complexity: 1455 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:39,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:39,471 INFO L93 Difference]: Finished difference Result 5826 states and 8485 transitions. [2024-11-13 13:53:39,471 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5826 states and 8485 transitions. [2024-11-13 13:53:39,510 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5684 [2024-11-13 13:53:39,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5826 states to 5826 states and 8485 transitions. [2024-11-13 13:53:39,540 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5826 [2024-11-13 13:53:39,547 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5826 [2024-11-13 13:53:39,547 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5826 states and 8485 transitions. [2024-11-13 13:53:39,556 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:39,556 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5826 states and 8485 transitions. [2024-11-13 13:53:39,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5826 states and 8485 transitions. [2024-11-13 13:53:39,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5826 to 5818. [2024-11-13 13:53:39,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5818 states, 5818 states have (on average 1.4570299071845996) internal successors, (8477), 5817 states have internal predecessors, (8477), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:39,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5818 states to 5818 states and 8477 transitions. [2024-11-13 13:53:39,697 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5818 states and 8477 transitions. [2024-11-13 13:53:39,698 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:53:39,698 INFO L424 stractBuchiCegarLoop]: Abstraction has 5818 states and 8477 transitions. [2024-11-13 13:53:39,698 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 13:53:39,699 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5818 states and 8477 transitions. [2024-11-13 13:53:39,796 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5676 [2024-11-13 13:53:39,796 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:39,796 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:39,798 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:39,798 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:39,799 INFO L745 eck$LassoCheckResult]: Stem: 33564#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 33565#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 34223#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34224#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34225#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 33682#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33683#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34221#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34215#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33757#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33758#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33995#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33996#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33841#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33842#L838 assume !(0 == ~M_E~0); 34003#L838-2 assume !(0 == ~T1_E~0); 33363#L843-1 assume !(0 == ~T2_E~0); 33364#L848-1 assume !(0 == ~T3_E~0); 33483#L853-1 assume !(0 == ~T4_E~0); 33828#L858-1 assume !(0 == ~T5_E~0); 33315#L863-1 assume !(0 == ~T6_E~0); 33316#L868-1 assume !(0 == ~T7_E~0); 34266#L873-1 assume !(0 == ~T8_E~0); 34264#L878-1 assume !(0 == ~E_1~0); 34244#L883-1 assume !(0 == ~E_2~0); 34245#L888-1 assume !(0 == ~E_3~0); 33964#L893-1 assume !(0 == ~E_4~0); 33965#L898-1 assume !(0 == ~E_5~0); 34278#L903-1 assume !(0 == ~E_6~0); 34242#L908-1 assume !(0 == ~E_7~0); 34099#L913-1 assume !(0 == ~E_8~0); 33376#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33377#L402 assume !(1 == ~m_pc~0); 33589#L402-2 is_master_triggered_~__retres1~0#1 := 0; 33508#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33509#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33763#L1035 assume !(0 != activate_threads_~tmp~1#1); 33764#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33816#L421 assume !(1 == ~t1_pc~0); 34239#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34267#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33379#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33380#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 33870#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34275#L440 assume !(1 == ~t2_pc~0); 34309#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33518#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33519#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33708#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 34116#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33711#L459 assume !(1 == ~t3_pc~0); 33712#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34236#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33337#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33338#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33502#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33512#L478 assume 1 == ~t4_pc~0; 33513#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33969#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33455#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33456#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 33417#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33418#L497 assume !(1 == ~t5_pc~0); 33466#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 33467#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34041#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34162#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 34231#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34232#L516 assume 1 == ~t6_pc~0; 34303#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33994#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33691#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33558#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 33559#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33984#L535 assume !(1 == ~t7_pc~0); 33985#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 34056#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34057#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34092#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 34082#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34083#L554 assume 1 == ~t8_pc~0; 34019#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33340#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34109#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33646#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 33647#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33326#L931 assume !(1 == ~M_E~0); 33327#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34258#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34285#L941-1 assume !(1 == ~T3_E~0); 33817#L946-1 assume !(1 == ~T4_E~0); 33818#L951-1 assume !(1 == ~T5_E~0); 33573#L956-1 assume !(1 == ~T6_E~0); 33574#L961-1 assume !(1 == ~T7_E~0); 33966#L966-1 assume !(1 == ~T8_E~0); 33967#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 34085#L976-1 assume !(1 == ~E_2~0); 34045#L981-1 assume !(1 == ~E_3~0); 34046#L986-1 assume !(1 == ~E_4~0); 37044#L991-1 assume !(1 == ~E_5~0); 33601#L996-1 assume !(1 == ~E_6~0); 34272#L1001-1 assume !(1 == ~E_7~0); 34014#L1006-1 assume !(1 == ~E_8~0); 34015#L1011-1 assume { :end_inline_reset_delta_events } true; 37017#L1272-2 [2024-11-13 13:53:39,799 INFO L747 eck$LassoCheckResult]: Loop: 37017#L1272-2 assume !false; 37010#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37005#L813-1 assume !false; 37004#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 36998#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 36990#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 33727#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33728#L696 assume !(0 != eval_~tmp~0#1); 34195#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37847#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37844#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37842#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37840#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37838#L848-3 assume !(0 == ~T3_E~0); 37837#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37824#L858-3 assume !(0 == ~T5_E~0); 37821#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37819#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37815#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37812#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37809#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37807#L888-3 assume !(0 == ~E_3~0); 37804#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37803#L898-3 assume !(0 == ~E_5~0); 37802#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37800#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37797#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37794#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37791#L402-27 assume 1 == ~m_pc~0; 37786#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 37782#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37778#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 37774#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37770#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37766#L421-27 assume !(1 == ~t1_pc~0); 37762#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 37758#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37753#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 37749#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37745#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37741#L440-27 assume !(1 == ~t2_pc~0); 37737#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 37733#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37728#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 37724#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37719#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37715#L459-27 assume !(1 == ~t3_pc~0); 37709#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 37705#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37700#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 37696#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37692#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37687#L478-27 assume 1 == ~t4_pc~0; 37681#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37676#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37670#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37665#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37630#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37627#L497-27 assume !(1 == ~t5_pc~0); 37624#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 37622#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37620#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37618#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37616#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37614#L516-27 assume 1 == ~t6_pc~0; 37611#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37609#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37607#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37605#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 37603#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37601#L535-27 assume 1 == ~t7_pc~0; 37597#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37595#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37593#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37591#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37588#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37585#L554-27 assume 1 == ~t8_pc~0; 37582#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37580#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37578#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37576#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37574#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37571#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37569#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37567#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37517#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37564#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37562#L951-3 assume !(1 == ~T5_E~0); 37561#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37492#L961-3 assume !(1 == ~T7_E~0); 37485#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37479#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37473#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37467#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37461#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37455#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37447#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37442#L1001-3 assume !(1 == ~E_7~0); 37436#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37432#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 37282#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 37267#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 37261#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 37253#L1291 assume !(0 == start_simulation_~tmp~3#1); 37245#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 37201#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 37191#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 37041#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 37040#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37038#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37035#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 37025#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 37017#L1272-2 [2024-11-13 13:53:39,800 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:39,800 INFO L85 PathProgramCache]: Analyzing trace with hash -1412932446, now seen corresponding path program 1 times [2024-11-13 13:53:39,800 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:39,800 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [858778467] [2024-11-13 13:53:39,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:39,800 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:39,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:39,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:39,884 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:39,884 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [858778467] [2024-11-13 13:53:39,884 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [858778467] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:39,884 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:39,884 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:53:39,884 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1504301174] [2024-11-13 13:53:39,884 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:39,885 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:39,885 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:39,885 INFO L85 PathProgramCache]: Analyzing trace with hash 312694293, now seen corresponding path program 1 times [2024-11-13 13:53:39,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:39,885 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1181584] [2024-11-13 13:53:39,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:39,886 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:39,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:39,937 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:39,937 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:39,937 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1181584] [2024-11-13 13:53:39,937 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1181584] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:39,937 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:39,937 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:39,937 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [890884984] [2024-11-13 13:53:39,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:39,938 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:39,938 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:39,939 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:53:39,939 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:53:39,940 INFO L87 Difference]: Start difference. First operand 5818 states and 8477 transitions. cyclomatic complexity: 2667 Second operand has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:40,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:40,298 INFO L93 Difference]: Finished difference Result 6025 states and 8684 transitions. [2024-11-13 13:53:40,298 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6025 states and 8684 transitions. [2024-11-13 13:53:40,335 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5880 [2024-11-13 13:53:40,379 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6025 states to 6025 states and 8684 transitions. [2024-11-13 13:53:40,379 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6025 [2024-11-13 13:53:40,386 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6025 [2024-11-13 13:53:40,387 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6025 states and 8684 transitions. [2024-11-13 13:53:40,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:40,396 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6025 states and 8684 transitions. [2024-11-13 13:53:40,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6025 states and 8684 transitions. [2024-11-13 13:53:40,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6025 to 6025. [2024-11-13 13:53:40,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6025 states, 6025 states have (on average 1.4413278008298755) internal successors, (8684), 6024 states have internal predecessors, (8684), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:40,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6025 states to 6025 states and 8684 transitions. [2024-11-13 13:53:40,547 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6025 states and 8684 transitions. [2024-11-13 13:53:40,548 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:53:40,548 INFO L424 stractBuchiCegarLoop]: Abstraction has 6025 states and 8684 transitions. [2024-11-13 13:53:40,549 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 13:53:40,549 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6025 states and 8684 transitions. [2024-11-13 13:53:40,579 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5880 [2024-11-13 13:53:40,579 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:40,580 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:40,581 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:40,581 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:40,582 INFO L745 eck$LassoCheckResult]: Stem: 45419#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 45420#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 46189#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46190#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46191#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 45544#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45545#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46183#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46167#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45630#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 45631#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45891#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45892#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45723#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45724#L838 assume !(0 == ~M_E~0); 45901#L838-2 assume !(0 == ~T1_E~0); 45215#L843-1 assume !(0 == ~T2_E~0); 45216#L848-1 assume !(0 == ~T3_E~0); 45336#L853-1 assume !(0 == ~T4_E~0); 45712#L858-1 assume !(0 == ~T5_E~0); 45169#L863-1 assume !(0 == ~T6_E~0); 45170#L868-1 assume !(0 == ~T7_E~0); 46247#L873-1 assume !(0 == ~T8_E~0); 46243#L878-1 assume !(0 == ~E_1~0); 46218#L883-1 assume !(0 == ~E_2~0); 46219#L888-1 assume !(0 == ~E_3~0); 45859#L893-1 assume !(0 == ~E_4~0); 45860#L898-1 assume !(0 == ~E_5~0); 46270#L903-1 assume !(0 == ~E_6~0); 46216#L908-1 assume !(0 == ~E_7~0); 46016#L913-1 assume !(0 == ~E_8~0); 45228#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45229#L402 assume !(1 == ~m_pc~0); 45447#L402-2 is_master_triggered_~__retres1~0#1 := 0; 45361#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45362#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45637#L1035 assume !(0 != activate_threads_~tmp~1#1); 45638#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45695#L421 assume !(1 == ~t1_pc~0); 46211#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46254#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45230#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 45231#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 45753#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46264#L440 assume !(1 == ~t2_pc~0); 46322#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45371#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45372#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 45572#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 46038#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45582#L459 assume !(1 == ~t3_pc~0); 45583#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46207#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45189#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 45190#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 45355#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45365#L478 assume 1 == ~t4_pc~0; 45366#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45863#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45307#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45308#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 45271#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45272#L497 assume !(1 == ~t5_pc~0); 45318#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 45319#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45947#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46098#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 46202#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46203#L516 assume 1 == ~t6_pc~0; 46313#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45890#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45554#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45413#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 45414#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45878#L535 assume !(1 == ~t7_pc~0); 45879#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 45962#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45963#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46006#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 45997#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45998#L554 assume 1 == ~t8_pc~0; 45917#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45192#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46028#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45508#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 45509#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45178#L931 assume !(1 == ~M_E~0); 45179#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46231#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46281#L941-1 assume !(1 == ~T3_E~0); 45696#L946-1 assume !(1 == ~T4_E~0); 45697#L951-1 assume !(1 == ~T5_E~0); 49823#L956-1 assume !(1 == ~T6_E~0); 46314#L961-1 assume !(1 == ~T7_E~0); 46315#L966-1 assume !(1 == ~T8_E~0); 49822#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 46294#L976-1 assume !(1 == ~E_2~0); 46295#L981-1 assume !(1 == ~E_3~0); 45701#L986-1 assume !(1 == ~E_4~0); 45702#L991-1 assume !(1 == ~E_5~0); 45458#L996-1 assume !(1 == ~E_6~0); 46260#L1001-1 assume !(1 == ~E_7~0); 45911#L1006-1 assume !(1 == ~E_8~0); 45912#L1011-1 assume { :end_inline_reset_delta_events } true; 45238#L1272-2 [2024-11-13 13:53:40,582 INFO L747 eck$LassoCheckResult]: Loop: 45238#L1272-2 assume !false; 45239#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45483#L813-1 assume !false; 46133#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 46134#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 45242#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 45594#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 45595#L696 assume !(0 != eval_~tmp~0#1); 46146#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49778#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49777#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49776#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 49775#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 49774#L848-3 assume !(0 == ~T3_E~0); 49773#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49772#L858-3 assume !(0 == ~T5_E~0); 49770#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49769#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49768#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49767#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49766#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49765#L888-3 assume !(0 == ~E_3~0); 49764#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 49763#L898-3 assume !(0 == ~E_5~0); 49762#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 49761#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 49760#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49759#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49758#L402-27 assume 1 == ~m_pc~0; 49756#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 49755#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49754#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 49753#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49752#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49751#L421-27 assume !(1 == ~t1_pc~0); 49750#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 49749#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49748#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 49747#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49746#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49745#L440-27 assume !(1 == ~t2_pc~0); 49744#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 49743#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49742#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 49741#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49740#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49737#L459-27 assume !(1 == ~t3_pc~0); 49735#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 49734#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49733#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49732#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 49729#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49727#L478-27 assume 1 == ~t4_pc~0; 49723#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49721#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49719#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49717#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49715#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49713#L497-27 assume !(1 == ~t5_pc~0); 49710#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 49708#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49706#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49704#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49702#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49700#L516-27 assume 1 == ~t6_pc~0; 49697#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49695#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49693#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49691#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 49689#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49685#L535-27 assume 1 == ~t7_pc~0; 49682#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49680#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49678#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49675#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49673#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49671#L554-27 assume 1 == ~t8_pc~0; 49667#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49665#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49663#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49661#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49659#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49657#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49654#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49652#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 49467#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49649#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49647#L951-3 assume !(1 == ~T5_E~0); 49646#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 45832#L961-3 assume !(1 == ~T7_E~0); 45615#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 45616#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46220#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48498#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48497#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48496#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 48495#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46140#L1001-3 assume !(1 == ~E_7~0); 45580#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45581#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 45264#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 45265#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 45524#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 45525#L1291 assume !(0 == start_simulation_~tmp~3#1); 45828#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 45719#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 45171#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 45172#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 45227#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 45678#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 45679#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 45773#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 45238#L1272-2 [2024-11-13 13:53:40,583 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:40,583 INFO L85 PathProgramCache]: Analyzing trace with hash -1894012704, now seen corresponding path program 1 times [2024-11-13 13:53:40,583 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:40,583 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1762312069] [2024-11-13 13:53:40,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:40,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:40,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:40,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:40,657 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:40,657 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1762312069] [2024-11-13 13:53:40,658 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1762312069] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:40,658 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:40,658 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:53:40,658 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [919545795] [2024-11-13 13:53:40,658 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:40,658 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:40,659 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:40,660 INFO L85 PathProgramCache]: Analyzing trace with hash 991966547, now seen corresponding path program 1 times [2024-11-13 13:53:40,660 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:40,661 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [8388236] [2024-11-13 13:53:40,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:40,661 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:40,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:40,721 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:40,721 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:40,721 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [8388236] [2024-11-13 13:53:40,721 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [8388236] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:40,721 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:40,722 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:40,722 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [492039315] [2024-11-13 13:53:40,722 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:40,722 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:40,722 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:40,722 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:53:40,723 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:53:40,723 INFO L87 Difference]: Start difference. First operand 6025 states and 8684 transitions. cyclomatic complexity: 2667 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:40,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:40,935 INFO L93 Difference]: Finished difference Result 11580 states and 16593 transitions. [2024-11-13 13:53:40,935 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11580 states and 16593 transitions. [2024-11-13 13:53:41,014 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11404 [2024-11-13 13:53:41,079 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11580 states to 11580 states and 16593 transitions. [2024-11-13 13:53:41,080 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11580 [2024-11-13 13:53:41,094 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11580 [2024-11-13 13:53:41,094 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11580 states and 16593 transitions. [2024-11-13 13:53:41,116 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:41,116 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11580 states and 16593 transitions. [2024-11-13 13:53:41,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11580 states and 16593 transitions. [2024-11-13 13:53:41,375 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11580 to 11564. [2024-11-13 13:53:41,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11564 states, 11564 states have (on average 1.4335005188516083) internal successors, (16577), 11563 states have internal predecessors, (16577), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:41,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11564 states to 11564 states and 16577 transitions. [2024-11-13 13:53:41,454 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11564 states and 16577 transitions. [2024-11-13 13:53:41,455 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:53:41,456 INFO L424 stractBuchiCegarLoop]: Abstraction has 11564 states and 16577 transitions. [2024-11-13 13:53:41,456 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 13:53:41,456 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11564 states and 16577 transitions. [2024-11-13 13:53:41,509 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11388 [2024-11-13 13:53:41,509 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:41,509 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:41,511 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:41,511 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:41,511 INFO L745 eck$LassoCheckResult]: Stem: 63028#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 63029#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 63738#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 63739#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63741#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 63149#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63150#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63731#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63725#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63227#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 63228#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 63473#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 63474#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 63315#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63316#L838 assume !(0 == ~M_E~0); 63482#L838-2 assume !(0 == ~T1_E~0); 62827#L843-1 assume !(0 == ~T2_E~0); 62828#L848-1 assume !(0 == ~T3_E~0); 62946#L853-1 assume !(0 == ~T4_E~0); 63302#L858-1 assume !(0 == ~T5_E~0); 62779#L863-1 assume !(0 == ~T6_E~0); 62780#L868-1 assume !(0 == ~T7_E~0); 63789#L873-1 assume !(0 == ~T8_E~0); 63787#L878-1 assume !(0 == ~E_1~0); 63767#L883-1 assume !(0 == ~E_2~0); 63768#L888-1 assume !(0 == ~E_3~0); 63440#L893-1 assume !(0 == ~E_4~0); 63441#L898-1 assume !(0 == ~E_5~0); 63809#L903-1 assume !(0 == ~E_6~0); 63765#L908-1 assume !(0 == ~E_7~0); 63584#L913-1 assume !(0 == ~E_8~0); 62839#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62840#L402 assume !(1 == ~m_pc~0); 63052#L402-2 is_master_triggered_~__retres1~0#1 := 0; 62973#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62974#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 63233#L1035 assume !(0 != activate_threads_~tmp~1#1); 63234#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63289#L421 assume !(1 == ~t1_pc~0); 63758#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63790#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62842#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 62843#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 63346#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63801#L440 assume !(1 == ~t2_pc~0); 63859#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 62982#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62983#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 63175#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 63606#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63178#L459 assume !(1 == ~t3_pc~0); 63179#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 63753#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62801#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 62802#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 62967#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62977#L478 assume !(1 == ~t4_pc~0); 62978#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 63665#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62918#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 62919#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 62880#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62881#L497 assume !(1 == ~t5_pc~0); 62929#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 62930#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63523#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 63660#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 63748#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63749#L516 assume 1 == ~t6_pc~0; 63847#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 63472#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63158#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63022#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 63023#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63461#L535 assume !(1 == ~t7_pc~0); 63462#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 63539#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63540#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63574#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 63563#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 63564#L554 assume 1 == ~t8_pc~0; 63499#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 62804#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 63596#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63112#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 63113#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62790#L931 assume !(1 == ~M_E~0); 62791#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 63778#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63819#L941-1 assume !(1 == ~T3_E~0); 63290#L946-1 assume !(1 == ~T4_E~0); 63291#L951-1 assume !(1 == ~T5_E~0); 63038#L956-1 assume !(1 == ~T6_E~0); 63039#L961-1 assume !(1 == ~T7_E~0); 63442#L966-1 assume !(1 == ~T8_E~0); 63443#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 63827#L976-1 assume !(1 == ~E_2~0); 63828#L981-1 assume !(1 == ~E_3~0); 63294#L986-1 assume !(1 == ~E_4~0); 63295#L991-1 assume !(1 == ~E_5~0); 63066#L996-1 assume !(1 == ~E_6~0); 70249#L1001-1 assume !(1 == ~E_7~0); 70247#L1006-1 assume !(1 == ~E_8~0); 70244#L1011-1 assume { :end_inline_reset_delta_events } true; 70241#L1272-2 [2024-11-13 13:53:41,512 INFO L747 eck$LassoCheckResult]: Loop: 70241#L1272-2 assume !false; 70239#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 70235#L813-1 assume !false; 70234#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 70229#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 70223#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 70220#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 70217#L696 assume !(0 != eval_~tmp~0#1); 70218#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 72013#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 72012#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 72011#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 72009#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 72010#L848-3 assume !(0 == ~T3_E~0); 63444#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 63445#L858-3 assume !(0 == ~T5_E~0); 72887#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 63503#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 63504#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 72886#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 62814#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 62815#L888-3 assume !(0 == ~E_3~0); 62816#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 62817#L898-3 assume !(0 == ~E_5~0); 63322#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 63689#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 63330#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 62855#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62856#L402-27 assume 1 == ~m_pc~0; 62805#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 62806#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63541#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 63542#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 63713#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63714#L421-27 assume !(1 == ~t1_pc~0); 63081#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 63082#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63416#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 63417#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 63798#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63464#L440-27 assume !(1 == ~t2_pc~0); 63465#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 63683#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63508#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 63367#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 63368#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63069#L459-27 assume !(1 == ~t3_pc~0); 63070#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 63729#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63341#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 63342#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 63460#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63788#L478-27 assume !(1 == ~t4_pc~0); 63057#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 63058#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63249#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63250#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 63637#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63690#L497-27 assume 1 == ~t5_pc~0; 63691#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63100#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63101#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 63044#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 63045#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63324#L516-27 assume !(1 == ~t6_pc~0); 63325#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 63165#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63166#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63484#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 63485#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63253#L535-27 assume 1 == ~t7_pc~0; 63254#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 63612#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63127#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63128#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 63199#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 63200#L554-27 assume 1 == ~t8_pc~0; 63413#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 62830#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62981#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63375#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 63088#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63089#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 62963#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 62964#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63197#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 63340#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 63106#L951-3 assume !(1 == ~T5_E~0); 63107#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 63414#L961-3 assume !(1 == ~T7_E~0); 63212#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 63213#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 63471#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 62848#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 62849#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 62837#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 62838#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 63554#L1001-3 assume !(1 == ~E_7~0); 63184#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 63185#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 62875#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 62876#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 63133#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 63134#L1291 assume !(0 == start_simulation_~tmp~3#1); 70277#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 70275#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 70266#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 70263#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 70259#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 70255#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70251#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 70243#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 70241#L1272-2 [2024-11-13 13:53:41,512 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:41,512 INFO L85 PathProgramCache]: Analyzing trace with hash -461177985, now seen corresponding path program 1 times [2024-11-13 13:53:41,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:41,513 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1357969605] [2024-11-13 13:53:41,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:41,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:41,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:41,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:41,577 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:41,577 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1357969605] [2024-11-13 13:53:41,578 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1357969605] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:41,578 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:41,578 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:53:41,579 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [199397300] [2024-11-13 13:53:41,579 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:41,579 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:41,580 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:41,580 INFO L85 PathProgramCache]: Analyzing trace with hash 415515826, now seen corresponding path program 1 times [2024-11-13 13:53:41,580 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:41,580 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926194478] [2024-11-13 13:53:41,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:41,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:41,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:41,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:41,632 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:41,632 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [926194478] [2024-11-13 13:53:41,632 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [926194478] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:41,633 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:41,633 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:41,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1822030435] [2024-11-13 13:53:41,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:41,633 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:41,633 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:41,634 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:53:41,634 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:53:41,634 INFO L87 Difference]: Start difference. First operand 11564 states and 16577 transitions. cyclomatic complexity: 5029 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:41,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:41,856 INFO L93 Difference]: Finished difference Result 21803 states and 31130 transitions. [2024-11-13 13:53:41,857 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21803 states and 31130 transitions. [2024-11-13 13:53:42,054 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21548 [2024-11-13 13:53:42,128 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21803 states to 21803 states and 31130 transitions. [2024-11-13 13:53:42,128 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21803 [2024-11-13 13:53:42,150 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21803 [2024-11-13 13:53:42,151 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21803 states and 31130 transitions. [2024-11-13 13:53:42,177 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:42,178 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21803 states and 31130 transitions. [2024-11-13 13:53:42,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21803 states and 31130 transitions. [2024-11-13 13:53:42,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21803 to 21771. [2024-11-13 13:53:42,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21771 states, 21771 states have (on average 1.4284139451564006) internal successors, (31098), 21770 states have internal predecessors, (31098), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:42,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21771 states to 21771 states and 31098 transitions. [2024-11-13 13:53:42,567 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21771 states and 31098 transitions. [2024-11-13 13:53:42,567 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:53:42,567 INFO L424 stractBuchiCegarLoop]: Abstraction has 21771 states and 31098 transitions. [2024-11-13 13:53:42,568 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 13:53:42,568 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21771 states and 31098 transitions. [2024-11-13 13:53:42,636 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21516 [2024-11-13 13:53:42,637 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:42,637 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:42,639 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:42,639 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:42,639 INFO L745 eck$LassoCheckResult]: Stem: 96399#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 96400#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 97085#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 97086#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 97088#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 96517#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96518#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 97081#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 97074#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 96595#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 96596#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 96842#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 96843#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 96680#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96681#L838 assume !(0 == ~M_E~0); 96851#L838-2 assume !(0 == ~T1_E~0); 96199#L843-1 assume !(0 == ~T2_E~0); 96200#L848-1 assume !(0 == ~T3_E~0); 96319#L853-1 assume !(0 == ~T4_E~0); 96667#L858-1 assume !(0 == ~T5_E~0); 96153#L863-1 assume !(0 == ~T6_E~0); 96154#L868-1 assume !(0 == ~T7_E~0); 97133#L873-1 assume !(0 == ~T8_E~0); 97130#L878-1 assume !(0 == ~E_1~0); 97112#L883-1 assume !(0 == ~E_2~0); 97113#L888-1 assume !(0 == ~E_3~0); 96811#L893-1 assume !(0 == ~E_4~0); 96812#L898-1 assume !(0 == ~E_5~0); 97152#L903-1 assume !(0 == ~E_6~0); 97109#L908-1 assume !(0 == ~E_7~0); 96950#L913-1 assume !(0 == ~E_8~0); 96211#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96212#L402 assume !(1 == ~m_pc~0); 96423#L402-2 is_master_triggered_~__retres1~0#1 := 0; 96343#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96344#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 96601#L1035 assume !(0 != activate_threads_~tmp~1#1); 96602#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96654#L421 assume !(1 == ~t1_pc~0); 97104#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 97135#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 96214#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 96215#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 96710#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 97149#L440 assume !(1 == ~t2_pc~0); 97199#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 96353#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96354#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 96544#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 96966#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96547#L459 assume !(1 == ~t3_pc~0); 96548#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 97101#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 96175#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 96176#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 96338#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96347#L478 assume !(1 == ~t4_pc~0); 96348#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 97021#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96290#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 96291#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 96252#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96253#L497 assume !(1 == ~t5_pc~0); 96301#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 96302#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96893#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 97016#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 97096#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 97097#L516 assume !(1 == ~t6_pc~0); 97036#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 96841#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 96527#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 96393#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 96394#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 96830#L535 assume !(1 == ~t7_pc~0); 96831#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 96908#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 96909#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 96942#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 96931#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96932#L554 assume 1 == ~t8_pc~0; 96869#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 96178#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96958#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 96480#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 96481#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96164#L931 assume !(1 == ~M_E~0); 96165#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 97124#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 97161#L941-1 assume !(1 == ~T3_E~0); 96655#L946-1 assume !(1 == ~T4_E~0); 96656#L951-1 assume !(1 == ~T5_E~0); 96409#L956-1 assume !(1 == ~T6_E~0); 96410#L961-1 assume !(1 == ~T7_E~0); 103192#L966-1 assume !(1 == ~T8_E~0); 96934#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 96935#L976-1 assume !(1 == ~E_2~0); 103185#L981-1 assume !(1 == ~E_3~0); 96659#L986-1 assume !(1 == ~E_4~0); 96660#L991-1 assume !(1 == ~E_5~0); 96437#L996-1 assume !(1 == ~E_6~0); 103055#L1001-1 assume !(1 == ~E_7~0); 96864#L1006-1 assume !(1 == ~E_8~0); 96865#L1011-1 assume { :end_inline_reset_delta_events } true; 97102#L1272-2 [2024-11-13 13:53:42,640 INFO L747 eck$LassoCheckResult]: Loop: 97102#L1272-2 assume !false; 103269#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 103264#L813-1 assume !false; 103262#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 103106#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 103100#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 103098#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 103095#L696 assume !(0 != eval_~tmp~0#1); 103096#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 104143#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 104141#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 104139#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 104137#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 104135#L848-3 assume !(0 == ~T3_E~0); 104133#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 104131#L858-3 assume !(0 == ~T5_E~0); 104129#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 104127#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 104125#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 104123#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 104121#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 104119#L888-3 assume !(0 == ~E_3~0); 104117#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 104114#L898-3 assume !(0 == ~E_5~0); 104110#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 104107#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 104104#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 104101#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 104098#L402-27 assume !(1 == ~m_pc~0); 104095#L402-29 is_master_triggered_~__retres1~0#1 := 0; 104091#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 104088#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 104085#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 104082#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 104079#L421-27 assume !(1 == ~t1_pc~0); 104076#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 104073#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 104070#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 104067#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 104064#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 104061#L440-27 assume !(1 == ~t2_pc~0); 104058#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 104054#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 104049#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 104045#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 104041#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 104038#L459-27 assume !(1 == ~t3_pc~0); 104035#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 104031#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 104027#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 104023#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 104019#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 104016#L478-27 assume !(1 == ~t4_pc~0); 104013#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 104009#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 104005#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 104002#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 103999#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 103995#L497-27 assume 1 == ~t5_pc~0; 103989#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 103984#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 103979#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 103973#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 103967#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 103960#L516-27 assume !(1 == ~t6_pc~0); 103955#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 103949#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 103944#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 103939#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 103934#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 103929#L535-27 assume 1 == ~t7_pc~0; 103923#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 103917#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 103911#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 103906#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 103902#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 103896#L554-27 assume !(1 == ~t8_pc~0); 103891#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 103884#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 103879#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 103877#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 103875#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103873#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 103870#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 103866#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 103816#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 103861#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 103858#L951-3 assume !(1 == ~T5_E~0); 103855#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 103852#L961-3 assume !(1 == ~T7_E~0); 103849#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 103846#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 103843#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 103840#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 103837#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 103834#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 103769#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 103827#L1001-3 assume !(1 == ~E_7~0); 103823#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 103819#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 103313#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 103303#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 103301#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 103298#L1291 assume !(0 == start_simulation_~tmp~3#1); 103295#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 103293#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 103283#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 103281#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 103278#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 103276#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 103274#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 103272#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 97102#L1272-2 [2024-11-13 13:53:42,640 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:42,641 INFO L85 PathProgramCache]: Analyzing trace with hash 2068972702, now seen corresponding path program 1 times [2024-11-13 13:53:42,641 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:42,641 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [790425199] [2024-11-13 13:53:42,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:42,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:42,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:42,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:42,713 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:42,713 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [790425199] [2024-11-13 13:53:42,713 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [790425199] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:42,713 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:42,713 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:53:42,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1694722212] [2024-11-13 13:53:42,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:42,714 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:42,714 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:42,714 INFO L85 PathProgramCache]: Analyzing trace with hash -1804206864, now seen corresponding path program 1 times [2024-11-13 13:53:42,715 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:42,715 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [772982048] [2024-11-13 13:53:42,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:42,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:42,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:42,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:42,795 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:42,795 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [772982048] [2024-11-13 13:53:42,795 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [772982048] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:42,795 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:42,795 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:42,796 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2010646635] [2024-11-13 13:53:42,796 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:42,796 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:42,796 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:42,796 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:53:42,797 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:53:42,798 INFO L87 Difference]: Start difference. First operand 21771 states and 31098 transitions. cyclomatic complexity: 9359 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:43,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:43,186 INFO L93 Difference]: Finished difference Result 43134 states and 61227 transitions. [2024-11-13 13:53:43,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43134 states and 61227 transitions. [2024-11-13 13:53:43,363 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 42688 [2024-11-13 13:53:43,538 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43134 states to 43134 states and 61227 transitions. [2024-11-13 13:53:43,539 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43134 [2024-11-13 13:53:43,583 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43134 [2024-11-13 13:53:43,584 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43134 states and 61227 transitions. [2024-11-13 13:53:43,638 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:43,638 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43134 states and 61227 transitions. [2024-11-13 13:53:43,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43134 states and 61227 transitions. [2024-11-13 13:53:44,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43134 to 43006. [2024-11-13 13:53:44,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43006 states, 43006 states have (on average 1.4199646560944985) internal successors, (61067), 43005 states have internal predecessors, (61067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:44,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43006 states to 43006 states and 61067 transitions. [2024-11-13 13:53:44,782 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43006 states and 61067 transitions. [2024-11-13 13:53:44,782 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:53:44,783 INFO L424 stractBuchiCegarLoop]: Abstraction has 43006 states and 61067 transitions. [2024-11-13 13:53:44,783 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 13:53:44,783 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43006 states and 61067 transitions. [2024-11-13 13:53:44,942 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 42624 [2024-11-13 13:53:44,942 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:44,943 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:45,077 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:45,077 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:45,077 INFO L745 eck$LassoCheckResult]: Stem: 161314#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 161315#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 162022#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 162023#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 162025#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 161436#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 161437#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 162019#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 162013#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 161516#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 161517#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 161769#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 161770#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 161606#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 161607#L838 assume !(0 == ~M_E~0); 161781#L838-2 assume !(0 == ~T1_E~0); 161113#L843-1 assume !(0 == ~T2_E~0); 161114#L848-1 assume !(0 == ~T3_E~0); 161232#L853-1 assume !(0 == ~T4_E~0); 161595#L858-1 assume !(0 == ~T5_E~0); 161067#L863-1 assume !(0 == ~T6_E~0); 161068#L868-1 assume !(0 == ~T7_E~0); 162076#L873-1 assume !(0 == ~T8_E~0); 162074#L878-1 assume !(0 == ~E_1~0); 162055#L883-1 assume !(0 == ~E_2~0); 162056#L888-1 assume !(0 == ~E_3~0); 161737#L893-1 assume !(0 == ~E_4~0); 161738#L898-1 assume !(0 == ~E_5~0); 162093#L903-1 assume !(0 == ~E_6~0); 162052#L908-1 assume !(0 == ~E_7~0); 161887#L913-1 assume !(0 == ~E_8~0); 161126#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 161127#L402 assume !(1 == ~m_pc~0); 161342#L402-2 is_master_triggered_~__retres1~0#1 := 0; 161258#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 161259#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 161523#L1035 assume !(0 != activate_threads_~tmp~1#1); 161524#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 161579#L421 assume !(1 == ~t1_pc~0); 162045#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 162080#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 161128#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 161129#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 161636#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 162089#L440 assume !(1 == ~t2_pc~0); 162134#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 161268#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 161269#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 161465#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 161902#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 161473#L459 assume !(1 == ~t3_pc~0); 161474#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 162041#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 161087#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 161088#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 161253#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 161262#L478 assume !(1 == ~t4_pc~0); 161263#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 161957#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 161204#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 161205#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 161168#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 161169#L497 assume !(1 == ~t5_pc~0); 161215#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 161216#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 161818#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 161953#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 162035#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 162036#L516 assume !(1 == ~t6_pc~0); 161972#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 161768#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 161446#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 161308#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 161309#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 161756#L535 assume !(1 == ~t7_pc~0); 161757#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 161833#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 161834#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 161874#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 161865#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 161866#L554 assume !(1 == ~t8_pc~0); 161089#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 161090#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 161896#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 161398#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 161399#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 161076#L931 assume !(1 == ~M_E~0); 161077#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 162068#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 162103#L941-1 assume !(1 == ~T3_E~0); 168003#L946-1 assume !(1 == ~T4_E~0); 168002#L951-1 assume !(1 == ~T5_E~0); 168001#L956-1 assume !(1 == ~T6_E~0); 168000#L961-1 assume !(1 == ~T7_E~0); 167999#L966-1 assume !(1 == ~T8_E~0); 167998#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 167997#L976-1 assume !(1 == ~E_2~0); 167996#L981-1 assume !(1 == ~E_3~0); 167995#L986-1 assume !(1 == ~E_4~0); 167994#L991-1 assume !(1 == ~E_5~0); 161352#L996-1 assume !(1 == ~E_6~0); 167991#L1001-1 assume !(1 == ~E_7~0); 167987#L1006-1 assume !(1 == ~E_8~0); 167983#L1011-1 assume { :end_inline_reset_delta_events } true; 167978#L1272-2 [2024-11-13 13:53:45,078 INFO L747 eck$LassoCheckResult]: Loop: 167978#L1272-2 assume !false; 167977#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 167973#L813-1 assume !false; 167972#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 167961#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 167955#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 167953#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 167950#L696 assume !(0 != eval_~tmp~0#1); 167951#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 168330#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 168328#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 168326#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 168324#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 168322#L848-3 assume !(0 == ~T3_E~0); 168320#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 168318#L858-3 assume !(0 == ~T5_E~0); 168316#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 168314#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 168312#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 168310#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 168309#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 168305#L888-3 assume !(0 == ~E_3~0); 168303#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 168301#L898-3 assume !(0 == ~E_5~0); 168299#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 168296#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 168294#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 168292#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 168290#L402-27 assume !(1 == ~m_pc~0); 168288#L402-29 is_master_triggered_~__retres1~0#1 := 0; 168285#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 168283#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 168281#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 168279#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 168276#L421-27 assume !(1 == ~t1_pc~0); 168274#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 168272#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 168270#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 168268#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 168266#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 168264#L440-27 assume !(1 == ~t2_pc~0); 168262#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 168260#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 168258#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 168256#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 168254#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 168248#L459-27 assume !(1 == ~t3_pc~0); 168246#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 168244#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 168242#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 168240#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 168237#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 168235#L478-27 assume !(1 == ~t4_pc~0); 168233#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 168231#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 168229#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 168227#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 168225#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 168224#L497-27 assume !(1 == ~t5_pc~0); 168222#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 168221#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 168220#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 168219#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 168218#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 168216#L516-27 assume !(1 == ~t6_pc~0); 168213#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 168211#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 168209#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 168207#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 168205#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 168203#L535-27 assume 1 == ~t7_pc~0; 168200#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 168198#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 168196#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 168194#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 168192#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 168190#L554-27 assume !(1 == ~t8_pc~0); 168188#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 168186#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 168184#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 168182#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 168180#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 168176#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 168174#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 168172#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 168168#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 168165#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 168163#L951-3 assume !(1 == ~T5_E~0); 168161#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 168159#L961-3 assume !(1 == ~T7_E~0); 168157#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 168155#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 168153#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 168151#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 168149#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 168146#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 168142#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 168140#L1001-3 assume !(1 == ~E_7~0); 168138#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 168136#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 168134#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 168124#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 168122#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 168119#L1291 assume !(0 == start_simulation_~tmp~3#1); 168116#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 168114#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 168104#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 168101#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 168099#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 168097#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 168095#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 167982#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 167978#L1272-2 [2024-11-13 13:53:45,078 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:45,078 INFO L85 PathProgramCache]: Analyzing trace with hash 478577725, now seen corresponding path program 1 times [2024-11-13 13:53:45,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:45,079 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882083578] [2024-11-13 13:53:45,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:45,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:45,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:45,160 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:45,160 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:45,160 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882083578] [2024-11-13 13:53:45,160 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882083578] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:45,160 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:45,161 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:53:45,161 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1816797875] [2024-11-13 13:53:45,161 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:45,161 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:45,161 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:45,161 INFO L85 PathProgramCache]: Analyzing trace with hash -1701405617, now seen corresponding path program 1 times [2024-11-13 13:53:45,161 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:45,161 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [645308965] [2024-11-13 13:53:45,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:45,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:45,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:45,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:45,221 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:45,221 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [645308965] [2024-11-13 13:53:45,221 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [645308965] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:45,221 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:45,221 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:45,221 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [305902065] [2024-11-13 13:53:45,221 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:45,222 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:45,222 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:45,222 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:53:45,222 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:53:45,222 INFO L87 Difference]: Start difference. First operand 43006 states and 61067 transitions. cyclomatic complexity: 18125 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:45,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:45,362 INFO L93 Difference]: Finished difference Result 43006 states and 60873 transitions. [2024-11-13 13:53:45,363 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43006 states and 60873 transitions. [2024-11-13 13:53:45,688 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 42624 [2024-11-13 13:53:45,842 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43006 states to 43006 states and 60873 transitions. [2024-11-13 13:53:45,842 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43006 [2024-11-13 13:53:45,869 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43006 [2024-11-13 13:53:45,869 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43006 states and 60873 transitions. [2024-11-13 13:53:45,901 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:45,901 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43006 states and 60873 transitions. [2024-11-13 13:53:45,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43006 states and 60873 transitions. [2024-11-13 13:53:46,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43006 to 43006. [2024-11-13 13:53:46,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43006 states, 43006 states have (on average 1.415453657629168) internal successors, (60873), 43005 states have internal predecessors, (60873), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:46,761 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43006 states to 43006 states and 60873 transitions. [2024-11-13 13:53:46,761 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43006 states and 60873 transitions. [2024-11-13 13:53:46,762 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:53:46,762 INFO L424 stractBuchiCegarLoop]: Abstraction has 43006 states and 60873 transitions. [2024-11-13 13:53:46,762 INFO L331 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-13 13:53:46,762 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43006 states and 60873 transitions. [2024-11-13 13:53:46,926 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 42624 [2024-11-13 13:53:46,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:46,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:46,928 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:46,928 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:46,929 INFO L745 eck$LassoCheckResult]: Stem: 247335#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 247336#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 248040#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 248041#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 248042#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 247454#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 247455#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 248033#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 248023#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 247531#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 247532#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 247776#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 247777#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 247616#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 247617#L838 assume !(0 == ~M_E~0); 247786#L838-2 assume !(0 == ~T1_E~0); 247130#L843-1 assume !(0 == ~T2_E~0); 247131#L848-1 assume !(0 == ~T3_E~0); 247252#L853-1 assume !(0 == ~T4_E~0); 247603#L858-1 assume !(0 == ~T5_E~0); 247084#L863-1 assume !(0 == ~T6_E~0); 247085#L868-1 assume !(0 == ~T7_E~0); 248088#L873-1 assume !(0 == ~T8_E~0); 248086#L878-1 assume !(0 == ~E_1~0); 248069#L883-1 assume !(0 == ~E_2~0); 248070#L888-1 assume !(0 == ~E_3~0); 247744#L893-1 assume !(0 == ~E_4~0); 247745#L898-1 assume !(0 == ~E_5~0); 248103#L903-1 assume !(0 == ~E_6~0); 248067#L908-1 assume !(0 == ~E_7~0); 247887#L913-1 assume !(0 == ~E_8~0); 247143#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 247144#L402 assume !(1 == ~m_pc~0); 247359#L402-2 is_master_triggered_~__retres1~0#1 := 0; 247279#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 247280#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 247537#L1035 assume !(0 != activate_threads_~tmp~1#1); 247538#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 247591#L421 assume !(1 == ~t1_pc~0); 248063#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 248089#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 247146#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 247147#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 247643#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 248097#L440 assume !(1 == ~t2_pc~0); 248155#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 247289#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 247290#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 247480#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 247908#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 247483#L459 assume !(1 == ~t3_pc~0); 247484#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 248056#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247106#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 247107#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 247273#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 247283#L478 assume !(1 == ~t4_pc~0); 247284#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 247965#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 247223#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 247224#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 247184#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 247185#L497 assume !(1 == ~t5_pc~0); 247234#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 247235#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 247827#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 247960#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 248049#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 248050#L516 assume !(1 == ~t6_pc~0); 247979#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 247775#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 247464#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 247329#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 247330#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 247763#L535 assume !(1 == ~t7_pc~0); 247764#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 247843#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 247844#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 247878#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 247867#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 247868#L554 assume !(1 == ~t8_pc~0); 247108#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 247109#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 247899#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 247417#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 247418#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 247095#L931 assume !(1 == ~M_E~0); 247096#L931-2 assume !(1 == ~T1_E~0); 248081#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 248113#L941-1 assume !(1 == ~T3_E~0); 252387#L946-1 assume !(1 == ~T4_E~0); 252385#L951-1 assume !(1 == ~T5_E~0); 252383#L956-1 assume !(1 == ~T6_E~0); 252381#L961-1 assume !(1 == ~T7_E~0); 252379#L966-1 assume !(1 == ~T8_E~0); 252377#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 252375#L976-1 assume !(1 == ~E_2~0); 252373#L981-1 assume !(1 == ~E_3~0); 252371#L986-1 assume !(1 == ~E_4~0); 252369#L991-1 assume !(1 == ~E_5~0); 247373#L996-1 assume !(1 == ~E_6~0); 248141#L1001-1 assume !(1 == ~E_7~0); 251977#L1006-1 assume !(1 == ~E_8~0); 251975#L1011-1 assume { :end_inline_reset_delta_events } true; 251972#L1272-2 [2024-11-13 13:53:46,929 INFO L747 eck$LassoCheckResult]: Loop: 251972#L1272-2 assume !false; 251970#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 251965#L813-1 assume !false; 251963#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 251914#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 251908#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 251907#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 251903#L696 assume !(0 != eval_~tmp~0#1); 251904#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 254145#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 254143#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 254141#L838-5 assume !(0 == ~T1_E~0); 254139#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 254137#L848-3 assume !(0 == ~T3_E~0); 254135#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 254133#L858-3 assume !(0 == ~T5_E~0); 254131#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 254128#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 254126#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 254124#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 254122#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 254120#L888-3 assume !(0 == ~E_3~0); 254118#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 254116#L898-3 assume !(0 == ~E_5~0); 254114#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 254112#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 254109#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 254107#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 254105#L402-27 assume !(1 == ~m_pc~0); 254103#L402-29 is_master_triggered_~__retres1~0#1 := 0; 254100#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 254098#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 254096#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 254094#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 254092#L421-27 assume !(1 == ~t1_pc~0); 254090#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 254088#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 254086#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 254083#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 254081#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 254079#L440-27 assume !(1 == ~t2_pc~0); 254077#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 254075#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 254073#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 254071#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 254069#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 254062#L459-27 assume !(1 == ~t3_pc~0); 254059#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 254057#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 254055#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 254053#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 254050#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 254048#L478-27 assume !(1 == ~t4_pc~0); 254046#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 254044#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 254042#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 254040#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 254038#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 254036#L497-27 assume 1 == ~t5_pc~0; 254032#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 254029#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 254027#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 254023#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 254021#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 254019#L516-27 assume !(1 == ~t6_pc~0); 254017#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 254014#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 254012#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 254010#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 254008#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 254006#L535-27 assume 1 == ~t7_pc~0; 254003#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 254001#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 253947#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 253940#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 253934#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 253926#L554-27 assume !(1 == ~t8_pc~0); 253821#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 253809#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 253804#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 253795#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 253647#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 253637#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 253630#L931-5 assume !(1 == ~T1_E~0); 253489#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 253481#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 253474#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 253468#L951-3 assume !(1 == ~T5_E~0); 253463#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 253456#L961-3 assume !(1 == ~T7_E~0); 253450#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 253442#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 253435#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 253429#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 253423#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 252899#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 252895#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 252893#L1001-3 assume !(1 == ~E_7~0); 252891#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 252797#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 252677#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 252660#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 252651#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 252643#L1291 assume !(0 == start_simulation_~tmp~3#1); 252637#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 252550#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 252537#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 252532#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 252527#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 252521#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 252212#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 251974#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 251972#L1272-2 [2024-11-13 13:53:46,930 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:46,930 INFO L85 PathProgramCache]: Analyzing trace with hash -1109770177, now seen corresponding path program 1 times [2024-11-13 13:53:46,930 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:46,931 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1336927509] [2024-11-13 13:53:46,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:46,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:46,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:47,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:47,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:47,196 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1336927509] [2024-11-13 13:53:47,196 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1336927509] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:47,196 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:47,196 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:53:47,196 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [255139220] [2024-11-13 13:53:47,196 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:47,197 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:47,197 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:47,197 INFO L85 PathProgramCache]: Analyzing trace with hash -1725145868, now seen corresponding path program 1 times [2024-11-13 13:53:47,197 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:47,197 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1297220846] [2024-11-13 13:53:47,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:47,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:47,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:47,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:47,252 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:47,252 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1297220846] [2024-11-13 13:53:47,252 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1297220846] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:47,252 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:47,252 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:47,252 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1077560154] [2024-11-13 13:53:47,252 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:47,253 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:47,253 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:47,254 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:53:47,254 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:53:47,254 INFO L87 Difference]: Start difference. First operand 43006 states and 60873 transitions. cyclomatic complexity: 17931 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:47,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:47,397 INFO L93 Difference]: Finished difference Result 42995 states and 60691 transitions. [2024-11-13 13:53:47,397 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42995 states and 60691 transitions. [2024-11-13 13:53:47,768 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 42624 [2024-11-13 13:53:47,901 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42995 states to 42995 states and 60691 transitions. [2024-11-13 13:53:47,902 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42995 [2024-11-13 13:53:47,930 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42995 [2024-11-13 13:53:47,931 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42995 states and 60691 transitions. [2024-11-13 13:53:47,960 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:47,961 INFO L218 hiAutomatonCegarLoop]: Abstraction has 42995 states and 60691 transitions. [2024-11-13 13:53:47,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42995 states and 60691 transitions. [2024-11-13 13:53:48,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42995 to 22079. [2024-11-13 13:53:48,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22079 states, 22079 states have (on average 1.4100276280628652) internal successors, (31132), 22078 states have internal predecessors, (31132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:48,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22079 states to 22079 states and 31132 transitions. [2024-11-13 13:53:48,405 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22079 states and 31132 transitions. [2024-11-13 13:53:48,405 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:53:48,406 INFO L424 stractBuchiCegarLoop]: Abstraction has 22079 states and 31132 transitions. [2024-11-13 13:53:48,406 INFO L331 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-13 13:53:48,406 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22079 states and 31132 transitions. [2024-11-13 13:53:48,471 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21840 [2024-11-13 13:53:48,471 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:48,471 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:48,475 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:48,475 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:48,475 INFO L745 eck$LassoCheckResult]: Stem: 333342#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 333343#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 334060#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 334061#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 334062#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 333461#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 333462#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 334052#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 334041#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 333543#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 333544#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 333790#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 333791#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 333630#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 333631#L838 assume !(0 == ~M_E~0); 333799#L838-2 assume !(0 == ~T1_E~0); 333140#L843-1 assume !(0 == ~T2_E~0); 333141#L848-1 assume !(0 == ~T3_E~0); 333259#L853-1 assume !(0 == ~T4_E~0); 333617#L858-1 assume !(0 == ~T5_E~0); 333092#L863-1 assume !(0 == ~T6_E~0); 333093#L868-1 assume !(0 == ~T7_E~0); 334111#L873-1 assume !(0 == ~T8_E~0); 334109#L878-1 assume !(0 == ~E_1~0); 334087#L883-1 assume !(0 == ~E_2~0); 334088#L888-1 assume !(0 == ~E_3~0); 333758#L893-1 assume !(0 == ~E_4~0); 333759#L898-1 assume !(0 == ~E_5~0); 334125#L903-1 assume !(0 == ~E_6~0); 334085#L908-1 assume !(0 == ~E_7~0); 333902#L913-1 assume !(0 == ~E_8~0); 333153#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 333154#L402 assume !(1 == ~m_pc~0); 333368#L402-2 is_master_triggered_~__retres1~0#1 := 0; 333286#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 333287#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 333550#L1035 assume !(0 != activate_threads_~tmp~1#1); 333551#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 333605#L421 assume !(1 == ~t1_pc~0); 334078#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 334112#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 333155#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 333156#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 333661#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 334122#L440 assume !(1 == ~t2_pc~0); 334168#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 333295#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 333296#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 333488#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 333922#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 333495#L459 assume !(1 == ~t3_pc~0); 333496#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 334074#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 333114#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 333115#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 333280#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 333290#L478 assume !(1 == ~t4_pc~0); 333291#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 333983#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 333231#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 333232#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 333193#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 333194#L497 assume !(1 == ~t5_pc~0); 333242#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 333243#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 333838#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 333979#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 334069#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 334070#L516 assume !(1 == ~t6_pc~0); 333997#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 333789#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 333471#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 333336#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 333337#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 333778#L535 assume !(1 == ~t7_pc~0); 333779#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 333852#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 333853#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 333891#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 333879#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 333880#L554 assume !(1 == ~t8_pc~0); 333116#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 333117#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 333911#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 333423#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 333424#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 333103#L931 assume !(1 == ~M_E~0); 333104#L931-2 assume !(1 == ~T1_E~0); 334100#L936-1 assume !(1 == ~T2_E~0); 334136#L941-1 assume !(1 == ~T3_E~0); 333606#L946-1 assume !(1 == ~T4_E~0); 333607#L951-1 assume !(1 == ~T5_E~0); 333352#L956-1 assume !(1 == ~T6_E~0); 333353#L961-1 assume !(1 == ~T7_E~0); 333760#L966-1 assume !(1 == ~T8_E~0); 333761#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 333883#L976-1 assume !(1 == ~E_2~0); 333842#L981-1 assume !(1 == ~E_3~0); 333610#L986-1 assume !(1 == ~E_4~0); 333379#L991-1 assume !(1 == ~E_5~0); 333380#L996-1 assume !(1 == ~E_6~0); 334116#L1001-1 assume !(1 == ~E_7~0); 333810#L1006-1 assume !(1 == ~E_8~0); 333811#L1011-1 assume { :end_inline_reset_delta_events } true; 334076#L1272-2 [2024-11-13 13:53:48,476 INFO L747 eck$LassoCheckResult]: Loop: 334076#L1272-2 assume !false; 339295#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 339290#L813-1 assume !false; 339288#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 339276#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 339271#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 339270#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 339265#L696 assume !(0 != eval_~tmp~0#1); 339266#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 339513#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 339511#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 339509#L838-5 assume !(0 == ~T1_E~0); 339507#L843-3 assume !(0 == ~T2_E~0); 339505#L848-3 assume !(0 == ~T3_E~0); 339503#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 339501#L858-3 assume !(0 == ~T5_E~0); 339499#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 339497#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 339494#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 339492#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 339490#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 339488#L888-3 assume !(0 == ~E_3~0); 339486#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 339484#L898-3 assume !(0 == ~E_5~0); 339482#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 339480#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 339478#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 339476#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 339474#L402-27 assume !(1 == ~m_pc~0); 339472#L402-29 is_master_triggered_~__retres1~0#1 := 0; 339469#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 339467#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 339465#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 339463#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 339461#L421-27 assume !(1 == ~t1_pc~0); 339459#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 339457#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 339455#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 339453#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 339451#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 339449#L440-27 assume !(1 == ~t2_pc~0); 339447#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 339445#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 339443#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 339441#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 339439#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 339438#L459-27 assume 1 == ~t3_pc~0; 339437#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 339435#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 339433#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 339430#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 339429#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 339428#L478-27 assume !(1 == ~t4_pc~0); 339427#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 339426#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 339425#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 339424#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 339423#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 339422#L497-27 assume 1 == ~t5_pc~0; 339421#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 339419#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 339418#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 339416#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 339415#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 339414#L516-27 assume !(1 == ~t6_pc~0); 339413#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 339412#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 339411#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 339410#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 339408#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 339405#L535-27 assume !(1 == ~t7_pc~0); 339403#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 339400#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 339398#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 339396#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 339394#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 339392#L554-27 assume !(1 == ~t8_pc~0); 339390#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 339388#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 339386#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 339384#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 339382#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 339379#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 339377#L931-5 assume !(1 == ~T1_E~0); 339375#L936-3 assume !(1 == ~T2_E~0); 339373#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 339371#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 339367#L951-3 assume !(1 == ~T5_E~0); 339365#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 339363#L961-3 assume !(1 == ~T7_E~0); 339361#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 339358#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 339356#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 339354#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 339352#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 339350#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 339348#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 339346#L1001-3 assume !(1 == ~E_7~0); 339344#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 339342#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 339339#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 339329#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 339327#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 339324#L1291 assume !(0 == start_simulation_~tmp~3#1); 339321#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 339319#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 339309#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 339307#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 339305#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 339303#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 339301#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 339299#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 334076#L1272-2 [2024-11-13 13:53:48,477 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:48,477 INFO L85 PathProgramCache]: Analyzing trace with hash -2130838531, now seen corresponding path program 1 times [2024-11-13 13:53:48,477 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:48,478 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [672950754] [2024-11-13 13:53:48,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:48,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:48,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:48,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:48,575 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:48,575 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [672950754] [2024-11-13 13:53:48,575 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [672950754] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:48,575 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:48,575 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:48,575 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1351775238] [2024-11-13 13:53:48,575 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:48,575 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:48,576 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:48,576 INFO L85 PathProgramCache]: Analyzing trace with hash -1993934286, now seen corresponding path program 1 times [2024-11-13 13:53:48,576 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:48,576 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [256542114] [2024-11-13 13:53:48,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:48,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:48,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:48,633 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:48,633 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:48,633 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [256542114] [2024-11-13 13:53:48,634 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [256542114] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:48,634 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:48,634 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:48,634 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [950968370] [2024-11-13 13:53:48,634 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:48,635 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:48,635 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:48,635 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:53:48,636 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:53:48,636 INFO L87 Difference]: Start difference. First operand 22079 states and 31132 transitions. cyclomatic complexity: 9085 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:49,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:49,144 INFO L93 Difference]: Finished difference Result 45574 states and 64007 transitions. [2024-11-13 13:53:49,144 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45574 states and 64007 transitions. [2024-11-13 13:53:49,357 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 45056 [2024-11-13 13:53:49,530 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45574 states to 45574 states and 64007 transitions. [2024-11-13 13:53:49,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45574 [2024-11-13 13:53:49,562 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45574 [2024-11-13 13:53:49,562 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45574 states and 64007 transitions. [2024-11-13 13:53:49,606 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:49,606 INFO L218 hiAutomatonCegarLoop]: Abstraction has 45574 states and 64007 transitions. [2024-11-13 13:53:49,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45574 states and 64007 transitions. [2024-11-13 13:53:50,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45574 to 24766. [2024-11-13 13:53:50,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24766 states, 24766 states have (on average 1.4045061778244368) internal successors, (34784), 24765 states have internal predecessors, (34784), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:50,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24766 states to 24766 states and 34784 transitions. [2024-11-13 13:53:50,106 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24766 states and 34784 transitions. [2024-11-13 13:53:50,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:53:50,107 INFO L424 stractBuchiCegarLoop]: Abstraction has 24766 states and 34784 transitions. [2024-11-13 13:53:50,107 INFO L331 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-13 13:53:50,107 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24766 states and 34784 transitions. [2024-11-13 13:53:50,388 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 24448 [2024-11-13 13:53:50,389 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:50,389 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:50,390 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:50,390 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:50,391 INFO L745 eck$LassoCheckResult]: Stem: 401004#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 401005#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 401718#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 401719#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 401721#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 401124#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 401125#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 401712#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 401702#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 401204#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 401205#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 401456#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 401457#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 401291#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 401292#L838 assume !(0 == ~M_E~0); 401467#L838-2 assume !(0 == ~T1_E~0); 400800#L843-1 assume !(0 == ~T2_E~0); 400801#L848-1 assume !(0 == ~T3_E~0); 400920#L853-1 assume !(0 == ~T4_E~0); 401278#L858-1 assume !(0 == ~T5_E~0); 400755#L863-1 assume !(0 == ~T6_E~0); 400756#L868-1 assume !(0 == ~T7_E~0); 401778#L873-1 assume !(0 == ~T8_E~0); 401771#L878-1 assume 0 == ~E_1~0;~E_1~0 := 1; 401772#L883-1 assume !(0 == ~E_2~0); 401802#L888-1 assume !(0 == ~E_3~0); 401803#L893-1 assume !(0 == ~E_4~0); 401804#L898-1 assume !(0 == ~E_5~0); 401805#L903-1 assume !(0 == ~E_6~0); 401854#L908-1 assume !(0 == ~E_7~0); 401881#L913-1 assume !(0 == ~E_8~0); 401880#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 401587#L402 assume !(1 == ~m_pc~0); 401588#L402-2 is_master_triggered_~__retres1~0#1 := 0; 400948#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 400949#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 401879#L1035 assume !(0 != activate_threads_~tmp~1#1); 401265#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 401266#L421 assume !(1 == ~t1_pc~0); 401779#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 401780#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 401878#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 401320#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 401321#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 401852#L440 assume !(1 == ~t2_pc~0); 401853#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 400958#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 400959#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 401815#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 401816#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 401159#L459 assume !(1 == ~t3_pc~0); 401160#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 401876#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 401874#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 401872#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 401871#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 400952#L478 assume !(1 == ~t4_pc~0); 400953#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 401710#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 401711#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 401134#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 401135#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 401479#L497 assume !(1 == ~t5_pc~0); 401480#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 401511#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 401512#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 401794#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 401795#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 401840#L516 assume !(1 == ~t6_pc~0); 401841#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 401454#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 401455#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 401870#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 401869#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 401442#L535 assume !(1 == ~t7_pc~0); 401443#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 401868#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 401835#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 401561#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 401551#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 401552#L554 assume !(1 == ~t8_pc~0); 400777#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 400778#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 401865#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 401088#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 401089#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 400765#L931 assume !(1 == ~M_E~0); 400766#L931-2 assume !(1 == ~T1_E~0); 401811#L936-1 assume !(1 == ~T2_E~0); 401812#L941-1 assume !(1 == ~T3_E~0); 401849#L946-1 assume !(1 == ~T4_E~0); 401737#L951-1 assume !(1 == ~T5_E~0); 401013#L956-1 assume !(1 == ~T6_E~0); 401014#L961-1 assume !(1 == ~T7_E~0); 401842#L966-1 assume !(1 == ~T8_E~0); 401859#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 401554#L976-1 assume !(1 == ~E_2~0); 401516#L981-1 assume !(1 == ~E_3~0); 401271#L986-1 assume !(1 == ~E_4~0); 401043#L991-1 assume !(1 == ~E_5~0); 401044#L996-1 assume !(1 == ~E_6~0); 401787#L1001-1 assume !(1 == ~E_7~0); 401477#L1006-1 assume !(1 == ~E_8~0); 401478#L1011-1 assume { :end_inline_reset_delta_events } true; 401738#L1272-2 [2024-11-13 13:53:50,391 INFO L747 eck$LassoCheckResult]: Loop: 401738#L1272-2 assume !false; 406035#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 406027#L813-1 assume !false; 406025#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 405943#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 405870#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 405863#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 405857#L696 assume !(0 != eval_~tmp~0#1); 405858#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 407101#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 407094#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 407087#L838-5 assume !(0 == ~T1_E~0); 407081#L843-3 assume !(0 == ~T2_E~0); 407073#L848-3 assume !(0 == ~T3_E~0); 407066#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 407060#L858-3 assume !(0 == ~T5_E~0); 406690#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 406688#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 406686#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 406683#L878-3 assume !(0 == ~E_1~0); 406684#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 407297#L888-3 assume !(0 == ~E_3~0); 407295#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 407293#L898-3 assume !(0 == ~E_5~0); 407291#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 407289#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 407286#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 407284#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 407282#L402-27 assume 1 == ~m_pc~0; 407278#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 407276#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 407274#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 407272#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 407270#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 407268#L421-27 assume !(1 == ~t1_pc~0); 407266#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 407264#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 407261#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 407259#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 407257#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 407255#L440-27 assume !(1 == ~t2_pc~0); 407253#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 407251#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 407249#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 407247#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 407245#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 407240#L459-27 assume !(1 == ~t3_pc~0); 407238#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 407236#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 407234#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 407232#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 407229#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 407227#L478-27 assume !(1 == ~t4_pc~0); 407225#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 407223#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 407221#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 407219#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 407217#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 407215#L497-27 assume !(1 == ~t5_pc~0); 407210#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 407207#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 407205#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 407203#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 407201#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 407199#L516-27 assume !(1 == ~t6_pc~0); 407197#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 407195#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 407192#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 407190#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 407188#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 407186#L535-27 assume !(1 == ~t7_pc~0); 407184#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 407181#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 407155#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 407148#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 407140#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 407131#L554-27 assume !(1 == ~t8_pc~0); 407125#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 407121#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 407117#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 407113#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 407109#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 407104#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 407097#L931-5 assume !(1 == ~T1_E~0); 407091#L936-3 assume !(1 == ~T2_E~0); 407084#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 407078#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 407069#L951-3 assume !(1 == ~T5_E~0); 407063#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 407057#L961-3 assume !(1 == ~T7_E~0); 407052#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 406604#L971-3 assume !(1 == ~E_1~0); 406601#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 406599#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 406597#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 406595#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 406531#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 406521#L1001-3 assume !(1 == ~E_7~0); 406513#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 406430#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 406410#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 406397#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 406390#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 406082#L1291 assume !(0 == start_simulation_~tmp~3#1); 406079#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 406077#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 406067#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 406065#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 406063#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 406060#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 406058#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 406056#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 401738#L1272-2 [2024-11-13 13:53:50,392 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:50,393 INFO L85 PathProgramCache]: Analyzing trace with hash -1073000453, now seen corresponding path program 1 times [2024-11-13 13:53:50,393 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:50,393 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [47482639] [2024-11-13 13:53:50,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:50,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:50,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:50,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:50,466 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:50,467 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [47482639] [2024-11-13 13:53:50,467 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [47482639] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:50,467 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:50,467 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:50,467 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2102544805] [2024-11-13 13:53:50,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:50,468 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:50,468 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:50,468 INFO L85 PathProgramCache]: Analyzing trace with hash 1899230867, now seen corresponding path program 1 times [2024-11-13 13:53:50,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:50,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [309937022] [2024-11-13 13:53:50,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:50,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:50,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:50,524 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:50,524 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:50,524 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [309937022] [2024-11-13 13:53:50,524 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [309937022] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:50,524 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:50,524 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:50,524 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1549421795] [2024-11-13 13:53:50,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:50,525 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:50,525 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:50,525 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:53:50,525 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:53:50,525 INFO L87 Difference]: Start difference. First operand 24766 states and 34784 transitions. cyclomatic complexity: 10050 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:50,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:50,755 INFO L93 Difference]: Finished difference Result 41983 states and 58906 transitions. [2024-11-13 13:53:50,755 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41983 states and 58906 transitions. [2024-11-13 13:53:50,912 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 41552 [2024-11-13 13:53:51,038 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41983 states to 41983 states and 58906 transitions. [2024-11-13 13:53:51,039 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41983 [2024-11-13 13:53:51,064 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41983 [2024-11-13 13:53:51,065 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41983 states and 58906 transitions. [2024-11-13 13:53:51,092 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:51,092 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41983 states and 58906 transitions. [2024-11-13 13:53:51,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41983 states and 58906 transitions. [2024-11-13 13:53:51,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41983 to 22079. [2024-11-13 13:53:51,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22079 states, 22079 states have (on average 1.4001539924815436) internal successors, (30914), 22078 states have internal predecessors, (30914), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:51,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22079 states to 22079 states and 30914 transitions. [2024-11-13 13:53:51,760 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22079 states and 30914 transitions. [2024-11-13 13:53:51,761 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:53:51,761 INFO L424 stractBuchiCegarLoop]: Abstraction has 22079 states and 30914 transitions. [2024-11-13 13:53:51,761 INFO L331 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-13 13:53:51,761 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22079 states and 30914 transitions. [2024-11-13 13:53:51,809 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21840 [2024-11-13 13:53:51,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:51,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:51,815 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:51,815 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:51,815 INFO L745 eck$LassoCheckResult]: Stem: 467762#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 467763#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 468446#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 468447#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 468449#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 467877#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 467878#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 468443#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 468436#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 467953#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 467954#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 468203#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 468204#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 468039#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 468040#L838 assume !(0 == ~M_E~0); 468213#L838-2 assume !(0 == ~T1_E~0); 467560#L843-1 assume !(0 == ~T2_E~0); 467561#L848-1 assume !(0 == ~T3_E~0); 467680#L853-1 assume !(0 == ~T4_E~0); 468026#L858-1 assume !(0 == ~T5_E~0); 467514#L863-1 assume !(0 == ~T6_E~0); 467515#L868-1 assume !(0 == ~T7_E~0); 468497#L873-1 assume !(0 == ~T8_E~0); 468495#L878-1 assume !(0 == ~E_1~0); 468475#L883-1 assume !(0 == ~E_2~0); 468476#L888-1 assume !(0 == ~E_3~0); 468170#L893-1 assume !(0 == ~E_4~0); 468171#L898-1 assume !(0 == ~E_5~0); 468512#L903-1 assume !(0 == ~E_6~0); 468473#L908-1 assume !(0 == ~E_7~0); 468308#L913-1 assume !(0 == ~E_8~0); 467573#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 467574#L402 assume !(1 == ~m_pc~0); 467787#L402-2 is_master_triggered_~__retres1~0#1 := 0; 467707#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 467708#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 467960#L1035 assume !(0 != activate_threads_~tmp~1#1); 467961#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 468012#L421 assume !(1 == ~t1_pc~0); 468466#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 468498#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 467575#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 467576#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 468068#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 468509#L440 assume !(1 == ~t2_pc~0); 468551#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 467717#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 467718#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 467904#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 468325#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 467911#L459 assume !(1 == ~t3_pc~0); 467912#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 468462#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 467534#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 467535#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 467701#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 467711#L478 assume !(1 == ~t4_pc~0); 467712#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 468380#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 467652#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 467653#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 467616#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 467617#L497 assume !(1 == ~t5_pc~0); 467663#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 467664#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 468252#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 468375#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 468457#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 468458#L516 assume !(1 == ~t6_pc~0); 468396#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 468202#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 467887#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 467756#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 467757#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 468190#L535 assume !(1 == ~t7_pc~0); 468191#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 468266#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 468267#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 468301#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 468291#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 468292#L554 assume !(1 == ~t8_pc~0); 467536#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 467537#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 468316#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 467843#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 467844#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 467524#L931 assume !(1 == ~M_E~0); 467525#L931-2 assume !(1 == ~T1_E~0); 468488#L936-1 assume !(1 == ~T2_E~0); 468520#L941-1 assume !(1 == ~T3_E~0); 468013#L946-1 assume !(1 == ~T4_E~0); 468014#L951-1 assume !(1 == ~T5_E~0); 467771#L956-1 assume !(1 == ~T6_E~0); 467772#L961-1 assume !(1 == ~T7_E~0); 468172#L966-1 assume !(1 == ~T8_E~0); 468173#L971-1 assume !(1 == ~E_1~0); 468294#L976-1 assume !(1 == ~E_2~0); 468256#L981-1 assume !(1 == ~E_3~0); 468017#L986-1 assume !(1 == ~E_4~0); 467798#L991-1 assume !(1 == ~E_5~0); 467799#L996-1 assume !(1 == ~E_6~0); 468504#L1001-1 assume !(1 == ~E_7~0); 468223#L1006-1 assume !(1 == ~E_8~0); 468224#L1011-1 assume { :end_inline_reset_delta_events } true; 468464#L1272-2 [2024-11-13 13:53:51,816 INFO L747 eck$LassoCheckResult]: Loop: 468464#L1272-2 assume !false; 474016#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 474008#L813-1 assume !false; 474004#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 473720#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 473705#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 473695#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 473693#L696 assume !(0 != eval_~tmp~0#1); 473694#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 475775#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 475773#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 475771#L838-5 assume !(0 == ~T1_E~0); 475769#L843-3 assume !(0 == ~T2_E~0); 475767#L848-3 assume !(0 == ~T3_E~0); 475765#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 475763#L858-3 assume !(0 == ~T5_E~0); 475761#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 475759#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 475757#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 475756#L878-3 assume !(0 == ~E_1~0); 475755#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 475753#L888-3 assume !(0 == ~E_3~0); 475751#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 475749#L898-3 assume !(0 == ~E_5~0); 475734#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 475732#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 475662#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 475659#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 475656#L402-27 assume !(1 == ~m_pc~0); 475652#L402-29 is_master_triggered_~__retres1~0#1 := 0; 475649#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 475647#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 475644#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 475640#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 475637#L421-27 assume !(1 == ~t1_pc~0); 475633#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 475629#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 475624#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 475619#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 475615#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 475610#L440-27 assume !(1 == ~t2_pc~0); 475606#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 475602#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 475598#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 475594#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 475589#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 475585#L459-27 assume !(1 == ~t3_pc~0); 475581#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 475576#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 475571#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 475566#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 475560#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 475555#L478-27 assume !(1 == ~t4_pc~0); 475549#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 475543#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 475537#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 475531#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 475526#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 475521#L497-27 assume 1 == ~t5_pc~0; 475516#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 475512#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 475509#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 475505#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 475498#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 475492#L516-27 assume !(1 == ~t6_pc~0); 475486#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 475481#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 475476#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 475471#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 475465#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 475460#L535-27 assume !(1 == ~t7_pc~0); 475455#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 475448#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 475442#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 475436#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 475429#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 475423#L554-27 assume !(1 == ~t8_pc~0); 475416#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 475411#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 475406#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 475401#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 475396#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 475391#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 475387#L931-5 assume !(1 == ~T1_E~0); 475381#L936-3 assume !(1 == ~T2_E~0); 475374#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 475368#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 475362#L951-3 assume !(1 == ~T5_E~0); 475356#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 475350#L961-3 assume !(1 == ~T7_E~0); 475344#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 475338#L971-3 assume !(1 == ~E_1~0); 475331#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 475325#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 475319#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 475313#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 475306#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 475300#L1001-3 assume !(1 == ~E_7~0); 474121#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 474118#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 474116#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 474106#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 474104#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 474101#L1291 assume !(0 == start_simulation_~tmp~3#1); 474098#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 474096#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 474086#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 474084#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 474082#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 474056#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 474045#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 474034#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 468464#L1272-2 [2024-11-13 13:53:51,816 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:51,819 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 1 times [2024-11-13 13:53:51,819 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:51,819 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1786688832] [2024-11-13 13:53:51,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:51,820 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:51,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:53:51,833 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:53:51,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:53:51,923 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:53:51,923 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:51,923 INFO L85 PathProgramCache]: Analyzing trace with hash 1341523539, now seen corresponding path program 1 times [2024-11-13 13:53:51,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:51,924 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023050060] [2024-11-13 13:53:51,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:51,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:51,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:51,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:51,978 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:51,978 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2023050060] [2024-11-13 13:53:51,978 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2023050060] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:51,978 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:51,978 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:51,978 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1421226464] [2024-11-13 13:53:51,978 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:51,979 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:51,979 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:51,979 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:53:51,979 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:53:51,979 INFO L87 Difference]: Start difference. First operand 22079 states and 30914 transitions. cyclomatic complexity: 8867 Second operand has 3 states, 3 states have (on average 37.333333333333336) internal successors, (112), 3 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:52,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:52,068 INFO L93 Difference]: Finished difference Result 24766 states and 34669 transitions. [2024-11-13 13:53:52,068 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24766 states and 34669 transitions. [2024-11-13 13:53:52,158 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 24448 [2024-11-13 13:53:52,228 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24766 states to 24766 states and 34669 transitions. [2024-11-13 13:53:52,228 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24766 [2024-11-13 13:53:52,242 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24766 [2024-11-13 13:53:52,242 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24766 states and 34669 transitions. [2024-11-13 13:53:52,260 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:52,260 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24766 states and 34669 transitions. [2024-11-13 13:53:52,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24766 states and 34669 transitions. [2024-11-13 13:53:52,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24766 to 24766. [2024-11-13 13:53:52,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24766 states, 24766 states have (on average 1.3998627150125171) internal successors, (34669), 24765 states have internal predecessors, (34669), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:52,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24766 states to 24766 states and 34669 transitions. [2024-11-13 13:53:52,530 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24766 states and 34669 transitions. [2024-11-13 13:53:52,530 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:53:52,531 INFO L424 stractBuchiCegarLoop]: Abstraction has 24766 states and 34669 transitions. [2024-11-13 13:53:52,531 INFO L331 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-13 13:53:52,531 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24766 states and 34669 transitions. [2024-11-13 13:53:52,599 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 24448 [2024-11-13 13:53:52,600 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:52,600 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:52,602 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:52,602 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:52,603 INFO L745 eck$LassoCheckResult]: Stem: 514613#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 514614#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 515368#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 515369#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 515371#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 514732#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 514733#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 515361#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 515347#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 514813#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 514814#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 515070#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 515071#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 514902#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 514903#L838 assume !(0 == ~M_E~0); 515080#L838-2 assume !(0 == ~T1_E~0); 514410#L843-1 assume !(0 == ~T2_E~0); 514411#L848-1 assume !(0 == ~T3_E~0); 514529#L853-1 assume !(0 == ~T4_E~0); 514889#L858-1 assume !(0 == ~T5_E~0); 514365#L863-1 assume !(0 == ~T6_E~0); 514366#L868-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 515425#L873-1 assume !(0 == ~T8_E~0); 515422#L878-1 assume !(0 == ~E_1~0); 515423#L883-1 assume !(0 == ~E_2~0); 515451#L888-1 assume !(0 == ~E_3~0); 515452#L893-1 assume !(0 == ~E_4~0); 515449#L898-1 assume !(0 == ~E_5~0); 515450#L903-1 assume !(0 == ~E_6~0); 515401#L908-1 assume !(0 == ~E_7~0); 515193#L913-1 assume !(0 == ~E_8~0); 514422#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 514423#L402 assume !(1 == ~m_pc~0); 514637#L402-2 is_master_triggered_~__retres1~0#1 := 0; 514636#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 515269#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 514820#L1035 assume !(0 != activate_threads_~tmp~1#1); 514821#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 515396#L421 assume !(1 == ~t1_pc~0); 515397#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 515511#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 514425#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 514426#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 515438#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 515439#L440 assume !(1 == ~t2_pc~0); 515516#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 514565#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 514566#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 515471#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 515472#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 514765#L459 assume !(1 == ~t3_pc~0); 514766#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 515553#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 515551#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 515549#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 515548#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 514559#L478 assume !(1 == ~t4_pc~0); 514560#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 515359#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 515360#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 514742#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 514463#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 514464#L497 assume !(1 == ~t5_pc~0); 514511#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 514512#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 515127#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 515440#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 515441#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 515508#L516 assume !(1 == ~t6_pc~0); 515509#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 515068#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 515069#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 515545#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 515544#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 515057#L535 assume !(1 == ~t7_pc~0); 515058#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 515543#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 515497#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 515185#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 515175#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 515176#L554 assume !(1 == ~t8_pc~0); 514387#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 514388#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 515540#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 514695#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 514696#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 514375#L931 assume !(1 == ~M_E~0); 514376#L931-2 assume !(1 == ~T1_E~0); 515416#L936-1 assume !(1 == ~T2_E~0); 515465#L941-1 assume !(1 == ~T3_E~0); 514876#L946-1 assume !(1 == ~T4_E~0); 514877#L951-1 assume !(1 == ~T5_E~0); 514622#L956-1 assume !(1 == ~T6_E~0); 514623#L961-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 515040#L966-1 assume !(1 == ~T8_E~0); 515041#L971-1 assume !(1 == ~E_1~0); 515178#L976-1 assume !(1 == ~E_2~0); 515133#L981-1 assume !(1 == ~E_3~0); 514882#L986-1 assume !(1 == ~E_4~0); 514650#L991-1 assume !(1 == ~E_5~0); 514651#L996-1 assume !(1 == ~E_6~0); 515432#L1001-1 assume !(1 == ~E_7~0); 515092#L1006-1 assume !(1 == ~E_8~0); 515093#L1011-1 assume { :end_inline_reset_delta_events } true; 515394#L1272-2 [2024-11-13 13:53:52,603 INFO L747 eck$LassoCheckResult]: Loop: 515394#L1272-2 assume !false; 522273#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 522268#L813-1 assume !false; 522266#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 522251#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 522245#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 522244#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 522240#L696 assume !(0 != eval_~tmp~0#1); 522241#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 522513#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 522511#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 522509#L838-5 assume !(0 == ~T1_E~0); 522507#L843-3 assume !(0 == ~T2_E~0); 522506#L848-3 assume !(0 == ~T3_E~0); 522505#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 522501#L858-3 assume !(0 == ~T5_E~0); 522499#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 522496#L868-3 assume !(0 == ~T7_E~0); 522497#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 523304#L878-3 assume !(0 == ~E_1~0); 523303#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 523302#L888-3 assume !(0 == ~E_3~0); 523300#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 523299#L898-3 assume !(0 == ~E_5~0); 523298#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 523297#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 523296#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 523295#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 523293#L402-27 assume !(1 == ~m_pc~0); 522554#L402-29 is_master_triggered_~__retres1~0#1 := 0; 522550#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 522548#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 522546#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 522544#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 522542#L421-27 assume !(1 == ~t1_pc~0); 522540#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 522538#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 522536#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 522534#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 522532#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 522530#L440-27 assume !(1 == ~t2_pc~0); 522528#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 522525#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 522523#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 522521#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 522519#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 522489#L459-27 assume !(1 == ~t3_pc~0); 522487#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 522485#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 522483#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 522481#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 522478#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 522476#L478-27 assume !(1 == ~t4_pc~0); 522474#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 522472#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 522470#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 522467#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 522465#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 522463#L497-27 assume 1 == ~t5_pc~0; 522461#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 522458#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 522456#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 522454#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 522452#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 522450#L516-27 assume !(1 == ~t6_pc~0); 522448#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 522446#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 522444#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 522442#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 522440#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 522438#L535-27 assume !(1 == ~t7_pc~0); 522436#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 522433#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 522432#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 522428#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 522426#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 522424#L554-27 assume !(1 == ~t8_pc~0); 522422#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 522419#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 522417#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 522415#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 522413#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 522411#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 522409#L931-5 assume !(1 == ~T1_E~0); 522407#L936-3 assume !(1 == ~T2_E~0); 522405#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 522403#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 522400#L951-3 assume !(1 == ~T5_E~0); 522398#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 522341#L961-3 assume !(1 == ~T7_E~0); 522338#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 522336#L971-3 assume !(1 == ~E_1~0); 522334#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 522332#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 522330#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 522328#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 522326#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 522324#L1001-3 assume !(1 == ~E_7~0); 522322#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 522319#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 522317#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 522307#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 522305#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 522302#L1291 assume !(0 == start_simulation_~tmp~3#1); 522299#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 522297#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 522287#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 522285#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 522283#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 522281#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 522279#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 522276#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 515394#L1272-2 [2024-11-13 13:53:52,603 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:52,604 INFO L85 PathProgramCache]: Analyzing trace with hash 818266363, now seen corresponding path program 1 times [2024-11-13 13:53:52,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:52,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [234438481] [2024-11-13 13:53:52,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:52,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:52,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:52,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:52,856 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:52,857 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [234438481] [2024-11-13 13:53:52,857 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [234438481] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:52,857 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:52,857 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:52,857 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1842131188] [2024-11-13 13:53:52,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:52,858 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:52,858 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:52,858 INFO L85 PathProgramCache]: Analyzing trace with hash -1602058539, now seen corresponding path program 1 times [2024-11-13 13:53:52,859 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:52,859 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1574138783] [2024-11-13 13:53:52,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:52,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:52,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:52,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:52,912 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:52,913 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1574138783] [2024-11-13 13:53:52,913 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1574138783] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:52,913 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:52,913 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:52,913 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1829388401] [2024-11-13 13:53:52,913 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:52,914 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:52,914 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:52,914 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:53:52,914 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:53:52,915 INFO L87 Difference]: Start difference. First operand 24766 states and 34669 transitions. cyclomatic complexity: 9935 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:53,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:53,101 INFO L93 Difference]: Finished difference Result 44057 states and 61627 transitions. [2024-11-13 13:53:53,101 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44057 states and 61627 transitions. [2024-11-13 13:53:53,277 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 43680 [2024-11-13 13:53:53,386 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44057 states to 44057 states and 61627 transitions. [2024-11-13 13:53:53,386 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44057 [2024-11-13 13:53:53,412 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44057 [2024-11-13 13:53:53,412 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44057 states and 61627 transitions. [2024-11-13 13:53:53,441 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:53,441 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44057 states and 61627 transitions. [2024-11-13 13:53:53,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44057 states and 61627 transitions. [2024-11-13 13:53:53,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44057 to 22079. [2024-11-13 13:53:53,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22079 states, 22079 states have (on average 1.3986593595724444) internal successors, (30881), 22078 states have internal predecessors, (30881), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:53,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22079 states to 22079 states and 30881 transitions. [2024-11-13 13:53:53,787 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22079 states and 30881 transitions. [2024-11-13 13:53:53,788 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:53:53,788 INFO L424 stractBuchiCegarLoop]: Abstraction has 22079 states and 30881 transitions. [2024-11-13 13:53:53,789 INFO L331 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-13 13:53:53,789 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22079 states and 30881 transitions. [2024-11-13 13:53:53,970 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21840 [2024-11-13 13:53:53,970 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:53,970 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:53,972 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:53,972 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:53,972 INFO L745 eck$LassoCheckResult]: Stem: 583442#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 583443#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 584137#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 584138#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 584140#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 583559#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 583560#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 584131#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 584124#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 583637#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 583638#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 583885#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 583886#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 583723#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 583724#L838 assume !(0 == ~M_E~0); 583894#L838-2 assume !(0 == ~T1_E~0); 583244#L843-1 assume !(0 == ~T2_E~0); 583245#L848-1 assume !(0 == ~T3_E~0); 583362#L853-1 assume !(0 == ~T4_E~0); 583710#L858-1 assume !(0 == ~T5_E~0); 583198#L863-1 assume !(0 == ~T6_E~0); 583199#L868-1 assume !(0 == ~T7_E~0); 584183#L873-1 assume !(0 == ~T8_E~0); 584181#L878-1 assume !(0 == ~E_1~0); 584164#L883-1 assume !(0 == ~E_2~0); 584165#L888-1 assume !(0 == ~E_3~0); 583852#L893-1 assume !(0 == ~E_4~0); 583853#L898-1 assume !(0 == ~E_5~0); 584200#L903-1 assume !(0 == ~E_6~0); 584162#L908-1 assume !(0 == ~E_7~0); 583997#L913-1 assume !(0 == ~E_8~0); 583256#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 583257#L402 assume !(1 == ~m_pc~0); 583465#L402-2 is_master_triggered_~__retres1~0#1 := 0; 583387#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 583388#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 583643#L1035 assume !(0 != activate_threads_~tmp~1#1); 583644#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 583698#L421 assume !(1 == ~t1_pc~0); 584157#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 584184#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 583259#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 583260#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 583753#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 584195#L440 assume !(1 == ~t2_pc~0); 584237#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 583397#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 583398#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 583586#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 584015#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 583589#L459 assume !(1 == ~t3_pc~0); 583590#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 584154#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 583218#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 583219#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 583381#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 583391#L478 assume !(1 == ~t4_pc~0); 583392#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 584069#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 583334#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 583335#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 583297#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 583298#L497 assume !(1 == ~t5_pc~0); 583345#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 583346#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 583937#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 584063#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 584147#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 584148#L516 assume !(1 == ~t6_pc~0); 584084#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 583884#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 583569#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 583436#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 583437#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 583873#L535 assume !(1 == ~t7_pc~0); 583874#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 583951#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 583952#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 583989#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 583979#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 583980#L554 assume !(1 == ~t8_pc~0); 583220#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 583221#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 584006#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 583521#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 583522#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 583208#L931 assume !(1 == ~M_E~0); 583209#L931-2 assume !(1 == ~T1_E~0); 584175#L936-1 assume !(1 == ~T2_E~0); 584208#L941-1 assume !(1 == ~T3_E~0); 583699#L946-1 assume !(1 == ~T4_E~0); 583700#L951-1 assume !(1 == ~T5_E~0); 583451#L956-1 assume !(1 == ~T6_E~0); 583452#L961-1 assume !(1 == ~T7_E~0); 583854#L966-1 assume !(1 == ~T8_E~0); 583855#L971-1 assume !(1 == ~E_1~0); 583982#L976-1 assume !(1 == ~E_2~0); 583941#L981-1 assume !(1 == ~E_3~0); 583703#L986-1 assume !(1 == ~E_4~0); 583478#L991-1 assume !(1 == ~E_5~0); 583479#L996-1 assume !(1 == ~E_6~0); 584189#L1001-1 assume !(1 == ~E_7~0); 583906#L1006-1 assume !(1 == ~E_8~0); 583907#L1011-1 assume { :end_inline_reset_delta_events } true; 584155#L1272-2 [2024-11-13 13:53:53,973 INFO L747 eck$LassoCheckResult]: Loop: 584155#L1272-2 assume !false; 588985#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 588981#L813-1 assume !false; 588980#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 588970#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 588964#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 588962#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 588959#L696 assume !(0 != eval_~tmp~0#1); 588960#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 589299#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 589297#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 589295#L838-5 assume !(0 == ~T1_E~0); 589293#L843-3 assume !(0 == ~T2_E~0); 589291#L848-3 assume !(0 == ~T3_E~0); 589288#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 589286#L858-3 assume !(0 == ~T5_E~0); 589284#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 589282#L868-3 assume !(0 == ~T7_E~0); 589280#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 589278#L878-3 assume !(0 == ~E_1~0); 589276#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 589274#L888-3 assume !(0 == ~E_3~0); 589272#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 589270#L898-3 assume !(0 == ~E_5~0); 589268#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 589264#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 589262#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 589260#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 589255#L402-27 assume 1 == ~m_pc~0; 589250#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 589246#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 589245#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 589244#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 589243#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 589241#L421-27 assume !(1 == ~t1_pc~0); 589238#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 589236#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 589234#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 589232#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 589230#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 589228#L440-27 assume !(1 == ~t2_pc~0); 589226#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 589224#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 589222#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 589220#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 589218#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 589216#L459-27 assume 1 == ~t3_pc~0; 589213#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 589210#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 589207#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 589204#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 589201#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 589197#L478-27 assume !(1 == ~t4_pc~0); 589193#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 589189#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 589185#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 589181#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 589178#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 589175#L497-27 assume !(1 == ~t5_pc~0); 589171#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 589168#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 589165#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 589162#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 589159#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 589156#L516-27 assume !(1 == ~t6_pc~0); 589152#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 589149#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 589146#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 589143#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 589140#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 589136#L535-27 assume 1 == ~t7_pc~0; 589131#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 589127#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 589123#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 589120#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 589117#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 589114#L554-27 assume !(1 == ~t8_pc~0); 589110#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 589107#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 589104#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 589101#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 589098#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 589094#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 589091#L931-5 assume !(1 == ~T1_E~0); 589088#L936-3 assume !(1 == ~T2_E~0); 589085#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 589082#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 589079#L951-3 assume !(1 == ~T5_E~0); 589076#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 589073#L961-3 assume !(1 == ~T7_E~0); 589070#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 589067#L971-3 assume !(1 == ~E_1~0); 589064#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 589061#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 589057#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 589054#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 589051#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 589048#L1001-3 assume !(1 == ~E_7~0); 589045#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 589042#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 589038#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 589027#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 589024#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 589020#L1291 assume !(0 == start_simulation_~tmp~3#1); 589017#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 589013#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 589003#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 589001#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 589000#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 588997#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 588993#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 588989#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 584155#L1272-2 [2024-11-13 13:53:53,974 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:53,974 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 2 times [2024-11-13 13:53:53,974 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:53,975 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1907387783] [2024-11-13 13:53:53,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:53,975 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:53,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:53:53,993 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:53:54,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:53:54,039 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:53:54,040 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:54,041 INFO L85 PathProgramCache]: Analyzing trace with hash 1609865497, now seen corresponding path program 1 times [2024-11-13 13:53:54,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:54,041 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2040894258] [2024-11-13 13:53:54,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:54,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:54,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:54,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:54,106 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:54,106 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2040894258] [2024-11-13 13:53:54,107 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2040894258] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:54,107 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:54,107 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:54,107 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [9050725] [2024-11-13 13:53:54,107 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:54,107 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:54,108 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:54,108 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:53:54,108 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:53:54,108 INFO L87 Difference]: Start difference. First operand 22079 states and 30881 transitions. cyclomatic complexity: 8834 Second operand has 3 states, 3 states have (on average 37.333333333333336) internal successors, (112), 3 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:54,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:54,391 INFO L93 Difference]: Finished difference Result 40270 states and 55884 transitions. [2024-11-13 13:53:54,391 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40270 states and 55884 transitions. [2024-11-13 13:53:54,549 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 39824 [2024-11-13 13:53:54,633 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40270 states to 40270 states and 55884 transitions. [2024-11-13 13:53:54,633 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40270 [2024-11-13 13:53:54,657 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40270 [2024-11-13 13:53:54,657 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40270 states and 55884 transitions. [2024-11-13 13:53:54,690 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:54,690 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40270 states and 55884 transitions. [2024-11-13 13:53:54,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40270 states and 55884 transitions. [2024-11-13 13:53:55,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40270 to 40254. [2024-11-13 13:53:55,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40254 states, 40254 states have (on average 1.387886918070254) internal successors, (55868), 40253 states have internal predecessors, (55868), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:55,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40254 states to 40254 states and 55868 transitions. [2024-11-13 13:53:55,290 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40254 states and 55868 transitions. [2024-11-13 13:53:55,290 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:53:55,290 INFO L424 stractBuchiCegarLoop]: Abstraction has 40254 states and 55868 transitions. [2024-11-13 13:53:55,290 INFO L331 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-13 13:53:55,291 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40254 states and 55868 transitions. [2024-11-13 13:53:55,526 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 39808 [2024-11-13 13:53:55,527 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:55,527 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:55,527 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:55,528 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:55,528 INFO L745 eck$LassoCheckResult]: Stem: 645801#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 645802#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 646540#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 646541#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 646542#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 645922#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 645923#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 646533#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 646525#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 645999#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 646000#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 646253#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 646254#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 646088#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 646089#L838 assume !(0 == ~M_E~0); 646266#L838-2 assume !(0 == ~T1_E~0); 645598#L843-1 assume !(0 == ~T2_E~0); 645599#L848-1 assume !(0 == ~T3_E~0); 645719#L853-1 assume !(0 == ~T4_E~0); 646075#L858-1 assume !(0 == ~T5_E~0); 645553#L863-1 assume !(0 == ~T6_E~0); 645554#L868-1 assume !(0 == ~T7_E~0); 646599#L873-1 assume !(0 == ~T8_E~0); 646596#L878-1 assume !(0 == ~E_1~0); 646578#L883-1 assume !(0 == ~E_2~0); 646579#L888-1 assume !(0 == ~E_3~0); 646218#L893-1 assume !(0 == ~E_4~0); 646219#L898-1 assume !(0 == ~E_5~0); 646625#L903-1 assume !(0 == ~E_6~0); 646575#L908-1 assume 0 == ~E_7~0;~E_7~0 := 1; 646576#L913-1 assume !(0 == ~E_8~0); 646725#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 646393#L402 assume !(1 == ~m_pc~0); 646394#L402-2 is_master_triggered_~__retres1~0#1 := 0; 645745#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 645746#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 646723#L1035 assume !(0 != activate_threads_~tmp~1#1); 646062#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 646063#L421 assume !(1 == ~t1_pc~0); 646602#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 646603#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 646722#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 646118#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 646119#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 646685#L440 assume !(1 == ~t2_pc~0); 646686#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 646721#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 645951#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 645952#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 646397#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 646398#L459 assume !(1 == ~t3_pc~0); 646558#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 646559#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 646613#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 645738#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 645739#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 646690#L478 assume !(1 == ~t4_pc~0); 646458#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 646459#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 646713#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 645932#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 645933#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 646279#L497 assume !(1 == ~t5_pc~0); 646280#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 646712#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 646453#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 646454#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 646553#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 646554#L516 assume !(1 == ~t6_pc~0); 646470#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 646471#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 645934#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 645795#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 645796#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 646329#L535 assume !(1 == ~t7_pc~0); 646709#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 646325#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 646326#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 646728#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 646727#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 646543#L554 assume !(1 == ~t8_pc~0); 646544#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 646640#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 646385#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 646386#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 646724#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 645563#L931 assume !(1 == ~M_E~0); 645564#L931-2 assume !(1 == ~T1_E~0); 646589#L936-1 assume !(1 == ~T2_E~0); 646639#L941-1 assume !(1 == ~T3_E~0); 646064#L946-1 assume !(1 == ~T4_E~0); 646065#L951-1 assume !(1 == ~T5_E~0); 645810#L956-1 assume !(1 == ~T6_E~0); 645811#L961-1 assume !(1 == ~T7_E~0); 646220#L966-1 assume !(1 == ~T8_E~0); 646221#L971-1 assume !(1 == ~E_1~0); 646357#L976-1 assume !(1 == ~E_2~0); 646315#L981-1 assume !(1 == ~E_3~0); 646068#L986-1 assume !(1 == ~E_4~0); 645839#L991-1 assume !(1 == ~E_5~0); 645840#L996-1 assume !(1 == ~E_6~0); 646609#L1001-1 assume 1 == ~E_7~0;~E_7~0 := 2; 646277#L1006-1 assume !(1 == ~E_8~0); 646278#L1011-1 assume { :end_inline_reset_delta_events } true; 646560#L1272-2 [2024-11-13 13:53:55,528 INFO L747 eck$LassoCheckResult]: Loop: 646560#L1272-2 assume !false; 656972#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 655378#L813-1 assume !false; 656969#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 656957#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 656951#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 656949#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 656946#L696 assume !(0 != eval_~tmp~0#1); 656947#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 657203#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 657201#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 657199#L838-5 assume !(0 == ~T1_E~0); 657197#L843-3 assume !(0 == ~T2_E~0); 657195#L848-3 assume !(0 == ~T3_E~0); 657193#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 657191#L858-3 assume !(0 == ~T5_E~0); 657189#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 657187#L868-3 assume !(0 == ~T7_E~0); 657185#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 657183#L878-3 assume !(0 == ~E_1~0); 657181#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 657179#L888-3 assume !(0 == ~E_3~0); 657177#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 657175#L898-3 assume !(0 == ~E_5~0); 657173#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 657171#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 657170#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 657168#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 657166#L402-27 assume 1 == ~m_pc~0; 657163#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 657160#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 657158#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 657156#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 657154#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 657152#L421-27 assume !(1 == ~t1_pc~0); 657150#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 657148#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 657146#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 657144#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 657142#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 657140#L440-27 assume !(1 == ~t2_pc~0); 657138#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 657136#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 657134#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 657132#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 657130#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 657123#L459-27 assume !(1 == ~t3_pc~0); 657121#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 657119#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 657117#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 657114#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 657111#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 657109#L478-27 assume !(1 == ~t4_pc~0); 657107#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 657105#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 657103#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 657101#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 657099#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 657097#L497-27 assume 1 == ~t5_pc~0; 657094#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 657091#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 657089#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 657087#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 657085#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 657083#L516-27 assume !(1 == ~t6_pc~0); 657081#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 657079#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 657077#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 657075#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 657073#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 657070#L535-27 assume 1 == ~t7_pc~0; 657067#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 657065#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 657063#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 657061#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 657059#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 657057#L554-27 assume !(1 == ~t8_pc~0); 657055#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 657053#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 657051#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 657049#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 657047#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 657045#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 657043#L931-5 assume !(1 == ~T1_E~0); 657041#L936-3 assume !(1 == ~T2_E~0); 657039#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 657037#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 657035#L951-3 assume !(1 == ~T5_E~0); 657033#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 657031#L961-3 assume !(1 == ~T7_E~0); 657029#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 657027#L971-3 assume !(1 == ~E_1~0); 657025#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 657023#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 657021#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 657019#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 657017#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 657016#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 657014#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 657013#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 657012#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 657000#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 656998#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 656995#L1291 assume !(0 == start_simulation_~tmp~3#1); 656993#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 656990#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 656981#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 656980#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 656979#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 656978#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 656977#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 656975#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 646560#L1272-2 [2024-11-13 13:53:55,528 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:55,529 INFO L85 PathProgramCache]: Analyzing trace with hash 1110080763, now seen corresponding path program 1 times [2024-11-13 13:53:55,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:55,529 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510536815] [2024-11-13 13:53:55,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:55,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:55,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:55,576 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:55,576 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:55,576 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1510536815] [2024-11-13 13:53:55,576 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1510536815] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:55,576 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:55,576 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:53:55,577 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [915601631] [2024-11-13 13:53:55,577 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:55,577 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:53:55,577 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:55,577 INFO L85 PathProgramCache]: Analyzing trace with hash -2006741675, now seen corresponding path program 1 times [2024-11-13 13:53:55,578 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:55,578 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161775654] [2024-11-13 13:53:55,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:55,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:55,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:55,676 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:55,678 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:55,678 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1161775654] [2024-11-13 13:53:55,678 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1161775654] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:55,678 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:55,678 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:53:55,679 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1828751488] [2024-11-13 13:53:55,679 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:55,679 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:55,679 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:55,679 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:53:55,679 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:53:55,679 INFO L87 Difference]: Start difference. First operand 40254 states and 55868 transitions. cyclomatic complexity: 15646 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:55,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:55,828 INFO L93 Difference]: Finished difference Result 22079 states and 30526 transitions. [2024-11-13 13:53:55,828 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22079 states and 30526 transitions. [2024-11-13 13:53:55,912 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21840 [2024-11-13 13:53:55,966 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22079 states to 22079 states and 30526 transitions. [2024-11-13 13:53:55,967 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22079 [2024-11-13 13:53:55,981 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22079 [2024-11-13 13:53:55,982 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22079 states and 30526 transitions. [2024-11-13 13:53:55,997 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:55,997 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22079 states and 30526 transitions. [2024-11-13 13:53:56,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22079 states and 30526 transitions. [2024-11-13 13:53:56,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22079 to 22079. [2024-11-13 13:53:56,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22079 states, 22079 states have (on average 1.3825807328230446) internal successors, (30526), 22078 states have internal predecessors, (30526), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:56,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22079 states to 22079 states and 30526 transitions. [2024-11-13 13:53:56,229 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22079 states and 30526 transitions. [2024-11-13 13:53:56,230 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:53:56,230 INFO L424 stractBuchiCegarLoop]: Abstraction has 22079 states and 30526 transitions. [2024-11-13 13:53:56,230 INFO L331 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-13 13:53:56,231 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22079 states and 30526 transitions. [2024-11-13 13:53:56,293 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21840 [2024-11-13 13:53:56,293 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:56,293 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:56,294 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:56,294 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:56,295 INFO L745 eck$LassoCheckResult]: Stem: 708144#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 708145#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 708848#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 708849#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 708851#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 708263#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 708264#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 708845#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 708831#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 708341#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 708342#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 708597#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 708598#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 708430#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 708431#L838 assume !(0 == ~M_E~0); 708609#L838-2 assume !(0 == ~T1_E~0); 707941#L843-1 assume !(0 == ~T2_E~0); 707942#L848-1 assume !(0 == ~T3_E~0); 708060#L853-1 assume !(0 == ~T4_E~0); 708419#L858-1 assume !(0 == ~T5_E~0); 707897#L863-1 assume !(0 == ~T6_E~0); 707898#L868-1 assume !(0 == ~T7_E~0); 708891#L873-1 assume !(0 == ~T8_E~0); 708889#L878-1 assume !(0 == ~E_1~0); 708873#L883-1 assume !(0 == ~E_2~0); 708874#L888-1 assume !(0 == ~E_3~0); 708564#L893-1 assume !(0 == ~E_4~0); 708565#L898-1 assume !(0 == ~E_5~0); 708909#L903-1 assume !(0 == ~E_6~0); 708870#L908-1 assume !(0 == ~E_7~0); 708707#L913-1 assume !(0 == ~E_8~0); 707954#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 707955#L402 assume !(1 == ~m_pc~0); 708171#L402-2 is_master_triggered_~__retres1~0#1 := 0; 708087#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 708088#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 708348#L1035 assume !(0 != activate_threads_~tmp~1#1); 708349#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 708404#L421 assume !(1 == ~t1_pc~0); 708866#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 708894#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 707956#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 707957#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 708460#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 708903#L440 assume !(1 == ~t2_pc~0); 708955#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 708097#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 708098#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 708291#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 708723#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 708300#L459 assume !(1 == ~t3_pc~0); 708301#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 708863#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 707915#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 707916#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 708081#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 708091#L478 assume !(1 == ~t4_pc~0); 708092#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 708774#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 708032#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 708033#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 707996#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 707997#L497 assume !(1 == ~t5_pc~0); 708043#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 708044#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 708647#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 708769#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 708858#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 708859#L516 assume !(1 == ~t6_pc~0); 708788#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 708596#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 708273#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 708138#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 708139#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 708583#L535 assume !(1 == ~t7_pc~0); 708584#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 708661#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 708662#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 708696#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 708687#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 708688#L554 assume !(1 == ~t8_pc~0); 707917#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 707918#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 708717#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 708228#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 708229#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 707905#L931 assume !(1 == ~M_E~0); 707906#L931-2 assume !(1 == ~T1_E~0); 708883#L936-1 assume !(1 == ~T2_E~0); 708921#L941-1 assume !(1 == ~T3_E~0); 708405#L946-1 assume !(1 == ~T4_E~0); 708406#L951-1 assume !(1 == ~T5_E~0); 708153#L956-1 assume !(1 == ~T6_E~0); 708154#L961-1 assume !(1 == ~T7_E~0); 708566#L966-1 assume !(1 == ~T8_E~0); 708567#L971-1 assume !(1 == ~E_1~0); 708690#L976-1 assume !(1 == ~E_2~0); 708651#L981-1 assume !(1 == ~E_3~0); 708410#L986-1 assume !(1 == ~E_4~0); 708181#L991-1 assume !(1 == ~E_5~0); 708182#L996-1 assume !(1 == ~E_6~0); 708897#L1001-1 assume !(1 == ~E_7~0); 708618#L1006-1 assume !(1 == ~E_8~0); 708619#L1011-1 assume { :end_inline_reset_delta_events } true; 708864#L1272-2 [2024-11-13 13:53:56,295 INFO L747 eck$LassoCheckResult]: Loop: 708864#L1272-2 assume !false; 710244#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 709948#L813-1 assume !false; 710241#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 710057#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 710051#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 710049#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 710046#L696 assume !(0 != eval_~tmp~0#1); 710047#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 712300#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 712298#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 712296#L838-5 assume !(0 == ~T1_E~0); 712294#L843-3 assume !(0 == ~T2_E~0); 712292#L848-3 assume !(0 == ~T3_E~0); 712290#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 712288#L858-3 assume !(0 == ~T5_E~0); 712286#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 712283#L868-3 assume !(0 == ~T7_E~0); 712281#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 712279#L878-3 assume !(0 == ~E_1~0); 712236#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 712229#L888-3 assume !(0 == ~E_3~0); 712221#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 712213#L898-3 assume !(0 == ~E_5~0); 712207#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 712206#L908-3 assume !(0 == ~E_7~0); 712205#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 712204#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 712203#L402-27 assume 1 == ~m_pc~0; 712186#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 712184#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 712182#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 712179#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 712177#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 712175#L421-27 assume !(1 == ~t1_pc~0); 712173#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 712171#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 712169#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 712167#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 712153#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 712147#L440-27 assume !(1 == ~t2_pc~0); 712141#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 712136#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 712131#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 712126#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 712121#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 712116#L459-27 assume 1 == ~t3_pc~0; 712108#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 712105#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 712104#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 712101#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 712099#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 712097#L478-27 assume !(1 == ~t4_pc~0); 712095#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 712093#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 712090#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 712088#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 712086#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 712084#L497-27 assume 1 == ~t5_pc~0; 711594#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 711591#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 711589#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 711587#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 711585#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 711583#L516-27 assume !(1 == ~t6_pc~0); 711581#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 711579#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 711577#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 711575#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 711573#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 711571#L535-27 assume !(1 == ~t7_pc~0); 711568#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 711566#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 711564#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 711562#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 711560#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 711558#L554-27 assume !(1 == ~t8_pc~0); 711556#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 711554#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 711552#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 711550#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 711548#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 711546#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 711544#L931-5 assume !(1 == ~T1_E~0); 711542#L936-3 assume !(1 == ~T2_E~0); 711540#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 711538#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 711534#L951-3 assume !(1 == ~T5_E~0); 711531#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 711528#L961-3 assume !(1 == ~T7_E~0); 711524#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 711521#L971-3 assume !(1 == ~E_1~0); 711518#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 711515#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 711512#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 711510#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 711507#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 711505#L1001-3 assume !(1 == ~E_7~0); 711503#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 711501#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 710288#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 710278#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 710277#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 710273#L1291 assume !(0 == start_simulation_~tmp~3#1); 710270#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 710268#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 710258#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 710256#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 710253#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 710251#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 710249#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 710247#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 708864#L1272-2 [2024-11-13 13:53:56,296 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:56,296 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 3 times [2024-11-13 13:53:56,296 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:56,296 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1124428951] [2024-11-13 13:53:56,296 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:56,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:56,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:53:56,310 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:53:56,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:53:56,336 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:53:56,337 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:56,337 INFO L85 PathProgramCache]: Analyzing trace with hash -1234726373, now seen corresponding path program 1 times [2024-11-13 13:53:56,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:56,337 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436988040] [2024-11-13 13:53:56,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:56,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:56,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:56,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:56,402 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:56,402 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1436988040] [2024-11-13 13:53:56,402 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1436988040] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:56,402 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:56,402 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:53:56,403 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1174468641] [2024-11-13 13:53:56,403 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:56,403 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:56,403 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:56,403 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:53:56,403 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:53:56,403 INFO L87 Difference]: Start difference. First operand 22079 states and 30526 transitions. cyclomatic complexity: 8479 Second operand has 5 states, 5 states have (on average 22.4) internal successors, (112), 5 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:56,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:56,558 INFO L93 Difference]: Finished difference Result 22303 states and 30750 transitions. [2024-11-13 13:53:56,558 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22303 states and 30750 transitions. [2024-11-13 13:53:56,636 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 22064 [2024-11-13 13:53:56,691 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22303 states to 22303 states and 30750 transitions. [2024-11-13 13:53:56,691 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22303 [2024-11-13 13:53:56,705 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22303 [2024-11-13 13:53:56,705 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22303 states and 30750 transitions. [2024-11-13 13:53:56,719 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:56,720 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22303 states and 30750 transitions. [2024-11-13 13:53:56,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22303 states and 30750 transitions. [2024-11-13 13:53:57,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22303 to 22175. [2024-11-13 13:53:57,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22175 states, 22175 states have (on average 1.3809244644870349) internal successors, (30622), 22174 states have internal predecessors, (30622), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:57,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22175 states to 22175 states and 30622 transitions. [2024-11-13 13:53:57,149 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22175 states and 30622 transitions. [2024-11-13 13:53:57,149 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:53:57,149 INFO L424 stractBuchiCegarLoop]: Abstraction has 22175 states and 30622 transitions. [2024-11-13 13:53:57,150 INFO L331 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-13 13:53:57,150 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22175 states and 30622 transitions. [2024-11-13 13:53:57,206 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21936 [2024-11-13 13:53:57,206 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:57,206 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:57,208 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:57,208 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:57,208 INFO L745 eck$LassoCheckResult]: Stem: 752533#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 752534#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 753243#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 753244#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 753246#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 752650#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 752651#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 753237#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 753226#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 752727#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 752728#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 752974#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 752975#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 752814#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 752815#L838 assume !(0 == ~M_E~0); 752985#L838-2 assume !(0 == ~T1_E~0); 752331#L843-1 assume !(0 == ~T2_E~0); 752332#L848-1 assume !(0 == ~T3_E~0); 752450#L853-1 assume !(0 == ~T4_E~0); 752801#L858-1 assume !(0 == ~T5_E~0); 752285#L863-1 assume !(0 == ~T6_E~0); 752286#L868-1 assume !(0 == ~T7_E~0); 753290#L873-1 assume !(0 == ~T8_E~0); 753288#L878-1 assume !(0 == ~E_1~0); 753272#L883-1 assume !(0 == ~E_2~0); 753273#L888-1 assume !(0 == ~E_3~0); 752941#L893-1 assume !(0 == ~E_4~0); 752942#L898-1 assume !(0 == ~E_5~0); 753312#L903-1 assume !(0 == ~E_6~0); 753270#L908-1 assume !(0 == ~E_7~0); 753095#L913-1 assume !(0 == ~E_8~0); 752343#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 752344#L402 assume !(1 == ~m_pc~0); 752556#L402-2 is_master_triggered_~__retres1~0#1 := 0; 752477#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 752478#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 752734#L1035 assume !(0 != activate_threads_~tmp~1#1); 752735#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 752787#L421 assume !(1 == ~t1_pc~0); 753263#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 753291#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 752346#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 752347#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 752843#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 753304#L440 assume !(1 == ~t2_pc~0); 753358#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 752486#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 752487#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 752677#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 753115#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 752680#L459 assume !(1 == ~t3_pc~0); 752681#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 753260#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 752305#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 752306#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 752471#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 752481#L478 assume !(1 == ~t4_pc~0); 752482#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 753174#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 752422#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 752423#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 752384#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 752385#L497 assume !(1 == ~t5_pc~0); 752433#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 752434#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 753029#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 753169#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 753254#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 753255#L516 assume !(1 == ~t6_pc~0); 753186#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 752973#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 752660#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 752527#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 752528#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 752961#L535 assume !(1 == ~t7_pc~0); 752962#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 753045#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 753046#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 753085#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 753072#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 753073#L554 assume !(1 == ~t8_pc~0); 752307#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 752308#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 753106#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 752613#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 752614#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 752295#L931 assume !(1 == ~M_E~0); 752296#L931-2 assume !(1 == ~T1_E~0); 753284#L936-1 assume !(1 == ~T2_E~0); 753322#L941-1 assume !(1 == ~T3_E~0); 752788#L946-1 assume !(1 == ~T4_E~0); 752789#L951-1 assume !(1 == ~T5_E~0); 752542#L956-1 assume !(1 == ~T6_E~0); 752543#L961-1 assume !(1 == ~T7_E~0); 752943#L966-1 assume !(1 == ~T8_E~0); 752944#L971-1 assume !(1 == ~E_1~0); 753076#L976-1 assume !(1 == ~E_2~0); 753033#L981-1 assume !(1 == ~E_3~0); 752793#L986-1 assume !(1 == ~E_4~0); 752569#L991-1 assume !(1 == ~E_5~0); 752570#L996-1 assume !(1 == ~E_6~0); 753298#L1001-1 assume !(1 == ~E_7~0); 752999#L1006-1 assume !(1 == ~E_8~0); 753000#L1011-1 assume { :end_inline_reset_delta_events } true; 753261#L1272-2 [2024-11-13 13:53:57,209 INFO L747 eck$LassoCheckResult]: Loop: 753261#L1272-2 assume !false; 768470#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 768012#L813-1 assume !false; 768469#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 768463#L634 assume !(0 == ~m_st~0); 768464#L638 assume !(0 == ~t1_st~0); 768467#L642 assume !(0 == ~t2_st~0); 768461#L646 assume !(0 == ~t3_st~0); 768462#L650 assume !(0 == ~t4_st~0); 768466#L654 assume !(0 == ~t5_st~0); 768459#L658 assume !(0 == ~t6_st~0); 768460#L662 assume !(0 == ~t7_st~0); 768465#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 768468#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 771164#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 771162#L696 assume !(0 != eval_~tmp~0#1); 771160#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 771158#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 771156#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 771154#L838-5 assume !(0 == ~T1_E~0); 771153#L843-3 assume !(0 == ~T2_E~0); 771152#L848-3 assume !(0 == ~T3_E~0); 771151#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 771150#L858-3 assume !(0 == ~T5_E~0); 771148#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 771146#L868-3 assume !(0 == ~T7_E~0); 771144#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 771143#L878-3 assume !(0 == ~E_1~0); 771141#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 771140#L888-3 assume !(0 == ~E_3~0); 771139#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 771138#L898-3 assume !(0 == ~E_5~0); 771137#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 771135#L908-3 assume !(0 == ~E_7~0); 771134#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 771133#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 771132#L402-27 assume !(1 == ~m_pc~0); 771131#L402-29 is_master_triggered_~__retres1~0#1 := 0; 771129#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 771128#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 771127#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 771125#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 771123#L421-27 assume !(1 == ~t1_pc~0); 771121#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 771119#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 771116#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 771114#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 771112#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 771110#L440-27 assume !(1 == ~t2_pc~0); 771108#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 771106#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 771103#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 771101#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 771099#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 771094#L459-27 assume !(1 == ~t3_pc~0); 771091#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 771089#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 771087#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 771085#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 771082#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 771080#L478-27 assume !(1 == ~t4_pc~0); 771078#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 771075#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 771073#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 771071#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 771069#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 771067#L497-27 assume 1 == ~t5_pc~0; 771065#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 771063#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 771061#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 771059#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 771058#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 771057#L516-27 assume !(1 == ~t6_pc~0); 771056#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 771054#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 771052#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 771050#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 771048#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 771046#L535-27 assume !(1 == ~t7_pc~0); 771043#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 771039#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 771037#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 771035#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 771034#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 771033#L554-27 assume !(1 == ~t8_pc~0); 771032#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 771031#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 771030#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 771029#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 771028#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 771027#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 771026#L931-5 assume !(1 == ~T1_E~0); 771025#L936-3 assume !(1 == ~T2_E~0); 771024#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 771023#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 771022#L951-3 assume !(1 == ~T5_E~0); 771021#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 771020#L961-3 assume !(1 == ~T7_E~0); 771018#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 771016#L971-3 assume !(1 == ~E_1~0); 771014#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 771011#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 771009#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 771007#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 771005#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 771003#L1001-3 assume !(1 == ~E_7~0); 771001#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 770999#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 770997#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 770987#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 770986#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 770974#L1291 assume !(0 == start_simulation_~tmp~3#1); 770971#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 770970#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 770948#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 768721#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 768719#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 768717#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 768472#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 768471#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 753261#L1272-2 [2024-11-13 13:53:57,210 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:57,210 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 4 times [2024-11-13 13:53:57,210 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:57,210 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434315038] [2024-11-13 13:53:57,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:57,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:57,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:53:57,224 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:53:57,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:53:57,256 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:53:57,258 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:57,258 INFO L85 PathProgramCache]: Analyzing trace with hash -157047935, now seen corresponding path program 1 times [2024-11-13 13:53:57,258 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:57,258 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [249885521] [2024-11-13 13:53:57,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:57,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:57,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:57,349 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:57,349 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:57,349 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [249885521] [2024-11-13 13:53:57,349 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [249885521] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:57,349 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:57,350 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:53:57,350 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [698803485] [2024-11-13 13:53:57,350 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:57,350 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:57,350 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:57,350 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:53:57,351 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:53:57,351 INFO L87 Difference]: Start difference. First operand 22175 states and 30622 transitions. cyclomatic complexity: 8479 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:57,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:57,647 INFO L93 Difference]: Finished difference Result 22946 states and 31393 transitions. [2024-11-13 13:53:57,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22946 states and 31393 transitions. [2024-11-13 13:53:57,712 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 22704 [2024-11-13 13:53:57,746 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22946 states to 22946 states and 31393 transitions. [2024-11-13 13:53:57,746 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22946 [2024-11-13 13:53:57,757 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22946 [2024-11-13 13:53:57,757 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22946 states and 31393 transitions. [2024-11-13 13:53:57,770 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:57,771 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22946 states and 31393 transitions. [2024-11-13 13:53:57,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22946 states and 31393 transitions. [2024-11-13 13:53:57,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22946 to 22946. [2024-11-13 13:53:57,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22946 states, 22946 states have (on average 1.368125163427177) internal successors, (31393), 22945 states have internal predecessors, (31393), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:57,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22946 states to 22946 states and 31393 transitions. [2024-11-13 13:53:57,979 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22946 states and 31393 transitions. [2024-11-13 13:53:57,980 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:53:57,980 INFO L424 stractBuchiCegarLoop]: Abstraction has 22946 states and 31393 transitions. [2024-11-13 13:53:57,980 INFO L331 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-11-13 13:53:57,980 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22946 states and 31393 transitions. [2024-11-13 13:53:58,039 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 22704 [2024-11-13 13:53:58,039 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:58,039 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:58,040 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:58,040 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:58,041 INFO L745 eck$LassoCheckResult]: Stem: 797659#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 797660#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 798356#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 798357#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 798359#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 797777#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 797778#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 798352#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 798345#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 797854#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 797855#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 798108#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 798109#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 797942#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 797943#L838 assume !(0 == ~M_E~0); 798121#L838-2 assume !(0 == ~T1_E~0); 797459#L843-1 assume !(0 == ~T2_E~0); 797460#L848-1 assume !(0 == ~T3_E~0); 797578#L853-1 assume !(0 == ~T4_E~0); 797931#L858-1 assume !(0 == ~T5_E~0); 797414#L863-1 assume !(0 == ~T6_E~0); 797415#L868-1 assume !(0 == ~T7_E~0); 798404#L873-1 assume !(0 == ~T8_E~0); 798401#L878-1 assume !(0 == ~E_1~0); 798386#L883-1 assume !(0 == ~E_2~0); 798387#L888-1 assume !(0 == ~E_3~0); 798076#L893-1 assume !(0 == ~E_4~0); 798077#L898-1 assume !(0 == ~E_5~0); 798420#L903-1 assume !(0 == ~E_6~0); 798384#L908-1 assume !(0 == ~E_7~0); 798226#L913-1 assume !(0 == ~E_8~0); 797472#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 797473#L402 assume !(1 == ~m_pc~0); 797685#L402-2 is_master_triggered_~__retres1~0#1 := 0; 797908#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 798288#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 797861#L1035 assume !(0 != activate_threads_~tmp~1#1); 797862#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 797917#L421 assume !(1 == ~t1_pc~0); 798377#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 798407#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 797474#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 797475#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 797973#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 798418#L440 assume !(1 == ~t2_pc~0); 798460#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 797613#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 797614#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 797804#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 798242#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 797813#L459 assume !(1 == ~t3_pc~0); 797814#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 798374#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 797434#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 797435#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 797597#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 797607#L478 assume !(1 == ~t4_pc~0); 797608#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 798296#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 797550#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 797551#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 797515#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 797516#L497 assume !(1 == ~t5_pc~0); 797561#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 797562#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 798160#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 798291#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 798369#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 798370#L516 assume !(1 == ~t6_pc~0); 798309#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 798107#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 797787#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 797653#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 797654#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 798095#L535 assume !(1 == ~t7_pc~0); 798096#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 798176#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 798177#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 798218#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 798207#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 798208#L554 assume !(1 == ~t8_pc~0); 797436#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 797437#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 798234#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 797744#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 797745#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 797424#L931 assume !(1 == ~M_E~0); 797425#L931-2 assume !(1 == ~T1_E~0); 798397#L936-1 assume !(1 == ~T2_E~0); 798426#L941-1 assume !(1 == ~T3_E~0); 797918#L946-1 assume !(1 == ~T4_E~0); 797919#L951-1 assume !(1 == ~T5_E~0); 797668#L956-1 assume !(1 == ~T6_E~0); 797669#L961-1 assume !(1 == ~T7_E~0); 798078#L966-1 assume !(1 == ~T8_E~0); 798079#L971-1 assume !(1 == ~E_1~0); 798210#L976-1 assume !(1 == ~E_2~0); 798166#L981-1 assume !(1 == ~E_3~0); 797922#L986-1 assume !(1 == ~E_4~0); 797696#L991-1 assume !(1 == ~E_5~0); 797697#L996-1 assume !(1 == ~E_6~0); 798411#L1001-1 assume !(1 == ~E_7~0); 798133#L1006-1 assume !(1 == ~E_8~0); 798134#L1011-1 assume { :end_inline_reset_delta_events } true; 798375#L1272-2 [2024-11-13 13:53:58,041 INFO L747 eck$LassoCheckResult]: Loop: 798375#L1272-2 assume !false; 807605#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 805961#L813-1 assume !false; 807603#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 807559#L634 assume !(0 == ~m_st~0); 807560#L638 assume !(0 == ~t1_st~0); 807563#L642 assume !(0 == ~t2_st~0); 807557#L646 assume !(0 == ~t3_st~0); 807558#L650 assume !(0 == ~t4_st~0); 807562#L654 assume !(0 == ~t5_st~0); 807555#L658 assume !(0 == ~t6_st~0); 807556#L662 assume !(0 == ~t7_st~0); 807561#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 807564#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 808157#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 808155#L696 assume !(0 != eval_~tmp~0#1); 808153#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 808151#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 808149#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 808127#L838-5 assume !(0 == ~T1_E~0); 808122#L843-3 assume !(0 == ~T2_E~0); 808118#L848-3 assume !(0 == ~T3_E~0); 808114#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 808109#L858-3 assume !(0 == ~T5_E~0); 808104#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 808100#L868-3 assume !(0 == ~T7_E~0); 808096#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 808092#L878-3 assume !(0 == ~E_1~0); 808088#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 808083#L888-3 assume !(0 == ~E_3~0); 808078#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 808073#L898-3 assume !(0 == ~E_5~0); 808069#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 808065#L908-3 assume !(0 == ~E_7~0); 808061#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 808057#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 808053#L402-27 assume !(1 == ~m_pc~0); 808046#L402-29 is_master_triggered_~__retres1~0#1 := 0; 808042#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 808038#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 808035#L1035-27 assume !(0 != activate_threads_~tmp~1#1); 808032#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 808030#L421-27 assume !(1 == ~t1_pc~0); 808028#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 808026#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 808024#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 808022#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 808019#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 808017#L440-27 assume !(1 == ~t2_pc~0); 808015#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 808013#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 808011#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 808010#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 808006#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 808001#L459-27 assume !(1 == ~t3_pc~0); 807998#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 807997#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 807996#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 807993#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 807991#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 807990#L478-27 assume !(1 == ~t4_pc~0); 807988#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 807987#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 807986#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 807985#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 807984#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 807981#L497-27 assume !(1 == ~t5_pc~0); 807977#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 807974#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 807971#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 807967#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 807963#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 807959#L516-27 assume !(1 == ~t6_pc~0); 807955#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 807951#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 807947#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 807943#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 807939#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 807935#L535-27 assume !(1 == ~t7_pc~0); 807930#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 807927#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 807926#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 807925#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 807923#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 807922#L554-27 assume !(1 == ~t8_pc~0); 807921#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 807882#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 807876#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 807870#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 807863#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 807859#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 807810#L931-5 assume !(1 == ~T1_E~0); 807807#L936-3 assume !(1 == ~T2_E~0); 807803#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 807798#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 807793#L951-3 assume !(1 == ~T5_E~0); 807788#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 807783#L961-3 assume !(1 == ~T7_E~0); 807777#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 807773#L971-3 assume !(1 == ~E_1~0); 807769#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 807765#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 807761#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 807757#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 807752#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 807747#L1001-3 assume !(1 == ~E_7~0); 807741#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 807736#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 807730#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 807718#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 807714#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 807678#L1291 assume !(0 == start_simulation_~tmp~3#1); 807674#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 807672#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 807657#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 807651#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 807646#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 807640#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 807635#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 807630#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 798375#L1272-2 [2024-11-13 13:53:58,042 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:58,042 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 5 times [2024-11-13 13:53:58,042 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:58,042 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [531342724] [2024-11-13 13:53:58,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:58,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:58,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:53:58,056 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:53:58,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:53:58,081 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:53:58,082 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:58,082 INFO L85 PathProgramCache]: Analyzing trace with hash -1196749154, now seen corresponding path program 1 times [2024-11-13 13:53:58,082 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:58,082 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [431998637] [2024-11-13 13:53:58,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:58,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:58,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:58,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:58,267 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:58,267 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [431998637] [2024-11-13 13:53:58,267 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [431998637] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:58,267 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:58,267 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:53:58,267 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2006018651] [2024-11-13 13:53:58,267 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:58,268 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:58,268 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:58,269 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:53:58,269 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:53:58,269 INFO L87 Difference]: Start difference. First operand 22946 states and 31393 transitions. cyclomatic complexity: 8479 Second operand has 3 states, 3 states have (on average 40.0) internal successors, (120), 3 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:58,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:58,425 INFO L93 Difference]: Finished difference Result 43506 states and 58825 transitions. [2024-11-13 13:53:58,426 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43506 states and 58825 transitions. [2024-11-13 13:53:58,577 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43136 [2024-11-13 13:53:58,674 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43506 states to 43506 states and 58825 transitions. [2024-11-13 13:53:58,674 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43506 [2024-11-13 13:53:58,697 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43506 [2024-11-13 13:53:58,697 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43506 states and 58825 transitions. [2024-11-13 13:53:58,723 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:53:58,723 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43506 states and 58825 transitions. [2024-11-13 13:53:58,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43506 states and 58825 transitions. [2024-11-13 13:53:59,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43506 to 41570. [2024-11-13 13:53:59,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41570 states, 41570 states have (on average 1.3546547991339908) internal successors, (56313), 41569 states have internal predecessors, (56313), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:59,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41570 states to 41570 states and 56313 transitions. [2024-11-13 13:53:59,097 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41570 states and 56313 transitions. [2024-11-13 13:53:59,098 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:53:59,098 INFO L424 stractBuchiCegarLoop]: Abstraction has 41570 states and 56313 transitions. [2024-11-13 13:53:59,098 INFO L331 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2024-11-13 13:53:59,098 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41570 states and 56313 transitions. [2024-11-13 13:53:59,181 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41200 [2024-11-13 13:53:59,181 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:53:59,181 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:53:59,182 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:59,182 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:53:59,182 INFO L745 eck$LassoCheckResult]: Stem: 864120#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 864121#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 864851#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 864852#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 864853#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 864238#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 864239#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 864845#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 864835#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 864313#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 864314#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 864577#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 864578#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 864401#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 864402#L838 assume !(0 == ~M_E~0); 864589#L838-2 assume !(0 == ~T1_E~0); 863917#L843-1 assume !(0 == ~T2_E~0); 863918#L848-1 assume !(0 == ~T3_E~0); 864035#L853-1 assume !(0 == ~T4_E~0); 864390#L858-1 assume !(0 == ~T5_E~0); 863872#L863-1 assume !(0 == ~T6_E~0); 863873#L868-1 assume !(0 == ~T7_E~0); 864919#L873-1 assume !(0 == ~T8_E~0); 864917#L878-1 assume !(0 == ~E_1~0); 864891#L883-1 assume !(0 == ~E_2~0); 864892#L888-1 assume !(0 == ~E_3~0); 864539#L893-1 assume !(0 == ~E_4~0); 864540#L898-1 assume !(0 == ~E_5~0); 864946#L903-1 assume !(0 == ~E_6~0); 864889#L908-1 assume !(0 == ~E_7~0); 864698#L913-1 assume !(0 == ~E_8~0); 863930#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 863931#L402 assume !(1 == ~m_pc~0); 864145#L402-2 is_master_triggered_~__retres1~0#1 := 0; 864365#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 864772#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 864319#L1035 assume !(0 != activate_threads_~tmp~1#1); 864320#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 864375#L421 assume !(1 == ~t1_pc~0); 864878#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 864920#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 863932#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 863933#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 864434#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 864938#L440 assume !(1 == ~t2_pc~0); 865011#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 864070#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 864071#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 864264#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 864719#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 864272#L459 assume !(1 == ~t3_pc~0); 864273#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 864873#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 863892#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 863893#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 864054#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 864064#L478 assume !(1 == ~t4_pc~0); 864065#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 864781#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 864006#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 864007#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 863971#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 863972#L497 assume !(1 == ~t5_pc~0); 864017#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 864018#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 864633#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 864775#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 864862#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 864863#L516 assume !(1 == ~t6_pc~0); 864795#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 864574#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 864248#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 864114#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 864115#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 864560#L535 assume !(1 == ~t7_pc~0); 864561#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 864648#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 864649#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 864690#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 864677#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 864678#L554 assume !(1 == ~t8_pc~0); 863894#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 863895#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 864711#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 864204#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 864205#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 863882#L931 assume !(1 == ~M_E~0); 863883#L931-2 assume !(1 == ~T1_E~0); 864908#L936-1 assume !(1 == ~T2_E~0); 864960#L941-1 assume !(1 == ~T3_E~0); 864376#L946-1 assume !(1 == ~T4_E~0); 864377#L951-1 assume !(1 == ~T5_E~0); 864129#L956-1 assume !(1 == ~T6_E~0); 864130#L961-1 assume !(1 == ~T7_E~0); 864541#L966-1 assume !(1 == ~T8_E~0); 864542#L971-1 assume !(1 == ~E_1~0); 864680#L976-1 assume !(1 == ~E_2~0); 864638#L981-1 assume !(1 == ~E_3~0); 864380#L986-1 assume !(1 == ~E_4~0); 864156#L991-1 assume !(1 == ~E_5~0); 864157#L996-1 assume !(1 == ~E_6~0); 864926#L1001-1 assume !(1 == ~E_7~0); 864600#L1006-1 assume !(1 == ~E_8~0); 864601#L1011-1 assume { :end_inline_reset_delta_events } true; 864876#L1272-2 [2024-11-13 13:53:59,183 INFO L747 eck$LassoCheckResult]: Loop: 864876#L1272-2 assume !false; 879735#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 879537#L813-1 assume !false; 879731#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 879728#L634 assume !(0 == ~m_st~0); 879729#L638 assume !(0 == ~t1_st~0); 879970#L642 assume !(0 == ~t2_st~0); 879968#L646 assume !(0 == ~t3_st~0); 879966#L650 assume !(0 == ~t4_st~0); 879964#L654 assume !(0 == ~t5_st~0); 879962#L658 assume !(0 == ~t6_st~0); 879960#L662 assume !(0 == ~t7_st~0); 879957#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 879955#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 879953#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 879950#L696 assume !(0 != eval_~tmp~0#1); 879948#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 879946#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 879944#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 879942#L838-5 assume !(0 == ~T1_E~0); 879940#L843-3 assume !(0 == ~T2_E~0); 879938#L848-3 assume !(0 == ~T3_E~0); 879936#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 879934#L858-3 assume !(0 == ~T5_E~0); 879932#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 879930#L868-3 assume !(0 == ~T7_E~0); 879928#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 879926#L878-3 assume !(0 == ~E_1~0); 879924#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 879922#L888-3 assume !(0 == ~E_3~0); 879920#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 879918#L898-3 assume !(0 == ~E_5~0); 879916#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 879914#L908-3 assume !(0 == ~E_7~0); 879912#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 879910#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 879908#L402-27 assume 1 == ~m_pc~0; 879905#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 879903#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 879901#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 879898#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 879896#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 879894#L421-27 assume !(1 == ~t1_pc~0); 879892#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 879891#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 879890#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 879889#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 879888#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 879886#L440-27 assume !(1 == ~t2_pc~0); 879885#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 879884#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 879883#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 879882#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 879880#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 879877#L459-27 assume 1 == ~t3_pc~0; 879878#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 879879#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 879881#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 879867#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 879866#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 879865#L478-27 assume !(1 == ~t4_pc~0); 879863#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 879862#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 879861#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 879860#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 879859#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 879855#L497-27 assume 1 == ~t5_pc~0; 879853#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 879850#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 879848#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 879844#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 879842#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 879840#L516-27 assume !(1 == ~t6_pc~0); 879838#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 879836#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 879834#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 879832#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 879830#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 879828#L535-27 assume !(1 == ~t7_pc~0); 879825#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 879823#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 879821#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 879819#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 879817#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 879813#L554-27 assume !(1 == ~t8_pc~0); 879811#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 879809#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 879807#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 879804#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 879802#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 879800#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 879798#L931-5 assume !(1 == ~T1_E~0); 879796#L936-3 assume !(1 == ~T2_E~0); 879794#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 879792#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 879790#L951-3 assume !(1 == ~T5_E~0); 879788#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 879785#L961-3 assume !(1 == ~T7_E~0); 879783#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 879781#L971-3 assume !(1 == ~E_1~0); 879779#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 879777#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 879775#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 879773#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 879771#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 879769#L1001-3 assume !(1 == ~E_7~0); 879767#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 879765#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 879761#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 879759#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 879757#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 879754#L1291 assume !(0 == start_simulation_~tmp~3#1); 879751#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 879748#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 879746#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 879744#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 879742#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 879740#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 879738#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 879736#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 864876#L1272-2 [2024-11-13 13:53:59,183 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:59,183 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 6 times [2024-11-13 13:53:59,183 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:59,183 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1615829363] [2024-11-13 13:53:59,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:59,184 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:59,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:53:59,198 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:53:59,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:53:59,346 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:53:59,346 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:53:59,347 INFO L85 PathProgramCache]: Analyzing trace with hash 796560453, now seen corresponding path program 1 times [2024-11-13 13:53:59,347 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:53:59,347 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1851885329] [2024-11-13 13:53:59,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:53:59,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:53:59,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:53:59,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:53:59,457 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:53:59,457 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1851885329] [2024-11-13 13:53:59,457 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1851885329] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:53:59,457 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:53:59,457 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:53:59,457 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1551525695] [2024-11-13 13:53:59,457 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:53:59,458 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:53:59,458 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:53:59,458 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:53:59,458 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:53:59,458 INFO L87 Difference]: Start difference. First operand 41570 states and 56313 transitions. cyclomatic complexity: 14775 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:53:59,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:53:59,860 INFO L93 Difference]: Finished difference Result 41618 states and 55896 transitions. [2024-11-13 13:53:59,860 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41618 states and 55896 transitions. [2024-11-13 13:54:00,066 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41248 [2024-11-13 13:54:00,187 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41618 states to 41618 states and 55896 transitions. [2024-11-13 13:54:00,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41618 [2024-11-13 13:54:00,214 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41618 [2024-11-13 13:54:00,214 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41618 states and 55896 transitions. [2024-11-13 13:54:00,247 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:54:00,247 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41618 states and 55896 transitions. [2024-11-13 13:54:00,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41618 states and 55896 transitions. [2024-11-13 13:54:00,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41618 to 41618. [2024-11-13 13:54:00,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41618 states, 41618 states have (on average 1.3430727089240233) internal successors, (55896), 41617 states have internal predecessors, (55896), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:54:00,828 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41618 states to 41618 states and 55896 transitions. [2024-11-13 13:54:00,828 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41618 states and 55896 transitions. [2024-11-13 13:54:00,829 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:54:00,829 INFO L424 stractBuchiCegarLoop]: Abstraction has 41618 states and 55896 transitions. [2024-11-13 13:54:00,829 INFO L331 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2024-11-13 13:54:00,829 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41618 states and 55896 transitions. [2024-11-13 13:54:00,969 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41248 [2024-11-13 13:54:00,969 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:54:00,969 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:54:00,971 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:54:00,972 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:54:00,972 INFO L745 eck$LassoCheckResult]: Stem: 947312#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 947313#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 948051#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 948052#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 948054#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 947431#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 947432#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 948043#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 948035#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 947510#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 947511#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 947775#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 947776#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 947597#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 947598#L838 assume !(0 == ~M_E~0); 947786#L838-2 assume !(0 == ~T1_E~0); 947114#L843-1 assume !(0 == ~T2_E~0); 947115#L848-1 assume !(0 == ~T3_E~0); 947231#L853-1 assume !(0 == ~T4_E~0); 947586#L858-1 assume !(0 == ~T5_E~0); 947070#L863-1 assume !(0 == ~T6_E~0); 947071#L868-1 assume !(0 == ~T7_E~0); 948116#L873-1 assume !(0 == ~T8_E~0); 948112#L878-1 assume !(0 == ~E_1~0); 948086#L883-1 assume !(0 == ~E_2~0); 948087#L888-1 assume !(0 == ~E_3~0); 947744#L893-1 assume !(0 == ~E_4~0); 947745#L898-1 assume !(0 == ~E_5~0); 948144#L903-1 assume !(0 == ~E_6~0); 948083#L908-1 assume !(0 == ~E_7~0); 947891#L913-1 assume !(0 == ~E_8~0); 947127#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 947128#L402 assume !(1 == ~m_pc~0); 947339#L402-2 is_master_triggered_~__retres1~0#1 := 0; 947562#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 947969#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 947517#L1035 assume !(0 != activate_threads_~tmp~1#1); 947518#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 947572#L421 assume !(1 == ~t1_pc~0); 948071#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 948120#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 947129#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 947130#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 947631#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 948133#L440 assume !(1 == ~t2_pc~0); 948198#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 947267#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 947268#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 947458#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 947911#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 947466#L459 assume !(1 == ~t3_pc~0); 947467#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 948067#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 947088#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 947089#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 947252#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 947262#L478 assume !(1 == ~t4_pc~0); 947263#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 947977#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 947202#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 947203#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 947168#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 947169#L497 assume !(1 == ~t5_pc~0); 947213#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 947214#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 947828#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 947972#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 948061#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 948062#L516 assume !(1 == ~t6_pc~0); 947995#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 947774#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 947441#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 947306#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 947307#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 947763#L535 assume !(1 == ~t7_pc~0); 947764#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 947845#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 947846#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 947883#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 947874#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 947875#L554 assume !(1 == ~t8_pc~0); 947090#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 947091#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 947902#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 947396#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 947397#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 947078#L931 assume !(1 == ~M_E~0); 947079#L931-2 assume !(1 == ~T1_E~0); 948101#L936-1 assume !(1 == ~T2_E~0); 948154#L941-1 assume !(1 == ~T3_E~0); 947573#L946-1 assume !(1 == ~T4_E~0); 947574#L951-1 assume !(1 == ~T5_E~0); 947321#L956-1 assume !(1 == ~T6_E~0); 947322#L961-1 assume !(1 == ~T7_E~0); 947746#L966-1 assume !(1 == ~T8_E~0); 947747#L971-1 assume !(1 == ~E_1~0); 947877#L976-1 assume !(1 == ~E_2~0); 947835#L981-1 assume !(1 == ~E_3~0); 947577#L986-1 assume !(1 == ~E_4~0); 947348#L991-1 assume !(1 == ~E_5~0); 947349#L996-1 assume !(1 == ~E_6~0); 948124#L1001-1 assume !(1 == ~E_7~0); 947797#L1006-1 assume !(1 == ~E_8~0); 947798#L1011-1 assume { :end_inline_reset_delta_events } true; 948069#L1272-2 [2024-11-13 13:54:00,973 INFO L747 eck$LassoCheckResult]: Loop: 948069#L1272-2 assume !false; 982283#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 956740#L813-1 assume !false; 956736#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 956733#L634 assume !(0 == ~m_st~0); 956734#L638 assume !(0 == ~t1_st~0); 982535#L642 assume !(0 == ~t2_st~0); 982533#L646 assume !(0 == ~t3_st~0); 982531#L650 assume !(0 == ~t4_st~0); 982529#L654 assume !(0 == ~t5_st~0); 982527#L658 assume !(0 == ~t6_st~0); 982525#L662 assume !(0 == ~t7_st~0); 982522#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 982520#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 982518#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 982516#L696 assume !(0 != eval_~tmp~0#1); 982514#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 982512#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 982510#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 982508#L838-5 assume !(0 == ~T1_E~0); 982506#L843-3 assume !(0 == ~T2_E~0); 982505#L848-3 assume !(0 == ~T3_E~0); 982504#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 982503#L858-3 assume !(0 == ~T5_E~0); 982502#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 982501#L868-3 assume !(0 == ~T7_E~0); 982493#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 982491#L878-3 assume !(0 == ~E_1~0); 982489#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 982486#L888-3 assume !(0 == ~E_3~0); 982484#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 982482#L898-3 assume !(0 == ~E_5~0); 982479#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 982477#L908-3 assume !(0 == ~E_7~0); 982475#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 982474#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 982473#L402-27 assume 1 == ~m_pc~0; 982470#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 982468#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 982467#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 982465#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 982463#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 982460#L421-27 assume !(1 == ~t1_pc~0); 982458#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 982456#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 982451#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 982449#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 982447#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 982445#L440-27 assume !(1 == ~t2_pc~0); 982443#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 982441#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 982439#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 982437#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 982435#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 982430#L459-27 assume 1 == ~t3_pc~0; 982431#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 982432#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 982677#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 982419#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 982417#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 982415#L478-27 assume !(1 == ~t4_pc~0); 982413#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 982410#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 982408#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 982406#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 982404#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 982402#L497-27 assume !(1 == ~t5_pc~0); 982399#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 982397#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 982395#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 982393#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 982390#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 982388#L516-27 assume !(1 == ~t6_pc~0); 982386#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 982384#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 982382#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 982380#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 982378#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 982376#L535-27 assume !(1 == ~t7_pc~0); 982373#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 982371#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 982369#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 982366#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 982364#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 982362#L554-27 assume !(1 == ~t8_pc~0); 982360#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 982358#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 982356#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 982354#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 982352#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 982350#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 982348#L931-5 assume !(1 == ~T1_E~0); 982346#L936-3 assume !(1 == ~T2_E~0); 982344#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 982342#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 982340#L951-3 assume !(1 == ~T5_E~0); 982338#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 982336#L961-3 assume !(1 == ~T7_E~0); 982334#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 982332#L971-3 assume !(1 == ~E_1~0); 982330#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 982328#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 982326#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 982324#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 982322#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 982320#L1001-3 assume !(1 == ~E_7~0); 982318#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 982316#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 982313#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 982311#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 982309#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 982307#L1291 assume !(0 == start_simulation_~tmp~3#1); 982305#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 982303#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 982302#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 982294#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 982292#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 982290#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 982288#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 982286#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 948069#L1272-2 [2024-11-13 13:54:00,973 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:54:00,974 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 7 times [2024-11-13 13:54:00,974 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:54:00,974 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706786675] [2024-11-13 13:54:00,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:54:00,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:54:01,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:54:01,150 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:54:01,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:54:01,178 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:54:01,178 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:54:01,178 INFO L85 PathProgramCache]: Analyzing trace with hash 1786584546, now seen corresponding path program 1 times [2024-11-13 13:54:01,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:54:01,179 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1383481256] [2024-11-13 13:54:01,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:54:01,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:54:01,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:54:01,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:54:01,261 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:54:01,262 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1383481256] [2024-11-13 13:54:01,262 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1383481256] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:54:01,262 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:54:01,263 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:54:01,263 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [533045249] [2024-11-13 13:54:01,264 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:54:01,264 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:54:01,264 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:54:01,264 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:54:01,264 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:54:01,265 INFO L87 Difference]: Start difference. First operand 41618 states and 55896 transitions. cyclomatic complexity: 14310 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:54:01,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:54:01,611 INFO L93 Difference]: Finished difference Result 42386 states and 56439 transitions. [2024-11-13 13:54:01,611 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42386 states and 56439 transitions. [2024-11-13 13:54:01,755 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 42016 [2024-11-13 13:54:01,848 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42386 states to 42386 states and 56439 transitions. [2024-11-13 13:54:01,848 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42386 [2024-11-13 13:54:01,870 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42386 [2024-11-13 13:54:01,870 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42386 states and 56439 transitions. [2024-11-13 13:54:01,891 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:54:01,892 INFO L218 hiAutomatonCegarLoop]: Abstraction has 42386 states and 56439 transitions. [2024-11-13 13:54:01,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42386 states and 56439 transitions. [2024-11-13 13:54:02,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42386 to 42386. [2024-11-13 13:54:02,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42386 states, 42386 states have (on average 1.3315481526919266) internal successors, (56439), 42385 states have internal predecessors, (56439), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:54:02,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42386 states to 42386 states and 56439 transitions. [2024-11-13 13:54:02,228 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42386 states and 56439 transitions. [2024-11-13 13:54:02,229 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:54:02,230 INFO L424 stractBuchiCegarLoop]: Abstraction has 42386 states and 56439 transitions. [2024-11-13 13:54:02,230 INFO L331 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2024-11-13 13:54:02,230 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42386 states and 56439 transitions. [2024-11-13 13:54:02,447 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 42016 [2024-11-13 13:54:02,447 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:54:02,447 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:54:02,448 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:54:02,449 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:54:02,449 INFO L745 eck$LassoCheckResult]: Stem: 1031325#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1031326#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1032069#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1032070#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1032072#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1031446#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1031447#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1032065#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1032048#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1031527#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1031528#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1031788#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1031789#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1031616#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1031617#L838 assume !(0 == ~M_E~0); 1031797#L838-2 assume !(0 == ~T1_E~0); 1031126#L843-1 assume !(0 == ~T2_E~0); 1031127#L848-1 assume !(0 == ~T3_E~0); 1031243#L853-1 assume !(0 == ~T4_E~0); 1031602#L858-1 assume !(0 == ~T5_E~0); 1031080#L863-1 assume !(0 == ~T6_E~0); 1031081#L868-1 assume !(0 == ~T7_E~0); 1032131#L873-1 assume !(0 == ~T8_E~0); 1032128#L878-1 assume !(0 == ~E_1~0); 1032102#L883-1 assume !(0 == ~E_2~0); 1032103#L888-1 assume !(0 == ~E_3~0); 1031757#L893-1 assume !(0 == ~E_4~0); 1031758#L898-1 assume !(0 == ~E_5~0); 1032151#L903-1 assume !(0 == ~E_6~0); 1032099#L908-1 assume !(0 == ~E_7~0); 1031906#L913-1 assume !(0 == ~E_8~0); 1031138#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1031139#L402 assume !(1 == ~m_pc~0); 1031350#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1031582#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1031984#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1031534#L1035 assume !(0 != activate_threads_~tmp~1#1); 1031535#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1031590#L421 assume !(1 == ~t1_pc~0); 1032093#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1032134#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1031141#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1031142#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1031651#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1032147#L440 assume !(1 == ~t2_pc~0); 1032196#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1031277#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1031278#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1031474#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1031925#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1031480#L459 assume !(1 == ~t3_pc~0); 1031481#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1032088#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1031100#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1031101#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1031262#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1031272#L478 assume !(1 == ~t4_pc~0); 1031273#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1031992#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1031214#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1031215#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1031178#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1031179#L497 assume !(1 == ~t5_pc~0); 1031225#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1031226#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1031838#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1031987#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1032080#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1032081#L516 assume !(1 == ~t6_pc~0); 1032004#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1031787#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1031456#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1031319#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1031320#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1031776#L535 assume !(1 == ~t7_pc~0); 1031777#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1031852#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1031853#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1031898#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1031887#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1031888#L554 assume !(1 == ~t8_pc~0); 1031102#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1031103#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1031916#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1031407#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1031408#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1031090#L931 assume !(1 == ~M_E~0); 1031091#L931-2 assume !(1 == ~T1_E~0); 1032117#L936-1 assume !(1 == ~T2_E~0); 1032162#L941-1 assume !(1 == ~T3_E~0); 1031591#L946-1 assume !(1 == ~T4_E~0); 1031592#L951-1 assume !(1 == ~T5_E~0); 1031335#L956-1 assume !(1 == ~T6_E~0); 1031336#L961-1 assume !(1 == ~T7_E~0); 1031759#L966-1 assume !(1 == ~T8_E~0); 1031760#L971-1 assume !(1 == ~E_1~0); 1031890#L976-1 assume !(1 == ~E_2~0); 1031842#L981-1 assume !(1 == ~E_3~0); 1031595#L986-1 assume !(1 == ~E_4~0); 1031364#L991-1 assume !(1 == ~E_5~0); 1031365#L996-1 assume !(1 == ~E_6~0); 1032142#L1001-1 assume !(1 == ~E_7~0); 1031809#L1006-1 assume !(1 == ~E_8~0); 1031810#L1011-1 assume { :end_inline_reset_delta_events } true; 1032091#L1272-2 [2024-11-13 13:54:02,449 INFO L747 eck$LassoCheckResult]: Loop: 1032091#L1272-2 assume !false; 1040909#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1040905#L813-1 assume !false; 1040904#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1040902#L634 assume !(0 == ~m_st~0); 1040903#L638 assume !(0 == ~t1_st~0); 1041178#L642 assume !(0 == ~t2_st~0); 1041176#L646 assume !(0 == ~t3_st~0); 1041173#L650 assume !(0 == ~t4_st~0); 1041171#L654 assume !(0 == ~t5_st~0); 1041169#L658 assume !(0 == ~t6_st~0); 1041167#L662 assume !(0 == ~t7_st~0); 1041164#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1041162#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1041160#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1041158#L696 assume !(0 != eval_~tmp~0#1); 1041156#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1041154#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1041152#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1041150#L838-5 assume !(0 == ~T1_E~0); 1041149#L843-3 assume !(0 == ~T2_E~0); 1041148#L848-3 assume !(0 == ~T3_E~0); 1041144#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1041142#L858-3 assume !(0 == ~T5_E~0); 1041140#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1041138#L868-3 assume !(0 == ~T7_E~0); 1041137#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1041136#L878-3 assume !(0 == ~E_1~0); 1041134#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1041132#L888-3 assume !(0 == ~E_3~0); 1041130#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1041127#L898-3 assume !(0 == ~E_5~0); 1041123#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1041119#L908-3 assume !(0 == ~E_7~0); 1041115#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1041113#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1041110#L402-27 assume 1 == ~m_pc~0; 1041106#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1041102#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1041098#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1041093#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1041090#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1041087#L421-27 assume !(1 == ~t1_pc~0); 1041085#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1041082#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1041080#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1041078#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 1041075#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1041073#L440-27 assume !(1 == ~t2_pc~0); 1041071#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1041070#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1041069#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1041067#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 1041066#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1041062#L459-27 assume 1 == ~t3_pc~0; 1041063#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1041064#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1041065#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1041054#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1041052#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1041050#L478-27 assume !(1 == ~t4_pc~0); 1041048#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1041043#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1041041#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1041039#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1041037#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1041035#L497-27 assume 1 == ~t5_pc~0; 1041033#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1041030#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1041028#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1041026#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1041024#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1041022#L516-27 assume !(1 == ~t6_pc~0); 1041020#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1041018#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1041016#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1041012#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 1041010#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1041008#L535-27 assume !(1 == ~t7_pc~0); 1041005#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1041002#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1041000#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1040998#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1040996#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1040994#L554-27 assume !(1 == ~t8_pc~0); 1040992#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1040990#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1040988#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1040986#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1040983#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1040981#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1040979#L931-5 assume !(1 == ~T1_E~0); 1040977#L936-3 assume !(1 == ~T2_E~0); 1040975#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1040973#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1040971#L951-3 assume !(1 == ~T5_E~0); 1040969#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1040967#L961-3 assume !(1 == ~T7_E~0); 1040965#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1040963#L971-3 assume !(1 == ~E_1~0); 1040960#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1040958#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1040956#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1040954#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1040952#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1040950#L1001-3 assume !(1 == ~E_7~0); 1040948#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1040946#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1040943#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1040941#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1040939#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1040936#L1291 assume !(0 == start_simulation_~tmp~3#1); 1040934#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1040929#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1040927#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1040925#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1040924#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1040921#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1040917#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1040913#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1032091#L1272-2 [2024-11-13 13:54:02,450 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:54:02,450 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 8 times [2024-11-13 13:54:02,450 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:54:02,450 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1263695760] [2024-11-13 13:54:02,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:54:02,450 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:54:02,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:54:02,464 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:54:02,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:54:02,489 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:54:02,490 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:54:02,490 INFO L85 PathProgramCache]: Analyzing trace with hash -1657243839, now seen corresponding path program 1 times [2024-11-13 13:54:02,490 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:54:02,490 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [604396244] [2024-11-13 13:54:02,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:54:02,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:54:02,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:54:02,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:54:02,572 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:54:02,573 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [604396244] [2024-11-13 13:54:02,573 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [604396244] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:54:02,573 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:54:02,573 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:54:02,573 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1876078529] [2024-11-13 13:54:02,573 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:54:02,573 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:54:02,573 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:54:02,574 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:54:02,574 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:54:02,574 INFO L87 Difference]: Start difference. First operand 42386 states and 56439 transitions. cyclomatic complexity: 14085 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:54:02,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:54:02,950 INFO L93 Difference]: Finished difference Result 43154 states and 56982 transitions. [2024-11-13 13:54:02,951 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43154 states and 56982 transitions. [2024-11-13 13:54:03,108 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 42784 [2024-11-13 13:54:03,203 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43154 states to 43154 states and 56982 transitions. [2024-11-13 13:54:03,204 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43154 [2024-11-13 13:54:03,225 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43154 [2024-11-13 13:54:03,225 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43154 states and 56982 transitions. [2024-11-13 13:54:03,248 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:54:03,248 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43154 states and 56982 transitions. [2024-11-13 13:54:03,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43154 states and 56982 transitions. [2024-11-13 13:54:03,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43154 to 43154. [2024-11-13 13:54:03,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43154 states, 43154 states have (on average 1.3204337952449368) internal successors, (56982), 43153 states have internal predecessors, (56982), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:54:04,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43154 states to 43154 states and 56982 transitions. [2024-11-13 13:54:04,003 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43154 states and 56982 transitions. [2024-11-13 13:54:04,003 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:54:04,004 INFO L424 stractBuchiCegarLoop]: Abstraction has 43154 states and 56982 transitions. [2024-11-13 13:54:04,004 INFO L331 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2024-11-13 13:54:04,004 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43154 states and 56982 transitions. [2024-11-13 13:54:04,067 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 42784 [2024-11-13 13:54:04,067 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:54:04,067 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:54:04,068 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:54:04,068 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:54:04,069 INFO L745 eck$LassoCheckResult]: Stem: 1116878#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1116879#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1117615#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1117616#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1117618#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1116995#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1116996#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1117610#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1117599#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1117076#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1117077#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1117341#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1117342#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1117164#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1117165#L838 assume !(0 == ~M_E~0); 1117352#L838-2 assume !(0 == ~T1_E~0); 1116673#L843-1 assume !(0 == ~T2_E~0); 1116674#L848-1 assume !(0 == ~T3_E~0); 1116794#L853-1 assume !(0 == ~T4_E~0); 1117150#L858-1 assume !(0 == ~T5_E~0); 1116628#L863-1 assume !(0 == ~T6_E~0); 1116629#L868-1 assume !(0 == ~T7_E~0); 1117674#L873-1 assume !(0 == ~T8_E~0); 1117669#L878-1 assume !(0 == ~E_1~0); 1117647#L883-1 assume !(0 == ~E_2~0); 1117648#L888-1 assume !(0 == ~E_3~0); 1117308#L893-1 assume !(0 == ~E_4~0); 1117309#L898-1 assume !(0 == ~E_5~0); 1117691#L903-1 assume !(0 == ~E_6~0); 1117645#L908-1 assume !(0 == ~E_7~0); 1117454#L913-1 assume !(0 == ~E_8~0); 1116685#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1116686#L402 assume !(1 == ~m_pc~0); 1116901#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1117128#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1117528#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1117083#L1035 assume !(0 != activate_threads_~tmp~1#1); 1117084#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1117137#L421 assume !(1 == ~t1_pc~0); 1117638#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1117675#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1116688#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1116689#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1117193#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1117687#L440 assume !(1 == ~t2_pc~0); 1117736#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1116830#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1116831#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1117022#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1117472#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1117026#L459 assume !(1 == ~t3_pc~0); 1117027#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1117635#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1116648#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1116649#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1116814#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1116824#L478 assume !(1 == ~t4_pc~0); 1116825#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1117538#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1116764#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1116765#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1116726#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1116727#L497 assume !(1 == ~t5_pc~0); 1116775#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1116776#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1117394#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1117531#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1117630#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1117631#L516 assume !(1 == ~t6_pc~0); 1117553#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1117340#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1117005#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1116871#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1116872#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1117328#L535 assume !(1 == ~t7_pc~0); 1117329#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1117408#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1117409#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1117446#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1117435#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1117436#L554 assume !(1 == ~t8_pc~0); 1116650#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1116651#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1117465#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1116958#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1116959#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1116638#L931 assume !(1 == ~M_E~0); 1116639#L931-2 assume !(1 == ~T1_E~0); 1117662#L936-1 assume !(1 == ~T2_E~0); 1117699#L941-1 assume !(1 == ~T3_E~0); 1117138#L946-1 assume !(1 == ~T4_E~0); 1117139#L951-1 assume !(1 == ~T5_E~0); 1116887#L956-1 assume !(1 == ~T6_E~0); 1116888#L961-1 assume !(1 == ~T7_E~0); 1117310#L966-1 assume !(1 == ~T8_E~0); 1117311#L971-1 assume !(1 == ~E_1~0); 1117438#L976-1 assume !(1 == ~E_2~0); 1117398#L981-1 assume !(1 == ~E_3~0); 1117143#L986-1 assume !(1 == ~E_4~0); 1116914#L991-1 assume !(1 == ~E_5~0); 1116915#L996-1 assume !(1 == ~E_6~0); 1117681#L1001-1 assume !(1 == ~E_7~0); 1117365#L1006-1 assume !(1 == ~E_8~0); 1117366#L1011-1 assume { :end_inline_reset_delta_events } true; 1117636#L1272-2 [2024-11-13 13:54:04,069 INFO L747 eck$LassoCheckResult]: Loop: 1117636#L1272-2 assume !false; 1138201#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1138196#L813-1 assume !false; 1138194#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1138191#L634 assume !(0 == ~m_st~0); 1138192#L638 assume !(0 == ~t1_st~0); 1138457#L642 assume !(0 == ~t2_st~0); 1138455#L646 assume !(0 == ~t3_st~0); 1138453#L650 assume !(0 == ~t4_st~0); 1138450#L654 assume !(0 == ~t5_st~0); 1138448#L658 assume !(0 == ~t6_st~0); 1138446#L662 assume !(0 == ~t7_st~0); 1138444#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1138443#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1138441#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1138440#L696 assume !(0 != eval_~tmp~0#1); 1138439#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1138438#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1138436#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1138434#L838-5 assume !(0 == ~T1_E~0); 1138430#L843-3 assume !(0 == ~T2_E~0); 1138428#L848-3 assume !(0 == ~T3_E~0); 1138426#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1138424#L858-3 assume !(0 == ~T5_E~0); 1138419#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1138417#L868-3 assume !(0 == ~T7_E~0); 1138414#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1138412#L878-3 assume !(0 == ~E_1~0); 1138410#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1138408#L888-3 assume !(0 == ~E_3~0); 1138406#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1138404#L898-3 assume !(0 == ~E_5~0); 1138400#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1138398#L908-3 assume !(0 == ~E_7~0); 1138396#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1138394#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1138391#L402-27 assume 1 == ~m_pc~0; 1138388#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1138384#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1138382#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1138379#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1138377#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1138374#L421-27 assume !(1 == ~t1_pc~0); 1138372#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1138370#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1138368#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1138366#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 1138364#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1138362#L440-27 assume !(1 == ~t2_pc~0); 1138360#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1138358#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1138355#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1138353#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 1138351#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1138346#L459-27 assume !(1 == ~t3_pc~0); 1138344#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1138342#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1138340#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1138338#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 1138335#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1138333#L478-27 assume !(1 == ~t4_pc~0); 1138332#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1138329#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1138327#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1138325#L1067-27 assume !(0 != activate_threads_~tmp___3~0#1); 1138323#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1138321#L497-27 assume 1 == ~t5_pc~0; 1138319#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1138316#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1138314#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1138312#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1138310#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1138308#L516-27 assume !(1 == ~t6_pc~0); 1138306#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1138305#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1138304#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1138302#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 1138300#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1138296#L535-27 assume !(1 == ~t7_pc~0); 1138293#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1138291#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1138290#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1138287#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1138285#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1138283#L554-27 assume !(1 == ~t8_pc~0); 1138281#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1138279#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1138277#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1138275#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1138273#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1138271#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1138269#L931-5 assume !(1 == ~T1_E~0); 1138267#L936-3 assume !(1 == ~T2_E~0); 1138265#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1138263#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1138261#L951-3 assume !(1 == ~T5_E~0); 1138259#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1138255#L961-3 assume !(1 == ~T7_E~0); 1138253#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1138251#L971-3 assume !(1 == ~E_1~0); 1138249#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1138246#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1138244#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1138242#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1138240#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1138238#L1001-3 assume !(1 == ~E_7~0); 1138236#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1138234#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1138231#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1138229#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1138226#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1138223#L1291 assume !(0 == start_simulation_~tmp~3#1); 1138220#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1138217#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1138215#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1138213#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1138211#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1138209#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1138207#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1138205#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1117636#L1272-2 [2024-11-13 13:54:04,069 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:54:04,069 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 9 times [2024-11-13 13:54:04,069 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:54:04,069 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209872177] [2024-11-13 13:54:04,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:54:04,070 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:54:04,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:54:04,082 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:54:04,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:54:04,106 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:54:04,107 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:54:04,107 INFO L85 PathProgramCache]: Analyzing trace with hash -2115271396, now seen corresponding path program 1 times [2024-11-13 13:54:04,107 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:54:04,107 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1766906817] [2024-11-13 13:54:04,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:54:04,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:54:04,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:54:04,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:54:04,182 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:54:04,182 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1766906817] [2024-11-13 13:54:04,182 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1766906817] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:54:04,183 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:54:04,183 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:54:04,183 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [145748230] [2024-11-13 13:54:04,183 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:54:04,183 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:54:04,183 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:54:04,184 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:54:04,184 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:54:04,184 INFO L87 Difference]: Start difference. First operand 43154 states and 56982 transitions. cyclomatic complexity: 13860 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:54:04,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:54:04,486 INFO L93 Difference]: Finished difference Result 43250 states and 56629 transitions. [2024-11-13 13:54:04,486 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43250 states and 56629 transitions. [2024-11-13 13:54:04,652 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 42880 [2024-11-13 13:54:04,757 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43250 states to 43250 states and 56629 transitions. [2024-11-13 13:54:04,757 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43250 [2024-11-13 13:54:04,782 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43250 [2024-11-13 13:54:04,782 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43250 states and 56629 transitions. [2024-11-13 13:54:04,808 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:54:04,809 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43250 states and 56629 transitions. [2024-11-13 13:54:04,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43250 states and 56629 transitions. [2024-11-13 13:54:05,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43250 to 43250. [2024-11-13 13:54:05,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43250 states, 43250 states have (on average 1.3093410404624277) internal successors, (56629), 43249 states have internal predecessors, (56629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:54:05,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43250 states to 43250 states and 56629 transitions. [2024-11-13 13:54:05,584 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43250 states and 56629 transitions. [2024-11-13 13:54:05,585 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:54:05,585 INFO L424 stractBuchiCegarLoop]: Abstraction has 43250 states and 56629 transitions. [2024-11-13 13:54:05,585 INFO L331 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2024-11-13 13:54:05,585 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43250 states and 56629 transitions. [2024-11-13 13:54:05,687 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 42880 [2024-11-13 13:54:05,687 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:54:05,687 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:54:05,688 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:54:05,689 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:54:05,689 INFO L745 eck$LassoCheckResult]: Stem: 1203288#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1203289#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1204013#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1204014#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1204016#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1203405#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1203406#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1204010#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1203998#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1203482#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1203483#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1203746#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1203747#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1203570#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1203571#L838 assume !(0 == ~M_E~0); 1203758#L838-2 assume !(0 == ~T1_E~0); 1203086#L843-1 assume !(0 == ~T2_E~0); 1203087#L848-1 assume !(0 == ~T3_E~0); 1203206#L853-1 assume !(0 == ~T4_E~0); 1203559#L858-1 assume !(0 == ~T5_E~0); 1203040#L863-1 assume !(0 == ~T6_E~0); 1203041#L868-1 assume !(0 == ~T7_E~0); 1204075#L873-1 assume !(0 == ~T8_E~0); 1204072#L878-1 assume !(0 == ~E_1~0); 1204044#L883-1 assume !(0 == ~E_2~0); 1204045#L888-1 assume !(0 == ~E_3~0); 1203713#L893-1 assume !(0 == ~E_4~0); 1203714#L898-1 assume !(0 == ~E_5~0); 1204096#L903-1 assume !(0 == ~E_6~0); 1204041#L908-1 assume !(0 == ~E_7~0); 1203859#L913-1 assume !(0 == ~E_8~0); 1203100#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1203101#L402 assume !(1 == ~m_pc~0); 1203315#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1203536#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1203933#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1203490#L1035 assume !(0 != activate_threads_~tmp~1#1); 1203491#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1203545#L421 assume !(1 == ~t1_pc~0); 1204033#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1204079#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1203102#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1203103#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1203602#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1204088#L440 assume !(1 == ~t2_pc~0); 1204142#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1203241#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1203242#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1203432#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1203878#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1203441#L459 assume !(1 == ~t3_pc~0); 1203442#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1204029#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1203060#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1203061#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1203226#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1203236#L478 assume !(1 == ~t4_pc~0); 1203237#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1203942#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1203178#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1203179#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1203141#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1203142#L497 assume !(1 == ~t5_pc~0); 1203189#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1203190#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1203800#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1203936#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1204023#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1204024#L516 assume !(1 == ~t6_pc~0); 1203958#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1203745#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1203415#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1203282#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1203283#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1203733#L535 assume !(1 == ~t7_pc~0); 1203734#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1203815#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1203816#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1203852#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1203842#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1203843#L554 assume !(1 == ~t8_pc~0); 1203062#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1203063#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1203870#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1203372#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1203373#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1203050#L931 assume !(1 == ~M_E~0); 1203051#L931-2 assume !(1 == ~T1_E~0); 1204060#L936-1 assume !(1 == ~T2_E~0); 1204106#L941-1 assume !(1 == ~T3_E~0); 1203546#L946-1 assume !(1 == ~T4_E~0); 1203547#L951-1 assume !(1 == ~T5_E~0); 1203297#L956-1 assume !(1 == ~T6_E~0); 1203298#L961-1 assume !(1 == ~T7_E~0); 1203715#L966-1 assume !(1 == ~T8_E~0); 1203716#L971-1 assume !(1 == ~E_1~0); 1203844#L976-1 assume !(1 == ~E_2~0); 1203805#L981-1 assume !(1 == ~E_3~0); 1203550#L986-1 assume !(1 == ~E_4~0); 1203326#L991-1 assume !(1 == ~E_5~0); 1203327#L996-1 assume !(1 == ~E_6~0); 1204081#L1001-1 assume !(1 == ~E_7~0); 1203770#L1006-1 assume !(1 == ~E_8~0); 1203771#L1011-1 assume { :end_inline_reset_delta_events } true; 1204031#L1272-2 [2024-11-13 13:54:05,689 INFO L747 eck$LassoCheckResult]: Loop: 1204031#L1272-2 assume !false; 1213890#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1213885#L813-1 assume !false; 1213883#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1213881#L634 assume !(0 == ~m_st~0); 1213882#L638 assume !(0 == ~t1_st~0); 1214130#L642 assume !(0 == ~t2_st~0); 1214128#L646 assume !(0 == ~t3_st~0); 1214126#L650 assume !(0 == ~t4_st~0); 1214124#L654 assume !(0 == ~t5_st~0); 1214122#L658 assume !(0 == ~t6_st~0); 1214120#L662 assume !(0 == ~t7_st~0); 1214116#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1214114#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1214112#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1214109#L696 assume !(0 != eval_~tmp~0#1); 1214107#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1214105#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1214103#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1214101#L838-5 assume !(0 == ~T1_E~0); 1214099#L843-3 assume !(0 == ~T2_E~0); 1214097#L848-3 assume !(0 == ~T3_E~0); 1214095#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1214093#L858-3 assume !(0 == ~T5_E~0); 1214091#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1214089#L868-3 assume !(0 == ~T7_E~0); 1214087#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1214085#L878-3 assume !(0 == ~E_1~0); 1214083#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1214081#L888-3 assume !(0 == ~E_3~0); 1214079#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1214077#L898-3 assume !(0 == ~E_5~0); 1214075#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1214073#L908-3 assume !(0 == ~E_7~0); 1214071#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1214069#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1214067#L402-27 assume 1 == ~m_pc~0; 1214064#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1214062#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1214060#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1214057#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1214056#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1214055#L421-27 assume !(1 == ~t1_pc~0); 1214054#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1214052#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1214051#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1214050#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 1214049#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1214047#L440-27 assume !(1 == ~t2_pc~0); 1214046#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1214045#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1214044#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1214043#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 1214041#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1214038#L459-27 assume 1 == ~t3_pc~0; 1214039#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1214040#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1214042#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1214029#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1214027#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1214024#L478-27 assume !(1 == ~t4_pc~0); 1214022#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1214020#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1214019#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1214018#L1067-27 assume !(0 != activate_threads_~tmp___3~0#1); 1214017#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1214015#L497-27 assume !(1 == ~t5_pc~0); 1214012#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1214011#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1214010#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1214008#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1214005#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1214003#L516-27 assume !(1 == ~t6_pc~0); 1214001#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1213996#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1213994#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1213992#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 1213990#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1213988#L535-27 assume !(1 == ~t7_pc~0); 1213985#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1213983#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1213981#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1213977#L1091-27 assume !(0 != activate_threads_~tmp___6~0#1); 1213975#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1213973#L554-27 assume !(1 == ~t8_pc~0); 1213971#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1213968#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1213966#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1213962#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1213960#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1213958#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1213956#L931-5 assume !(1 == ~T1_E~0); 1213953#L936-3 assume !(1 == ~T2_E~0); 1213951#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1213949#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1213947#L951-3 assume !(1 == ~T5_E~0); 1213945#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1213943#L961-3 assume !(1 == ~T7_E~0); 1213941#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1213939#L971-3 assume !(1 == ~E_1~0); 1213937#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1213934#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1213932#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1213930#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1213928#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1213926#L1001-3 assume !(1 == ~E_7~0); 1213924#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1213922#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1213919#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1213917#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1213915#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1213912#L1291 assume !(0 == start_simulation_~tmp~3#1); 1213908#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1213905#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1213903#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1213901#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1213899#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1213897#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1213895#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1213893#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1204031#L1272-2 [2024-11-13 13:54:05,690 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:54:05,690 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 10 times [2024-11-13 13:54:05,690 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:54:05,690 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1523939378] [2024-11-13 13:54:05,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:54:05,691 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:54:05,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:54:05,706 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:54:05,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:54:05,735 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:54:05,736 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:54:05,736 INFO L85 PathProgramCache]: Analyzing trace with hash 1751840156, now seen corresponding path program 1 times [2024-11-13 13:54:05,736 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:54:05,737 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1307567858] [2024-11-13 13:54:05,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:54:05,737 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:54:05,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:54:05,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:54:05,830 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:54:05,830 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1307567858] [2024-11-13 13:54:05,830 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1307567858] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:54:05,830 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:54:05,830 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:54:05,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2061630888] [2024-11-13 13:54:05,830 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:54:05,831 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:54:05,831 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:54:05,831 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:54:05,831 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:54:05,831 INFO L87 Difference]: Start difference. First operand 43250 states and 56629 transitions. cyclomatic complexity: 13411 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:54:06,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:54:06,267 INFO L93 Difference]: Finished difference Result 44693 states and 58072 transitions. [2024-11-13 13:54:06,267 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44693 states and 58072 transitions. [2024-11-13 13:54:06,422 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 44320 [2024-11-13 13:54:06,522 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44693 states to 44693 states and 58072 transitions. [2024-11-13 13:54:06,522 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44693 [2024-11-13 13:54:06,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44693 [2024-11-13 13:54:06,545 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44693 states and 58072 transitions. [2024-11-13 13:54:06,571 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:54:06,572 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44693 states and 58072 transitions. [2024-11-13 13:54:06,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44693 states and 58072 transitions. [2024-11-13 13:54:06,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44693 to 44693. [2024-11-13 13:54:06,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44693 states, 44693 states have (on average 1.299353366298973) internal successors, (58072), 44692 states have internal predecessors, (58072), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:54:07,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44693 states to 44693 states and 58072 transitions. [2024-11-13 13:54:07,539 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44693 states and 58072 transitions. [2024-11-13 13:54:07,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:54:07,540 INFO L424 stractBuchiCegarLoop]: Abstraction has 44693 states and 58072 transitions. [2024-11-13 13:54:07,540 INFO L331 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2024-11-13 13:54:07,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44693 states and 58072 transitions. [2024-11-13 13:54:07,624 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 44320 [2024-11-13 13:54:07,625 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:54:07,625 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:54:07,626 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:54:07,626 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:54:07,626 INFO L745 eck$LassoCheckResult]: Stem: 1291241#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1291242#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1291992#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1291993#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1291995#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1291360#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1291361#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1291986#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1291978#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1291438#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1291439#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1291704#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1291705#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1291523#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1291524#L838 assume !(0 == ~M_E~0); 1291714#L838-2 assume !(0 == ~T1_E~0); 1291036#L843-1 assume !(0 == ~T2_E~0); 1291037#L848-1 assume !(0 == ~T3_E~0); 1291157#L853-1 assume !(0 == ~T4_E~0); 1291510#L858-1 assume !(0 == ~T5_E~0); 1290991#L863-1 assume !(0 == ~T6_E~0); 1290992#L868-1 assume !(0 == ~T7_E~0); 1292051#L873-1 assume !(0 == ~T8_E~0); 1292048#L878-1 assume !(0 == ~E_1~0); 1292025#L883-1 assume !(0 == ~E_2~0); 1292026#L888-1 assume !(0 == ~E_3~0); 1291669#L893-1 assume !(0 == ~E_4~0); 1291670#L898-1 assume !(0 == ~E_5~0); 1292073#L903-1 assume !(0 == ~E_6~0); 1292023#L908-1 assume !(0 == ~E_7~0); 1291825#L913-1 assume !(0 == ~E_8~0); 1291048#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1291049#L402 assume !(1 == ~m_pc~0); 1291264#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1291489#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1291900#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1291445#L1035 assume !(0 != activate_threads_~tmp~1#1); 1291446#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1291498#L421 assume !(1 == ~t1_pc~0); 1292015#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1292052#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1291052#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1291053#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1291556#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1292066#L440 assume !(1 == ~t2_pc~0); 1292128#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1291193#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1291194#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1291388#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1291845#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1291393#L459 assume !(1 == ~t3_pc~0); 1291394#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1292011#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1291011#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1291012#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1291177#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1291187#L478 assume !(1 == ~t4_pc~0); 1291188#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1291909#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1291128#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1291129#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1291090#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1291091#L497 assume !(1 == ~t5_pc~0); 1291139#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1291627#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1292150#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1292067#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1292005#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1292006#L516 assume !(1 == ~t6_pc~0); 1291923#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1291703#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1291370#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1291235#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1291236#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1291691#L535 assume !(1 == ~t7_pc~0); 1291692#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1291777#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1291778#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1291816#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1291805#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1291806#L554 assume !(1 == ~t8_pc~0); 1291013#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1291014#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1291835#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1291321#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1291322#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1291001#L931 assume !(1 == ~M_E~0); 1291002#L931-2 assume !(1 == ~T1_E~0); 1292039#L936-1 assume !(1 == ~T2_E~0); 1292082#L941-1 assume !(1 == ~T3_E~0); 1291499#L946-1 assume !(1 == ~T4_E~0); 1291500#L951-1 assume !(1 == ~T5_E~0); 1291250#L956-1 assume !(1 == ~T6_E~0); 1291251#L961-1 assume !(1 == ~T7_E~0); 1291671#L966-1 assume !(1 == ~T8_E~0); 1291672#L971-1 assume !(1 == ~E_1~0); 1291808#L976-1 assume !(1 == ~E_2~0); 1291767#L981-1 assume !(1 == ~E_3~0); 1291503#L986-1 assume !(1 == ~E_4~0); 1291277#L991-1 assume !(1 == ~E_5~0); 1291278#L996-1 assume !(1 == ~E_6~0); 1292058#L1001-1 assume !(1 == ~E_7~0); 1291730#L1006-1 assume !(1 == ~E_8~0); 1291731#L1011-1 assume { :end_inline_reset_delta_events } true; 1292013#L1272-2 [2024-11-13 13:54:07,626 INFO L747 eck$LassoCheckResult]: Loop: 1292013#L1272-2 assume !false; 1299307#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1299302#L813-1 assume !false; 1299301#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1299299#L634 assume !(0 == ~m_st~0); 1299300#L638 assume !(0 == ~t1_st~0); 1299544#L642 assume !(0 == ~t2_st~0); 1299542#L646 assume !(0 == ~t3_st~0); 1299539#L650 assume !(0 == ~t4_st~0); 1299537#L654 assume !(0 == ~t5_st~0); 1299535#L658 assume !(0 == ~t6_st~0); 1299533#L662 assume !(0 == ~t7_st~0); 1299530#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1299528#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1299526#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1299524#L696 assume !(0 != eval_~tmp~0#1); 1299521#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1299519#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1299517#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1299515#L838-5 assume !(0 == ~T1_E~0); 1299513#L843-3 assume !(0 == ~T2_E~0); 1299511#L848-3 assume !(0 == ~T3_E~0); 1299509#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1299507#L858-3 assume !(0 == ~T5_E~0); 1299505#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1299503#L868-3 assume !(0 == ~T7_E~0); 1299501#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1299499#L878-3 assume !(0 == ~E_1~0); 1299497#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1299495#L888-3 assume !(0 == ~E_3~0); 1299493#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1299491#L898-3 assume !(0 == ~E_5~0); 1299489#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1299487#L908-3 assume !(0 == ~E_7~0); 1299485#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1299483#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1299481#L402-27 assume 1 == ~m_pc~0; 1299478#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1299476#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1299474#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1299471#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1299469#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1299467#L421-27 assume !(1 == ~t1_pc~0); 1299465#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1299463#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1299462#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1299461#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 1299460#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1299458#L440-27 assume !(1 == ~t2_pc~0); 1299457#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1299456#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1299454#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1299453#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 1299452#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1299450#L459-27 assume 1 == ~t3_pc~0; 1299451#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1299449#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1299447#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1299443#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1299441#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1299440#L478-27 assume !(1 == ~t4_pc~0); 1299439#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1299437#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1299436#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1299435#L1067-27 assume !(0 != activate_threads_~tmp___3~0#1); 1299434#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1299433#L497-27 assume 1 == ~t5_pc~0; 1299431#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1299432#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1299438#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1299420#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1299418#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1299415#L516-27 assume !(1 == ~t6_pc~0); 1299413#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1299411#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1299409#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1299407#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 1299405#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1299403#L535-27 assume !(1 == ~t7_pc~0); 1299400#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1299398#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1299396#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1299394#L1091-27 assume !(0 != activate_threads_~tmp___6~0#1); 1299392#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1299390#L554-27 assume !(1 == ~t8_pc~0); 1299388#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1299384#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1299382#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1299380#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1299378#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1299375#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1299373#L931-5 assume !(1 == ~T1_E~0); 1299371#L936-3 assume !(1 == ~T2_E~0); 1299369#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1299367#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1299365#L951-3 assume !(1 == ~T5_E~0); 1299363#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1299361#L961-3 assume !(1 == ~T7_E~0); 1299360#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1299356#L971-3 assume !(1 == ~E_1~0); 1299354#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1299352#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1299350#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1299347#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1299345#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1299343#L1001-3 assume !(1 == ~E_7~0); 1299341#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1299339#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1299336#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1299334#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1299332#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1299328#L1291 assume !(0 == start_simulation_~tmp~3#1); 1299325#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1299322#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1299320#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1299318#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1299316#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1299314#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1299312#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1299310#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1292013#L1272-2 [2024-11-13 13:54:07,627 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:54:07,627 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 11 times [2024-11-13 13:54:07,627 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:54:07,627 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [696511185] [2024-11-13 13:54:07,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:54:07,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:54:07,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:54:07,639 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:54:07,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:54:07,662 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:54:07,662 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:54:07,662 INFO L85 PathProgramCache]: Analyzing trace with hash 1649038909, now seen corresponding path program 1 times [2024-11-13 13:54:07,662 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:54:07,662 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2006593601] [2024-11-13 13:54:07,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:54:07,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:54:07,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:54:07,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:54:07,738 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:54:07,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2006593601] [2024-11-13 13:54:07,738 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2006593601] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:54:07,738 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:54:07,738 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:54:07,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [78025383] [2024-11-13 13:54:07,739 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:54:07,739 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:54:07,739 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:54:07,739 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:54:07,739 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:54:07,739 INFO L87 Difference]: Start difference. First operand 44693 states and 58072 transitions. cyclomatic complexity: 13411 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:54:08,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:54:08,086 INFO L93 Difference]: Finished difference Result 45413 states and 58551 transitions. [2024-11-13 13:54:08,086 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45413 states and 58551 transitions. [2024-11-13 13:54:08,248 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 45040 [2024-11-13 13:54:08,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45413 states to 45413 states and 58551 transitions. [2024-11-13 13:54:08,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45413 [2024-11-13 13:54:08,380 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45413 [2024-11-13 13:54:08,380 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45413 states and 58551 transitions. [2024-11-13 13:54:08,406 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:54:08,406 INFO L218 hiAutomatonCegarLoop]: Abstraction has 45413 states and 58551 transitions. [2024-11-13 13:54:08,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45413 states and 58551 transitions. [2024-11-13 13:54:09,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45413 to 45413. [2024-11-13 13:54:09,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45413 states, 45413 states have (on average 1.289300420584414) internal successors, (58551), 45412 states have internal predecessors, (58551), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:54:09,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45413 states to 45413 states and 58551 transitions. [2024-11-13 13:54:09,259 INFO L240 hiAutomatonCegarLoop]: Abstraction has 45413 states and 58551 transitions. [2024-11-13 13:54:09,259 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:54:09,260 INFO L424 stractBuchiCegarLoop]: Abstraction has 45413 states and 58551 transitions. [2024-11-13 13:54:09,260 INFO L331 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2024-11-13 13:54:09,260 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45413 states and 58551 transitions. [2024-11-13 13:54:09,336 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 45040 [2024-11-13 13:54:09,336 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:54:09,336 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:54:09,337 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:54:09,337 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:54:09,337 INFO L745 eck$LassoCheckResult]: Stem: 1381354#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1381355#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1382129#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1382130#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1382132#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1381472#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1381473#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1382124#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1382112#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1381555#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1381556#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1381831#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1381832#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1381649#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1381650#L838 assume !(0 == ~M_E~0); 1381840#L838-2 assume !(0 == ~T1_E~0); 1381151#L843-1 assume !(0 == ~T2_E~0); 1381152#L848-1 assume !(0 == ~T3_E~0); 1381270#L853-1 assume !(0 == ~T4_E~0); 1381635#L858-1 assume !(0 == ~T5_E~0); 1381105#L863-1 assume !(0 == ~T6_E~0); 1381106#L868-1 assume !(0 == ~T7_E~0); 1382205#L873-1 assume !(0 == ~T8_E~0); 1382201#L878-1 assume !(0 == ~E_1~0); 1382169#L883-1 assume !(0 == ~E_2~0); 1382170#L888-1 assume !(0 == ~E_3~0); 1381794#L893-1 assume !(0 == ~E_4~0); 1381795#L898-1 assume !(0 == ~E_5~0); 1382230#L903-1 assume !(0 == ~E_6~0); 1382165#L908-1 assume !(0 == ~E_7~0); 1381955#L913-1 assume !(0 == ~E_8~0); 1381164#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1381165#L402 assume !(1 == ~m_pc~0); 1381379#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1381613#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1382035#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1381563#L1035 assume !(0 != activate_threads_~tmp~1#1); 1381564#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1381623#L421 assume !(1 == ~t1_pc~0); 1382156#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1382206#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1381166#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1381167#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1381680#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1382221#L440 assume !(1 == ~t2_pc~0); 1382295#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1381306#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1381307#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1381501#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1381977#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1381506#L459 assume !(1 == ~t3_pc~0); 1381507#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1382151#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1381125#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1381126#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1381291#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1381301#L478 assume !(1 == ~t4_pc~0); 1381302#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1382047#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1381240#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1381241#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1381203#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1381204#L497 assume !(1 == ~t5_pc~0); 1381251#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1381746#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1382307#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1382222#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1382142#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1382143#L516 assume !(1 == ~t6_pc~0); 1382066#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1381830#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1381482#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1381347#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1381348#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1381817#L535 assume !(1 == ~t7_pc~0); 1381818#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1381903#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1381904#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1381947#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1381937#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1381938#L554 assume !(1 == ~t8_pc~0); 1381127#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1381128#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1381967#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1381435#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1381436#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1381115#L931 assume !(1 == ~M_E~0); 1381116#L931-2 assume !(1 == ~T1_E~0); 1382189#L936-1 assume !(1 == ~T2_E~0); 1382246#L941-1 assume !(1 == ~T3_E~0); 1381624#L946-1 assume !(1 == ~T4_E~0); 1381625#L951-1 assume !(1 == ~T5_E~0); 1381363#L956-1 assume !(1 == ~T6_E~0); 1381364#L961-1 assume !(1 == ~T7_E~0); 1381796#L966-1 assume !(1 == ~T8_E~0); 1381797#L971-1 assume !(1 == ~E_1~0); 1381940#L976-1 assume !(1 == ~E_2~0); 1381893#L981-1 assume !(1 == ~E_3~0); 1381628#L986-1 assume !(1 == ~E_4~0); 1381390#L991-1 assume !(1 == ~E_5~0); 1381391#L996-1 assume !(1 == ~E_6~0); 1382211#L1001-1 assume !(1 == ~E_7~0); 1381852#L1006-1 assume !(1 == ~E_8~0); 1381853#L1011-1 assume { :end_inline_reset_delta_events } true; 1382154#L1272-2 [2024-11-13 13:54:09,337 INFO L747 eck$LassoCheckResult]: Loop: 1382154#L1272-2 assume !false; 1393876#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1393871#L813-1 assume !false; 1393869#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1393866#L634 assume !(0 == ~m_st~0); 1393867#L638 assume !(0 == ~t1_st~0); 1419375#L642 assume !(0 == ~t2_st~0); 1419373#L646 assume !(0 == ~t3_st~0); 1419370#L650 assume !(0 == ~t4_st~0); 1419368#L654 assume !(0 == ~t5_st~0); 1419366#L658 assume !(0 == ~t6_st~0); 1419364#L662 assume !(0 == ~t7_st~0); 1419361#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1419359#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1419357#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1419355#L696 assume !(0 != eval_~tmp~0#1); 1419353#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1419351#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1419349#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1419347#L838-5 assume !(0 == ~T1_E~0); 1419346#L843-3 assume !(0 == ~T2_E~0); 1394103#L848-3 assume !(0 == ~T3_E~0); 1394099#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1394097#L858-3 assume !(0 == ~T5_E~0); 1394095#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1394093#L868-3 assume !(0 == ~T7_E~0); 1394090#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1394088#L878-3 assume !(0 == ~E_1~0); 1394086#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1394084#L888-3 assume !(0 == ~E_3~0); 1394082#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1394080#L898-3 assume !(0 == ~E_5~0); 1394078#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1394076#L908-3 assume !(0 == ~E_7~0); 1394072#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1394070#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1394068#L402-27 assume 1 == ~m_pc~0; 1394065#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1394062#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1394060#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1394057#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1394055#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1394053#L421-27 assume !(1 == ~t1_pc~0); 1394051#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1394049#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1394047#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1394044#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 1394042#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1394040#L440-27 assume !(1 == ~t2_pc~0); 1394038#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1394036#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1394034#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1394032#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 1394030#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1394025#L459-27 assume !(1 == ~t3_pc~0); 1394023#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1394021#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1394019#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1394017#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 1394014#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1394012#L478-27 assume !(1 == ~t4_pc~0); 1394010#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1394008#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1394006#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1394004#L1067-27 assume !(0 != activate_threads_~tmp___3~0#1); 1394002#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1394000#L497-27 assume !(1 == ~t5_pc~0); 1393996#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1393994#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1393992#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1393990#L1075-27 assume !(0 != activate_threads_~tmp___4~0#1); 1393987#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1393985#L516-27 assume !(1 == ~t6_pc~0); 1393983#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1393981#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1393979#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1393978#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 1393977#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1393976#L535-27 assume !(1 == ~t7_pc~0); 1393974#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1393973#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1393972#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1393964#L1091-27 assume !(0 != activate_threads_~tmp___6~0#1); 1393962#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1393960#L554-27 assume !(1 == ~t8_pc~0); 1393956#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1393954#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1393952#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1393951#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 1393950#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1393949#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1393948#L931-5 assume !(1 == ~T1_E~0); 1393947#L936-3 assume !(1 == ~T2_E~0); 1393939#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1393937#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1393935#L951-3 assume !(1 == ~T5_E~0); 1393933#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1393931#L961-3 assume !(1 == ~T7_E~0); 1393929#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1393927#L971-3 assume !(1 == ~E_1~0); 1393925#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1393920#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1393918#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1393916#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1393914#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1393913#L1001-3 assume !(1 == ~E_7~0); 1393911#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1393909#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1393906#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1393904#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1393902#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1393899#L1291 assume !(0 == start_simulation_~tmp~3#1); 1393895#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1393892#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1393890#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1393887#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1393885#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1393883#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1393881#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1393879#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1382154#L1272-2 [2024-11-13 13:54:09,338 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:54:09,338 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 12 times [2024-11-13 13:54:09,338 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:54:09,338 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1047342464] [2024-11-13 13:54:09,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:54:09,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:54:09,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:54:09,349 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:54:09,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:54:09,371 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:54:09,372 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:54:09,372 INFO L85 PathProgramCache]: Analyzing trace with hash 1046817205, now seen corresponding path program 1 times [2024-11-13 13:54:09,372 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:54:09,372 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2057859016] [2024-11-13 13:54:09,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:54:09,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:54:09,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:54:09,383 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:54:09,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:54:09,402 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:54:09,403 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:54:09,403 INFO L85 PathProgramCache]: Analyzing trace with hash 481231283, now seen corresponding path program 1 times [2024-11-13 13:54:09,403 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:54:09,403 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [494783608] [2024-11-13 13:54:09,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:54:09,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:54:09,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:54:09,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:54:09,455 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:54:09,455 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [494783608] [2024-11-13 13:54:09,455 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [494783608] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:54:09,455 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:54:09,455 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:54:09,455 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [612594567] [2024-11-13 13:54:09,455 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:54:11,668 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 13:54:11,669 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 13:54:11,669 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 13:54:11,669 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 13:54:11,669 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-13 13:54:11,670 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:11,670 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 13:54:11,670 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 13:54:11,670 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.08.cil.c_Iteration34_Loop [2024-11-13 13:54:11,670 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 13:54:11,671 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 13:54:11,698 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,706 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,708 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,710 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,713 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,716 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,719 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,721 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,723 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,729 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,732 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,734 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,736 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,739 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,742 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,748 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,751 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,757 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,762 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,764 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,767 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,770 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,775 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,777 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,780 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,782 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,785 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,791 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,793 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,795 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,797 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,800 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,806 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,812 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,818 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,820 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,822 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,825 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,831 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,835 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,838 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,843 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,845 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,848 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,851 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,856 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,859 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,862 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,864 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,866 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,869 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,871 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,873 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,875 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,877 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,880 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,882 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,885 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,887 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,889 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,895 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,900 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,902 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,905 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,913 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,918 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,921 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,923 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,926 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,931 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,934 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,937 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,939 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,941 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,943 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,945 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,950 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,952 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,954 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,956 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,961 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,963 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,966 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,968 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,970 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,972 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,975 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,980 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,986 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,988 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,991 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,993 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,996 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:11,998 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:12,003 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:12,010 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:12,013 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:12,018 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:12,021 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:12,023 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:12,026 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:12,980 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 13:54:12,981 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-13 13:54:12,985 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:12,985 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:54:12,988 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:54:12,989 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-13 13:54:12,990 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:54:12,990 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:54:13,013 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:54:13,013 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:54:13,031 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-11-13 13:54:13,032 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:13,032 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:54:13,034 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:54:13,036 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-13 13:54:13,041 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:54:13,042 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:54:13,060 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:54:13,060 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:54:13,078 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-11-13 13:54:13,078 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:13,078 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:54:13,080 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:54:13,083 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-13 13:54:13,083 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:54:13,084 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:54:13,100 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:54:13,100 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Honda state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:54:13,118 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2024-11-13 13:54:13,118 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:13,118 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:54:13,121 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:54:13,122 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-13 13:54:13,124 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:54:13,124 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:54:13,150 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:54:13,151 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:54:13,168 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2024-11-13 13:54:13,168 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:13,169 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:54:13,170 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:54:13,172 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-13 13:54:13,173 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:54:13,173 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:54:13,190 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:54:13,190 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:54:13,207 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2024-11-13 13:54:13,207 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:13,208 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:54:13,209 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:54:13,211 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-13 13:54:13,212 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:54:13,212 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:54:13,237 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:54:13,237 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t8_st~0=4} Honda state: {~t8_st~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:54:13,253 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2024-11-13 13:54:13,254 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:13,254 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:54:13,256 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:54:13,258 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-13 13:54:13,259 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:54:13,259 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:54:13,276 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:54:13,276 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:54:13,293 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-11-13 13:54:13,293 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:13,293 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:54:13,295 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:54:13,298 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-13 13:54:13,299 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:54:13,299 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:54:13,315 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:54:13,315 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:54:13,332 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2024-11-13 13:54:13,333 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:13,333 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:54:13,335 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:54:13,337 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-13 13:54:13,338 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:54:13,338 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:54:13,374 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2024-11-13 13:54:13,375 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:13,375 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:54:13,377 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:54:13,379 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-13 13:54:13,380 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-13 13:54:13,380 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:54:13,398 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-13 13:54:13,415 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2024-11-13 13:54:13,415 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 13:54:13,416 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 13:54:13,416 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 13:54:13,416 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 13:54:13,416 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-13 13:54:13,416 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:13,416 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 13:54:13,416 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 13:54:13,416 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.08.cil.c_Iteration34_Loop [2024-11-13 13:54:13,416 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 13:54:13,416 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 13:54:13,420 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,427 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,430 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,433 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,436 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,438 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,445 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,448 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,453 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,456 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,459 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,461 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,464 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,466 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,469 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,472 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,474 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,477 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,479 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,485 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,490 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,493 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,498 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,501 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,503 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,506 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,509 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,518 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,520 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,525 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,528 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,534 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,537 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,545 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,548 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,550 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,552 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,554 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,561 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,564 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,567 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,573 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,576 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,579 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,581 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,584 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,586 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,591 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,595 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,598 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,603 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,606 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,608 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,610 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,612 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,615 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,618 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,620 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,626 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,631 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,634 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,636 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,639 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,646 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,648 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,650 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,655 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,658 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,661 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,663 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,665 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,667 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,669 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,672 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,678 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,680 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,683 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,685 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,687 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,692 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,695 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,698 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,700 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,702 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,704 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,706 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,709 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,711 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,713 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,718 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,721 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,726 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,728 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,732 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,741 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,743 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,748 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,751 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,756 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,759 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:13,764 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:54:14,490 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 13:54:14,494 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-13 13:54:14,500 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:14,500 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:54:14,506 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:54:14,508 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-11-13 13:54:14,509 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:54:14,525 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:54:14,525 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:54:14,526 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:54:14,526 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:54:14,526 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:54:14,530 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:54:14,531 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:54:14,533 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:54:14,550 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2024-11-13 13:54:14,550 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:14,551 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:54:14,552 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:54:14,553 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-11-13 13:54:14,554 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:54:14,565 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:54:14,565 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:54:14,565 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:54:14,565 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:54:14,565 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:54:14,566 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:54:14,566 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:54:14,567 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:54:14,586 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2024-11-13 13:54:14,587 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:14,587 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:54:14,589 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:54:14,592 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-11-13 13:54:14,593 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:54:14,609 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:54:14,609 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:54:14,609 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:54:14,609 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:54:14,609 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:54:14,610 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:54:14,610 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:54:14,613 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:54:14,633 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2024-11-13 13:54:14,633 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:14,634 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:54:14,636 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:54:14,638 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-11-13 13:54:14,640 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:54:14,655 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:54:14,655 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:54:14,656 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:54:14,656 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 13:54:14,656 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:54:14,657 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 13:54:14,657 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:54:14,660 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:54:14,678 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2024-11-13 13:54:14,678 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:14,679 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:54:14,681 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:54:14,682 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-11-13 13:54:14,683 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:54:14,696 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:54:14,696 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:54:14,696 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:54:14,696 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:54:14,696 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:54:14,699 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:54:14,699 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:54:14,702 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:54:14,719 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2024-11-13 13:54:14,719 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:14,719 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:54:14,720 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:54:14,721 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-11-13 13:54:14,722 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:54:14,733 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:54:14,733 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:54:14,733 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:54:14,733 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 13:54:14,733 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:54:14,734 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 13:54:14,734 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:54:14,736 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:54:14,747 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2024-11-13 13:54:14,748 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:14,748 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:54:14,749 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:54:14,750 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-11-13 13:54:14,751 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:54:14,762 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:54:14,762 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:54:14,762 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:54:14,762 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:54:14,762 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:54:14,763 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:54:14,763 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:54:14,764 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:54:14,775 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2024-11-13 13:54:14,775 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:14,775 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:54:14,777 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:54:14,778 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-11-13 13:54:14,778 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:54:14,789 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:54:14,790 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:54:14,790 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:54:14,790 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:54:14,790 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:54:14,791 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:54:14,791 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:54:14,793 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-13 13:54:14,800 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-13 13:54:14,803 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-13 13:54:14,804 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:54:14,805 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:54:14,809 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:54:14,811 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2024-11-13 13:54:14,812 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-13 13:54:14,812 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-13 13:54:14,812 INFO L474 LassoAnalysis]: Proved termination. [2024-11-13 13:54:14,813 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~M_E~0) = -1*~M_E~0 + 1 Supporting invariants [] [2024-11-13 13:54:14,825 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2024-11-13 13:54:14,826 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-13 13:54:14,849 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:54:14,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:54:14,920 INFO L255 TraceCheckSpWp]: Trace formula consists of 293 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-13 13:54:14,923 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:54:15,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:54:15,168 INFO L255 TraceCheckSpWp]: Trace formula consists of 242 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-13 13:54:15,170 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:54:15,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:54:15,538 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-13 13:54:15,539 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 45413 states and 58551 transitions. cyclomatic complexity: 13170 Second operand has 5 states, 5 states have (on average 44.8) internal successors, (224), 5 states have internal predecessors, (224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:54:16,703 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f37db1e9-8fe9-4b7a-b17f-45ef456e7b10/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2024-11-13 13:54:16,744 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 45413 states and 58551 transitions. cyclomatic complexity: 13170. Second operand has 5 states, 5 states have (on average 44.8) internal successors, (224), 5 states have internal predecessors, (224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 124295 states and 159866 transitions. Complement of second has 5 states. [2024-11-13 13:54:16,748 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-13 13:54:16,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 44.8) internal successors, (224), 5 states have internal predecessors, (224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:54:16,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 1179 transitions. [2024-11-13 13:54:16,755 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1179 transitions. Stem has 104 letters. Loop has 120 letters. [2024-11-13 13:54:16,761 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:54:16,765 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1179 transitions. Stem has 224 letters. Loop has 120 letters. [2024-11-13 13:54:16,767 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:54:16,767 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1179 transitions. Stem has 104 letters. Loop has 240 letters. [2024-11-13 13:54:16,774 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:54:16,774 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124295 states and 159866 transitions. [2024-11-13 13:54:17,192 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 84128 [2024-11-13 13:54:17,443 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124295 states to 124295 states and 159866 transitions. [2024-11-13 13:54:17,444 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 84758 [2024-11-13 13:54:17,499 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 84855 [2024-11-13 13:54:17,499 INFO L73 IsDeterministic]: Start isDeterministic. Operand 124295 states and 159866 transitions. [2024-11-13 13:54:17,500 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:54:17,500 INFO L218 hiAutomatonCegarLoop]: Abstraction has 124295 states and 159866 transitions. [2024-11-13 13:54:17,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124295 states and 159866 transitions. [2024-11-13 13:54:18,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124295 to 124198. [2024-11-13 13:54:18,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124198 states, 124198 states have (on average 1.2864055781896648) internal successors, (159769), 124197 states have internal predecessors, (159769), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:54:19,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124198 states to 124198 states and 159769 transitions. [2024-11-13 13:54:19,118 INFO L240 hiAutomatonCegarLoop]: Abstraction has 124198 states and 159769 transitions. [2024-11-13 13:54:19,118 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:54:19,118 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:54:19,119 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:54:19,119 INFO L87 Difference]: Start difference. First operand 124198 states and 159769 transitions. Second operand has 3 states, 3 states have (on average 74.66666666666667) internal successors, (224), 3 states have internal predecessors, (224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:54:20,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:54:20,078 INFO L93 Difference]: Finished difference Result 130870 states and 167497 transitions. [2024-11-13 13:54:20,078 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 130870 states and 167497 transitions. [2024-11-13 13:54:20,478 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 88576 [2024-11-13 13:54:20,845 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 130870 states to 130870 states and 167497 transitions. [2024-11-13 13:54:20,846 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 89206 [2024-11-13 13:54:20,908 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 89206 [2024-11-13 13:54:20,908 INFO L73 IsDeterministic]: Start isDeterministic. Operand 130870 states and 167497 transitions. [2024-11-13 13:54:20,909 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:54:20,909 INFO L218 hiAutomatonCegarLoop]: Abstraction has 130870 states and 167497 transitions. [2024-11-13 13:54:20,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130870 states and 167497 transitions. [2024-11-13 13:54:22,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130870 to 124198. [2024-11-13 13:54:22,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124198 states, 124198 states have (on average 1.2833137409620123) internal successors, (159385), 124197 states have internal predecessors, (159385), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:54:22,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124198 states to 124198 states and 159385 transitions. [2024-11-13 13:54:22,570 INFO L240 hiAutomatonCegarLoop]: Abstraction has 124198 states and 159385 transitions. [2024-11-13 13:54:22,571 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:54:22,571 INFO L424 stractBuchiCegarLoop]: Abstraction has 124198 states and 159385 transitions. [2024-11-13 13:54:22,571 INFO L331 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2024-11-13 13:54:22,571 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124198 states and 159385 transitions. [2024-11-13 13:54:23,360 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 84128 [2024-11-13 13:54:23,361 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:54:23,361 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:54:23,362 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:54:23,362 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:54:23,362 INFO L745 eck$LassoCheckResult]: Stem: 1807014#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1807015#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1808382#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1808383#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1808386#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1807241#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1807242#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1808372#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1808348#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1807387#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1807388#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1807859#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1807860#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1807542#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1807543#L838 assume !(0 == ~M_E~0); 1807878#L838-2 assume !(0 == ~T1_E~0); 1806654#L843-1 assume !(0 == ~T2_E~0); 1806655#L848-1 assume !(0 == ~T3_E~0); 1806864#L853-1 assume !(0 == ~T4_E~0); 1807517#L858-1 assume !(0 == ~T5_E~0); 1806575#L863-1 assume !(0 == ~T6_E~0); 1806576#L868-1 assume !(0 == ~T7_E~0); 1808494#L873-1 assume !(0 == ~T8_E~0); 1808486#L878-1 assume !(0 == ~E_1~0); 1808433#L883-1 assume !(0 == ~E_2~0); 1808434#L888-1 assume !(0 == ~E_3~0); 1807802#L893-1 assume !(0 == ~E_4~0); 1807803#L898-1 assume !(0 == ~E_5~0); 1808531#L903-1 assume !(0 == ~E_6~0); 1808429#L908-1 assume !(0 == ~E_7~0); 1808075#L913-1 assume !(0 == ~E_8~0); 1806673#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1806674#L402 assume !(1 == ~m_pc~0); 1807056#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1806911#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1806912#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1807399#L1035 assume !(0 != activate_threads_~tmp~1#1); 1807400#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1807495#L421 assume !(1 == ~t1_pc~0); 1808418#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1808495#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1806678#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1806679#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1807604#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1808521#L440 assume !(1 == ~t2_pc~0); 1808629#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1806925#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1806926#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1807292#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1808112#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1807297#L459 assume !(1 == ~t3_pc~0); 1807298#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1808412#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1806609#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1806610#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1806900#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1806917#L478 assume !(1 == ~t4_pc~0); 1806918#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1808242#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1806816#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1806817#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1806752#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1806753#L497 assume !(1 == ~t5_pc~0); 1806831#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1807727#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1807959#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1808522#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1808402#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1808403#L516 assume !(1 == ~t6_pc~0); 1808269#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1807858#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1807259#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1807004#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1807005#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1807838#L535 assume !(1 == ~t7_pc~0); 1807839#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1807984#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1807985#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1808060#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1808045#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1808046#L554 assume !(1 == ~t8_pc~0); 1806611#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1806612#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1808096#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1807168#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1807169#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1806591#L931 assume !(1 == ~M_E~0); 1806592#L931-2 assume !(1 == ~T1_E~0); 1808465#L936-1 assume !(1 == ~T2_E~0); 1808553#L941-1 assume !(1 == ~T3_E~0); 1807496#L946-1 assume !(1 == ~T4_E~0); 1807497#L951-1 assume !(1 == ~T5_E~0); 1807030#L956-1 assume !(1 == ~T6_E~0); 1807031#L961-1 assume !(1 == ~T7_E~0); 1807804#L966-1 assume !(1 == ~T8_E~0); 1807805#L971-1 assume !(1 == ~E_1~0); 1808049#L976-1 assume !(1 == ~E_2~0); 1807965#L981-1 assume !(1 == ~E_3~0); 1807503#L986-1 assume !(1 == ~E_4~0); 1807082#L991-1 assume !(1 == ~E_5~0); 1807083#L996-1 assume !(1 == ~E_6~0); 1808510#L1001-1 assume !(1 == ~E_7~0); 1807903#L1006-1 assume !(1 == ~E_8~0); 1807904#L1011-1 assume { :end_inline_reset_delta_events } true; 1808415#L1272-2 assume !false; 1815989#L1273 [2024-11-13 13:54:23,363 INFO L747 eck$LassoCheckResult]: Loop: 1815989#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1853501#L813-1 assume !false; 1853497#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1853495#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1853493#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1853492#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1853489#L696 assume 0 != eval_~tmp~0#1; 1853488#L696-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1853485#L704 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 1853486#L83 assume !(0 == ~m_pc~0); 1865169#L86 assume 1 == ~m_pc~0; 1865154#$Ultimate##322 assume !false; 1855035#L103 ~m_pc~0 := 1;~m_st~0 := 2; 1855033#master_returnLabel#1 assume { :end_inline_master } true; 1855023#L704-2 havoc eval_~tmp_ndt_1~0#1; 1855020#L701-1 assume !(0 == ~t1_st~0); 1855016#L715-1 assume !(0 == ~t2_st~0); 1855012#L729-1 assume !(0 == ~t3_st~0); 1855013#L743-1 assume !(0 == ~t4_st~0); 1853688#L757-1 assume !(0 == ~t5_st~0); 1853685#L771-1 assume !(0 == ~t6_st~0); 1853680#L785-1 assume !(0 == ~t7_st~0); 1853681#L799-1 assume !(0 == ~t8_st~0); 1853769#L813-1 assume !false; 1853767#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1853765#L634 assume !(0 == ~m_st~0); 1853763#L638 assume !(0 == ~t1_st~0); 1853761#L642 assume !(0 == ~t2_st~0); 1853759#L646 assume !(0 == ~t3_st~0); 1853756#L650 assume !(0 == ~t4_st~0); 1853754#L654 assume !(0 == ~t5_st~0); 1853752#L658 assume !(0 == ~t6_st~0); 1853751#L662 assume !(0 == ~t7_st~0); 1853748#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1853745#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1853743#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1853740#L696 assume !(0 != eval_~tmp~0#1); 1853738#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1853736#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1853734#L838-3 assume !(0 == ~M_E~0); 1853732#L838-5 assume !(0 == ~T1_E~0); 1853730#L843-3 assume !(0 == ~T2_E~0); 1853727#L848-3 assume !(0 == ~T3_E~0); 1853725#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1853723#L858-3 assume !(0 == ~T5_E~0); 1853721#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1853719#L868-3 assume !(0 == ~T7_E~0); 1853717#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1853715#L878-3 assume !(0 == ~E_1~0); 1853713#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1853711#L888-3 assume !(0 == ~E_3~0); 1853709#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1853707#L898-3 assume !(0 == ~E_5~0); 1853705#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1853704#L908-3 assume !(0 == ~E_7~0); 1853700#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1853698#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1853696#L402-27 assume 1 == ~m_pc~0; 1853694#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1853691#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1853687#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1853682#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1853679#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1853676#L421-27 assume !(1 == ~t1_pc~0); 1853674#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1853671#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1853669#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1853667#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 1853664#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1853662#L440-27 assume !(1 == ~t2_pc~0); 1853660#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1853659#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1853658#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1853656#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 1853654#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1853652#L459-27 assume 1 == ~t3_pc~0; 1853653#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1853651#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1853649#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1853645#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1853643#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1853640#L478-27 assume !(1 == ~t4_pc~0); 1853638#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1853636#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1853631#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1853629#L1067-27 assume !(0 != activate_threads_~tmp___3~0#1); 1853627#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1853625#L497-27 assume !(1 == ~t5_pc~0); 1853621#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1853619#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1853617#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1853615#L1075-27 assume !(0 != activate_threads_~tmp___4~0#1); 1853612#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1853610#L516-27 assume !(1 == ~t6_pc~0); 1853608#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1853606#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1853604#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1853602#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 1853600#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1853597#L535-27 assume !(1 == ~t7_pc~0); 1853594#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1853592#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1853589#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1853587#L1091-27 assume !(0 != activate_threads_~tmp___6~0#1); 1853585#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1853583#L554-27 assume !(1 == ~t8_pc~0); 1853581#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1853579#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1853577#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1853575#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 1853571#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1853569#L931-3 assume !(1 == ~M_E~0); 1853567#L931-5 assume !(1 == ~T1_E~0); 1853565#L936-3 assume !(1 == ~T2_E~0); 1853562#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1853560#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1853558#L951-3 assume !(1 == ~T5_E~0); 1853556#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1853554#L961-3 assume !(1 == ~T7_E~0); 1853552#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1853550#L971-3 assume !(1 == ~E_1~0); 1853548#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1853545#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1853543#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1853541#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1853539#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1853537#L1001-3 assume !(1 == ~E_7~0); 1853535#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1853533#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1853531#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1853529#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1853527#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1853524#L1291 assume !(0 == start_simulation_~tmp~3#1); 1853522#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1853521#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1853517#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1853515#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1853513#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1853510#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1853509#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1853508#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1853505#L1272-2 assume !false; 1815989#L1273 [2024-11-13 13:54:23,363 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:54:23,364 INFO L85 PathProgramCache]: Analyzing trace with hash -2024511545, now seen corresponding path program 1 times [2024-11-13 13:54:23,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:54:23,364 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1154594743] [2024-11-13 13:54:23,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:54:23,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:54:23,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:54:23,379 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:54:23,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:54:23,410 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:54:23,410 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:54:23,410 INFO L85 PathProgramCache]: Analyzing trace with hash -777065291, now seen corresponding path program 1 times [2024-11-13 13:54:23,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:54:23,411 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [831897014] [2024-11-13 13:54:23,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:54:23,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:54:23,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:54:23,463 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-11-13 13:54:23,463 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:54:23,463 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [831897014] [2024-11-13 13:54:23,463 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [831897014] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:54:23,464 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:54:23,464 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:54:23,464 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [253771355] [2024-11-13 13:54:23,464 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:54:23,464 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:54:23,464 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:54:23,465 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:54:23,465 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:54:23,465 INFO L87 Difference]: Start difference. First operand 124198 states and 159385 transitions. cyclomatic complexity: 35283 Second operand has 3 states, 3 states have (on average 46.0) internal successors, (138), 3 states have internal predecessors, (138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:54:24,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:54:24,221 INFO L93 Difference]: Finished difference Result 224968 states and 285309 transitions. [2024-11-13 13:54:24,221 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 224968 states and 285309 transitions. [2024-11-13 13:54:25,800 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 142032 [2024-11-13 13:54:26,398 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 224968 states to 219816 states and 278877 transitions. [2024-11-13 13:54:26,398 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 146824 [2024-11-13 13:54:26,460 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 146824 [2024-11-13 13:54:26,460 INFO L73 IsDeterministic]: Start isDeterministic. Operand 219816 states and 278877 transitions. [2024-11-13 13:54:26,511 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:54:26,511 INFO L218 hiAutomatonCegarLoop]: Abstraction has 219816 states and 278877 transitions. [2024-11-13 13:54:26,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219816 states and 278877 transitions. [2024-11-13 13:54:28,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219816 to 219688. [2024-11-13 13:54:29,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 219688 states, 219688 states have (on average 1.2688403554131313) internal successors, (278749), 219687 states have internal predecessors, (278749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)